GD32F310xx Datasheet
GigaDevice Semiconductor Inc.
GD32F310xx
Arm® Cortex®-M4 32-bit MCU
Datasheet
Revision 1.1
(Apr. 2022)
0
GD32F310xx Datasheet
Table of Contents
Table of Contents ........................................................................................................... 0
List of Figures ................................................................................................................ 0
List of Tables .................................................................................................................. 1
1
General description ................................................................................................. 0
2
Device overview ....................................................................................................... 1
3
2.1
Device information ...................................................................................................... 1
2.2
Block diagram .............................................................................................................. 2
2.3
Pinouts and pin assignment ....................................................................................... 3
2.4
Memory map ................................................................................................................ 6
2.5
Clock tree ..................................................................................................................... 8
2.6
Pin definitions .............................................................................................................. 9
2.6.1
GD32F310CxT6 LQFP48 pin definitions ................................................................................ 9
2.6.2
GD32F310KxT6 LQFP32 pin definitions .............................................................................. 12
2.6.3
GD32F310KxU6 QFN32 pin definitions ................................................................................ 14
2.6.4
GD32F310GxU6 QFN28 pin definitions ............................................................................... 16
2.6.5
GD32F310FxP6 TSSOP20 pin definitions ........................................................................... 17
2.6.6
GD32F310xx pin alternate functions .................................................................................... 20
Functional description .......................................................................................... 24
3.1
Arm® Cortex®-M4 core ............................................................................................... 24
3.2
On-chip memory ........................................................................................................ 24
3.3
Clock, reset and supply management ...................................................................... 25
3.4
Boot modes ................................................................................................................ 25
3.5
Power saving modes ................................................................................................. 26
3.6
Analog to digital converter (ADC) ............................................................................ 26
3.7
DMA ............................................................................................................................ 27
3.8
General-purpose inputs/outputs (GPIOs) ................................................................ 27
3.9
Timers and PWM generation..................................................................................... 27
3.10
Real time clock (RTC) ............................................................................................ 28
3.11
Inter-integrated circuit (I2C) .................................................................................. 29
3.12
Serial peripheral interface (SPI) ............................................................................ 29
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GD32F310xx Datasheet
4
5
3.13
Universal synchronous asynchronous receiver transmitter (USART) ............... 30
3.14
Inter-IC sound (I2S) ................................................................................................ 30
3.15
Debug mode ........................................................................................................... 30
3.16
Package and operation temperature ..................................................................... 30
Electrical characteristics ....................................................................................... 31
4.1
Absolute maximum ratings ....................................................................................... 31
4.2
Operating conditions characteristics ....................................................................... 31
4.3
Power consumption .................................................................................................. 33
4.4
EMC characteristics .................................................................................................. 38
4.5
Power supply supervisor characteristics ................................................................ 39
4.6
Electrical sensitivity .................................................................................................. 39
4.7
External clock characteristics .................................................................................. 40
4.8
Internal clock characteristics ................................................................................... 42
4.9
PLL characteristics.................................................................................................... 44
4.10
Memory characteristics ......................................................................................... 44
4.11
NRST pin characteristics ....................................................................................... 44
4.12
GPIO characteristics .............................................................................................. 45
4.13
ADC characteristics ............................................................................................... 47
4.14
Temperature sensor characteristics ..................................................................... 48
4.15
I2C characteristics ................................................................................................. 49
4.16
SPI characteristics ................................................................................................. 50
4.17
I2S characteristics.................................................................................................. 52
4.18
USART characteristics ........................................................................................... 54
4.19
TIMER characteristics ............................................................................................ 54
4.20
WDGT characteristics ............................................................................................ 54
4.21
Parameter conditions............................................................................................. 55
Package information.............................................................................................. 56
5.1
LQFP48 package outline dimensions....................................................................... 56
5.2
LQFP32 package outline dimensions....................................................................... 58
5.3
QFN32 package outline dimensions ........................................................................ 60
5.4
QFN28 package outline dimensions ........................................................................ 62
5.5
TSSOP20 package outline dimensions .................................................................... 64
1
GD32F310xx Datasheet
5.6
Thermal characteristics ............................................................................................ 66
6
Ordering information ............................................................................................. 68
7
Revision history ..................................................................................................... 69
2
GD32F310xx Datasheet
List of Figures
Figure 2-1. GD32F310xx block diagram ............................................................................................................... 2
Figure 2-2. GD32F310CxT6 LQFP48 pinouts ...................................................................................................... 3
Figure 2-3. GD32F310KxT6 LQFP32 pinouts ...................................................................................................... 3
Figure 2-4. GD32F310KxU6 QFN32 pinouts ........................................................................................................ 4
Figure 2-5. GD32F310GxU6 QFN28 pinouts........................................................................................................ 4
Figure 2-6. GD32F310FxP6 TSSOP20 pinouts ................................................................................................... 5
Figure 2-7. GD32F310xx clock tree ....................................................................................................................... 8
Figure 4-1. Recommended power supply decoupling capacitors (1) ........................................................... 32
Figure 4-2. Typical supply current consumption in Run mode ................................................................... 37
Figure 4-3. Typical supply current consumption in Sleep mode ................................................................ 37
Figure 4-4. Recommended external NRST pin circuit .................................................................................... 45
Figure 4-5. I/O port AC characteristics definition............................................................................................ 46
Figure 4-6. I2C bus timing diagram ..................................................................................................................... 49
Figure 4-7. SPI timing diagram - master mode ................................................................................................ 50
Figure 4-8. SPI timing diagram - slave mode ................................................................................................... 51
Figure 4-9. I2S timing diagram - master mode ................................................................................................. 53
Figure 4-10. I2S timing diagram - slave mode .................................................................................................. 53
Figure 5-1. LQFP48 package outline .................................................................................................................. 56
Figure 5-2. LQFP48 recommended footprint .................................................................................................... 57
Figure 5-3. LQFP32 package outline .................................................................................................................. 58
Figure 5-4. LQFP32 recommended footprint .................................................................................................... 59
Figure 5-5. QFN32 package outline ..................................................................................................................... 60
Figure 5-6. QFN32 recommended footprint ...................................................................................................... 61
Figure 5-7. QFN28 package outline ..................................................................................................................... 62
Figure 5-8. QFN28 recommended footprint ...................................................................................................... 63
Figure 5-9. TSSOP20 package outline ................................................................................................................ 64
Figure 5-10. TSSOP20 recommended footprint ............................................................................................... 65
0
GD32F310xx Datasheet
List of Tables
Table 2-1. GD32F310xx devices features and peripheral list ......................................................................... 1
Table 2-2. GD32F310xx memory map ................................................................................................................... 6
Table 2-3. GD32F310CxT6 LQFP48 pin definitions ........................................................................................... 9
Table 2-4. GD32F310KxT6 LQFP32 pin definitions ......................................................................................... 12
Table 2-5. GD32F310KxU6 QFP32 pin definitions ........................................................................................... 14
Table 2-6. GD32F310GxU6 QFN28 pin definitions ........................................................................................... 16
Table 2-7. GD32F310FxP6 TSSOP20 pin definitions ....................................................................................... 17
Table 2-8. Port A alternate functions summary ............................................................................................... 20
Table 2-9. Port B alternate functions summary ............................................................................................... 21
Table 2-10. Port C alternate functions summary ............................................................................................. 22
Table 2-11. Port D alternate functions summary ............................................................................................. 22
Table 2-12. Port F alternate functions summary ............................................................................................. 23
Table 4-1. Absolute maximum ratings(1)(4) ......................................................................................................... 31
Table 4-2. DC operating conditions..................................................................................................................... 31
Table 4-3. Clock frequency(1) ................................................................................................................................. 32
Table 4-4. Operating conditions at Power up/ Power down(1) ...................................................................... 32
Table 4-5. Start-up timings of Operating conditions (1)(2)(3) ............................................................................. 32
Table 4-6. Power saving mode wakeup timings characteristics(1)(2) ........................................................... 32
Table 4-7.Power consumption characteristics(2)(3)(3)(4)(5) ................................................................................. 33
Table 4-8. Peripheral current consumption characteristics(1) ...................................................................... 37
Table 4-9. EMS characteristics(1) ......................................................................................................................... 38
Table 4-10. Power supply supervisor characteristics .................................................................................... 39
Table 4-11. ESD characteristics(1) ........................................................................................................................ 40
Table 4-12. Static latch-up characteristics(1)..................................................................................................... 40
Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics .. 40
Table 4-14. High speed external user clock characteristics (HXTAL in bypass mode) ......................... 40
Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics ... 41
Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode) .......................... 41
Table 4-17. High speed internal clock (IRC8M) characteristics ................................................................... 42
Table 4-18. Low speed internal clock (IRC40K) characteristics .................................................................. 42
Table 4-19. High speed internal clock (IRC28M) characteristics ................................................................. 43
Table 4-20. High speed internal clock (IRC48M) characteristics ................................................................. 43
Table 4-21. PLL characteristics ............................................................................................................................ 44
Table 4-22 Flash memory characteristics.......................................................................................................... 44
Table 4-23. NRST pin characteristics ................................................................................................................. 44
Table 4-24. I/O port DC characteristics(1)(3) ........................................................................................................ 45
Table 4-25. I/O port AC characteristics(1)(2) ........................................................................................................ 46
Table 4-26. ADC characteristics .......................................................................................................................... 47
Table 4-27. ADC RAIN max for fADC = 40 MHz(1) .................................................................................................. 47
Table 4-28. ADC dynamic accuracy at fADC = 28 MHz(1) .................................................................................. 48
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GD32F310xx Datasheet
(1)
Table 4-29. ADC dynamic accuracy at fADC = 30 MHz .................................................................................. 48
Table 4-30.ADC dynamic accuracy at fADC = 36 MHz(1) ................................................................................... 48
Table 4-31. ADC static accuracy at fADC = 14 MHz(1) ........................................................................................ 48
Table 4-32. Temperature sensor characteristics(1) .......................................................................................... 48
Table 4-33. I2C characteristics(1)(2)(3) ................................................................................................................... 49
Table 4-34. Standard SPI characteristics .......................................................................................................... 50
Table 4-35. I2S characteristics ............................................................................................................................. 52
Table 4-36. USART characteristics(1) .................................................................................................................. 54
Table 4-37. TIMER characteristics(1).................................................................................................................... 54
Table 4-38. FWDGT min/max timeout period at 40 kHz (IRC40K)(1) ............................................................ 54
Table 4-39. WWDGT min-max timeout value at 36 MHz (fPCLK1)(1) ................................................................ 55
Table 5-1. LQFP48 package dimensions ........................................................................................................... 56
Table 5-2. LQFP32 package dimensions ........................................................................................................... 58
Table 5-3. QFN32 package dimensions .............................................................................................................. 60
Table 5-4. QFN28 package dimensions .............................................................................................................. 62
Table 5-5. TSSOP20 package dimensions ......................................................................................................... 64
Table 5-6. Package thermal characteristics(1)................................................................................................... 66
Table 6-1. Part ordering code for GD32F310xx devices ................................................................................ 68
Table 7-1. Revision history ................................................................................................................................... 69
2
GD32F310xx Datasheet
1
General description
The GD32F310xx device belongs to the value line of GD32 MCU family. It is a new 32-bit
general-purpose microcontroller based on the Arm® Cortex®-M4 RISC core with best costperformance ratio in terms of enhanced processing capacity, reduced power consumption
and peripheral set. The Cortex®-M4 core features implement a full set of DSP instructions to
address digital signal control markets that demand an efficient, easy-to-use blend of control
and signal processing capabilities. It also provides a powerful trace technology for enhanced
application security and advanced debug support.
The GD32F310xx device incorporates the Arm® Cortex®-M4 32-bit processor core operating
at 72 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It
provides up to 64 KB on-chip Flash memory and up to 8 KB SRAM memory. An extensive
range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one
12-bit ADC, up to five general 16-bit timers, a PWM advanced timer, as well as standard and
advanced communication interfaces: up to two SPIs, two I2Cs, an I2S, two USARTs.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make the GD32F310xx devices suitable for a wide range of applications,
especially in areas such as industrial control, motor drives, user interface, power monitor and
alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on.
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GD32F310xx Datasheet
2
Device overview
2.1
Device information
Table 2-1. GD32F310xx devices features and peripheral list
GD32F310xx
Timers
Flash
Part Number
F4P6
F6P6
F8P6
G8U6
K6T6
K8T6
K8U6
C8T6
Code area (KB)
16
32
64
64
32
64
64
64
Total (KB)
16
32
64
64
32
64
64
64
SRAM (KB)
4
6
8
8
6
8
8
8
General timer (16-
4
4
4
5
4
5
5
5
bit)
(2,13,15,16)
(2,13,15,16)
(2,13,15,16)
(2,13-16)
(2,13,15,16)
(2,13-16)
(2,13-16)
(2,13-16)
Advanced timer
1
1
1
1
1
1
1
1
(16-bit)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
SysTick
1
1
1
1
1
1
1
1
Watchdog
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
(0)
(0-1)
(0-1)
(0-1)
(0-1)
(0-1)
(0-1)
(0-1)
1
1
2
2
1
2
2
2
(0)
(0)
(0-1)
(0-1)
(0)
(0-1)
(0-1)
(0-1)
1
1
2
2
1
2
2
2
(0)
(0)
(0-1)
(0-1)
(0)
(0-1)
(0-1)
(0-1)
1
1
1
1
1
1
1
1
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
GPIO
15
15
15
23
25
25
27
39
EXTI
12
12
12
14
16
16
16
16
Units
1
1
1
1
1
1
1
1
Channels (External)
9
9
9
10
10
10
10
10
Channels (Internal)
3
3
3
3
3
3
3
3
Connectivity
USART
I2C
SPI
ADC
I2S
Package
TSSOP20
QFN28
LQFP32
QFN32 LQFP48
1
GD32F310xx Datasheet
2.2
Block diagram
Figure 2-1. GD32F310xx block diagram
LDO
1.2V
TPIU
SW
AHB Matrix
NVIC
ICode DCode System
ARM Cortex-M4
Processor
Fmax: 72MHz
AHB2: Fma x = 72MHz
IBus
GPIO Ports
A, B, C, D, F
SRAM
Controller
SRAM
Flash
Memory
Controller
Flash
Memory
POR/PDR
LVD
PLL
Fmax: 72MHz
HXTAL
4-32MHz
DBus
GP DMA
7chs
AHB1: Fma x = 72MHz
AHB to APB
Bridge 2
CRC
AHB to APB
Bridge 1
IRC8M
8MHz
RST/CLK
Controller
IRC48M
48MHz
Powered by LDO (1.2V)
PMU
EXTI
FWDGT
12-bit
SAR ADC
IRC28M
28MHz
ADC
RTC
I2C0
SPI0/I2S0
APB1: Fmax = 36MHz
TIMER15
APB2: Fmax = 36MHz
TIMER14
Powered by V DD/VDDA
WWDGT
USART0
TIMER0
IRC40K
40KHz
I2C1
CTC
USART1
SPI1
TIMER16
TIMER2
TIMER13
2
GD32F310xx Datasheet
2.3
Pinouts and pin assignment
Figure 2-2. GD32F310CxT6 LQFP48 pinouts
PA14
PA15
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS
VDD
48 47 46 45 44 43 42 41 40 39 38 37
VBAT
1
36
PF7
PC13
2
35
PF6
PC14-OSC32IN
3
34
PA13
PC15-OSC32OUT
PF0-OSCIN
4
33
PA12
5
32
PA11
31
PA10
30
PA9
GigaDevice
GD32F310CxT6
LQFP48
PF1-OSCOUT
NRST
VSSA
6
8
29
VDDA
9
28
PA8
PB15
PA0
10
27
PB14
PA1
PA2
11
26
PB13
25
PB12
7
12
13 14 15 16 17 18 19 20 21 22 23 24
VDD
VSS
PB11
PB10
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
Figure 2-3. GD32F310KxT6 LQFP32 pinouts
PA15
PB3
PB4
PB5
PB6
PB7
BOOT0
Vss
32 31 30 29 28 27 26 25
VDD
1
24
PA14
PF0-OSCIN
2
23
PA13
PF1-OSCOUT
3
22
PA12
NRST
VDDA
4
21
PA11
5
20
PA10
PA0
6
19
PA9
PA1
PA2
7
18
PA8
8
17
VDD
GigaDevice
GD32F310KxT6
LQFP32
9 10 11 12 13 14 15 16
VSS
PB1
PB0
PA7
PA6
PA5
PA4
PA3
3
GD32F310xx Datasheet
Figure 2-4. GD32F310KxU6 QFN32 pinouts
VDDA
PA0
5
PA1
7
PA2
8
PA15
PB3
3
PB4
OSCOUT/PF1
NRST
PB5
OSCIN/PF0
2
PB6
1
PB7
BOOT0
PB8
VDD
32 31 30 29 28 27 26 25
24
PA14
23
PA13
22
PA12
21
PA11
20
PA10
19
PA9
18
PA8
17
VDD
GigaDevice
GD32F310KxU6
QFN32
4
6
VSS, VSSA
9 10 11 12 13 14 15 16
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
Figure 2-5. GD32F310GxU6 QFN28 pinouts
PA14
PA15
PB3
PB4
PB5
PB6
PB7
28 27 26 25 24 23 22
1
21
2
20
PA13
OSCOUT/PF1
NRST
3
19
PA9
18
PA8
VDDA
PA0
5
17
VDD
16
PA1
7
VSS
PB1
BOOT0
OSCIN/PF0
GigaDevice
GD32F310GxU6
QFN28
4
6
8 9 10 11 12 13 14
15
PA10
PB0
PA7
PA6
PA5
PA4
PA3
PA2
4
GD32F310xx Datasheet
Figure 2-6. GD32F310FxP6 TSSOP20 pinouts
1
20
PA14
OSCIN/PF0
2
19
PA13
OSCOUT/PF1
3
18
PA10
4
17
PA9
BOOT0
NRST
PA0
GigaDevice
5
16
GD32F310FxP6
6
TSSOP20 15
PA1
7
14
PB1
PA2
8
13
PA7
PA3
9
12
PA6
PA4
10
11
PA5
VDDA
VDD
Vss
5
GD32F310xx Datasheet
2.4
Memory map
Table 2-2. GD32F310xx memory map
Pre-defined
Address
Peripherals
0xE000 0000 - 0xE00F FFFF
Cortex®-M4 internal peripherals
External Device
0xA000 0000 - 0xDFFF FFFF
Reserved
External RAM
0x6000 0000 - 0x9FFF FFFF
Reserved
0x5004 0000 - 0x5FFF FFFF
Reserved
0x5000 0000 - 0x5003 FFFF
Reserved
0x4800 1800 - 0x4FFF FFFF
Reserved
0x4800 1400 - 0x4800 17FF
GPIOF
0x4800 1000 - 0x4800 13FF
Reserved
0x4800 0C00 - 0x4800 0FFF
GPIOD
0x4800 0800 - 0x4800 0BFF
GPIOC
0x4800 0400 - 0x4800 07FF
GPIOB
0x4800 0000 - 0x4800 03FF
GPIOA
0x4002 4400 - 0x47FF FFFF
Reserved
0x4002 4000 - 0x4002 43FF
Reserved
0x4002 3400 - 0x4002 3FFF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2400 - 0x4002 2FFF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1400 - 0x4002 1FFF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0400 - 0x4002 0FFF
Reserved
0x4002 0000 - 0x4002 03FF
DMA
0x4001 8000 - 0x4001 FFFF
Reserved
0x4001 5C00 - 0x4001 7FFF
Reserved
0x4001 4C00 - 0x4001 5BFF
Reserved
0x4001 4800 - 0x4001 4BFF
TIMER16
0x4001 4400 - 0x4001 47FF
TIMER15
0x4001 4000 - 0x4001 43FF
TIMER14
0x4001 3C00 - 0x4001 3FFF
Reserved
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
Reserved
0x4001 3000 - 0x4001 33FF
SPI0/I2S0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
Reserved
0x4001 2400 - 0x4001 27FF
ADC
0x4001 0800 - 0x4001 23FF
Reserved
0x4001 0400 - 0x4001 07FF
EXTI
Regions
Bus
AHB1
AHB2
AHB1
Peripherals
APB2
6
GD32F310xx Datasheet
Pre-defined
Regions
Bus
APB1
SRAM
Code
Address
Peripherals
0x4001 0000 - 0x4001 03FF
SYSCFG
0x4000 CC00 - 0x4000 FFFF
Reserved
0x4000 C800 - 0x4000 CBFF
CTC
0x4000 C400 - 0x4000 C7FF
Reserved
0x4000 C000 - 0x4000 C3FF
Reserved
0x4000 8000 - 0x4000 BFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
Reserved
0x4000 7800 - 0x4000 7BFF
Reserved
0x4000 7400 - 0x4000 77FF
Reserved
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6400 - 0x4000 6FFF
Reserved
0x4000 6000 - 0x4000 63FF
Reserved
0x4000 5C00 - 0x4000 5FFF
Reserved
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 4800 - 0x4000 53FF
Reserved
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
Reserved
0x4000 3800 - 0x4000 3BFF
SPI1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIMER13
0x4000 1400 - 0x4000 1FFF
Reserved
0x4000 1000 - 0x4000 13FF
Reserved
0x4000 0800 - 0x4000 0FFF
Reserved
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
Reserved
0x2000 4000 - 0x3FFF FFFF
Reserved
0x2000 0000 - 0x2000 3FFF
SRAM
0x1FFF FC00 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF FBFF
Option bytes
0x1FFF EC00 - 0x1FFF F7FF
System memory
0x0802 0000 - 0x1FFF EBFF
Reserved
0x0800 0000 - 0x0801 FFFF
Main Flash memory
0x0010 0000 - 0x07FF FFFF
Reserved
0x0000 0000 - 0x000F FFFF
Aliased to Flash or system memory
7
GD32F310xx Datasheet
2.5
Clock tree
Figure 2-7. GD32F310xx clock tree
CK_I2S
(to I2S)
CK_FMC
SCS[1:0]
FMC enable
( by hardware)
( to FMC)
HCLK
CK_IRC8M
00
8 MHz
IRC8M
0
/2
1
×2,3,4
,64
PLL
CK_PLL 10
AHB enable
CK_ SYS
72 MHz max
AHB
Prescaler
÷1,2... 512
( to AHB bus, Cortex-M4, SRAM, DMA)
CK_ CST
CK_ AHB
÷8
72 MHz max
( to Cortex-M 4 SysTick)
FCLK
PLLMF
PREDV PLLSEL
PLLPRESEL
CK_IRC48M
01
1
4- 32 MHz
HXTAL
Clock
Monitor
÷1,2.
..16
0
TIMER1,2,5,13
if(APB1 prescaler
=1) = AHB
else
= AHB / (APB1
( free running clock
)
CK_TIMERx
TIMERx
enable
to TIMER 2,13
prescaler /2)
CK_HXTAL
/32
APB1
Prescaler
÷1,2,4,8,16
11
32. 768 KHz
LXTAL
CK_ RTC
01
( to RTC)
10
TIMER0,14,15,16
if(APB2 prescaler
=1) = AHB
else
= AHB / (APB2
CK_ APB1
PCLK1
36 MHz max
to APB1 peripherals
Peripheral enable
CK_TIMERx
TIMERx
enable
to TIMER0,14,15,16
prescaler /2)
RTCSRC[1:0]
40 KHz
IRC40K
CK_F WDGT
( to F WDGT)
APB2
Prescaler
÷1,2,4,8,16
CK_ APB2
PCLK2
to APB2 peripherals
36 MHz max
Peripheral enable
CK_ OUT
0
CK_IRC28M
CK_IRC40K
CK_ LXTAL
CK_SYS
CK_IRC8M
CK_ HXTAL
/1,2
CK_PLL
÷1,2,4... 128
CKOUTDIV
CK_ IRC8M
11
CK_L XTAL
10
CK_ SYS
01
CK_ USART0
to USART0
00
ADCSEL
28 MHz
IRC28M
÷1,2
0
CK_ ADC to ADC
1
40 MHz max
CTC
CK_IRC48M
CK_ CTC
48 MHz
IRC48M
ADC
Prescaler
÷2,4,6,8
48 MHz
ADC
Prescaler
÷3,5,7,9
Note:
If the APB prescaler is 1, the timer clock frequencies are set to AHB frequency divide by 1.
Otherwise, they are set to the AHB frequency divide by half of APB prescaler.
Legend:
HXTAL: High speed crystal oscillator
LXTAL: Low speed crystal oscillator
IRC8M: Internal 8M RC oscillators
IRC40K: Internal 40K RC oscillator
IRC48M: Internal 48M RC oscillator
IRC28M: Internal 28M RC oscillators
8
GD32F310xx Datasheet
2.6
Pin definitions
2.6.1
GD32F310CxT6 LQFP48 pin definitions
Table 2-3. GD32F310CxT6 LQFP48 pin definitions
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
VBAT
1
P
2
I/O
3
I/O
4
I/O
5
I/O
Default: VBAT
PC13TAMPER-
Functions description
Default: PC13
Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1
RTC
PC14OSC32IN
PC15OSC32OUT
Default: PC14
Additional: OSC32IN
Default: PC15
Additional: OSC32OUT
Default: PF0
PF0-OSCIN
5VT
Alternate: CTC_SYNC
Additional: OSCIN
PF1-
5VT
Default: PF1
6
I/O
NRST
7
I/O
VSSA
8
P
Default: VSSA
VDDA
9
P
Default: VDDA
PA0-WKUP
10
I/O
OSCOUT
Additional: OSCOUT
Default: NRST
Default: PA0
Alternate: USART1_CTS, I2C1_SCL
Additional: ADC_IN0, RTC_TAMP1, WKUP0
Default: PA1
PA1
11
I/O
Alternate: USART1_RTS, I2C1_SDA, EVENTOUT
Additional: ADC_IN1
Default: PA2
PA2
12
I/O
Alternate: USART1_TX, TIMER14_CH0
Additional: ADC_IN2
Default: PA3
PA3
13
I/O
Alternate: USART1_RX, TIMER14_CH1
Additional: ADC_IN3
Default: PA4
PA4
14
I/O
Alternate: SPI0_NSS, I2S0_WS, USART1_CK,
TIMER13_CH0, SPI1_NSS
Additional: ADC_IN4
Default: PA5
PA5
15
I/O
Alternate: SPI0_SCK, I2S0_CK
Additional: ADC_IN5
Default: PA6
PA6
16
I/O
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
TIMER0_BKIN, TIMER15_CH0, EVENTOUT
9
GD32F310xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Additional: ADC_IN6
Default: PA7
Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,
PA7
17
TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,
I/O
EVENTOUT
Additional: ADC_IN7
Default: PB0
PB0
18
Alternate: TIMER2_CH2, TIMER0_CH1_ON,
I/O
USART1_RX, EVENTOUT
Additional: ADC_IN8
Default: PB1
PB1
19
Alternate: TIMER2_CH3, TIMER13_CH0,
I/O
TIMER0_CH2_ON, SPI1_SCK
Additional: ADC_IN9
Default: PB2
PB2
20
I/O
5VT
PB10
21
I/O
5VT
PB11
22
I/O
5VT
VSS
23
P
Default: VSS
VDD
24
P
Default: VDD
Default: PB10
Alternate: I2C1_SCL, SPI1_IO2
Default: PB11
Alternate: I2C1_SDA, EVENTOUT, SPI1_IO3
Default: PB12
PB12
25
I/O
5VT
Alternate: SPI1_NSS, TIMER0_BKIN, I2C1_SMBA,
EVENTOUT
PB13
26
I/O
5VT
Default: PB13
Alternate: SPI1_SCK, TIMER0_CH0_ON
Default: PB14
PB14
27
I/O
5VT
Alternate: SPI1_MISO, TIMER0_CH1_ON,
TIMER14_CH0
Default: PB15
Alternate: SPI1_MOSI, TIMER0_CH2_ON,
PB15
28
I/O
5VT
TIMER14_CH0_ON, TIMER14_CH1
Additional: RTC_REFIN, WKUP6
Default: PA8
PA8
29
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT,
USART1_TX, EVENTOUT,CTC_SYNC
Default: PA9
PA9
30
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN ,
I2C0_SCL
Default: PA10
PA10
31
I/O
5VT
Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,
I2C0_SDA
Default: PA11
PA11
32
I/O
5VT
Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT,
SPI1_IO2
10
GD32F310xx Datasheet
Pin Name
Pins
PA12
33
Pin
I/O
Type(1)
Level(2)
I/O
5VT
Functions description
Default: PA12
Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT,
SPI1_IO3
PA13
34
I/O
5VT
PF6
35
I/O
5VT
PF7
36
I/O
5VT
PA14
37
I/O
5VT
Default: PA13
Alternate: IFRP_OUT, SWDIO, SPI1_MISO
Default: PF6
Alternate: I2C1_SCL
Default: PF7
Alternate: I2C1_SDA
Default: PA14
Alternate: USART1_TX, SWCLK, SPI1_MOSI
Default: PA15
PA15
38
I/O
5VT
Alternate: SPI0_NSS, I2S0_WS, USART1_RX,
SPI1_NSS, EVENTOUT
PB3
39
I/O
5VT
PB4
40
I/O
5VT
Default: PB3
Alternate: SPI0_SCK, I2S0_CK, EVENTOUT
Default: PB4
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
EVENTOUT
Default: PB5
PB5
41
I/O
5VT
Alternate: SPI0_MOSI, I2S0_SD, I2C0_SMBA,
TIMER15_BKIN, TIMER2_CH1
Additional:WKUP5
PB6
42
I/O
5VT
PB7
43
I/O
5VT
BOOT0
44
I
PB8
45
I/O
Default: PB6
Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON
Default: PB7
Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON
Default: BOOT0
5VT
Default: PB8
Alternate: I2C0_SCL, TIMER15_CH0
Default: PB9
PB9
46
I/O
5VT
Alternate: I2C0_SDA, IFRP_OUT,TIMER16_CH0,
EVENTOUT, I2S0_MCK
VSS
47
P
Default: VSS
VDD
48
P
Default: VDD
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
11
GD32F310xx Datasheet
2.6.2
GD32F310KxT6 LQFP32 pin definitions
Table 2-4. GD32F310KxT6 LQFP32 pin definitions
Pin Name
Pins
VDD
1
Pin
I/O
Type(1)
Level(2)
Functions description
Default: VDD
P
Default: PF0
PF0-OSCIN
2
I/O
5VT
Alternate: CTC_SYNC
Additional: OSCIN
PF1-
3
I/O
NRST
4
I/O
VDDA
5
P
OSCOUT
5VT
Default: PF1
Additional: OSCOUT
Default: NRST
Default: VDDA
Default: PA0
PA0-WKUP
6
I/O
Alternate: USART1_CTS(3), I2C1_SCL(4)
Additional: ADC_IN0, RTC_TAMP1, WKUP0
Default: PA1
PA1
7
I/O
Alternate: USART1_RTS(3), I2C1_SDA(4), EVENTOUT
Additional: ADC_IN1
Default: PA2
PA2
8
I/O
Alternate: USART1_TX(3), TIMER14_CH0
Additional: ADC_IN2
Default: PA3
PA3
9
I/O
Alternate: USART1_RX(3), TIMER14_CH1
Additional: ADC_IN3
Default: PA4
PA4
10
I/O
Alternate: SPI0_NSS, I2S0_WS, USART1_CK(3),
TIMER13_CH0, SPI1_NSS(4)
Additional: ADC_IN4
Default: PA5
PA5
11
I/O
Alternate: SPI0_SCK, I2S0_CK
Additional: ADC_IN5
Default: PA6
PA6
12
I/O
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
TIMER0_BRKIN, TIMER15_CH0, EVENTOUT
Additional: ADC_IN6
Default: PA7
Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,
PA7
13
I/O
TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,
EVENTOUT
Additional: ADC_IN7
Default: PB0
PB0
14
I/O
Alternate: TIMER2_CH2, TIMER0_CH1_ON,
USART1_RX(3), EVENTOUT
Additional: ADC_IN8
PB1
15
I/O
Default: PB1
Alternate: TIMER2_CH3, TIMER13_CH0,
12
GD32F310xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
TIMER0_CH2_ON, SPI1_SCK(4)
Additional: ADC_IN9
VSS
16
P
Default: VSS
VDD
17
P
Default: VDD
Default: PA8
PA8
18
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT,
USART1_TX(3), EVENTOUT, CTC_SYNC
Default: PA9
PA9
19
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1,
TIMER14_BRKIN, I2C0_SCL
Default: PA10
PA10
20
I/O
5VT
Alternate: USART0_RX, TIMER0_CH2,
TIMER16_BRKIN, I2C0_SDA
Default: PA11
PA11
21
I/O
5VT
Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT,
SPI1_IO2(4)
Default: PA12
PA12
22
I/O
5VT
Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT,
SPI1_IO3(4)
PA13
23
I/O
5VT
PA14
24
I/O
5VT
PA15
25
I/O
5VT
Default: PA13
Alternate: SWDIO, IFRP_OUT, SPI1_MISO(4)
Default: PA14
Alternate: USART1_TX(3), SWCLK, SPI1_MOSI(4)
Default: PA15
Alternate: SPI0_NSS, I2S0_WS, USART1_RX(3),
SPI1_NSS(4), EVENTOUT
PB3
26
I/O
5VT
Default: PB3
Alternate: SPI0_SCK, I2S0_CK, EVENTOUT
Default: PB4
PB4
27
I/O
5VT
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
EVENTOUT
Default: PB5
PB5
28
I/O
5VT
Alternate: SPI0_MOSI, I2S0_SD, I2C0_SMBA,
TIMER15_BRKIN, TIMER2_CH1
Additional: WKUP5
Default: PB6
PB6
29
I/O
5VT
PB7
30
I/O
5VT
BOOT0
31
I
Default: BOOT0
VSS
32
P
Default: VSS
Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON
Default: PB7
Alternate:I2C0_SDA, USART0_RX,TIMER16_CH0_ON
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Functions are available on GD32F310K8/6 devices.
13
GD32F310xx Datasheet
(4) Functions are available on GD32F310K8 devices only.
2.6.3
GD32F310KxU6 QFN32 pin definitions
Table 2-5. GD32F310KxU6 QFP32 pin definitions
Pin Name
Pins
VDD
1
Pin
I/O
Type(1)
Level(2)
Functions description
Default: VDD
P
Default: PF0
PF0-OSCIN
2
I/O
5VT
Alternate: CTC_SYNC
Additional: OSCIN
PF1-
3
I/O
NRST
4
I/O
VDDA
5
P
OSCOUT
5VT
Default: PF1
Additional: OSCOUT
Default: NRST
Default: VDDA
Default: PA0
PA0-WKUP
6
I/O
Alternate: USART1_CTS, I2C1_SCL
Additional: ADC_IN0, RTC_TAMP1, WKUP0
Default: PA1
PA1
7
I/O
Alternate: USART1_RTS, I2C1_SDA, EVENTOUT
Additional: ADC_IN1
Default: PA2
PA2
8
I/O
Alternate: USART1_TX, TIMER14_CH0
Additional: ADC_IN2
Default: PA3
PA3
9
I/O
Alternate: USART1_RX, TIMER14_CH1
Additional: ADC_IN3
Default: PA4
PA4
10
I/O
Alternate: SPI0_NSS, I2S0_WS, USART1_CK,
TIMER13_CH0, SPI1_NSS
Additional: ADC_IN4
Default: PA5
PA5
11
I/O
Alternate: SPI0_SCK, I2S0_CK
Additional: ADC_IN5
Default: PA6
PA6
12
I/O
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
TIMER0_BKIN, TIMER15_CH0, EVENTOUT
Additional: ADC_IN6
Default: PA7
Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,
PA7
13
I/O
TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,
EVENTOUT
Additional: ADC_IN7
Default: PB0
PB0
14
I/O
Alternate: TIMER2_CH2, TIMER0_CH1_ON,
USART1_RX, EVENTOUT
Additional: ADC_IN8
14
GD32F310xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PB1
PB1
15
Alternate: TIMER2_CH3, TIMER13_CH0,
I/O
TIMER0_CH2_ON, SPI1_SCK
Additional: ADC_IN9
PB2
16
I/O
VDD
17
P
PA8
18
I/O
5VT
Default: PB2
Default: VDD
Default: PA8
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT,
USART1_TX, EVENTOUT,CTC_SYNC
Default: PA9
PA9
19
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN ,
I2C0_SCL
Default: PA10
PA10
20
I/O
5VT
Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,
I2C0_SDA
Default: PA11
PA11
21
I/O
5VT
Alternate: USART0_CTS, TIMER0_CH3, EVENTOUT,
SPI1_IO2
Default: PA12
PA12
22
I/O
5VT
Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT,
SPI1_IO3
PA13
23
I/O
5VT
PA14
24
I/O
5VT
PA15
25
I/O
5VT
Default: PA13
Alternate: IFRP_OUT, SWDIO, SPI1_MISO
Default: PA14
Alternate: USART1_TX, SWCLK, SPI1_MOSI
Default: PA15
Alternate: SPI0_NSS, I2S0_WS, USART1_RX,
SPI1_NSS, EVENTOUT
PB3
26
I/O
5VT
PB4
27
I/O
5VT
Default: PB3
Alternate: SPI0_SCK, I2S0_CK, EVENTOUT
Default: PB4
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
EVENTOUT
Default: PB5
PB5
28
I/O
5VT
Alternate: SPI0_MOSI, I2S0_SD, I2C0_SMBA,
TIMER15_BKIN, TIMER2_CH1
Additional:WKUP5
PB6
29
I/O
5VT
PB7
30
I/O
5VT
BOOT0
31
I
PB8
32
I/O
Default: PB6
Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON
Default: PB7
Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON
Default: BOOT0
5VT
Default: PB8
Alternate: I2C0_SCL, TIMER15_CH0
Notes:
15
GD32F310xx Datasheet
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
2.6.4
GD32F310GxU6 QFN28 pin definitions
Table 2-6. GD32F310GxU6 QFN28 pin definitions
Pin Name
Pins
BOOT0
1
Pin
I/O
Type(1)
Level(2)
Functions description
Default: BOOT0
I
Default: PF0
PF0-OSCIN
2
I/O
5VT
Alternate: CTC_SYNC
Additional: OSCIN
PF1-
3
I/O
NRST
4
I/O
VDDA
5
P
OSCOUT
5VT
Default: PF1
Additional: OSCOUT
Default: NRST
Default: VDDA
Default: PA0
PA0-WKUP
6
I/O
Alternate: USART1_CTS, I2C1_SCL
Additional: ADC_IN0, RTC_TAMP1, WKUP0
Default: PA1
PA1
7
I/O
Alternate: USART1_RTS, I2C1_SDA, EVENTOUT
Additional: ADC_IN1
Default: PA2
PA2
8
I/O
Alternate: USART1_TX, TIMER14_CH0
Additional: ADC_IN2
Default: PA3
PA3
9
I/O
Alternate: USART1_RX, TIMER14_CH1
Additional: ADC_IN3
Default: PA4
PA4
10
I/O
Alternate: SPI0_NSS, I2S0_WS, USART1_CK,
TIMER13_CH0, SPI1_NSS
Additional: ADC_IN4
Default: PA5
PA5
11
I/O
Alternate: SPI0_SCK, I2S0_CK
Additional: ADC_IN5
Default: PA6
PA6
12
I/O
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
TIMER0_BKIN, TIMER15_CH0, EVENTOUT
Additional: ADC_IN6
Default: PA7
Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,
PA7
13
I/O
TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,
EVENTOUT
Additional: ADC_IN7
Default: PB0
PB0
14
I/O
Alternate: TIMER2_CH2, TIMER0_CH1_ON,
USART1_RX, EVENTOUT
16
GD32F310xx Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Additional: ADC_IN8
Default: PB1
PB1
15
Alternate: TIMER2_CH3, TIMER13_CH0,
I/O
TIMER0_CH2_ON, SPI1_SCK
Additional: ADC_IN9
VSS
16
P
Default: VSS
VDD
17
P
Default: VDD
Default: PA8
PA8
18
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT,
USART1_TX, EVENTOUT,CTC_SYNC
Default: PA9
PA9
19
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN ,
I2C0_SCL
Default: PA10
PA10
20
I/O
5VT
Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,
I2C0_SDA
PA13
21
I/O
5VT
PA14
22
I/O
5VT
Default: PA13
Alternate: IFRP_OUT, SWDIO, SPI1_MISO
Default: PA14
Alternate: USART1_TX, SWCLK, SPI1_MOSI
Default: PA15
PA15
23
I/O
5VT
Alternate: SPI0_NSS, I2S0_WS, USART1_RX,
SPI1_NSS, EVENTOUT
PB3
24
I/O
5VT
Default: PB3
Alternate: SPI0_SCK, I2S0_CK, EVENTOUT
Default: PB4
PB4
25
I/O
5VT
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
EVENTOUT
Default: PB5
PB5
26
I/O
5VT
Alternate: SPI0_MOSI, I2S0_SD, I2C0_SMBA,
TIMER15_BKIN, TIMER2_CH1
Additional:WKUP5
PB6
27
I/O
5VT
PB7
28
I/O
5VT
Default: PB6
Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON
Default: PB7
Alternate: I2C0_SDA, USART0_RX, TIMER16_CH0_ON
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
2.6.5
GD32F310FxP6 TSSOP20 pin definitions
Table 2-7. GD32F310FxP6 TSSOP20 pin definitions
17
GD32F310xx Datasheet
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
BOOT0
1
I
PF0-OSCIN
2
I/O
Functions description
Default: BOOT0
Default: PF0
5VT
Alternate: CTC_SYNC
Additional: OSCIN
PF1-
3
I/O
NRST
4
I/O
VDDA
5
P
OSCOUT
5VT
Default: PF1
Additional: OSCOUT
Default: NRST
Default: VDDA
Default: PA0
PA0-WKUP
6
I/O
Alternate: USART0_CTS(3), USART1_CTS(4),
I2C1_SCL(5)
Additional: ADC_IN0, RTC_TAMP1, WKUP0
Default: PA1
PA1
7
I/O
Alternate: USART0_RTS(3), USART1_RTS(4),
I2C1_SDA(5), EVENTOUT
Additional: ADC_IN1
Default: PA2
PA2
8
I/O
Alternate: USART0_TX(3), USART1_TX(4),
TIMER14_CH0
Additional: ADC_IN2
Default: PA3
PA3
9
I/O
Alternate: USART0_RX(3), USART1_RX(4),
TIMER14_CH1
Additional: ADC_IN3
Default: PA4
PA4
10
I/O
Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3),
USART1_CK(4), TIMER13_CH0, SPI1_NSS(5)
Additional: ADC_IN4
Default: PA5
PA5
11
I/O
Alternate: SPI0_SCK, I2S0_CK
Additional: ADC_IN5
Default: PA6
PA6
12
I/O
Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0,
TIMER0_BKIN, TIMER15_CH0, EVENTOUT
Additional: ADC_IN6
Default: PA7
Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1,
PA7
13
I/O
TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0,
EVENTOUT
Additional: ADC_IN7
Default: PB1
PB1
14
I/O
Alternate: TIMER2_CH3, TIMER13_CH0,
TIMER0_CH2_ON, SPI1_SCK(5)
Additional: ADC_IN9
VSS
15
P
Default: VSS
18
GD32F310xx Datasheet
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
VDD
16
P
PA9
17
I/O
Functions description
Default: VDD
Default: PA9
5VT
Alternate: USART0_TX, TIMER0_CH1, TIMER14_BKIN ,
I2C0_SCL
Default: PA10
PA10
18
I/O
5VT
Alternate: USART0_RX, TIMER0_CH2, TIMER16_BKIN,
I2C0_SDA
PA13
19
I/O
5VT
PA14
20
I/O
5VT
Default: PA13
Alternate: IFRP_OUT, SWDIO, SPI1_MISO(5)
Default: PA14
Alternate: USART0_TX(3), USART1_TX(4), SWCLK,
SPI1_MOSI(5)
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Functions are available on GD32F310F4 devices only.
(4) Functions are available on GD32F310F8/6 devices.
(5) Functions are available on GD32F310F8 devices.
19
GD32F310xx Datasheet
2.6.6
GD32F310xx pin alternate functions
Table 2-8. Port A alternate functions summary
Pin
Name
AF0
PA2
PA3
PA4
PA5
PA6
PA7
PA8
AF2
AF3
USART0_CTS(1)
PA0
PA1
AF1
USART0_RTS(1)
USART0_TX(1)
H0
USART1_TX(2)
AF6
I2C1_SDA(3)
USART1_RTS(2)
TIMER14_C
AF5
I2C1_SCL(3)
USART1_CTS(2)
EVENTOUT
AF4
TIMER14_C USART0_RX(1)
H1
USART1_RX(2)
SPI0_NSS/
USART0_CK(1)
TIMER13_C
SPI1_NSS(
I2S0_WS
USART1_CK(2)
H0
3)
SPI0_SCK/
I2S0_CK
SPI0_MISO/I
2S0_MCK
SPI0_MOSI/
I2S0_SD
TIMER2_CH1
5_CH0
TIMER0_CH0
T
TIMER13_C TIMER1 EVENTOU
_ON
H0
EVENTO USART1_T
6_CH0
T
CTC_SYN
USART0_CK
TIMER0_CH0
USART0_TX
TIMER0_CH1
I2C0_SCL
USART0_RX
TIMER0_CH2
I2C0_SDA
PA11 EVENTOUT
USART0_CTS
TIMER0_CH3
SPI1_IO2(3)
PA12 EVENTOUT
USART0_RTS
TIMER0_ETI
SPI1_IO3(3)
PA9
PA10
CK_OUT
TIMER1 EVENTOU
TIMER2_CH0 TIMER0_BKIN
TIMER14_B
KIN
TIMER16_B
KIN
PA13
SWDIO
PA14
SWCLK
PA15
UT
(2)
X
C
SPI1_MIS
IFRP_OUT
O(3)
USART0_TX(1)
SPI1_MOS
USART1_TX(2)
I(3)
SPI0_NSS/
USART0_RX(1)
EVENTO
SPI1_NSS(
I2S0_WS
USART1_RX(2)
UT
3)
20
GD32F310xx Datasheet
Table 2-9. Port B alternate functions summary
Pin
Nam
AF0
AF1
AF2
AF3
AF4
AF5
AF6
e
PB0
PB1
USART1
EVENTOUT TIMER2_CH2 TIMER0_CH1_ON
TIMER13_CH
0
_RX(2)
SPI1_SCK(
TIMER2_CH3 TIMER0_CH2_ON
3)
PB2
PB3
PB4
PB5
SPI0_SCK /
I2S0_CK
SPI0_MISO /
I2S0_MCK
SPI0_MOSI /
I2S0_SD
EVENTOUT
TIMER2_CH0
EVENTOUT
TIMER2_CH1
TIMER15_BKIN
I2C0_SCL
PB7 USART0_RX
I2C0_SDA
PB8
I2C0_SCL
TIMER15_CH0
I2C0_SDA
TIMER16_CH0
IFRP_OUT
I2C0_SCL
PB10
PB13
PB14
PB15
N
TIMER16_CH0_O
N
EVENTOU
I2S0_M
T
CK
(1)
SPI1_IO2(3)
I2C1_SCL(3)
PB11 EVENTOUT
PB12
A
TIMER15_CH0_O
PB6 USART0_TX
PB9
I2C0_SMB
SPI0_NSS(1)
SPI1_NSS(3)
I2C0_SDA(1),
EVENTOUT
SPI0_SCK(1)
SPI0_MISO(1) TIMER14_CH
0
SPI0_MOSI(1) TIMER14_CH
SPI1_MOSI(3)
I2C1_SM
TIMER0_BKIN
BA(3)
TIMER0_CH0_ON
SPI1_SCK(3)
SPI1_MISO(3)
SPI1_IO3(3)
I2C1_SDA(3)
1
TIMER0_CH1_ON
TIMER0_CH2_ON
TIMER14_
CH0_ON
21
GD32F310xx Datasheet
Table 2-10. Port C alternate functions summary
Pin
Name
AF0
PC0
EVENTOUT
PC1
EVENTOUT
PC2
EVENTOUT
PC3
EVENTOUT
PC4
EVENTOUT
AF1
AF2
AF3
AF4
AF5
AF6
PC5
PC6
TIMER2_CH0
PC7
TIMER2_CH1
PC8
TIMER2_CH2
PC9
TIMER2_CH3
I2S0_MCK
PC10
PC11
PC12
PC13
PC14
PC15
Table 2-11. Port D alternate functions summary
Pin
Name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
PD0
PD1
PD2 TIMER2_ETI
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
22
GD32F310xx Datasheet
Table 2-12. Port F alternate functions summary
Pin
Name
PF0
AF0
AF1
AF2
AF3
AF4
AF5
AF6
CTC_SYNC
PF1
PF2
PF3
PF4
EVENTOUT
PF5
EVENTOUT
PF6
PF7
I2C0_SCL(1)
I2C1_SCL(3)
I2C0_SDA(1)
I2C1_SDA(3)
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
Notes:
(1) Functions are available on GD32F310x4 devices only.
(2) Functions are available on GD32F310x8/6 devices.
(3) Functions are available on GD32F310x8 devices.
23
GD32F310xx Datasheet
3
Functional description
3.1
Arm® Cortex®-M4 core
The Arm® Cortex®-M4 processor is a high performance embedded processor with DSP
instructions which allow efficient signal processing and complex algorithm execution. It brings
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital
signal control markets demand. The processor is highly configurable enabling a wide range
of implementations from those requiring memory protection and powerful trace technology to
cost sensitive devices requiring minimal area, while delivering outstanding computational
performance and an advanced system response to interrupts.
32-bit Arm® Cortex®-M4 processor core:
Up to 72 MHz operation frequency
Single-cycle multiplication and hardware divider
Floating Point Unit (FPU)
Integrated DSP instructions
Integrated Nested Vectored Interrupt Controller (NVIC)
24-bit SysTick timer
The Cortex®-M4 processor is based on the Armv7-M architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex®-M4:
Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)
3.2
Nested Vectored Interrupt Controller (NVIC)
Flash Patch and Breakpoint (FPB)
Data Watchpoint and Trace (DWT)
Instrument Trace Macrocell (ITM)
Serial Wire Debug Port (SW-DP)
Trace Port Interface Unit (TPIU)
On-chip memory
Up to 64 Kbytes of Flash memory
Up to 8 Kbytes of SRAM with hardware parity checking
The Arm® Cortex®-M4 processor is structured in Harvard architecture which can use separate
buses to fetch instructions and load/store data. 64 Kbytes of inner Flash and 8 Kbytes of inner
SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock
speed with zero wait states. Table 2-2. GD32F310xx memory map shows the memory map
of the GD32F310xx series of devices, including code, SRAM, peripheral, and other predefined regions.
24
GD32F310xx Datasheet
3.3
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator
Internal 48 MHz RC oscillator
Internal 28 MHz RC oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include speed internal RC oscillator and external crystal oscillator, high speed and low speed
two types. Several prescalers allow the frequency configuration of the AHB and two APB
domains. The maximum frequency of the AHB, APB2 and APB1 domains is 72 MHz/36
MHz/36 MHz. See Figure 2-7. GD32F310xx clock tree for details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are
always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device
remains in reset mode when VDD is below a specified threshold. The embedded low voltage
detector (LVD) monitors the power supply, compares it to the voltage threshold and generates
an interrupt as a warning message for leading the MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main Flash memory (default)
Boot from system memory
Boot from on-chip SRAM
In default condition, boot from main Flash memory is selected. The boot loader is located in
the internal boot ROM memory (system memory). It is used to reprogram the Flash memory
by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15).
25
GD32F310xx Datasheet
3.5
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power
consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating
modes reduce the power consumption and allow the application to achieve the best balance
between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed
crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and
registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the
system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC
tamper and timestamp, LVD output and USART wakeup. When exiting the deep-sleep
mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except
backup registers) are lost. There are four wakeup sources for the standby mode,
including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the
rising edge on WKUP pin.
3.6
Analog to digital converter (ADC)
12-bit SAR ADC's conversion rate is up to 2.86 MSPS
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Input voltage range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor
One 12-bit 2.86 MSPS multi-channel ADCs are integrated in the device. It has a total of 19
multiplexed channels: 10 external channels, 1 channel for internal temperature sensor
(VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for battery voltage
(VBAT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling
scheme improves performance while off-loading the related computational burden from the
CPU. An analog watchdog block can be used to detect the channels, which are required to
remain within a specific threshold window. A configurable channel management block can be
used to perform conversions in single, continuous, scan or discontinuous mode to support
more advanced use.
The ADC can be triggered from the events generated by the general level 0 timers (TIMER2)
and the advanced timer (TIMER0) with internal connection. The temperature sensor can be
26
GD32F310xx Datasheet
used to generate a voltage that varies linearly with temperature. It is internally connected to
the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital
value.
3.7
DMA
7 channel DMA controller
Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs and I2S
The flexible general-purpose DMA controllers provide a hardware method of transferring data
between peripherals and/or memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Three types of access method are supported:
peripheral to memory, memory to peripheral, memory to memory.
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.8
General-purpose inputs/outputs (GPIOs)
Up to 39 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 39 general purpose I/O pins (GPIO) in GD32F310xx, named PA0 ~ PA15 and
PB0 ~ PB15, PC13 ~ PC15, PF0, PF1, PF6, PF7 to implement logic input/output functions.
Each of the GPIO ports has related control and configuration registers to satisfy the
requirements of specific applications. The external interrupts on the GPIO pins of the device
have related control and configuration registers in the Interrupt/event controller (EXTI). The
GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility
on the package pins. Each of the GPIO pins can be configured by software as output (pushpull, open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate
function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs
are high-current capable except for analog inputs.
3.9
Timers and PWM generation
One 16-bit advanced timer (TIMER0) and five 16-bit general timers (TIMER2, TIMER13
~ TIMER16)
Up to 4 independent channels of PWM, output compare or input capture for each general
timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for
output match
27
GD32F310xx Datasheet
Encoder interface controller with two inputs using quadrature decoder
24-bit SysTick timer down counter
2 watchdog timers (free watchdog timer and window watchdog timer)
The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels.
It has complementary PWM outputs with programmable dead-time generation. It can also be
used as a complete general timer. The 4 independent channels can be used for input capture,
output compare, PWM generation (edge-aligned or center-aligned mode) and single pulse
mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx
timer. It can be synchronized with external signals or to interconnect with other general timers
together which have the same architecture and features.
The general timer can be used for a variety of purposes including general time, input signal
pulse width measurement or output waveform generation such as a single pulse generation
or PWM output, up to 4 independent channels for input capture/output compare. TIMER2 is
based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TIMER13 ~ TIMER16
is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The general timer also
supports an encoder interface with two inputs using quadrature decoder.
The GD32F310xx have two watchdog peripherals, free watchdog and window watchdog.
They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is
clocked from an independent 40 KHz internal RC and as it operates independently of the
main clock, it can operate in deep-sleep and standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free-running timer for application
timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug
mode.
The SysTick timer is dedicated for OS, but could also be used as a standard down counter.
The features are shown below:
3.10
A 24-bit down counter
Auto reload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
Real time clock (RTC)
Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup
registers.
Calendar with subsecond, seconds, minutes, hours, week day, date, year and month
automatically correction
28
GD32F310xx Datasheet
Alarm function with wake up from deep-sleep and standby mode capability
On-the-fly correction for synchronization with master clock. Digital calibration with 0.954
ppm resolution for compensation of quartz crystal inaccuracy.
The real time clock is an independent timer which provides a set of continuously running
counters in backup registers to provide a real calendar function, and provides an alarm
interrupt or an expected interrupt. It is not reset by a system or power reset, or when the
device wakes up from standby mode. In the RTC unit, there are two prescalers used for
implementing the calendar and other functions. One prescaler is a 7-bit asynchronous
prescaler and the other is a 15-bit synchronous prescaler.
3.11
Inter-integrated circuit (I2C)
Up to two I2C bus interfaces can support both master and slave mode with a frequency
up to 1 MHz (Fast mode plus)
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode,
up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also
has an arbitration detect function to prevent the situation where more than one master
attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided
in I2C interface to perform packet error checking for I2C data.
3.12
Serial peripheral interface (SPI)
Up to two SPI interfaces with a frequency of up to 18 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including simplex
synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking.
29
GD32F310xx Datasheet
3.13
Universal synchronous asynchronous receiver transmitter
(USART)
Up to two USARTs with operating frequency up to 4.5 MB/s
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
ISO 7816-3 compliant smart card interface
The USART (USART0, USART1) are used to translate data between parallel and serial
interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous
transfer. It is also commonly used for RS-232 standard communication. The USART includes
a programmable baud rate generator which is capable of dividing the system clock to produce
a dedicated clock for the USART transmitter and receiver. The USART also supports DMA
function for high speed data communication.
3.14
Inter-IC sound (I2S)
One I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with
SPI0
Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio
applications by 3-wire serial lines. GD32F310xx contain an I2S-bus interface that can be
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI0. The
audio sampling frequency from 8 KHz to 192 KHz is supported with less than 0.5% accuracy
error.
3.15
Debug mode
Serial wire debug port (SW-DP)
Debug capabilities can be accessed by a debug tool via serial wire.
3.16
Package and operation temperature
LQFP48 (GD32F310Cx), LQFP32 (GD32F310KxT6), QFN32 (GD32F310KxU6), QFN28
(GD32F310GxU6) and TSSOP20 (GD32F310FxP6)
Operation temperature range: -40°C to +85°C (industrial level)
30
GD32F310xx Datasheet
4
Electrical characteristics
4.1
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Note that the device is not guaranteed to operate properly at the
maximum ratings. Exposure to the absolute maximum rating conditions for extended periods
may affect device reliability.
Table 4-1. Absolute maximum ratings(1)(4)
Symbol
Parameter
Min
Max
Unit
VDD
External voltage range(2)
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
VSS - 0.3
VDD + 3.6
V
Input voltage on other I/O
VSS - 0.3
3.6
V
|ΔVDDx|
Variations between different VDD power pins
—
50
mV
|VSSX −VSS|
Variations between different ground pins
—
50
mV
IIO
Maximum current for GPIO pin
—
±25
mA
TA
Operating temperature range
-40
+85
°C
Power dissipation at TA = 85°C of LQFP48
—
574
Power dissipation at TA = 85°C of LQFP32
—
724
Power dissipation at TA = 85°C of QFN32
—
939
Power dissipation at TA = 85°C of QFN28
—
845
Power dissipation at TA = 85°C of TSSOP20
—
595
TSTG
Storage temperature range
-65
+150
°C
TJ
Maximum junction temperature
—
125
°C
VIN
PD
(1)
(2)
(3)
(4)
4.2
Input voltage on 5V tolerant pin
(3)
mW
Guaranteed by design, not tested in production.
All main power and ground pins should be connected to an external power source within the allowable range.
VIN maximum value cannot exceed 5.5 V.
It is recommended that VDD and VDDA are powered by the same source. The maximum difference between VDD
and VDDA does not exceed 300 mV during power-up and operation.
Operating conditions characteristics
Table 4-2. DC operating conditions
Min(1) Typ Max(1) Unit
Symbol
Parameter
Conditions
VDD
Supply voltage
—
2.6
3.3
3.6
V
VDDA
Analog supply voltage
Same as VDD
2.6
3.3
3.6
V
VBAT
Battery supply voltage
—
1.8
—
3.6
V
(1)
Based on characterization, not tested in production.
31
GD32F310xx Datasheet
Figure 4-1. Recommended power supply decoupling capacitors(1)
VBAT
100 nF
VSS
N * VDD
4.7 μF + N * 100 nF
VSS
VDDA
1 μF
(1)
VSSA
10 nF
All decoupling capacitors need to be as close as possible to the pins on the PCB board.
Table 4-3. Clock frequency(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK1
AHB1 clock frequency
—
0
72
MHz
fHCLK2
AHB2 clock frequency
—
0
72
MHz
fAPB1
APB1 clock frequency
—
0
36
MHz
fAPB2
APB2 clock frequency
—
0
36
MHz
Min
Max
Unit
0
∞
20
∞
(1)
Guaranteed by design, not tested in production.
Table 4-4. Operating conditions at Power up/ Power down(1)
Symbol
tVDD
(1)
Parameter
Conditions
VDD rise time rate
—
VDD fall time rate
μs /V
Guaranteed by design, not tested in production.
Table 4-5. Start-up timings of Operating conditions (1)(2)(3)
Symbol
Parameter
tstart-up
Start-up time
(1)
(2)
(3)
Conditions
Typ
Clock source from HXTAL
33.2
Clock source from IRC8M
31.8
Unit
ms
Based on characterization, not tested in production.
After power-up, the start-up time is the time between the rising edge of NRST high and the main function.
PLL is off.
Table 4-6. Power saving mode wakeup timings characteristics(1)(2)
Symbol
Parameter
Typ
tSleep
Wakeup from Sleep mode
2.8
Wakeup from Deep-sleep mode（LDO On）
3.6
Wakeup from Deep-sleep mode（LDO in low power mode）
3.6
Wakeup from Standby mode
31.6
tDeep-sleep
tStandby
(1)
Unit
μs
ms
Based on characterization, not tested in production.
32
GD32F310xx Datasheet
(2)
4.3
The wakeup time is measured from the wakeup event to the point at which the application code reads the first
instruction under the below conditions: VDD = VDDA = 3.3 V, IRC8M = System clock = 8 MHz.
Power consumption
The power measurements specified in the tables represent that code with data executing from
on-chip Flash with the following specifications.
Table 4-7.Power consumption characteristics(2)(3)(3)(4)(5)
Symbol
Parameter
Conditions
Min Typ(1)
Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 72 MHz, All peripherals
—
14.64
—
mA
—
10.91
—
mA
—
10.29
—
mA
—
7.80
—
mA
—
8.10
—
mA
—
6.23
—
mA
—
5.91
—
mA
—
4.67
—
mA
—
4.45
—
mA
—
3.62
—
mA
—
3.01
—
mA
enabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 72 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 48 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 48 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 36 MHz, All peripherals
enabled
IDD + IDDA
Supply current
(Run mode)
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 36 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 24 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 24 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 16 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 16 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 8 MHz, All peripherals
enabled
33
GD32F310xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1)
Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
System clock = 8 MHz, All peripherals
—
2.51
—
mA
—
1.11
—
mA
—
0.86
—
mA
—
0.7
—
mA
—
0.58
—
mA
—
9.03
—
mA
—
4.77
—
mA
—
6.53
—
mA
—
3.69
—
mA
—
5.27
—
mA
—
3.14
—
mA
—
4.01
—
mA
—
2.60
—
mA
—
3.18
—
mA
disabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System clock = 4 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System clock
= 4 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System clock = 2 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System clock = 2 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 72 MHz, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 72 MHz, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 48 MHz, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 48 MHz, All
peripherals disabled
Supply current
(Sleep mode)
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 36 MHz, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 36 MHz, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 24 MHz, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 24 MHz, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 16 MHz, All
peripherals enabled
34
GD32F310xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1)
Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 16 MHz, All
—
2.23
—
mA
—
2.38
—
mA
—
1.82
—
mA
—
0.77
—
mA
—
0.49
—
mA
—
0.52
—
mA
—
0.38
—
mA
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 8 MHz, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 8 MHz,
CPU clock off, System clock = 8 MHz, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
CPU clock off, System clock = 4 MHz, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
CPU clock off, System clock = 4 MHz, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
CPU clock off, System clock = 2 MHz, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
CPU clock off, System clock =2 MHz, All
peripherals disabled
VDD = VDDA = 3.3 V, LDO in normal power
and normal driver mode, IRC40K off, RTC
— 172.26 330.00
μA
off, All GPIOs analog mode
VDD = VDDA = 3.3 V, LDO in low power and
Supply current
(Deep-sleep
mode)
normal driver mode, IRC40K off, RTC off,
— 120.37 278.11(1) μA
All GPIOs analog mode
VDD = VDDA = 3.3 V, LDO in normal power
and low driver mode, IRC40K off, RTC off,
— 146.29 304.03(1) μA
All GPIOs analog mode
VDD = VDDA = 3.3 V, LDO in low power and
low driver mode, IRC40K off, RTC off, All
—
94.66 252.40(1) μA
—
6.96 13.16(1) μA
—
6.63 12.83(1) μA
—
5.90
12.10
μA
—
3.69
9.89(1)
μA
—
2.32
—
μA
GPIOs analog mode
VDD = VDDA = 3.3 V, LXTAL off, IRC40K on,
RTC on
VDD = VDDA = 3.3 V, LXTAL off, IRC40K on,
Supply current
RTC off
(Standby mode) VDD = VDDA = 3.3 V, LXTAL off, IRC40K off,
RTC off, VDDA Monitor on
VDD = VDDA = 3.3 V, LXTAL off, IRC40K off,
RTC off, VDDA Monitor off
IBAT
Battery supply
current
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
35
GD32F310xx Datasheet
Symbol
Parameter
Conditions
Min Typ(1)
Max
Unit
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL High
—
2.10
—
μA
—
1.85
—
μA
—
1.90
—
μA
—
1.68
—
μA
—
1.44
—
μA
—
1.47
—
μA
—
1.24
—
μA
—
1.01
—
μA
—
1.32
—
μA
—
1.12
—
μA
—
0.88
—
μA
driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL High
driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium High driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL
Medium Low driving
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on, LXTAL Low
driving
(1)
(2)
(3)
(4)
(5)
Based on characterization, not tested in production.
Unless otherwise specified, all values given for TA = 25 ℃ and test result is mean value.
When System Clock is less than 4 MHz, an external source is used, and the HXTAL bypass function is needed,
no PLL.
When System Clock is greater than 8 MHz, a crystal 8 MHz is used, and the HXTAL bypass function is closed,
using PLL.
When analog peripheral blocks such as ADCs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an additional power
consumption should be considered.
36
GD32F310xx Datasheet
Figure 4-2. Typical supply current consumption in Run mode
Figure 4-3. Typical supply current consumption in Sleep mode
Table 4-8. Peripheral current consumption characteristics(1)
Peripherials(3)
AHB1
AHB2
Typical consumption(1)
CRC
0.10
DMA
0.32
GPIOF
0.11
Unit
mA
37
GD32F310xx Datasheet
Peripherials(3)
APB2
APB1
(1)
(2)
(3)
4.4
Typical consumption(1)
GPIOD
0.10
GPIOC
0.13
GPIOB
0.13
GPIOA
0.13
TIMER16
0.24
TIMER15
0.24
TIMER14
0.31
USART0
0.41
TIMER0
0.50
SPI0
0.19
ADC(2)
0.91
PMU
0.31
I2C1
0.17
I2C0
0.17
USART1
0.15
SPI1
0.12
WWDGT
0.11
TIMER13
0.15
TIMER2
0.29
I2S0
0.17
Unit
Based on characterization, not tested in production.
System clock = fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2, ADCON bit is set to 1.
If there is no other description, then HXTAL = 8 MHz, System clock = fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 =
fHCLK.
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in Table 4-9. EMS characteristics(1), based on the EMS levels and classes compliant
with IEC 61000 series standard.
Table 4-9. EMS characteristics(1)
Symbol
VESD
VFTB
(1)
Parameter
Voltage applied to all device pins to
induce a functional disturbance
Conditions
Level/Class
VDD = 3.3 V, TA = 25 °C,
LQFP48, fHCLK = 72 MHz
3A
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VDD = 3.3 V, TA = 25 °C,
induce a functional disturbance through
LQFP48, fHCLK = 72 MHz
100 pF on VDD and VSS pins
conforms to IEC 61000-4-4
3A
Based on characterization, not tested in production.
38
GD32F310xx Datasheet
4.5
Power supply supervisor characteristics
Table 4-10. Power supply supervisor characteristics
Symbol
VLVD(1)
VLVDhyst(2)
VPOR(1)
VPDR(1)
Conditions
Min
Typ
Max
Unit
LVDT[2:0] = 000, rising edge
—
2.15
—
V
LVDT[2:0] = 000, falling edge
—
2.04
—
V
LVDT[2:0] = 001, rising edge
—
2.30
—
V
LVDT[2:0] = 001, falling edge
—
2.20
—
V
LVDT[2:0] = 010, rising edge
—
2.44
—
V
LVDT[2:0] = 010, falling edge
—
2.34
—
V
LVDT[2:0] = 011, rising edge
—
2.57
—
V
Low Voltage Detector
LVDT[2:0] = 011, falling edge
—
2.46
—
V
Threshold
LVDT[2:0] = 100, rising edge
—
2.72
—
V
LVDT[2:0] = 100, falling edge
—
2.61
—
V
LVDT[2:0] = 101, rising edge
—
2.86
—
V
LVDT[2:0] = 101, falling edge
—
2.74
—
V
LVDT[2:0] = 110, rising edge
—
3.00
—
V
LVDT[2:0] = 110, falling edge
—
2.88
—
V
LVDT[2:0] = 111, rising edge
—
3.14
—
V
LVDT[2:0] = 111, falling edge
—
3.03
—
V
—
—
100
—
mV
—
2.38
—
V
—
1.84
—
V
LVD hysteresis
Power on reset
threshold
Power down reset
threshold
—
VPDRhyst(2)
PDR hysteresis
—
600
—
mV
tRSTTEMPO(2)
Reset temporization
—
2
—
ms
(1)
(2)
4.6
Parameter
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Electrical sensitivity
The device is strained in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up
39
GD32F310xx Datasheet
(LU) test is based on the two measurement methods.
Table 4-11. ESD characteristics(1)
Symbol
VESD(HBM)
VESD(CDM)
(1)
Parameter
Conditions
Electrostatic discharge
TA = 25 °C;
voltage (human body model)
JS-001-2017
Electrostatic discharge
TA = 25 °C;
voltage (charge device model)
JS-002-2018
Min
Typ
Max
Unit
—
—
2000
V
—
—
500
V
Min
Typ
Max
Unit
—
—
±200
mA
—
—
5.4
V
Based on characterization, not tested in production.
Table 4-12. Static latch-up characteristics(1)
Symbol
Parameter
Conditions
I-test
LU
TA = 25 °C; JESD78D
Vsupply over voltage
(1)
4.7
Based on characterization, not tested in production.
External clock characteristics
Table 4-13. High speed external clock (HXTAL) generated from a crystal/ceramic
characteristics
Symbol
fHXTAL
RF
(1)
(2)
Parameter
Conditions
Min
Typ Max
Unit
Crystal or ceramic frequency
2.6 V ≤ VDD ≤ 3.6 V
4
8
32
MHz
Feedback resistor
VDD = 3.3 V
—
400
—
kΩ
—
—
20
30
pF
Crystal or ceramic duty cycle
—
30
50
70
%
Oscillator transconductance
Startup
—
25
—
mA/V
—
1.3
—
mA
—
1.8
—
ms
Recommended matching
CHXTAL
(2)(3)
capacitance on OSCIN and
OSCOUT
Ducy(HXTAL)
(2)
gm(2)
IDD(HXTAL)
(1)
Crystal or ceramic operating
current
VDD = 3.3 V, fHCLK =
fIRC8M = 8 MHz
TA = 25 °C
VDD = 3.3 V, fHCLK =
tSUHXTAL(1)
Crystal or ceramic startup time
fIRC8M = 8 MHz
TA = 25 °C
(1)
(2)
(3)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN
and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic
manufacturer. For CS, it is PCB and MCU pin stray capacitance.
Table 4-14. High speed external user clock characteristics (HXTAL in bypass mode)
Symbol
fHXTAL_ext(1)
Parameter
External clock source or oscillator
frequency
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V
1
8
50
MHz
40
GD32F310xx Datasheet
Symbol
Parameter
VHXTALH(2)
OSCIN input pin high level voltage
(2)
OSCIN input pin low level voltage
VHXTALL
tH/L(HXTAL)(2)
tR/F(HXTAL)
(2)
CIN(2)
Ducy(HXTAL)
(1)
(2)
(2)
Conditions
VDD = 3.3 V
Min
Typ
Max
0.7 VDD
—
VDD
VSS
—
0.3 VDD
Unit
V
OSCIN high or low time
—
5
—
—
OSCIN rise or fall time
—
—
—
10
OSCIN input capacitance
—
—
5
—
pF
Duty cycle
—
30
50
70
%
ns
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Table 4-15. Low speed external clock (LXTAL) generated from a crystal/ceramic
characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLXTAL(1)
Crystal or ceramic frequency
—
—
32.768
—
kHz
—
—
15
—
pF
—
30
—
70
%
—
4
—
—
6
—
Recommended matching
CLXTAL
(2)(3)
capacitance on OSC32IN
and OSC32OUT
Ducy(LXTAL)
(2)
Crystal or ceramic duty cycle
Lower driving
capability
Medium low driving
gm(2)
Oscillator transconductance
capability
μA/V
Medium high driving
capability
Higher driving
capability
Lower driving
capability
Medium low driving
IDDLXTAL
(1)
Crystal or ceramic operating
capability
current
Medium high driving
Higher driving
capability
(1)
(2)
(3)
(4)
Crystal or ceramic startup
time
12
—
—
18
—
—
0.6
—
—
0.7
—
μA
capability
tSULXTAL(1)(4)
—
—
—
1.0
—
—
1.3
—
—
1.8
—
s
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN
and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic
manufacturer. For CS, it is PCB and MCU pin stray capacitance.
tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator
stabilization flags is SET. This value varies significantly with the crystal manufacturer.
Table 4-16. Low speed external user clock characteristics (LXTAL in bypass mode)
Symbol
fLXTAL_ext
(1)
Parameter
Conditions
Min
Typ
Max
Unit
External clock source or oscillator
VDD = 3.3 V
—
32.768
1000
kHz
41
GD32F310xx Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
0.7 VDD
—
VDD
—
VSS
—
0.3 VDD
frequency
OSC32IN input pin high level
VLXTALH(2)
VLXTALL
V
OSC32IN input pin low level
(2)
voltage
tH/L(LXTAL) (2)
OSC32IN high or low time
—
450
—
—
tR/F(LXTAL) (2)
OSC32IN rise or fall time
—
—
—
50
CIN(2)
OSC32IN input capacitance
—
—
5
—
pF
Ducy(LXTAL) (2)
Duty cycle
—
30
50
70
%
(1)
(2)
4.8
voltage
ns
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Internal clock characteristics
Table 4-17. High speed internal clock (IRC8M) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = VDDA = 3.3 V
—
8
—
MHz
-2
—
+2
%
VDD = VDDA = 3.3 V, TA = 25 °C
-1.0
—
+1.0
%
—
—
0.5
—
%
VDD = VDDA = 3.3 V
45
50
55
%
VDD = VDDA = 3.3 V
—
66
—
μA
VDD = VDDA = 3.3 V
—
2
—
μs
Min
Typ
Max
Unit
20
40
45
kHz
VDD = VDDA = 3.3 V
—
0.4
—
μA
VDD = VDDA = 3.3 V
—
110
—
μs
High Speed Internal
fIRC8M
Oscillator (IRC8M)
frequency
IRC8M oscillator Frequency
accuracy, Factory-trimmed
ACCIRC8M
VDD = VDDA = 3.3 V,
TA = -40 °C ~ +85 °C(1)
IRC8M oscillator Frequency
accuracy, User trimming
step(1)
DucyIRC8M(2) IRC8M oscillator duty cycle
IDDAIRC8M(1)
tSUIRC8M(1)
(1)
(2)
IRC8M oscillator operating
current
IRC8M oscillator startup
time
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Table 4-18. Low speed internal clock (IRC40K) characteristics
Symbol
fIRC40K(1)
IDDAIRC40K(2)
tSUIRC40K(2)
(1)
(2)
Parameter
Conditions
Low Speed Internal oscillator
VDD = VDDA = 3.3 V,
(IRC40K) frequency
TA = -40 °C ~ +85 °C
IRC40K oscillator operating
current
IRC40K oscillator startup
time
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
42
GD32F310xx Datasheet
Table 4-19. High speed internal clock (IRC28M) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD = VDDA = 3.3 V
—
28
—
MHz
-4
—
+4
%
-1.0
—
+1.0
%
—
—
0.5
—
%
VDD = VDDA = 3.3 V
45
50
55
%
VDD = VDDA = 3.3 V
—
120
—
μA
VDD = VDDA = 3.3 V
—
1.6
—
μs
Conditions
Min
Typ
Max
Unit
VDD = VDDA = 3.3 V
—
48
—
MHz
-4.0
—
+4.0
%
VDD = VDDA = 3.3 V, TA = 25°C
-2.0
—
+2.0
%
—
—
0.12
—
%
VDD = VDDA = 3.3 V
45
50
55
%
VDD = VDDA = 3.3 V
—
260
—
μA
VDD = VDDA = 3.3 V
—
1.5
—
μs
High Speed Internal Oscillator
fIRC28M
(IRC28M) frequency
VDD = VDDA = 3.3 V,
IRC28M oscillator Frequency
TA = -40 °C ~ +85 °C
accuracy, Factory-trimmed
VDD = VDDA = 3.3 V,
ACCIRC28M
TA = 25°C
IRC28M oscillator Frequency
accuracy, User trimming step(1)
DIRC28M(2)
IRC28M oscillator duty cycle
IDDAIRC28M(1)
tSUIRC28M(1)
(1)
(2)
IRC28M oscillator operating
current
IRC28M oscillator startup time
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Table 4-20. High speed internal clock (IRC48M) characteristics
Symbol
Parameter
High Speed Internal
fIRC48M
Oscillator (IRC48M)
frequency
IRC48M oscillator Frequency
accuracy, Factory-trimmed
VDD = VDDA = 3.3 V,
TA = -40 °C ~+85 °C
ACCIRC48M
IRC48M oscillator Frequency
accuracy, User trimming
step(1)
DIRC48M(2) IRC48M oscillator duty cycle
IDDAIRC48M(1)
tSUIRC48M(1)
(1)
(2)
IRC48M oscillator operating
current
IRC48M oscillator startup
time
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
43
GD32F310xx Datasheet
4.9
PLL characteristics
Table 4-21. PLL characteristics
Symbol
fPLLIN
(1)
fPLLOUT
(2)
fVCO(2)
tLOCK(2)
IDDA(1) (3)
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
—
1
—
25
MHz
PLL output clock frequency
—
16
—
72
MHz
—
—
—
72
MHz
—
—
—
300
μs
VCO freq = 72 MHz
—
270
—
μA
—
32.1
—
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDDA
Cycle to cycle Jitter
JitterPLL(4)
（rms）
System clock
Cycle to cycle Jitter
ps
—
（peak to peak）
(1)
(2)
(3)
(4)
4.10
255.6
—
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
System clock = IRC8M = 8 MHz, fPLLOUT = 72 MHz.
Value given with main PLL running.
Memory characteristics
Table 4-22 Flash memory characteristics
Symbol
Parameter
Conditions
Min(1) Typ(1)
Max(2)
Unit
Number of guaranteed
PECYC
program /erase cycles
—
100
—
—
kcycles
before failure (Endurance)
tRET
Data retention time
—
—
20
—
years
wtPROG
Word programming time
TA = -40 °C ~ +85 °C
—
37.5
86
μs
tERASE
Page erase time
TA = -40 °C ~ +85 °C
—
45
300
ms
tMERASE(64KB)
Mass erase time
TA = -40 °C ~ +85 °C
—
0.5
1.6
s
(1)
(2)
4.11
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
NRST pin characteristics
Table 4-23. NRST pin characteristics
Symbol
Parameter
VIL(NRST)(1)
NRST Input low level voltage
(1)
NRST Input high level voltage
VIH(NRST)
Vhyst(2)
Rpu
(2)
Schmidt trigger Voltage hysteresis
Pull-up equivalent resistor
Conditions
2.6 V ≤ VDD = VDDA ≤
3.6 V
—
Min
Typ
Max
Unit
-0.5
—
0.3 VDD
0.7 VDD
—
VDD + 0.5
—
360
—
mV
—
40
—
kΩ
V
44
GD32F310xx Datasheet
(1)
(2)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Figure 4-4. Recommended external NRST pin circuit
VDD
VDD
External reset circuit
RPU
10kΩ
NRST
K
100 nF
GND
4.12
GPIO characteristics
Table 4-24. I/O port DC characteristics(1)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.6 V ≤ VDD = VDDA ≤ 3.6 V
—
—
0.3 VDD
V
2.6 V ≤ VDD = VDDA ≤ 3.6 V
—
—
0.3 VDD
V
2.6 V ≤ VDD = VDDA ≤ 3.6 V
0.7 VDD
—
—
V
2.6 V ≤ VDD = VDDA ≤ 3.6 V
0.7 VDD
—
—
V
Low level output voltage
VDD = 2.6 V
—
—
0.19
for 8 IO Pins
VDD = 3.3 V
—
—
0.17
(each IIO = +8 mA)
VDD = 3.6 V
—
—
0.17
Low level output voltage
VDD = 2.6 V
—
—
0.50
for 8 IO Pins
VDD = 3.3 V
—
—
0.43
(each IIO = +20 mA)
VDD = 3.6 V
—
—
0.42
High level output voltage
VDD = 2.6 V
2.37
—
—
for 8 IO Pins
VDD = 3.3 V
3.10
—
—
(each IIO = +8 mA)
VDD = 3.6 V
3.42
—
—
High level output voltage
VDD = 2.6 V
2.00
—
—
for 8 IO Pins
VDD = 3.3 V
2.78
—
—
Standard IO Low level input
VIL
voltage
5V-tolerant IO Low level
input voltage
Standard IO High level
VIH
input voltage
5V-tolerant IO High level
input voltage
VOL
VOL
VOH
VOH
V
V
V
V
45
GD32F310xx Datasheet
Symbol
RPU(2)
RPD(2)
(1)
(2)
(3)
Parameter
Conditions
Min
Typ
Max
(each IIO = +20 mA)
VDD = 3.6 V
3.11
—
—
Unit
Internal pull-
All pins
VIN = VSS
30
40
50
kΩ
up resistor
PA10
—
7.5
10
13.5
kΩ
Internal pull-
All pins
VIN = VDD
30
40
50
kΩ
down resistor
PA10
—
7.5
10
13.5
kΩ
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
All pins except PC13 / PC14 / PC15. Since PC13 to PC15 are supplied through the Power Switch, which can
only be obtained by a small current, the speed of GPIOs PC13 to PC15 should not exceed 2 MHz when they
are in output mode(maximum load: 30 pF).
Table 4-25. I/O port AC characteristics(1)(2)
GPIOx_OSPD[1:0] bit value(3)
GPIOx_OSPD0->OSPDy[1:0] = X0
（IO_Speed = 2 MHz）
GPIOx_OSPD0->OSPDy[1:0] = 01
（IO_Speed = 10 MHz）
GPIOx_OSPD0->OSPDy[1:0] = 11
（IO_Speed = 50 MHz）
Parameter
TRise/TFall
TRise/TFall
TRise/TFall
GPIOx_OSPD0->OSPDy[1:0] = 11 and
GPIOx_OSPD1->SPDy = 1
TRise/TFall
（IO_Speed mode = MAX）
(1)
(2)
(3)
(4)
Conditions
Max
2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF
26.03
2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF
27.94
2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF
32.71
2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF
4.03
2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF
4.30
2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF
5.41
2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF
2.95
2.6 ≤ VDD ≤ 3.6V, CL = 30 pF
3.38
2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF
3.78
2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF
2.59
2.6 ≤ VDD ≤ 3.6V, CL = 30 pF
3.07
2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF
4.03
Unit
ns
ns
ns
ns
Based on characterization, not tested in production.
Unless otherwise specified, all test results given for TA = 25 ℃.
The I/O speed is configured using the GPIOx_OSPD0->OSPDy [1:0] bits. Refer to the GD32F3x0 user manual
which is selected to set the GPIO port output speed.
The maximum frequency is defined in Figure 4-5. I/O port AC characteristics definition, and maximum
frequency cannot exceed 72 MHz.
Figure 4-5. I/O port AC characteristics definition
90%
EXTERNAL
OUTPU T
ON 50pF
90%
50%
50%
10%
tr(IO)out
10%
tf(IO)out
T
If (tr + tf) ≤ 2/3 T, then maximum frequency is achieved .
The duty cycle is （45%-55%）when loaded by 50 pF
46
GD32F310xx Datasheet
4.13
ADC characteristics
Table 4-26. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
2.6
3.3
3.6
V
VIN(1)
ADC input voltage range
—
0
—
VDDA
V
fADC(1)
ADC clock
—
0.1
—
36
MHz
12-bit
0.007
—
2.57
10-bit
0.008
—
3.00
8-bit
0.01
—
3.60
6-bit
0.011
—
4.50
Analog input voltage
10 external; 3 internal
0
—
VDDA
V
External input impedance
See Equation 1
—
—
171
kΩ
—
—
—
0.2
kΩ
—
—
4
pF
fS(1)
VAIN(1)
(2)
RAIN
RADC(2)
Sampling rate
Input sampling switch
resistance
No pin/pad capacitance
CADC(2)
Input sampling capacitance
tCAL(2)
Calibration time
fADC = 40 MHz
—
3.63
—
μs
Sampling time
fADC = 40 MHz
0.04
—
6.65
μs
12-bit
—
14
—
10-bit
—
12
—
8-bit
—
10
—
6-bit
—
8
—
—
—
—
1
(2)
ts
included
Total conversion
tCONV(2)
time(including sampling
time)
tSU(2)
(1)
(2)
MSPS
Startup time
1/ fADC
μs
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Equation 1 ：RAIN max formula R AIN <
Ts
fADC ∗CADC ∗ln(2N+2 )
− R ADC
The formula above (Equation 1) is used to determine the maximum external impedance allowed for
an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 4-27. ADC RAIN max for fADC = 36 MHz(1)
(1)
Ts(cycles)
ts(μs)
RAINmax (kΩ)
1.5
0.04
0.8
7.5
0.20
5.1
13.5
0.37
9.4
28.5
0.79
20.1
41.5
1.15
29.4
55.5
1.54
39.5
71.5
1.98
50.9
239.5
6.65
171
Based on characterization, not tested in production.
47
GD32F310xx Datasheet
(1)
Table 4-28. ADC dynamic accuracy at f ADC = 14 MHz
(1)
Symbol
Parameter
Test conditions
Min Typ
Max
Unit
ENOB
Effective number of bits
fADC = 14 MHz
—
10.9
—
bits
SNDR
Signal-to-noise and distortion ratio
VDDA = VDD = 3.3 V
—
67.3
—
SNR
Signal-to-noise ratio
Input Frequency = 20 kHz
—
67.6
—
THD
Total harmonic distortion
Temperature = 25℃
—
-79
—
dB
Based on characterization, not tested in production.
Table 4-29. ADC dynamic accuracy at fADC = 28 MHz(1)
Symbol
Parameter
Test conditions
Min
Typ
ENOB
Effective number of bits
fADC = 28 MHz
—
10.8
—
SNDR
Signal-to-noise and distortion ratio
VDDA = VDD = 3.3 V
—
66.7
—
SNR
Signal-to-noise ratio
Input Frequency = 20 kHz
—
67.0
—
THD
Total harmonic distortion
Temperature = 25 ℃
—
-78
—
(1)
Max Unit
bits
dB
Based on characterization, not tested in production.
Table 4-30.ADC dynamic accuracy at fADC = 36 MHz(1)
Symbol
Parameter
Test conditions
Min
Typ
ENOB
Effective number of bits
fADC = 36 MHz
—
10.8
—
SNDR
Signal-to-noise and distortion ratio
VDDA = VDD = 3.3 V
—
66.7
—
SNR
Signal-to-noise ratio
Input Frequency = 20
—
67.0
—
—
-78
—
Typ
Max
±1
—
±1
—
±1.5
—
kHz
THD
(1)
Total harmonic distortion
Temperature = 25℃
Max Unit
bits
dB
Based on characterization, not tested in production.
Table 4-31. ADC static accuracy at fADC = 14 MHz(1)
Symbol
Parameter
Offset
Offset error
(1)
4.14
DNL
Differential linearity error
INL
Integral linearity error
Test conditions
fADC = 14 MHz
VDDA = VDD = 3.3 V
Unit
LSB
Based on characterization, not tested in production.
Temperature sensor characteristics
Table 4-32. Temperature sensor characteristics(1)
Symbol
Parameter
Min
Typ
Max
Unit
TL
VSENSE linearity with temperature
—
±1.5
—
℃
Avg_Slope
Average slope
—
4.3
—
mV/℃
V25
Voltage at 25 °C
—
1.45
—
V
ADC sampling time when reading the temperature
—
17.1
—
μs
tS_temp
(1)
(2)
(2)
Based on characterization, not tested in production.
Shortest sampling time can be determined in the application by multiple iterations.
48
GD32F310xx Datasheet
4.15
I2C characteristics
Table 4-33. I2C characteristics(1)(2)(3)
Symbol
Parameter
time
Standard
mode
Fast mode
Fast mode
plus
Unit
Min
Max
Min
Max
Min
Max
—
4.0
—
0.6
—
0.2
—
μs
tSCL (L)
SCL clock low time
—
4.7
—
1.3
—
0.5
—
μs
tsu(SDA)
SDA setup time
—
2
—
0.8
—
0.1
—
μs
—
250
—
250
—
130
—
ns
—
—
1000
20
300
—
120
ns
—
—
300
—
300
—
120
ns
—
4.0
—
0.6
—
0.26
—
μs
SDA data hold
th(SDA)
time
SDA and SCL rise
tr(SDA/SCL)
time
SDA and SCL fall
tf(SDA/SCL)
time
Start condition
th(STA)
(3)
ons
SCL clock high
tSCL(H)
(1)
(2)
Conditi
hold time
Guaranteed by design, not tested in production.
Test condition: GPIO_SPEED set 2 MHz and external pull-up resistor value is 1 kΩ when operate EEPROM
with I2C.
The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the
falling edge of SCL.
Figure 4-6. I2C bus timing diagram
tsu(STA)
SDA
70%
30%
tf(SDA)
tr(SDA)
tSCL(H)
th(STA)
SCL
tbuff
th(SDA)
tsu(SDA)
70%
30%
tSCL(L)
tr(SCL)
tf(SCL)
tsu(STO)
49
GD32F310xx Datasheet
4.16
SPI characteristics
Table 4-34. Standard SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK(1)
—
—
18
MHz
SCK clock frequency
—
tSCK(H)
(1)
SCK clock high time
Master mode, fPCLKx = 72 MHz
25.78 27.78 29.78
ns
tSCK(L)
(1)
SCK clock low time
Master mode, fPCLKx = 72 MHz
25.78 27.78 29.78
ns
SPI master mode
(2)
Data output valid time
—
—
6.67
—
ns
(2)
Data output hold time
—
—
5.67
—
ns
(1)
Data input setup time
—
1
—
—
ns
(1)
Data input hold time
—
0
—
—
ns
tV(MO)
tH(MO)
tSU(MI)
tH(MI)
SPI slave mode
tSU(NSS)
tH(NSS)
tA(SO)
NSS enable setup time
—
0
—
—
ns
NSS enable hold time
—
1
—
—
ns
Data output access time
—
—
10.8
—
ns
(1)
(2)
Data output disable time
—
—
15.5
—
ns
(2)
Data output valid time
—
—
13.5
—
ns
(2)
Data output hold time
—
—
11.1
—
ns
tSU(SI) (1)
Data input setup time
—
0
—
—
ns
tH(SI) (1)
Data input hold time
—
3
—
—
ns
tDIS(SO)
tV(SO)
tH(SO)
(1)
(2)
(1)
(2)
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Figure 4-7. SPI timing diagram - master mode
tSCK
SCK (CKPH=0 CKPL=0)
SCK (CKPH=0 CKPL=1)
SCK (CKPH=1 CKPL=0)
tSCK(H)
tSCK(L)
SCK (CKPH=1 CKPL=1)
tSU(MI)
MISO
D[0]
LF=1,FF16=0
D[7]
tH(MI)
MOSI
D[0]
D[7]
tV(MO)
tH(MO)
50
GD32F310xx Datasheet
Figure 4-8. SPI timing diagram - slave mode
NSS
tSCK
tSU(NSS)
SCK (CKPH=0 CKPL=0)
tSCK(H)
SCK (CKPH=0 CKPL=1)
tSCK(L)
tH(NSS)
tH(SO)
tDIS(SO)
tV(SO)
tA(SO)
MISO
D[0]
D[7]
tSU(SI)
MOSI
D[0]
D[7]
tH(SI)
51
GD32F310xx Datasheet
4.17
I2S characteristics
Table 4-35. I2S characteristics
Symbol
Parameter
Conditions
Master mode (data: 16 bits,
fCK(1)
Clock frequency
Audio frequency = 96 kHz)
Slave mode
tH(1)
tL
Clock high time
(1)
—
Clock low time
Min
Typ
Max
3.084 3.086 3.088
Unit
MHz
0
—
10
162
—
—
ns
162
—
—
ns
tV(WS)
(2)
WS valid time
Master mode
—
1.88
—
ns
tH(WS)
(2)
WS hold time
Master mode
—
2.5
—
ns
WS setup time
Slave mode
0
—
—
ns
WS hold time
Slave mode
2
—
—
ns
Slave mode
—
50
—
%
tSU(WS)
tH(WS)
(1)
(1)
Ducy(sck) (1)
I2S slave input clock duty
cycle
tSU(SD_MR) (1)
Data input setup time
Master mode
2
—
—
ns
tSU(SD_SR)
(1)
Data input setup time
Slave mode
0
—
—
ns
tH(SD_MR)
(1)
Master receiver
0
—
—
ns
tH(SD_SR)
(1)
Slave receiver
1
—
—
ns
—
13.5
—
ns
—
13.8
—
ns
—
7.55
—
ns
—
8.33
—
ns
Data input hold time
tV (SD_ST) (2)
Data output valid time
tH (SD_ST)(2)
Data output hold time
TV(SD_MT)(2)
Data output valid time
tH(SD_MT)(2)
Data output hold time
(1)
(2)
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
Guaranteed by design, not tested in production
Based on characterization, not tested in production.
52
GD32F310xx Datasheet
Figure 4-9. I2S timing diagram - master mode
tCK
CPOL=0
tL
CPOL=1
tV(WS)
tH
tH(WS)
WS output
tH(SD_MT)
tV(SD_MT)
SD transmit
D[0]
SD receive
D[0]
tSU(SD_MR)
tH(SD_MR)
Figure 4-10. I2S timing diagram - slave mode
tCK
CPOL=0
tL
CPOL=1
tH
tH(WS)
WS input
tSU(WS)
SD transmit
SD receive
tV(SD_ST)
tH(SD_ST)
D[0]
D[0]
tSU(SD_SR)
tH(SD_SR)
53
GD32F310xx Datasheet
4.18
USART characteristics
Table 4-36. USART characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
fPCLKx = 72 MHz
—
—
36
MHz
tSCK(H)
SCK clock high time
fPCLKx = 72 MHz
13.8
—
—
ns
tSCK(L)
SCK clock low time
fPCLKx = 72 MHz
13.8
—
—
ns
(1)
4.19
Guaranteed by design, not tested in production.
TIMER characteristics
Table 4-37. TIMER characteristics(1)
Symbol
Parameter
tres
Timer resolution time
fEXT
Conditions
Min
Max
Unit
—
1
—
tTIMERxCLK
fTIMERxCLK = 72 MHz
13.9
—
ns
Timer external clock
—
0
fTIMERxCLK/2
MHz
frequency
fTIMERxCLK = 72 MHz
0
36
MHz
Timer resolution
—
—
16
bit
16-bit counter clock period
—
1
65536
tTIMERxCLK
fTIMERxCLK = 72 MHz
0.0139
910
μs
—
—
fTIMERxCLK = 72 MHz
—
RES
tCOUNTER
when internal clock is
selected
tMAX_COUNT
(1)
4.20
Maximum possible count
65536 × 65536 tTIMERxCLK
59.6
s
Guaranteed by design, not tested in production.
WDGT characteristics
Table 4-38. FWDGT min/max timeout period at 40 kHz (IRC40K)(1)
Prescaler divider
PSC[2:0] bits
1/4
(1)
Min timeout RLD[11:0] Max timeout RLD[11:0] =
= 0x000
0xFFF
000
0.025
409.525
1/8
001
0.025
819.025
1/16
010
0.025
1638.025
1/32
011
0.025
3276.025
1/64
100
0.025
6552.025
1/128
101
0.025
13104.025
1/256
110 or 111
0.025
26208.025
Unit
ms
Guaranteed by design, not tested in production.
54
GD32F310xx Datasheet
Table 4-39. WWDGT min-max timeout value at 36 MHz (fPCLK1)(1)
PSC[1:0]
1/1
00
113.78
1/2
01
227.56
1/4
10
455.11
1/8
11
910.22
(1)
4.21
Min timeout value
Prescaler divider
CNT[6:0] = 0x40
Unit
Max timeout value
CNT[6:0] = 0x7F
Unit
7.28
μs
14.56
29.13
ms
58.25
Guaranteed by design, not tested in production.
Parameter conditions
Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TA = 25 ℃.
55
GD32F310xx Datasheet
5
Package information
5.1
LQFP48 package outline dimensions
Figure 5-1. LQFP48 package outline
A3
A2 A
θ
c
A1
F
eB
D
D1
36
0.25
25
L
24
37
L1
DETAIL: F
E1 E
b
b1
13
48
c1c
BASE METAL
WITH PLATING
1
12
b
e
SECTION B-B
BB
Table 5-1. LQFP48 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.18
—
0.26
b1
0.17
0.20
0.23
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
8.80
9.00
9.20
D1
6.90
7.00
7.10
E
8.80
9.00
9.20
E1
6.90
7.00
7.10
e
—
0.50
—
eB
8.10
—
8.25
L
0.45
—
0.75
L1
—
1.00
—
56
GD32F310xx Datasheet
Symbol
Min
Typ
Max
θ
0°
—
7°
(Original dimensions are in millimeters)
Figure 5-2. LQFP48 recommended footprint
9.70
37
48
7.30
36
12
25
24
13
5.80
9.70
0.30
1
1.20
0.50
(Original dimensions are in millimeters)
57
GD32F310xx Datasheet
5.2
LQFP32 package outline dimensions
Figure 5-3. LQFP32 package outline
A3
A2 A
c
θ
A1
F
eB
D
D1
L
24
0.25
17
L1
DETAIL: F
16
25
E1
b
E
b1
c1 c
9
32
BASE METAL
8
1
WITH PLATING
B B
b
e
SECTION B-B
Table 5-2. LQFP32 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.33
—
0.41
b1
0.32
0.35
0.38
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
8.80
9.00
9.20
D1
6.90
7.00
7.10
E
8.80
9.00
9.20
E1
6.90
7.00
7.10
e
—
0.80
—
eB
8.10
—
8.25
L
0.45
—
0.75
L1
—
1.00
—
θ
0°
—
7°
58
GD32F310xx Datasheet
(Original dimensions are in millimeters)
Figure 5-4. LQFP32 recommended footprint
9.70
25
32
7.30
24
8
17
9
16
6.05
9.70
0.45
1
1.20
0.80
(Original dimensions are in millimeters)
59
GD32F310xx Datasheet
QFN32 package outline dimensions
Figure 5-5. QFN32 package outline
D
D2
h
32
L
32
1
PIN 1#
Laser Mark
E2
Ne
2
E
2
h
1
b
e
EXPOSED THERMAL
PAD ZONE
Ne
BOTTOM VIEW
A1
A
TOP VIEW
c
5.3
SIDE VIEW
Table 5-3. QFN32 package dimensions
Symbol
Min
Typ
Max
A
0.70
0.75
0.80
A1
0
0.02
0.05
b
0.18
0.25
0.30
c
0.18
0.20
0.25
D
4.90
5.00
5.10
D2
3.40
3.50
3.60
E
4.90
5.00
5.10
E2
3.40
3.50
3.60
e
—
0.50
—
h
0.30
0.35
0.40
L
0.35
0.40
0.45
Ne
—
3.50
—
(Original dimensions are in millimeters)
60
GD32F310xx Datasheet
Figure 5-6. QFN32 recommended footprint
5.70
25
32
4.20
1
3.80
5.70
3.45
0.30
24
3.45
8
16
9
17
0.80
0.50
(Original dimensions are in millimeters)
61
GD32F310xx Datasheet
QFN28 package outline dimensions
Figure 5-7. QFN28 package outline
D2
D
b
28
L
28
1
1
h
PIN 1#
(Laser Mark)
2
E2
Ne
h
E
2
b1
e
Nd
TOP VIEW
EXPOSED THERMAL
PAD ZONE
A
BOTTOM VIEW
A1
c
5.4
SIDE VIEW
Table 5-4. QFN28 package dimensions
Symbol
Min
Typ
Max
A
0.70
0.75
0.80
A1
0
0.02
0.05
b
0.15
0.20
0.25
b1
—
0.14
—
c
0.18
0.20
0.25
D
3.90
4.00
4.10
D2
2.70
2.80
2.90
E
3.90
4.00
4.10
E2
2.70
2.80
2.90
e
—
0.40
—
h
0.30
0.35
0.40
L
0.30
0.35
0.40
Nd
—
2.40
—
Ne
—
2.40
—
(Original dimensions are in millimeters)
62
GD32F310xx Datasheet
Figure 5-8. QFN28 recommended footprint
4.70
28
22
3.20
1
2.65
4.70
2.75
0.25
21
2.75
7
14
8
15
0.75
0.40
(Original dimensions are in millimeters)
63
GD32F310xx Datasheet
5.5
TSSOP20 package outline dimensions
Figure 5-9. TSSOP20 package outline
D
A3
0.25
A2 A
c
A1
θ
L
L1
b
b1
E1
E
c1 c
BASE METAL
WITH PLATING
SECTION B-B
e
b
B
B
Table 5-5. TSSOP20 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.20
A1
0.05
—
0.15
A2
0.80
1.00
1.05
A3
0.39
0.44
0.49
b
0.20
—
0.28
b1
0.19
0.22
0.25
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
6.40
6.50
6.60
E
6.20
6.40
6.60
E1
4.30
4.40
4.50
e
—
0.65
—
L
0.45
0.60
0.75
L1
—
1.00
—
θ
0°
—
8°
(Original dimensions are in millimeters)
64
GD32F310xx Datasheet
Figure 5-10. TSSOP20 recommended footprint
1
1.20
10
5.90
11
20
0.33
0.65
(Original dimensions are in millimeters)
65
GD32F310xx Datasheet
5.6
Thermal characteristics
Thermal resistance is used to characterize the thermal performance of the package device,
which is represented by the Greek letter “θ”. For semiconductor devices, thermal resistance
represents the steady-state temperature rise of the chip junction due to the heat dissipated
on the chip surface.
θJA: Thermal resistance, junction-to-ambient.
θJB: Thermal resistance, junction-to-board.
θJC: Thermal resistance, junction-to-case.
ᴪJB: Thermal characterization parameter, junction-to-board.
ᴪJT: Thermal characterization parameter, junction-to-top center.
θJA =(TJ -TA )/PD
(5-1)
θJB =(TJ -TB )/PD
(5-2)
θJC =(TJ -TC )/PD
(5-3)
Where, TJ = Junction temperature.
TA = Ambient temperature
TB = Board temperature
TC = Case temperature which is monitoring on package surface
PD = Total power dissipation
θJA represents the resistance of the heat flows from the heating junction to ambient air. It is
an indicator of package heat dissipation capability. Lower θJA can be considerate as better
overall thermal performance. θJA is generally used to estimate junction temperature.
θJB is used to measure the heat flow resistance between the chip surface and the PCB board.
θJC represents the thermal resistance between the chip surface and the package top case.
θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat
dissipation methods outside the device package).
Table 5-6. Package thermal characteristics(1)
Symbol
θJA
θJB
Condition
Natural convection, 2S2P PCB
Cold plate, 2S2P PCB
Package
Value
LQFP48
69.64
LQFP32
55.26
QFN32
42.58
QFN28
47.32
TSSOP20
67.24
LQFP48
43.16
LQFP32
26.24
Unit
°C/W
°C/W
66
GD32F310xx Datasheet
Symbol
θJC
ᴪJB
ᴪJT
(1)
Condition
Cold plate, 2S2P PCB
Natural convection, 2S2P PCB
Natural convection, 2S2P PCB
Package
Value
QFN32
12.22
QFN28
12.97
TSSOP20
37.72
LQFP48
25.36
LQFP32
25.23
QFN32
16.76
QFN28
20.26
TSSOP20
25.06
LQFP48
47.75
LQFP32
32.03
QFN32
12.81
QFN28
13.07
TSSOP20
49.07
LQFP48
2.45
LQFP32
2.06
QFN32
0.69
QFN28
0.75
TSSOP20
2.37
Unit
°C/W
°C/W
°C/W
Thermal characteristics are based on simulation, and meet JEDEC specification.
67
GD32F310xx Datasheet
6
Ordering information
Table 6-1. Part ordering code for GD32F310xx devices
Ordering code
Flash (KB)
Package
Package type
GD32F310C8T6
64
LQFP48
Green
GD32F310K8T6
64
LQFP32
Green
GD32F310K6T6
32
LQFP32
Green
GD32F310K8U6
64
QFN32
Green
GD32F310G8U6
64
QFN28
Green
GD32F310F8P6
64
TSSOP20
Green
GD32F310F6P6
32
TSSOP20
Green
GD32F310F4P6
16
TSSOP20
Green
Temperature
operating range
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
68
GD32F310xx Datasheet
7
Revision history
Table 7-1. Revision history
Revision No.
Description
Date
1.0
Initial Release
Dec.4, 2021
Update Arm® Cortex®-M4 core.
Update Debug mode.
Update Table 4-24. I/O port DC characteristics(1)(3) .
Update Table 4-25. I/O port AC characteristics(1)(2) .
Update Table 4-26. ADC characteristics .
Update Table 4-27. ADC RAIN max for fADC = 36
1.1
MHz(1) .
Update Table 4-28. ADC dynamic accuracy at fADC
= 14 MHz(1) .
Update Table 4-29. ADC dynamic accuracy at fADC
= 28 MHz(1) .
Update Table 4-30.ADC dynamic accuracy at fADC
= 36 MHz(1) .
Apr.7, 2022
69
GD32F310xx Datasheet
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