NSD1624-DSPR

NSD1624 High Reliability, Half Bridge Gate Driver Datasheet (EN) 0.4 Product Overview Applications NSD1624 is a high voltage, high side-low side gate driver having capability to deliver 4A source and sink current to drive power MOSFETs or IGBTs.  Half-bridge, full-bridge and LLC converters. The high side section is designed to endure a DC voltage over 1200V with innovative and proven isolation technology. NSD1624 offers best in class propagation delay, low quiescent current, high negative and dv/dt immunity on SW pin.  Solar inverters, Motor controls and EV charges Both high side and low side driver section work from 10V to 20V supply voltages having independent under voltage lockout (UVLO) protection. NSD1624 has two independent input pins (HIN and LIN) which are compatible for TTL and CMOS logic. NSD1624 is available in LGA10, SOP8, and SOP14 package with operating temperature range from  High density switching power supplies for Server, Telecom and Industrial Device Information Part Number NSD1624-DLAJR Package LGA10 Body Size 4.0 mm × 4.0 mm NSD1624-DSPKR SOP14(150mil) 8.6 mm × 3.9 mm NSD1624-DSPR SOP8(150mil) 4.9 mm × 3.9 mm Functional Block Diagram -40°C to 125°C. Key Features  High voltage range: Up to 1200V(SOP14)/700V(SOP8)  Less than 35ns Propagation Delay  Less than 7ns Delay Matching NSD1624 Block Diagram  4 A Source / 6A Sink Currents  High Negative and Transient Immunity up to 150V/ns on SW pin  Gate Drive Supply Voltage from 10V to 17V  TTL and CMOS Compatible Input Logic  UVLO Protection for High-side and Low-side Drivers  Separated Grounds for Logic (SGND) and Driver in SOP14 package  High and Low Voltage Pins Separated for Maximum Creepage and Clearance in SOP14 package Copyright © 2021, NOVOSENSE Page 1 NSD1624 1 INDEX 1. PIN CONFIGURATION AND FUNCTIONS ..................................................................................................................... 3 2. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................. 4 3. RECOMMENDED OPERATING CONDITIONS ............................................................................................................ 5 4. THERMAL INFORMATION .............................................................................................................................................. 5 5. SPECIFICATIONS ............................................................................................................................................................... 5 5.1. 5.2. 5.3. 5.4. 6. ELECTRICAL CHARACTERISTICS ....................................................................................................................................... 5 SWITCHING CHARACTERISTICS......................................................................................................................................... 6 TYPICAL PERFORMANCE CHARACTERISTICS .................................................................................................................... 7 PARAMETER MEASUREMENT INFORMATION ................................................................................................................... 10 GENERAL DESCRIPTION ............................................................................................................................................... 10 6.1. OVERVIEW ...................................................................................................................................................................... 10 6.2. FUNCTIONAL BLOCK DIAGRAM ...................................................................................................................................... 10 6.3. FEATURE DESCRIPTION................................................................................................................................................... 11 6.3.1 Under Voltage Lock Out (UVLO) ............................................................................................................................11 6.3.2 Input Stage ..............................................................................................................................................................11 6.3.3 Input Table ..............................................................................................................................................................11 6.3.4 Output Stage ............................................................................................................................................................11 7. APPLICATION NOTE ....................................................................................................................................................... 12 7.1. 7.2. 7.3. 7.4. TYPICAL APPLICATION CIRCUIT ..................................................................................................................................... 12 ESD STRUCTURE ............................................................................................................................................................ 12 LAYOUT RECOMMENDATIONS......................................................................................................................................... 13 EXAMPLE........................................................................................................................................................................ 13 8. PACKAGE INFORMATION ............................................................................................................................................. 14 9. ORDERING INFORMATION........................................................................................................................................... 16 10. DOCUMENTATION SUPPORT ................................................................................................................................... 16 11. TAPE AND REEL INFORMATION ............................................................................................................................. 17 12. REVISION HISTORY .................................................................................................................................................... 18 Copyright © 2021, NOVOSENSE Page 2 NSD1624 Datasheet (EN) 0.4 1. Pin Configuration and Functions VDD 1 10 BST HI 2 9 HO LI 3 8 SW GND 4 7 NC GND 5 6 LO Figure 1.1 NSD1624 LGA10 Package HI 1 8 BST LI 2 7 HO GND 3 6 SW LO 4 5 VDD Figure 1.2 NSD1624 SOP8 Package HI 1 14 NC LI 2 13 BST SGND 3 12 HO NC 4 11 SW GND 5 10 NC LO 6 9 NC VDD 7 8 NC Figure 1.3 NSD1624 SOP14 Package Copyright © 2021, NOVOSENSE Page 3 NSD1624 Datasheet (EN) 0.4 Table 1.1 NSD1624 Pin Configuration and Description PIN NO. SYMBOL FUNCTION LGA10 SOP14 SOP8 4,5 5 3 GND 2 1 1 HI Logic input for high-side driver. 3 2 2 LI Logic input for low-side driver. 1 7 5 VDD 6 6 4 LO Low-side driver output. 9 12 7 HO High-side driver output. 10 13 8 BST High-side floating supply. 8 11 6 SW High-side supply return. / 3 / SGND 7 4,8,9,10,14 Power Ground, return for low-side driver. Power supply for the input logic part and low-side driver. NC Signal ground, reference for input Not connected 2. Absolute Maximum Ratings Parameters Symbol Min Max Unit Input Supply Voltage VVDD -0.3 24 V High side SW pin voltage VSW -700 700 V High side SW pin voltage VSW -700 700 V High side floating voltage VBST - VSW -0.3 24 V VHO VSW-0.3 VBST+0.3 V VHO, Transient for 100ns VSW-2 VBST+0.3 VLO -0.3 VVDD+0.3 V VLO, Transient for 100ns -2 VVDD+0.3 V VSGND -5 5 V VHI, VLI, VVDD VSGND -0.3 VSGND+20 V Junction Temperature TJ -40 150 ℃ Storage Temperature TJ.ST -40 150 ℃ HBM -2000 2000 V CDM -1000 1000 V High side output voltage Low side output voltage Signal ground to GND1) Input voltage to Signal ground Electrostatic discharge 1) Only for NSD1624 SOP14 Package Copyright © 2021, NOVOSENSE Page 4 NSD1624 Datasheet (EN) 0.4 3. Recommended Operating Conditions Parameters Symbol Min Max Unit Input Supply Voltage Range VVDD 10 17 V High Side Floating Voltage VBST - VSW 10 17 V High Side SW Pin Voltage VSW -700 700 V High Side Output Voltage VHO VSW VBST V Low Side Output Voltage VLO 0 VVDD V Input Signal Voltage Range VHI, VLI VSGND VSGND+17 V Signal ground VSGND -3 3 V Junction Temperature TJ -40 125 ℃ Ambient Temperature Ta -40 125 ℃ Comments 4. Thermal Information Parameters Symbol LGA10 SOP8 SOP14 Unit Junction-to-ambient thermal resistance θJA ℃/W Junction-to-case(top) thermal resistance θJC(top) ℃/W θJB ℃/W Junction-to-board thermal resistance 1) Standard JESD51-3 Low Effective Thermal Conductivity Test Board (1s) in an environment described in JESD51-2a. 2) Standard JESD51-3 Low Effective Thermal Conductivity Test Board (1s) by transient dual interface test method described in JESD51-14. 3) Obtained by Simulating in an environment described in JESD51-2a. 5. Specifications 5.1. Electrical Characteristics At VVDD = VBST = 15 V, VSGND = VSW = 0, all voltages are with respect to GND, no load on LO and HO, –40°C < TJ < 125°C Parameter Symbol Min Typ Max Unit Comments Supply Section VDD quiescent current IVDD_Q 0.4 0.5 mA VLI = VH I= 0 High-side supply quiescent current IBST_Q 0.6 0.7 mA VLI = VHI = 0 VDD operating current IVDD_O 1.1 / mA f = 500 kHz, CLOAD = 0 Copyright © 2021, NOVOSENSE Page 5 NSD1624 Datasheet (EN) 0.4 High-side supply operating current IBST_O SW to GND leakage current ISW_LK 1.3 / mA f = 500 kHz, C LOAD = 0 0.01 uA VSW = 700V INPUT SECTION Input rising threshold VHI_H, VLI_H 1.8 2.1 2.4 V Input falling threshold VHI_L, VLI_L 0.9 1.2 1.5 V Input voltage Hysteresis VHI_HYS, VLI_HYS 0.9 V High Level Logic Input Bias Current IIN+ 17 uA VLI / VHI = 5V Low Level Logic Input Bias Current IIN- 0 uA VLI = VHI = 0V Input pulldown resistance RIN 260 kohm VLI = VHI = 3V 10 UNDER VOLTAGE LOCKOUT turn-on threshold voltage of VDD VDD_UV+ 8.6 9.1 9.5 V turn-off threshold voltage of VDD VDD_UV- 8.2 8.7 9.1 V V CC hysteresis VDD_UVH UVLO positive Threshold on VBST-VSW VBST_UV+ 7.9 8.4 8.9 V UVLO negative Threshold on VBST-VSW VBST_UV- 7.4 7.9 8.3 V VBST hysteresis VBST_UVH 0.5 V Low level output voltage VOL 0.06 V ILO =100 mA High level output voltage VOH 0.12 V ILO =-100 mA, VLOH = VVDD-VLO Low level output Resistance ROL 0.6 Ohm High level output Resistance ROH 1.2 Ohm Peak source current IOSRC 4 A V O=0 V Peak sink current IOSNK 6 A V O=VDD 0.4 V Output SECTION 5.2. Switching Characteristics At VVDD = VBST = 15 V, VSGND = VSW = 0, all voltages are with respect to GND, no load on LO and HO if not mentioned, –40°C < TJ < 125°C Parameter Symbol High Side Startup Time Typ Max Unit Tstartup 10 15 us between VB>UVLO and First HO Pulse Rise Time LO, HO TR 10 ns C load = 1000 pF Fall Time LO, HO TF 9 ns C load = 1000 pF Low-to-high delay matching TLHDM ns Pulse width = 1 us Copyright © 2021, NOVOSENSE Min 7 Comments Page 6 NSD1624 Datasheet (EN) 0.4 High-to-low delay matching THLDM 7 ns Minimum Input Filter TMPW 11 17 ns Turn-on delay, LI to LO TLDLH 22 35 ns Turn-off delay, LI to LO TLDHL 22 35 ns Turn-on delay, HI to HO THDLH 22 35 ns Turn-off delay, HI to HO THDHL 22 35 ns Pulse width = 1 us 5.3. Typical Performance Characteristics 9 9.5 9 8.5 8 VDD ON 7.5 VDD OFF 7 -40 -20 0 BST UVLO Threshold(V) VDD UVLO Threshold(V) 10 8.5 8 7.5 7 BST ON 6.5 BST OFF 6 20 40 60 80 100 120 140 -40 -20 Ambient Temperature (°C) Figure 5.1 VDD UVLO Threshold vs Temperature 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 5.2 BST UVLO Threshold vs Temperature 3 2.5 2 1.5 1 LI ON 0.5 LI OFF 0 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 5.3 Low Input Logic Threshold vs Temperature Copyright © 2021, NOVOSENSE High Input Threshold(V) 3 Low Input Threshold(V) 0 2.5 2 1.5 1 HI ON 0.5 HI OFF 0 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 5.4 High Input Logic Threshold vs Temperature Page 7 500 400 300 200 100 VDD=15V 0 -40 -20 0 BST Quiescent Current(uA) VDD Quiescent Current(uA) NSD1624 800 700 600 500 400 BST=15V 300 20 40 60 80 100 120 140 -40 -20 Ambient Temperature (°C) Figure 5.5 VDD Quiescent Current vs Temperature Figure 5.6 BST Quiescent Current vs Temperature 30 25 20 VDD=10V VDD=12V VDD=15V 15 10 -40 -20 0 Low Side PDLH(ns) Low Side PDHL(ns) 20 40 60 80 100 120 140 Ambient Temperature (°C) 30 25 20 VDD=10V VDD=12V VDD=15V 15 10 20 40 60 80 100 120 140 -40 -20 Ambient Temperature (°C) Figure 5.7 Low Side Turn-off Delay vs Temperature 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 5.8 Low Side Turn-on Delay vs Temperature 35 30 25 VDD=10V VDD=12V VDD=15V 20 15 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 5.9 High Side Turn-off Delay vs Temperature Copyright © 2021, NOVOSENSE High Side PDLH(ns) 35 High Side PDHL(ns) 0 30 25 VDD=10V VDD=12V VDD=15V 20 15 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 5.10 High Side Turn-on Delay vs Temperature Page 8 NSD1624 VDD=10V VDD=12V VDD=15V 8 6 4 2 10 Turn-on DM(ns) Turn-off DM(ns) 10 0 VDD=10V VDD=12V VDD=15V 8 6 4 2 0 -40 -20 0 20 40 60 80 100 120 140 -40 -20 Ambient Temperature (°C) Figure 5.11 Turn-off Delay Match vs Temperature Figure 5.12 Turn-on Delay Match vs Temperature 10 8 6 4 VDD=10V VDD=12V VDD=15V 2 0 -40 -20 0 LO Falling Time(ns) LO Rising Time(ns) 20 40 60 80 100 120 140 Ambient Temperature (°C) 10 8 6 4 VDD=10V VDD=12V VDD=15V 2 0 20 40 60 80 100 120 140 -40 -20 Ambient Temperature (°C) Figure 5.13 LO Rising Time(Co=1000pF) vs Temperature 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 5.14 LO Falling time(Co=1000pF) vs Temperature 10 8 6 4 VDD=10V VDD=12V VDD=15V 2 0 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 5.15 HO Rising Time(Co=1000pF) vs Temperature Copyright © 2021, NOVOSENSE HO Falling Time(ns) 10 HO Rising Time(ns) 0 8 6 4 VDD=10V VDD=12V VDD=15V 2 0 -40 -20 0 20 40 60 80 100 120 140 Ambient Temperature (°C) Figure 5.16 HO Falling time(Co=1000pF) vs Temperature Page 9 NSD1624 Datasheet (EN) 0.4 5.4. Parameter Measurement Information IN=LI/HI L0 VIN_H VIN_L 90% 90% TLDLH TLDHL 10% 90% 10% 10% TF TR TLHDM 90% 90% 90% THLDM H0 10% 10% THDLH 10% TF TR THDHL Figure 5.17 Propagation Delay, Channel to Channel Delay Match, rise and fall time 6. General Description 6.1. Overview NSD1624 is a high reliability low side-high side gate driver with two independent input pins HIN and LIN dedicated to be used in ACDC and DC-AC power applications. Driver inputs are compatible with CMOS and TTL logic hence it provides easy interface with analog and digital controllers. The high side is a floating section that usually require an effective bootstrap circuit to bias. High side Isolated driver has high negative and dv/dt immunity on SW pin that improve the robustness of the driver. NSD1624 has independent under voltage lock out feature for both high and low side gate drivers which ensure the working of both channels at VDD_UV+ and VBST_UV+. In popular power converter topologies such as; half bridge, full bridge converter, LLC, two switch forward converter and phase-shift full bridge, low and high side gate driver provides a function of buffer and level shifter. This driver can drive the top side MOSFET and IGBT whose source and emitter node is a dynamically changing. Therefore, to make them stable referenced to a fixed potential, floatingdriver devices are necessary to use in these topologies. NSD1624 offers best in class propagation delay, less than 7ns delay matching, low quiescent and operating current at high frequencies. Input pins (HI and LI) allow full and independent flexible ON-OFF state of the output. 6.2. Functional Block Diagram VDD BST HI MOD DEMOD UVLO And Logic HO UVLO SW VDD LI DELAY SGND LO GND Figure 6.1 Functional Block Diagram Copyright © 2021, NOVOSENSE Page 10 NSD1624 Datasheet (EN) 0.4 6.3. Feature Description 6.3.1 Under Voltage Lock Out (UVLO) NSD1624 has independent under voltage lock out feature for both high and low side gate drivers which ensure the working of both channels at VDD_UV+ and VBST_UV+. If the VDD is below the VDD_UV+, the output of both high and low side channel will remain low. Similarly, if the VBST is below the VBST_UV+, the output of high side channel will remain low. So the high side bias voltage has no influence on the low side output channel, regardless of the state of the input signal. The VDD and VBST ULVO protection circuits have hysteresis (VVDD_HYS) to prevent ground noise in power supply. Hysteresis also allow small drops in supply power which are usually happen in startup. 6.3.2 Input Stage NSD1624 is a low side-high side gate driver with two independent input pins HIN and LIN. Both the inputs are compatible with CMOS and TTL logic which ensures that the inputs can be driven with analog and digital controllers. The typical value of high input threshold (VIN_H) is 2.1 V whereas the low threshold (VIN_L) 1.2V. The typical value of hysteresis on input pins is 0.9 V which offers higher noise immunity compared to traditional TTL logic implementations. NSD1624 also feature tight control of the input pin threshold voltage levels which ease system design consideration and ensure stable operation across temperature. Both the input pins are internally pulled-down through a resistor of 260K which indicates its logic state in case of floating pin. This feature can be regarded as important because the outputs stay low in case of any input is floating. It is recommended to ground the unused input pin especially in the practical applications. The input logic is explained in the following table. 6.3.3 Input Table INPUTS 6.3.4 OUTPUTS LI HI LO HO L H L H H L H L H H L L L L L L Output Stage NSD1624 is equipped with two independent drivers. The device has ability to provide 4A source and sink current which can effectively charge and discharge a load capacitor of 1nF in 10ns. There is no dead-time built in function in NSD1624, so both outputs can be turnedon at the same time. This feature allows NSD1624 to be used for two-switch converter. Copyright © 2021, NOVOSENSE Page 11 NSD1624 Datasheet (EN) 0.4 7. Application Note 7.1. Typical Application Circuit The circuit shows a typical half-bridge configuration by using the driver NSD1624 which could be used in several popular power converter topologies such as half-bridge/full bridge/LLC isolated topologies applications. VBUS VDD CVDD 1 VDD BST S1 10 CBOOT RHI PWM1 2 HI HO 9 3 LI SW 8 4 GND NC 7 5 GND LO 6 RG CHI RLI PWM2 Controller CLI S2 RG GND COMP GND Figure 7.1 Simplified Half-Bridge Schematic 7.2. ESD Structure Figure.7.2 illustrates the multiple parasitic diodes involved in the ESD protection components of NSD1624 device. VDD BST HI HO LI SW 10V 10V LO SGND GND 10V Figure 7.2 ESD Structure for SOP14 Copyright © 2021, NOVOSENSE Page 12 NSD1624 Datasheet (EN) 0.4 7.3. Layout Recommendations PCB layout is important to get optimal performance. Some of the layout guidelines to be followed are listed below:  High frequency switching current that charges and discharges the gate of external power transistor, that causes EMI and ringing issues. In order to minimize the parasitic inductance and ringing on the gate terminal of the low side MOSFET S2, keep the low side loop ‘LO-S2-GND’ as small as possible. Similarly, keep the path of high side driver ‘HO-S1-SW’ as minimum as possible.  Place a bypass capacitor CVDD as close to VDD pin as possible and minimized the path of ‘VDD-CVDD-GND’. Similarly, follow the same rule for ‘VBST-CBOOT-SW’ loop.  Place a RC input filter with R=2 to 5Ω, & C=100pF close to the driver input pins (HI, LI)  Use of SMD type devices with low-ESR and low-ESL capacitor are highly recommended.  Large amount of copper should be placed at VDD, BST, GND, and SW pins for thermal dissipation. 7.4. Example Copyright © 2021, NOVOSENSE Page 13 NSD1624 Datasheet (EN) 0.4 8. Package information Figure 9.1 LGA10 4X4 Package Shape and Dimension Figure 9.2 SOP8 Package Shape and Dimension Copyright © 2021, NOVOSENSE Page 14 NSD1624 Datasheet (EN) 0.4 Figure 9.3 SOP14 Package Shape and Dimension Copyright © 2021, NOVOSENSE Page 15 NSD1624 Datasheet (EN) 0.4 9. Ordering Information Part No. Temperature Automotive Package Type Package Drawing MSL SPQ NSD1624-DLAR NSD1624-DSPR NSD1624-DSPKR -40 to 125℃ -40 to 125℃ -40 to 125℃ NO NO NO LGA10 SOP8(150mil) SOP14(150mil) LGA10 SOP8 SOP14 TBD TBD TBD TBD TBD TBD 10. Documentation Support Part Number Product Folder Datasheet Technical Documents Isolator selection guide Click here Click here Click here Click here Copyright © 2021, NOVOSENSE Page 16 NSD1624 Datasheet (EN) 0.4 11. Tape and Reel Information Copyright © 2021, NOVOSENSE Page 17 NSD1624 Datasheet (EN) 0.4 Figure 12.1 Tape and Reel Information 12. Revision History Revision 0.4 Description Initial version Copyright © 2021, NOVOSENSE Date 2021/7/09 Page 18