JWH5086A
16V/16A Synchronous
Step-Down Converter
ESCRIPTION
FEATURES
The JWH5086A is a monolithic buck switching
regulator based on I2 architecture for fast transient
response. Operating with an input range of
2.7V~16V, JWH5086A delivers 16A of continuous
output current with two integrated N-Channel
MOSFETs. The internal synchronous power
switches provide high efficiency without the use of
an external Schottky diode. The operation
frequency is set easily to 700 kHz, 800 kHz, or
1000 kHz with the MODE configuration, allowing
the JWH5086A frequency to remain constant
regardless of the input and output voltages.
2.7V to 16V Operating Input Range with
External 3.3V VCC Bias
4V to 16V Operating Input Range with
Internal Bias or External 3.3V VCC Bias
16A output current
Differential Output Voltage Remote Sense
Programmable Accurate Current Limit Level
±0.5% Reference Voltage over 0℃ to +70℃
Junction Temperature Range
FCCM Operation Mode
Power Good Indicator
Programmable Soft-Start Time
Selectable Switching Frequency from
700kHz, 800kHz, and 1000kHz
Output Discharge Function
Non-Latch OCP, UVP, OVP, UVLO
Thermal Protection
Available in QFN3X4-21 Package
JWH5086A guarantees robustness with output
short protection, over-voltage protection, thermal
protection and under voltage protection.
JWH5086A is available in QFN3×4-21 package,
which provides a compact solution with minimal
external components.
APPLICATIONS
Company’s Logo is Protected, “JW” and “JOULWATT” are Registered
Telecom and Networking Systems
Server, Cloud-Computing, Storage
Base Stations
General Purpose Point-of-Load
Trademarks of Joulwatt Technology Co., Ltd.
TYPICAL APPLICATION
CB S T
100nF
VO U T
VIN
4V~16V
L 0 .2 2 u H
V IN
SW
PG
EN
O N /O F F
MODE
CI N
10uFX3
BST
JWH5086A
RP G 10k
C f f (o p t.)
R1 2k
FB
CS
1uF
R2
CO U T
47uFX5
RGND
RM O D E
6 0 .4 k
0 .6 V ~ 5 . 5 V
RC S
6 .9 8 k
VCC
CV C C
1u F
PGND
SS
AGND
CS S
100nF
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ORDER INFORMATION
DEVICE1)
PACKAGE
JWH5086AQFNAG#TR
QFN3X4-21
TOP MARKING2)
JH5086A
YW□□□□□
ENVIRONMENTAL3)
Green
Notes:
JW
# TR
1)
J
2 ) L in e 1 :
T a p e a n d R e e l ( If T R is n o t s h o w n , it m e a n s T u b e )
Package Code
P a rt N o .
YW
Lot num ber
P ro d u ct co d e
L in e 2 :
W eek code
J o u lw a t t L O G O
Year code
3 ) A ll J o u lW a t t p r o d u c t s a r e p a c k a g e d w it h P b - f r e e a n d H a lo g e n - f r e e m a t e r ia ls a n d c o m p lia n t t o R o H S s t a n d a r d s .
PIN CONFIGURATION
TOP VIEW
V IN
SW
21
20
BST
1
AGND
2
18
PGND
CS
3
17
PGND
MODE
4
16
PGND
SS
5
15
PGND
RGND
6
14
PGND
FB
7
13
PGND
EN
8
12
PGND
PG
9
11
PGND
10
19
VCC
V IN
ABSOLUTE MAXIMUM RATING1)
VIN Pin…….......................................................................................................................... -0.3V to 18V
SW Pin.................................................................................... -0.3V (-5V for 25ns) to 18V (25V for 25ns)
VIN-SW.................................................................................-0.3V (-5V for 25ns) to 18.3V (25V for 25ns)
BST-SW ............................................................................................................ -0.3V to 4V (5V for 25ns)
VCC Pin ................................................................................................................................. -0.3V to 4V
All other Pins .......................................................................................................................... -0.3V to 4V
Junction Temperature 2) ..............................................................................................................150ºC
Lead Temperature ..........................................................................................................................260ºC
Storage Temperature………………………………………………………………………...-65 ºC to +150 ºC
ESD Susceptibility (Human Body Model) .........................................................................................±2kV
Charged device model (CDM), per JEDEC specification JESD22- V C101.................................... ±500V
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RECOMMENDED OPERATING CONDITIONS3)
Input Voltage VIN ...................................................................................................................... 4V to 16V
Output Voltage VOUT ............................................................................................................. 0.6V to 5.5V
External VCC Bias VCC_EXT ......................................................................................................Up to 3.6V
Maximum Internal VCC Output Current IVCC_MAX............................................................................150mA
Maximum Output Current IOUT_MAX ..................................................................................................... 16A
Maximum Output Current Limit IOC_MAX .............................................................................................. 20A
Maximum Peak Inductor Current Limit IL_Peak .....................................................................................30A
Operation Junction Temperature Tj.. ................................................................................ -40°C to 125°C
THERMAL PERFORMANCE4)
θJB 5) θJc_TOP 5)
QFN3X4-21............................................................................................................................8....18ºC/W
Note:
1)
3)
4)
Exceeding these ratings may damage the device. These stress ratings do not imply function operation of the device
at any other conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS.
The JWH5086A includes thermal protection that is intended to protect the device in overload conditions. Continuous
operation over the specified absolute maximum operating junction temperature may damage the device.
The device is not guaranteed to function outside of its operating conditions.
Measured on JESD51-7, 4-layer PCB.
5)
θ Thermal resistance from junction to board around PGND pin soldering point.
2)
JB
θ
Jc_TOP
Thermal resistance from junction to top of package.
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ELECTRICAL CHARACTERISTICS
VIN=12V, TJ=-40℃~125℃,Unless otherwise stated.
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
VIN_HTH
VIN rising, VCC=3.3V
2.1
2.4
2.7
V
VIN_LTH
VIN falling, VCC=3.3V
1.55
1.85
2.15
V
Shutdown Current
ISD
VEN =0
0.5
5
μA
Supply Current
IQ
VEN=2V, VFB=0.7V
550
800
μA
Enable Input Rising Threshold
VEN_HTH
1.22
1.27
V
Enable Hysteresis
VEN_TH_HYS
Enable Input Current
IEN
Feedback Voltage
VREF
Feedback Current
IFB
Top Switch Resistance
VIN Under Voltage Lock-out Threshold
1.17
VEN=2V
200
mV
0
μA
TJ=-40℃ to 125℃
594
600
606
mV
TJ= 0℃ to 70℃
597
600
603
mV
10
100
nA
RDS(ON)T
8.9
13.8
mΩ
Bottom Switch Resistance
RDS(ON)B
2.6
4.8
mΩ
Top Switch Leakage Current
ILEAK_TOP
VIN=16V, VSW=0V
10
μA
Bottom Switch Leakage Current
ILEAK_BOT
VIN=16V, VSW=16V
10
μA
Current Limit Threshold
VLIM
ICS to IOUT Ratio
ICS/IOUT
Bottom Switch Negative Current Limit
ILIM_NEG
Minimum On
Time6)
TON_MIN
Minimum Off
Time6)
TOFF_MIN
Switching Frequency
FSW
VFB=0.6V
RCS =6K
1.15
1.2
1.25
V
8
9
11
μA/A
-21
-16
-12
A
50
ns
100
180
ns
MODE=GND
560
660
760
kHz
MODE=30.1K
640
750
860
kHz
MODE=60.4K
860
970
1080
kHz
110
200
Ω
Discharge FET Ron
RDIS
Soft-Start Charge Current
ISS_CHAR
VSS=0V
Soft-Start Pull Down Current
ISS_DISCHAR
VSS=1V
0.4
0.55
0.7
mA
Soft-Start Time6)
TSS
CSS=1nF
0.5
1
1.5
ms
VCC_HTH
VCC rising
2.65
2.8
2.95
V
VCC_LTH
VCC falling
2.35
2.5
2.65
V
3.1
3.2
3.35
V
VCC Under-voltage Lockout Threshold
VCC Regulator
VCC
VCC Load Regulation
42
ICC=100mA
Power Good High Threshold
PG_HTH
Power Good Low Threshold
PG_LTH
μA
0.5
%
VFB from low to high
89.5%
92.5%
95.5%
VREF
VFB from high to low
102%
105%
108%
VREF
VFB from low to high
113%
117%
121%
VREF
VFB from high to low
77%
80%
83%
VREF
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VIN=12V, TJ=-40℃~125℃,Unless otherwise stated.
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
0.7
1.1
1.5
ms
Power Good Delay Time
PG_DLY
VPG from low to high
Power Good Sink Current
IPG
VPG =0.5V
Power Good Leakage Current
ILEAK_PG
VPG=3.3V
3
mA
3.5
5
μA
520
800
mV
620
900
mV
VIN=0V, Pull PG up
VOL_100
to 3.3V through a
100kΩ resistor
Power Good Low-level Output Voltage
VIN=0V, Pull PG up
VOL_10
to 3.3V through a
10kΩ resistor
Output Over-voltage Threshold
VFB Rising
113%
117%
121%
VREF
Output Under-voltage Threshold
VFB Falling
77%
80%
83%
VREF
Output UVP Delay
TDLY_UVP
1.7
μs
UVP/OCP Hiccup OFF Time
THICCUP_OFF
12
ms
Thermal Shutdown6)
TTSD
160
°C
TTSD_HYST
30
°C
TDLY_POWERON
95
μs
Thermal Shutdown
Hysteresis6)
Power On Delay Time
Note:
6)
Guaranteed by design.
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PIN DESCRIPTION
Pin
Name
1
BST
2
AGND
3
CS
4
MODE
5
SS
6
RGND
Description
Connect a 0.1uF capacitor between BST and SW pin to supply current for the top switch
driver.
Analog ground pin. Select AGND as the control circuit reference point.
Current limit. Connect a resistor to AGND to set the current limit trip point.
Frequency selection. Program MODE to select the operating switching frequency.
Soft-start time setting pin. The soft-start time is determined by the capacitance between SS
pin and AGND.
Differential remote sense negative input. Connect this pin directly to the negative side of
the voltage sense point. Short to GND if remote sense is not used.
Feedback (Differential remote sense positive input). An external resistor divider from the
7
FB
output to RGND (tapped to FB) sets the output voltage. It is recommended to place the
resistor divider as close to FB as possible. Vias should be avoided on the FB traces.
8
EN
9
PG
10, 21
VIN
11-18
GND
19
VCC
20
SW
Enable control pin. Pull this pin high to turn on the regulator. Do not leave this pin floating.
Power good monitor output. Open drain output when the output voltage is within 92.5% to
117% of internal reference voltage.
Input voltage pin. VIN supplies power to the IC. Connect a 2.7V to 16V supply to VIN and
bypass VIN to GND with a suitably large capacitor to eliminate noise on the input to the IC.
Power ground pin
Internal 3.2V LDO Output. Power supply for internal analog circuits and driving circuit.
Decouple this pin to ground with a minimum 1uF ceramic capacitor.
SW is the switching node that supplies power to the output. Connect the output LC filter
from SW to the output load.
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BLOCK DIAGRAM
V IN
+
-
PG
+
C u rre n t
S ensor
-
0 .5 5 5 V
0 .7 0 2 V
+
VCC
U V L O /O T P
BST
-
FB
RGND
SS
+
EA
SW
R e fe re n c e
C u r r e n t R ip p le
A d ju s tm e n t
L o g ic
C o n tro l
MODE
S e le c tio n
MODE
V a lle y C u r r e n t
L im it & Z C D
CS
Current
Sensor
+
AGND
V IN
PGND
3 .2 V L D O
VCC
+
1 .2 2 V
-
EN
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TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 1.2V, L = 0.22μH, COUT = 47μF×5, FSW = 700kHz, TA = +25°C, unless otherwise noted.
Steady State Test
Startup through Enable
Shutdown through Enable
VIN=12V, VOUT=1.2V
IOUT=16A
VIN=12V, VOUT=1.2V
IOUT=16A
VIN=12V, VOUT=1.2V
IOUT=16A
EN
2V/div
EN
2V/div
VOUT(AC)
20mV/div
SW
10V/div
IL
20A/div
VOUT
1V/div
VOUT
1V/div
SW
10V/div
SW
10V/div
IL
20A/div
IL
20A/div
4ms/div
2us/div
4ms/div
Steady State Test
Short Circuit Protection
Short Circuit Recovery
VIN=12V, VOUT=1.2V
IOUT=0A
VIN=12V, VOUT=1.2V
IOUT=0A→Short
VIN=12V, VOUT=1.2V
IOUT=Short→0A
VOUT(AC)
20mV/div
VOUT
1V/div
VOUT
1V/div
IL
20A/div
IL
20A/div
SW
10V/div
IL
20A/div
2us/div
10ms/div
10ms/div
Short Circuit Protection
Short Circuit Recovery
Load Transient
VIN=12V, VOUT=1.2V
IOUT=16A→Short
VIN=12V, VOUT=1.2V
IOUT=Short→16A
VIN=12V, VOUT=1.2V
IOUT=1.6A~16A
VOUT
1V/div
VOUT
1V/div
IL
20A/div
IL
20A/div
10ms/div
VOUT(AC)
50mV/div
IL
20A/div
10ms/div
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TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs. Load Current
Efficiency vs. Load Current
(VOUT=1.2V, L=0.22uH, FSW=700kHz)
(VOUT=1.8V, L=0.22uH, FSW=1MHz)
Efficiency vs. Load Current
Frequency vs. Load Current
(VOUT=3.3V, L=0.22uH, FSW=1MHz)
(VIN=12V, VOUT=1.8V, L=0.22μH)
Load Regulation
FB Voltage Regulaion vs. Junction Temperature
(VOUT=1.2V, L=0.22uH, FSW=700kHz)
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FUNCTIONAL DESCRIPTION
JWH5086A is a synchronous step-down
regulator based on I2 control architecture. It
regulates input voltages from 2.7V to 16V down
to as low as 0.6V output voltage, and is capable
of supplying up to 16A of load current.
Power Switch
Frequency Selection
JWH5086A operates in forced continuous
conduction mode (FCCM), and the switching
frequency is fairly constant; hence the output
ripple keeps almost the same throughout the
whole load range.
JWH5086A has three options for switching
frequency selection. Selecting the switching
frequency is done by choosing the resistance
value of the resistor connected between MODE
and AGND (See Table 1).
Table 1 --- Frequency selection
Switching
Frequency7)
GND
700kHz
30.1kΩ(±20%) to GND
800kHz
60.4kΩ(±20%) to GND
1000kHz
Note:
7)
The JWH5086A shuts down when voltage at EN
pin is below 0.3V. The entire regulator is off and
the supply current consumed by the JWH5086A
drops below 5uA.
VIN Under-Voltage Protection
N-Channel MOSFET switches are integrated on
the JWH5086A to down convert the input voltage
to the regulated output voltage. Since the top
MOSFET needs a gate voltage greater than the
input voltage, a boost capacitor connected
between BST and SW pins is required to drive
the gate of the top switch. The boost capacitor is
charged by the internal/external rail when SW is
low.
MODE
Shut-Down Mode
Refer to ELECTRICAL CHARACTERISTICS for
more accurate switching frequency data.
In addition to the enable function, the
JWH5086A provides an Under Voltage Lock-out
(UVLO) function that monitors the input voltage.
To prevent operation without fully-enhanced
internal MOSFET switches, this function inhibits
switching when input voltage drops below the
UVLO-falling threshold. The IC resumes
switching when input voltage exceeds the
UVLO-rising threshold.
Enable
and
Protection
Adjustable
UVLO
The JWH5086A is enabled when the VIN pin
voltage rises above 2.4V and the EN pin voltage
exceeds the enable threshold of 1.22V. The
JWH5086A is disabled when the VIN pin voltage
falls below 1.85V or when the EN pin voltage is
below 1.02V. Do not leave this pin floating.
If an application requires a higher VIN undervoltage lockout (UVLO) threshold, use a
resistive divider connected between VIN and
ground with the central tap connected to EN to
adjust the input voltage UVLO. (Shown in Figure
1). So that when VIN rises to the pre-set value,
VEN rises above 1.22V to enable the device and
when VIN drops below the pre-set value, VEN
drops below 1.02V to trigger input under voltage
lockout protection.
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JWH5086A
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VIN
The JWH5086A has a configured external soft
start time and a constant internal soft start time,
it will follow the slower one between them.
Therefore, the minimum soft start time is about
1ms even a smaller capacitor is used. The soft
start will not be ready until both the internal and
external SS voltage exceeds 0.85V.
V IN
RUVLO_upper
JW H 5086A
EN
RUVLO_lower
GND
Figure. 1 Adjustable UVLO
The input voltage UVLO threshold (VUVLO) and
hysteresis (VUVLO_HYS) can be calculated by the
following equation.
VUVLO
RUVLO_upper RUVLO_lower
VEN_TH
RUVLO_lower
VUVLO_HYS
RUVLO_upper RUVLO_lower
VEN_HYS
RUVLO_lower
where
VEN_TH is enable shutdown threshold (1.22V
typ.);
VEN_HYS is enable shutdown hysteresis (200mV
typ.).
Soft Start
Soft-start is designed in JWH5086A to prevent
the converter output voltage from overshooting
during startup and short-circuit recovery. An
internal current source (ISS) of 42uA is designed
to charge the external soft-start capacitor (CSS)
and generates a soft-start (SS) voltage ramping
up from 0V to 1.5V. When it is less than internal
reference voltage (VREF, typ. 0.6V), SS voltage
overrides VREF and the error amplifier uses SS
voltage as the reference. When SS exceeds
VREF, VREF regains control.
The soft start time (10% to 90%) TSS can be
calculated by the following equation.
TSS ( ms)
CSS ( nF) VREF ( V) 0.8
ISS ( A )
where CSS is the soft-start capacitance
connected between SS pin and AGND pin.
At power up, the soft start pin is discharged
before MOSFETs switching to ensure a proper
power up. Also, during normal operation, the
JWH5086A will stop switching and the soft-start
pin will be discharged, when the VIN UVLO is
exceeded, EN pin pulled below 1.02V, or a
thermal shutdown event occurs.
Current Sense
Protection (OCP)
and
Over-Current
The JWH5086A features an on-die current
sense and a programmable positive current limit
threshold.
The cycle-by-cycle current limit is activated
when the JWH5086A is enabled. The SW valley
current limit is proportional to ICS current, which
is set by a resistor (RCS) from CS to AGND.
The following equation calculates the current
limit threshold setting from RCS:
RCS ( )
VOCP
GCS ILIM
VIN VOUT VOUT
VIN
1
2 L fSW
where
VOCP=1.2V,
GCS = 9 μA/A, and
ILIM = the desired output current limit.
The OCP HICCUP is active 3ms after the
JWH5086A is enabled, Once OCP HICCUP is
active, if the JWH5086A detects over-current
condition for consecutive 31 cycles, or if the FB
drops below under-voltage protection (UVP)
threshold, it enters HICCUP mode. In HICCUP
mode, the JWH5086A latches off the high side
MOSFET immediately, and latches off low side
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JWH5086A
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MOSFET after ZCD is detected. Meanwhile, the
SS capacitor is also discharged. After about
12ms, the JWH5086A will try to soft start
automatically. If the over-current condition still
holds after 3ms of running, the JWH5086A
repeats this operation cycle until the over-current
condition disappears, and the output voltage
rises smoothly back to the regulation level.
Negative Inductor Current limit
When the low side MOSFET detects a -16A
current, the part turns off the low side MOSFET
to limit the negative current.
Pre-Bias Start-Up
The JWH5086A has been designed for a
monotonic start-up into pre-biased loads. If the
output is pre-biased to a certain voltage during
start-up, the IC disables switching for both the
high-side and low-side MOSFETs until the
voltage on the SS capacitor exceeds the sensed
output voltage at FB. Before SS voltage reaches
pre-biased FB level, if the BST voltage (from
BST to SW) is lower than 1.8V, the low-side
MOSFET is turned on to allow the BST voltage
to be charged through VCC. The low-side
MOSFET is turned on for very narrow pulses, so
the drop in pre-biased level is negligible.
Output Voltage Discharge
When the JWH5086A is disabled through EN, it
enables the output voltage discharge mode. This
causes both the high side MOSFET and the low
side MOSFET to latch off. A discharge FET
connected between SW and PGND is turned on
to discharge the output voltage. The typical
switch on resistance of this FET is about 110Ω.
Once the FB voltage drops below 10%* VREF, the
discharge FET is turned off.
Output Over-voltage Protection
The JWH5086A monitors the output voltage by
connecting FB to the tap of the output voltage
feedback resistor divider to detect an
overvoltage condition. This provides autorecovery OVP mode.
If the FB voltage is between 105% and 117% of
REF voltage, the low side MOSFET remains on
until it hits the low-side negative current limit
(NOCP). Once it hits NOCP, the low side
MOSFET is turned off and the high side
MOSFET is turned on until the negative current
reaches to zero. The JWH5086A keeps this
operation to try to bring down the output voltage.
If the FB voltage furtherly exceeds 117% of the
REF voltage, it enters OVP mode. The high side
MOSFET is turned off and the low side MOSFET
remains on until it hits NOCP. Once it hits NOCP,
the power MOSFETs stop switching. The power
MOSFETs would not restart switching until the
FB voltage drops below 105% of REF voltage.
PGOOD goes low until the FB voltage drops
below 105% of REF voltage.
Power Good
The JWH5086A has power-good (PG) output.
The PG pin is the open drain of a MOSFET.
Connect to VCC or another voltage source
through a resistor. After applying the input
voltage, the power MOSFETs start switching,
PG is pulled to GND before SS is ready. After
the FB voltage reaches 92.5% of the REF
voltage and soft start is ready, PG is pulled high
after a 1.1ms delay.
When the FB voltage drops to 80% of the REF
voltage, PG is pulled low within 1.7us deglitch
time. When the FB voltage rises above 92.5% of
the REF voltage, PG is pulled high again after a
1.1ms delay time.
When the FB voltage exceeds 117% of the REF
voltage, PG is pulled low within 1.7us deglitch
time. When the FB voltage drops to 105% of the
REF voltage, PG is pulled high again with 1.1ms
deglitch time.
Once EN UVLO or OTP is triggered, PG is pulled
low within 1.7us deglitch time even FB voltage is
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JWH5086A
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still in threshold range.
If the input supply fails to power the JWH5086A,
PG is clamped low even though PG is tied to an
external DC source through a pull-up resistor.
Thermal Protection
When the temperature of the JWH5086A rises
above 160°C, it is forced into thermal shut-down
and SS capacitor is discharged.
Only when core temperature drops below 130°C
can the regulator become active again.
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APPLICATION INFORMATION
Output Voltage Set
The output voltage is determined by the resistor
divider connected at the FB pin, and the voltage
ratio is:
RL
VFB = VOUT ∗
RH + RL
where VFB is the feedback voltage and VOUT is
the output voltage.
To improve efficiency at very light load, using
larger value resistors is preferred. However,
using too high of resistance causes the circuit to
be more susceptible to noise, and voltage errors
from the VFB input current will be more noticeable.
If RH is determined, such as 2kΩ, and then RL
can be calculated by:
RL =
RH
VOUT
0.6 − 1
the following equation when the input ripple
voltage is determined.
IOUT
VOUT
VOUT
CIN =
∗
∗ (1 −
)
FSW ∗ ∆VIN VIN
VIN
where CIN is the input capacitance value, FSW is
the switching frequency, △VIN is the input ripple
voltage.
The input capacitor can be electrolytic, tantalum
or ceramic. To minimizing the potential noise, a
small X5R or X7R ceramic capacitor, e.g., 0.1μF,
should be placed as close to the IC as possible
when using electrolytic capacitors. 3x10μF/25V
ceramic capacitors are recommended in typical
application.
Output Capacitor
The output capacitor is required to maintain the
DC output voltage, and the capacitance value
determines the output ripple voltage. The output
voltage ripple can be calculated by:
VOUT
VOUT
VOUT
1
∗ (1 −
) ∗ (R ESR +
)
FSW ∗ L
VIN
8 ∗ FSW ∗ COUT
RH
∆VOUT =
RL
where COUT is the output capacitance value and
RESR is the equivalent series resistance value of
the output capacitor.
FB
Input Capacitor
The input capacitor is used to supply the AC
input current to the step-down converter and
maintain the DC input voltage. The capacitors
must have a ripple current rating that exceeds
the converter’s maximum input ripple current.
The RMS ripple current through the input
capacitor can be calculated by:
VOUT
VOUT
ICIN = IOUT ∗ √
∗ (1 −
)
VIN
VIN
where IOUT is the load current, VOUT is the output
voltage, VIN is the input voltage.
Thus, the input capacitor can be calculated by
The output capacitor can be low ESR electrolytic,
tantalum or ceramic, which lower ESR
capacitors get lower output ripple voltage.
The output capacitors also affect the system
stability and transient response, and at least
5x47μF ceramic capacitors are recommended in
typical application.
Inductor
The inductor is used to supply constant current
to the output load, and the value determines the
ripple current which affect the efficiency and the
output voltage ripple. The ripple current is
typically allowed to be 40% of the maximum
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JWH5086A
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switch current limit, thus the inductance value
can be calculated by:
VOUT
VOUT
L=
∗ (1 −
)
FSW ∗ ∆IL
VIN
where VIN is the input voltage, VOUT is the output
voltage, FSW is the switching frequency, and △IL
is the peak-to-peak inductor ripple current.
External Bootstrap Capacitor
The bootstrap capacitor is required to supply
voltage to the top switch driver. A 0.1μF low ESR
ceramic capacitor is recommended to connected
to the BST pin and SW pin.
5.
6.
7.
PCB Layout Note
The PCB layout is critical for best operating
performance, follow the guidelines as below.
1. Place the input decoupling capacitor as
close to device (VIN pin and PGND) as
possible to eliminate noise at the input pin.
The loop area formed by input capacitor and
GND must be minimized.
2. A solid ground inner plane is recommended
to isolate the signal traces from noisy power
traces.
3. AGND Pin (Pin 2) is recommended to be
connected to a solid PGND plane on inner
layer.
4. If a solid PGND plane on inner layer is not
available for PCB design, it is highly
8.
9.
10.
recommended to connect the AGND to the
point of the VOUT capacitor’s ground directly.
Alternatively, connect AGND and PGND at
the point of the VCC capacitor’s ground, and
place output capacitors close to VCC
decoupling capacitor, then make the PGND
connection using an entire copper plane on
top layer.
Place as many PGND vias as possible and
make the ground plane as large as possible
to optimize heat dissipation and parasitic
impedance.
Place the VCC decoupling capacitor as
close as possible to the device.
Place the BST capacitor as close as possible
to the BST and SW pins. 20mil or wider
traces are recommended for the connection.
Place the feedback resistors close to device
to minimize the feedback trace, and put the
feedback trace far away from the inductor
and noisy power traces like SW node. It is
recommended to shield the pair of remote
sensing traces with ground planes above
and below.
Keep the switching node SW short to prevent
excessive capacitive coupling.
Make VIN, VOUT and ground bus
connections as wide as possible to reduce
voltage drop on the input and output paths of
the converter and maximize efficiency.
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JWH5086A
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0603
0603
VOUTSNS+
VOUTSNS0603
Via down to solid PGND
plane on inner layer
0603
0603
PG EN
BST
AGND
CS
MODE
SS
RGND
FB
EN
PG
0603
MODE
4
3
14
15
16
17
PGND
PGND
PGND
PGND
PGND
PGND
0402
5
13
PGND
19
6
12
1
7
11
18
8
2
9
VIN
0402
20
SW
1206
21
VIN
10
VIN
1206
SW
VCC
PGND
L
0603
0603
1206
PGND
VOUT
1206
PCB Layout Recommendation
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TAPE AND REEL INFORMATION
Reel
UNIT: mm
φ
W4
W1
W2
Package
Diameter
Ф
Thickness
W1
Width
W2
W4
QFN3*4-21
330±2
17.6±2
12.4±2
100±2
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JWH5086A
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Carrier Tape
UNIT: mm
P2
P0
B
T
F
E
Φ1
W
B0
Φ2
A
A
B
SECTION B-B
K0
P1
A0
SECTION A-A
Note:
1) The carrier type is black , and colorless transparent .
2) Carrier camber is within 1mm in 100 mm.
3) 10 pocket hole pitch cumulative tolerance:±0.20.
4) All dimensions are in mm .
Package
QFN3*4-21
Tape dimensions (mm)
P0
P2
P1
A0
B0
4.0±0.1
2.0±0.1
8.0±0.1
3.30±0.2
4.30±0.2
W
12±0.3
T
K0
Φ1
Φ2
E
F
0.25±0.1
1.1±0.15
1.5±0.10
1.55±0.1
1.75±0.1
5.50±0.10
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JWH5086A
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PACKAGE OUTLINE
QFN3X4-21
UNIT: mm
SYM BOL
M IL L IM E T E R
M IN
NOM
MAX
A
0 .8 0
0 .8 5
0 .9 0
A1
0 .0 0
0 .0 2
0 .0 5
A2
—
0 .6 5
—
A3
0 .2 0 3 R E F
0 .1 5
0 .2 5
0 .2 0
b1
0 .3 0
0 .3 5
D
2 .9 0
3 .0 0
3 .1 0
E
3 .9 0
4 .0 0
4 .1 0
b
e
0 .4 0 B S C
e1
0 .5 0 B S C
e2
0 .2 5
0 .6 0 B S C
L
0 .4 0
0 .5 0
L1
0 .5 0
0 .6 0
0 .7 0
L2
1 .6 0
1 .7 0
1 .8 0
L3
0 .6 0
0 .1 5 R E F
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPAE
Sprocket Holes
1
2
1
2
1
2
3
4
3
4
3
4
Procket Quadrants
Package Type
Pin1 Quadrant
QFN3X4-21
1
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JWH5086A
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IMPORTANT NOTICE
Joulwatt Technology Co.,Ltd reserves the right to make modifications, enhancements,
improvements, corrections or other changes without further notice to this document and any
product described herein.
Any unauthorized redistribution or copy of this document for any purpose is strictly forbidden.
Joulwatt Technology Co.,Ltd does not warrant or accept any liability whatsoever in respect
of any products purchased through unauthorized sales channel.
JOULWATT TECHNOLOGY CO.,LTD PROVIDES TECHNICAL AND RELIABILITY DATA
(INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS),
APPLICATION OR OTHER DESIGN ADVICE, SAFETY INFORMATION AND OTHER
RESOURCES, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING
WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS.
Copyright © 2022 JoulWatt
All rights are reserved by Joulwatt Technology Co.,Ltd
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