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N-Channel 650V (D-S) Power MOSFET
FEATURES
PRODUCT SUMMARY
650
VDS (V) at TJ max.
RDS(on) max. at 25 °C (Ω)
•
•
•
•
•
0.77
VGS = 10 V
Qg max. (nC)
43
Qgs (nC)
5
22
Qgd (nC)
Configuration
Low figure-of-merit (FOM) Ron x Qg
Low input capacitance (Ciss)
Reduced switching and conduction losses
Ultra low gate charge (Qg)
Avalanche energy rated (UIS)
Available
RoHS
APPLICATIONS
Single
•
•
•
•
Server and telecom power supplies
Switch mode power supplies (SMPS)
Power factor correction power supplies (PFC)
Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
TO-220AB
TO-220 FULLPAK
D
D2PAK
(TO-263)
G
G
D
S
G D S
G D S
S
Top View
N-Channel MOSFET
Top View
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
650
Gate-Source Voltage
VGS
± 30
ID
10
8.0
A
IDM
40
3.2
W/°C
Single Pulse Avalanche Energy b
EAS
mJ
Maximum Power Dissipation
PD
280
167/52
-55 to +150
15
°C
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
Linear Derating Factor
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
TJ, Tstg
TJ = 125 °C
Reverse Diode dV/dt d
Soldering Recommendations (Peak Temperature) c
for 10 s
dV/dt
UNIT
V
W
4.1
V/ns
300
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 4.5 A.
c. 1.6 mm from case.
d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
1
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THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
PARAMETER
RthJA
-
60
Maximum Junction-to-Case (Drain)
RthJC
-
0.8
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
VDS
VGS = 0 V, ID = 250 μA
650
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.75
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2
-
4
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 650 V, VGS = 0 V
-
-
1
VDS = 520 V, VGS = 0 V, TJ = 125 °C
-
-
10
-
0.77
-
Ω
-
S
Gate-Source Leakage
IGSS
Zero Gate Voltage Drain Current
IDSS
Drain-Source On-State Resistance
RDS(on)
VGS = 10 V
ID = 8 A
gfs
VDS = 30 V, ID = 8 A
-
16
Input Capacitance
Ciss
2350
-
Coss
-
70
-
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output Capacitance
-
8
-
Effective Output Capacitance, Energy
Related a
Co(er)
-
63
-
Effective Output Capacitance, Time
Related b
Co(tr)
-
213
-
-
43
-
-
5
-
-
22
25
Forward Transconductance
μA
Dynamic
pF
VDS = 0 V to 520 V, VGS = 0 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
-
13
tr
VDD = 520 V, ID = 8 A,
VGS = 10 V, Rg = 9.1 Ω
-
11
35
-
81
90
-
25
40
f = 1 MHz, open drain
-
3.5
-
-
-
15
Rise Time
Turn-Off Delay Time
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
ID = 8 A, VDS = 520 V
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 8 A, VGS = 0 V
TJ = 25 °C, IF = IS = 8 A,
dI/dt = 100 A/μs, VR = 400 V
S
-
-
40
-
-
1.5
V
-
345
-
ns
-
4.5
-
μC
-
35
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as C oss while VDS is rising from 0 % to 80 % VDSS.
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
40
30
ID = 8 A
TJ = 25 °C
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
50
20
10
2.5
2
1.5
1
VGS = 10 V
0.5
0
- 60 - 40 - 20 0
0
0
10
15
20
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
10 000
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
BOTTOM 6 V
20
30
VDS, Drain-to-Source Voltage (V)
TOP
25
25
TJ = 150 °C
Ciss
Capacitance (pF)
ID, Drain-to-Source Current (A)
30
5
15
10
1000
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
Coss
100
ġ
Crss
10
ġ
5
5V
1
0
0
5
10
15
20
25
30
0
VDS, Drain-to-Source Voltage (V)
400
300
500
600
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
50
24
VGS, Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
200
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
40
30
20
TJ = 25 °C
10
TJ = 150 °C
VDS = 30.8 V
VDS = 520 V
VDS = 325 V
VDS = 130 V
20
16
12
8
4
0
0
0
3
100
5
10
15
20
25
0
20
40
60
80
100
VGS, Gate-to-Source Voltage (V)
Qg, Total Gate Charge (nC)
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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20
ISD, Reverse Drain Current (A)
100
ID, Drain Current (A)
TJ = 150 °C
TJ = 25 °C
10
1
15
10
5
VGS = 0 V
0
0.1
0.2
0.6
0.4
0.8
1
1.2
1.4
25
1.6
VSD, Source-Drain Voltage (V)
100
125
150
TJ, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 9 - Maximum Drain Current vs. Case Temperature
800
1000
Operation in this Area
Limited by RDS(on)
775
IDM = Limited
10
100 μs
Limited by RDS(on)*
1
1 ms
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
BVDSS Limited
10 ms
VDS, Drain-to-Source
Breakdown Voltage (V)
100
ID, Drain Current (A)
75
50
725
700
675
650
625
0.01
600
- 60 - 40 - 20 0
1
10
100
1000
VDS - Drain -to-Source Voltage (V)
* VGS > minimum V GS at which R DS(on) is specified
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 8 - Maximum Safe Operating Area
Normalized Effective Transient
Thermal Impedance
750
Fig. 10 - Temperature vs. Drain-to-Source Voltage
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
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RD
VDS
QG
10 V
VGS
D.U.T.
RG
QGS
+
- VDD
QGD
VG
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 12 - Switching Time Test Circuit
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
90 %
50 kΩ
12 V
0.2 µF
0.3 µF
+
10 %
VGS
D.U.T.
td(on)
td(off) tf
tr
-
VDS
VGS
3 mA
Fig. 13 - Switching Time Waveforms
IG
ID
Current sampling resistors
L
Vary tp to obtain
required IAS
Fig. 17 - Gate Charge Test Circuit
VDS
D.U.T
RG
+
-
IAS
V DD
10 V
0.01 Ω
tp
Fig. 14 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 15 - Unclamped Inductive Waveforms
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Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 18 - For N-Channel
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TO-220AB
MILLIMETERS
A
E
F
D
H(1)
Q
ØP
3
2
L(1)
1
M*
L
b(1)
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.25
4.65
0.167
0.183
b
0.69
1.01
0.027
0.040
b(1)
1.20
1.73
0.047
0.068
c
0.36
0.61
0.014
0.024
D
14.85
15.49
0.585
0.610
E
10.04
10.51
0.395
0.414
e
2.41
2.67
0.095
0.105
e(1)
4.88
5.28
0.192
0.208
F
1.14
1.40
0.045
0.055
H(1)
6.09
6.48
0.240
0.255
J(1)
2.41
2.92
0.095
0.115
L
13.35
14.02
0.526
0.552
L(1)
3.32
3.82
0.131
0.150
ØP
3.54
3.94
0.139
0.155
Q
2.60
3.00
0.102
0.118
ECN: X12-0208-Rev. N, 08-Oct-12
DWG: 5471
Notes
* M = 1.32 mm to 1.62 mm (dimension including protrusion)
Heatsink hole for HVM
C
b
e
J(1)
e(1)
7
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TO-220 FULLPAK (HIGH VOLTAGE)
A
E
A1
ØP
n
d1
d3
D
u
L1
V
L
b3
A2
b2
c
b
e
MILLIMETERS
DIM.
A
A1
A2
b
b2
b3
c
D
d1
d3
E
e
L
L1
n
ØP
u
v
ECN: X09-0126-Rev. B, 26-Oct-09
DWG: 5972
MIN.
4.570
2.570
2.510
0.622
1.229
1.229
0.440
8.650
15.88
12.300
10.360
INCHES
MAX.
4.830
2.830
2.850
0.890
1.400
1.400
0.629
9.800
16.120
12.920
10.630
MIN.
0.180
0.101
0.099
0.024
0.048
0.048
0.017
0.341
0.622
0.484
0.408
13.730
3.500
6.150
3.450
2.500
0.500
0.520
0.122
0.238
0.120
0.094
0.016
2.54 BSC
13.200
3.100
6.050
3.050
2.400
0.400
MAX.
0.190
0.111
0.112
0.035
0.055
0.055
0.025
0.386
0.635
0.509
0.419
0.100 BSC
0.541
0.138
0.242
0.136
0.098
0.020
Notes
1. To be used only for process drawing.
2. These dimensions apply to all TO-220, FULLPAK leadframe versions 3 leads.
3. All critical dimensions should C meet Cpk > 1.33.
4. All dimensions include burrs and plating thickness.
5. No chipping or package damage.
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TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L2
B
A1
L4
Detail “A”
Rotated 90° CW
scale 8:1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
4
E1
Section B - B and C - C
Scale: none
View A - A
INCHES
INCHES
MILLIMETERS
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
9
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