8Gb DDR4 SDRAM Datasheet
CXDQ3BFAM-CJ-A
ChangXin Memory Technologies, Inc.
Preliminary Ver 0.2
Oct. 24, 2021
ChangXin Memory Technologies, Inc. _ Confidential
DISCLAIMER
The information presented in this document is for reference purposes only and may contain
inaccuracies, omissions and errors. The information contained herein is subject to change or
rendered obsolete without notice, including but not limited to product and roadmap changes,
component changes, new model and/or product releases, firmware upgrades, or the like. This
document supersedes and replaces all information supplied prior to the publication hereof. Any
information set forth in this document shall not be replied on if the product described therein is
obtained from any unauthorized distributor or other source not authorized by ChangXin Memory
Technologies, Inc. (hereinafter referred to as “CXMT”).
CXMT assumes no obligation to update, correct or revise this information. CXMT reserves
the right to update, correct or revise this information without notice; in addition, CXMT has no
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Revision History
Revision No.
Date
Description
Ver 0.1
Aug. 2, 2021
Initial release
Ver 0.2
Oct. 22, 2021
Add IDD
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Contents
1. Core Specifications .....................................................................................................................7
1.1
Speed Bins ............................................................................................................................8
1.2
Key Features .........................................................................................................................8
1.3
Ordering Options .................................................................................................................10
1.4
Part Number Decoding ........................................................................................................10
1.5
Address Table......................................................................................................................10
2. DDR4 SDRAM Package Specifications ...................................................................................11
2.1
DDR4 SDRAM Package Dimension ...................................................................................12
2.2
DDR4 SDRAM x16 Ballout Using MO-207 .........................................................................13
2.3
Pinout Description ...............................................................................................................15
3. Absolute Maximum Ratings .....................................................................................................18
3.1
Absolute Maximum DC Ratings ..........................................................................................18
3.2
Recommended DC Operating Conditions ..........................................................................19
3.3
DRAM Component Operating Temperature Range............................................................20
4. AC & DC Input Measurement Levels .......................................................................................21
4.1
AC and DC Logic Input Levels for Single-ended Signals...................................................22
4.2
AC and DC Input Measurement Levels: Vref Tolerances ...................................................23
4.3
AC and DC Logic Input Levels for Differential Signals .......................................................24
4.4
4.5
4.3.1
Differential Signal Definition ........................................................................................24
4.3.2
Differential Swing Requirements for Clock (CK_t - CK_c)..........................................25
4.3.3
Single-ended Requirements for CK Differential Signals .............................................26
4.3.4
Address, Command, and Control Overshoot and Undershoot Specifications ..............28
4.3.5
Clock Overshoot and Undershoot Specifications .......................................................29
4.3.6
Data, Strobe and Mask Overshoot and Undershoot Specifications ...........................30
Slew Rate Definitions for Differential Input Signals ............................................................31
4.4.1
Slew Rate Definitions for Differential Input Signals (CK) ............................................31
4.4.2
Slew Rate Definition for Single-ended Input Signals (CMD/ADD) ..............................33
CK Differential Input Cross Point Voltage ...........................................................................34
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4.6
CMOS Rail to Rail Input Levels for RESET_n....................................................................36
4.7
AC & DC Logic Input Levels for DQS Signals ....................................................................37
4.7.1
Differential Signal Definition ........................................................................................37
4.7.2
Differential Swing Requirements for DQS (DQS_t - DQS_c) .....................................38
4.7.3
Peak Voltage Calculation Method ...............................................................................39
4.7.4
Differential Input Cross Point Voltage .........................................................................40
4.7.5
Differential Input Slew Rate Definition ........................................................................42
5. AC & DC Output Measurement Levels ....................................................................................44
5.1
Output Driver DC Electrical Characteristics .......................................................................45
5.1.1
Alert_n Output Drive Characteristic ............................................................................47
5.1.2
Output Driver Characteristic of Connectivity Test (CT) Mode.....................................48
5.2
Single-ended AC&DC Output Levels ..................................................................................50
5.3
Differential AC & DC Output Levels ....................................................................................50
5.4
Single-ended Output Slew Rate .........................................................................................51
5.5
Differential Output Slew Rate ..............................................................................................52
5.6
Single-ended AC and DC Output Levels of Connectivity Test Mode ..........................55
5.7
Test Load for Connectivity Test Mode Timing .....................................................................56
6. Speed Bin....................................................................................................................................57
6.1
DDR4-3200 Speed Bins and Operations ............................................................................57
6.2
tREFI and tRFC Parameters ...............................................................................................60
7. IDD and IDDQ Specification Parameters and Test Condition .........................................61
7.1
IDD, IPP and IDDQ Measurement Conditions....................................................................62
7.1.1
IDD0, IDD0A and IPP0 Measurement-Loop Pattern...................................................74
7.1.2
IDD1, IDD1A and IPP1 Measurement-Loop Pattern...................................................76
7.1.3
IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N, IDD3NA
and IDD3P Measurement-Loop Pattren ......................................................................78
7.1.4
IDD2NT and IDDQ2NT Measurement-Loop Pattern ..................................................80
7.1.5
IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern1 .....................82
7.1.6
IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern .................84
7.1.7
IDD4WC Measurement-Loop Pattern .........................................................................86
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7.2
7.1.8
IDD5B Measurement-Loop Pattern.............................................................................88
7.1.9
IDD7 Measurement-Loop Pattern................................................................................89
IDD Specifications ...............................................................................................................91
8. Input/Output Capacitance .........................................................................................................94
9. Electrical Characteristics & AC Timing ...................................................................................98
9.1
Reference Load for AC Timing and Output Slew Rate.......................................................99
9.2
tREFI..................................................................................................................................100
9.3
Clock Specification ............................................................................................................100
9.4
9.3.1
Definition for tCK(abs) ...............................................................................................100
9.3.2
Definition for tCK(avg) ...............................................................................................100
9.3.3
Definition for tCH(avg) and tCL(avg) .........................................................................101
9.3.4
Definition for tERR(nper) ...........................................................................................101
Timing Parameters by Speed Grade.................................................................................102
9.4.1
Timing Parameters by Speed Bin for DDR4-1600 to 2400 .......................................102
9.4.2
Timing Parameters by Speed Bin for DDR4-2666 to 3200.......................................110
9.5
Rounding Algorithms .........................................................................................................124
9.6
The DQ Input Receiver Compliance Mask for Voltage and Timing ....................125
9.7
Command, Control, and Address Setup, Hold, and Derating ...........................................131
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8Gb x16 DDR4 SDRAM Datasheet
1. Core Specifications
This chapter is an index to help you quickly know the key features of DDR4 component and
available product options.
•
Speed Bins on Page 8
•
Key Features on Page 8
•
Ordering Options on Page 10
•
Part Number Decoding on Page 10
•
Address Table on Page 10
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8Gb x16 DDR4 SDRAM Datasheet
1.1
Speed Bins
DDR4-3200
Speed
22-22-22
0.625
22
13.75
13.75
32
45.75
tCK (min)
CAS Latency
tRCD (min)
tRP (min)
tRAS (min)
tRC (min)
1.2
Key Features
•
Power supply : VDD = VDDQ = 1.2V (1.14V to 1.26V); VPP = 2.5V (2.375V to 2.75V)
•
JEDEC standard package: x16 96-ball FBGA
•
Array Configuration : 8 banks (x16) 2 groups of 4 banks
•
8n-bit prefetch architecture
•
Burst Length (BL) : 8 and 4 with Burst Chop (BC)
•
Programmable CAS Latency (CL)
•
Programmable CAS Write Latency (CWL)
•
Internal generated Vref for data inputs
•
On-Die Termination (ODT) : support Nominal, Park and Dynamic ODT
•
Differential clock and data strobe inputs (CK_t ,CK_c; DQS_t, DQS_c)
•
Interface: 1.2V Pseudo Open Drain (POD) IO
•
Per DRAM Addressability (PDA)
•
Data Bus Inversion (DBI)
•
Data Mask (DM) for write data
•
Maximum Power Saving Mode (MPSM)
•
LP ASR(Low Power Auto Self Refresh) mode is supported
•
Asynchronous reset for power up
•
Precharge: auto precharge option for each burst access
•
Operating case temperature : 0°C ≤ TCase ≤ 95°C
•
Support auto-refresh and self-refresh mode
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Unit
ns
nCK
ns
ns
ns
ns
8Gb x16 DDR4 SDRAM Datasheet
•
Average Refresh Period: 7.8 μs at 0°C ≤ TCase ≤ 85°C; 3.9 μs at 85°C < TCase ≤ 95°C
•
Fine granularity refresh 2x, 4x mode for smaller tRFC
•
Programmable data strobe preambles
•
Command Address (CA) Parity is supported
•
Write Cyclic Redundancy Code (CRC) is supported
•
hPPR and sPPR are supported
•
Connectivity test mode (TEN) is supported
•
Gear Down Mode
•
Output driver calibration through ZQ pin (RZQ: 240ohm ± 1%)
•
JEDEC JESD-79-4 compliant
•
RoHS compliant
Note:
The functionality described and the timing specifications included in this datasheet are for the DLL Enabled mode of
operation (normal operation), unless specifically stated otherwise.
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8Gb x16 DDR4 SDRAM Datasheet
1.3
Ordering Options
Table 1-1 Device Ordering Information
Part Number
CXDQ3BFAM-CJ-A
1.4
Organization
512M x 16
Data Rate
3200 Mbps
Part Number Decoding
CX
D
3
Q
B
F
A
M
C
J
A
Company
CX: ChangXin Memory
Die Version
A: A-die
Product Family
D: DRAM
Speed
J: 3200 Mbps 22-22-22
Product Type
Q: DDR4
Operating Temp.
C: Commercial (00C~950C)
Density
3: 8Gb
Package Material
M: Lead Free & Halogen Free
(RoHS compliant)
Package Type
B: 96-ball FBGA SDP
Voltage
A: 1.2V
Bit Organization
F: x16
1.5
Address Table
Table 1-2 8Gb Addressing Table
Parameter
512 M x16
Number of Bank Groups
2
Number of Banks per Bank Group
4
Bank Group Address
BG0
Bank Address per Bank Group
BA0~BA1
Row Address
A0~A15
Column Address
A0~A9
Page Size
2KB
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8Gb x16 DDR4 SDRAM Datasheet
2. DDR4 SDRAM Package Specifications
This chapter will mainly introduce the package dimension and ballout in x8 and x16 configurations
which may help to match your device.
•
DDR4 SDRAM Package Dimension on Page 12
•
DDR4 SDRAM x16 Ballout Using MO-207 on Page 13
•
Pinout Description on Page 15
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8Gb x16 DDR4 SDRAM Datasheet
DDR4 SDRAM Package Dimension
±
Ø
Ø
Ø
Unit: mm
0.1
±0.1
±
±0.1
0.1
Figure 2-1
A
±
±
0.1 A
±
2.1
96-Ball FBGA - x16 Component
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8Gb x16 DDR4 SDRAM Datasheet
2.2
DDR4 SDRAM x16 Ballout Using MO-207
1
2
3
VDDQ
VSSQ
DQU0
DQSU_c
VSSQ
VDDQ
VPP
VSS
VDD
DQSU_t
DQU1
VDD
VDDQ
DQU4
DQU2
DQU3
VDD
VSSQ
DQU6
DQU7
VSSQ
VDDQ
VSS
DMU_n VSSQ
DBIU_n
DML_n
VSSQ
VSS
DBIL_n
VDDQ DQSL_c
DQL1
VDDQ
ZQ
DQL0 DQSL_t
VDD
VSS
VDDQ
4
5
6
7
8
9
A
A
B
B
C
C
DQU5
VSSQ
D
D
E
E
F
F
VSSQ
G
G
VDDQ
H
H
DQL4
DQL2
DQL3
DQL5
VSSQ
VDD
VDDQ
DQL6
DQL7
VDDQ
VDD
VSS
CKE
ODT
CK_t
CK_c
VSS
VDD
WE_n/
ACT_n
CS_n
RAS_n
VDD
VSSQ
J
J
K
K
L
L
A14
A16
M
M
VREFCA
BG0
A10/AP
A12/
CAS_n
BC_n
A15
VSS
N
N
VSS
BA0
A4
A3
BA1
TEN
RESET_n
A6
A0
A1
A5
VDD
A8
A2
A9
A7
VPP
PAR
NC
A13
VDD
P
P
ALERT_n
R
R
T
T
VSS
Figure 2-2
A11
DDR4 Ball Assignments for the x16 Component
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8Gb x16 DDR4 SDRAM Datasheet
Note:
1
These pins are not connected for the x4 configuration.
2
TDQS_t is not valid for the x4 configuration.
3
TDQS_c is not valid for the x4 configuration.
4
A17 is only defined for the x4 configuration.
5
These pins are for stacked component such as 3DS. For mono package, these pins are NC.
6
ODT1 / CKE1 /CS1_n are used together only for DDP.
7
TEN is optional for 8Gb and above. This pin is not connected if TEN is not supported.
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8Gb x16 DDR4 SDRAM Datasheet
2.3
Pinout Description
Symbol
Type
CK_t, CK_c
Input
Clock: CK_t and CK_c are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CK_t and
negative edge of CK_c
CKE
Input
Clock Enable: CKE High activates, and CKE Low deactivates, internal clock
signals and device input buffers and output drivers. Taking CKE Low provides
Precharge Power- Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the
power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout
Read and Write accesses. Input buffers, excluding CK_t,CK_c, ODT and CKE
are disabled during power-down. Input buffers, excluding CKE, are disabled
during Self- Refresh
CS_n
Input
Chip Select: All commands are masked when CS_n is registered High. CS_
n provides for external Rank selection on systems with multiple Ranks. CS_n
is considered part of the command code
ODT
Input
On Die Termination: ODT (registered High) enables RTT_NOM termination
resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied
to each DQ, DQS_t, DQS_c and DM_n/DBI_n/TDQS_t, NU/TDQS_c (When
TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ, DQSU_t, DQSU_c,
DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be ignored if
MR1 is programmed to disable RTT_NOM
ACT_n
Input
Activation Command Input: ACT_n defines the Activation command being
entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/
A14 will be considered as Row Address A16, A15 and A14
Input
Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n)
define the command being entered. Those pins have multi function. For example, for activation with ACT_n Low, those are Addressing like A16,A15 and
A14 but for non-activation command with ACT_n High, those are command
pins for Read, Write and other commands defined in Command Truth Table
RAS_n/A16
CAS_n/A15
WE_n/A14
DM_n/DBI_n,
TDQS_t,
(DMU_n/ DBIU_n),
(DML_n/ DBIL_n)
Function
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for
Write data. Input data is masked when DM_n is sampled Low coincident with
that input data during a Write access. DM_n is sampled on both edges of
DQS. DM is muxed with DBI function by Mode Register A10, A11, A12 setting
Input/Output in MR5. For x8 device, the function of DM or TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifying whether to store/
output the true or inverted data. If DBI_n is Low, the data will be stored/output
after inversion inside the DDR4 SDRAM and not inverted if DBI_n is High.
TDQS is only supported in X8
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8Gb x16 DDR4 SDRAM Datasheet
Symbol
Type
Function
BG0 - BG1
Input
Bank Group Inputs: BG0 - BG1 define to which bank group an Active, Read,
Write or Precharge command is being applied. BG0 also determines which
mode register is to be accessed during a MRS cycle. x4/x8 have BG0 and
BG1, but x16 has only BG0
BA0 - BA1
Input
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write
or Precharge command is being applied. Bank address also determines
which mode register is to be accessed during a MRS cycle.
Input
Address Inputs: Provide the row address for ACTIVATE commands and
the column address for Read/Write commands to select one location out of
the memory array in the respective bank. (A10/AP, A12/BC_n, RAS_n/A16,
CAS_n/A15 and WE_n/A14 have additional functions, see coresponding entries in this table. The address inputs also provide the op-code during Mode
Register Set commands.
Input
Auto-precharge: A10 is sampled during Read/Write commands to determine
whether Autoprecharge should be performed to the accessed bank after the
Read/Write operation. (High: Autoprecharge; Low: no Autoprecharge). A10 is
sampled during a Precharge command to determine whether the Precharge
applies to one bank (A10 Low) or all banks (A10 High). If only one bank is to
be precharged, the bank is selected by bank addresses.
Input
Burst Chop: A12/BC_n is sampled during Read and Write commands to
determine if burst chop (on-the-fly) will be performed. (High, no burst chop;
Low: burst chopped). See “Command Truth Table” of Operation Guide for
details.
Input
Active Low Asynchronous Reset: Reset is active when RESET_n is Low, and
inactive when RESET_n is High. RESET_n must be High during normal operation. RESET_n is a CMOS rail to rail signal with DC high and low at 80%
and 20% of VDD
A0 - A16
A10/AP
A12/BC_n
RESET_n
DQ
Data Input/ Output: Bi-directional data bus. If CRC is enabled via mode
register then CRC code is added at the end of Data Burst. Any DQ from
Input /Output DQ0~DQ3 may indicate the internal Vref level during test via Mode Register
Setting MR4 A4=High. During this mode, RTT value should be set to Hi-Z.
Refer to vendor specific data sheets to determine which DQ is used.
DQS_t, DQS_c,
DQSU_t, DQSU_c,
DQSL_t, DQSL_c
Data Strobe: output with Read data, input with Write data. Edge-aligned with
Read data, centered-aligned with Write data. For the x16, DQSL corresponds
to the data on DQL0-DQL7;DQSU corresponds to the data on DQU0-DQU7.
Input /Output The data strobe DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to provide differential pair
signaling to the system during Reads and Writes. DDR4 SDRAM supports
differential data strobe only and does not support single-ended.
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8Gb x16 DDR4 SDRAM Datasheet
Symbol
TDQS_t, TDQS_c
PAR
ALERT_n
TEN
Type
Output
Input
Function
Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only.
When enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the
same termination resistance function on TDQS_t/TDQS_c that is applied to
DQS_t/DQS_c. When disabled via mode register A11 = 0 in MR1, DM/DBI/
TDQS will provide the data mask function or Data Bus Inversion depending
on MR5; A11, A12, A10 and TDQS_c is not used. x4/ x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
Command and Address Parity Input: DDR4 Supports Even Parity Check in
DRAMs with MR setting.
Once it is enabled via Register in MR5, then DRAM calculates Parity with
ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,BG0-BG1,BA0-BA1,A17-A0.Input
parity should maintain at the rising edge of the clock and at the same time
with command & address with CS_n Low
ALERT: It has multi functions such as CRC error flag, Command and Address Parity error flag as output signal. If there is error in CRC, then Alert_n
goes Low for the period time interval and goes back High. If there is error in
Command Address Parity Check, then ALERT_n goes Low for relatively long
Input/Output
period until on going DRAM internal recovery transaction to complete. During
Connectivity Test mode, this pin works as an input. Using this signal or not is
dependent on system. In case of not connected as Signal, ALERT_n pin must
be bounded to VDD on board.
Input
NC
Connectivity Test Mode Enable: Required on X16 devices and optional input
on x4/x8 with densities equal to or greater than 8Gb.High in this pin will enable Connectivity Test Mode operation along with other pins. It is a CMOS rail
to rail signal with AC high and low at 80% and 20% of VDD. Using this signal
or not is dependent on system. This pin may be DRAM internally pulled Low
through a weak pull-down resistor to VSS.
No Connect: No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply: 1.2 V +/- 0.06 V
VSSQ
Supply
DQ Ground
VDD
VSS
VPP
VREFCA
ZQ
Supply
Supply
Supply
Supply
Supply
Power Supply: 1.2 V +/- 0.06 V
Ground
DRAM Activating Power Supply: 2.5V (2.375V min, 2.75V max)
Reference voltage for CA
Reference Pin for ZQ calibration
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8Gb x16 DDR4 SDRAM Datasheet
3. Absolute Maximum Ratings
3.1
Absolute Maximum DC Ratings
Symbol
Parameter
Min
Max
Unit
Note
VDD
Voltage on VDD pin relative to Vss
-0.3
1.5
V
1,3
VDDQ
Voltage on VDDQ pin relative to Vss
-0.3
1.5
V
1,3
VPP
Voltage on VPP pin relative to Vss
Voltage on any pin except VrefCA relative to Vss
Storage Temperature
-0.3
3.0
V
4
-0.3
1.5
V
1,3,5
-55
100
°C
1,2
VIN, VOUT
TSTG
Note:
1
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2
Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
3
VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than
0.6*VDDQ, When VDD and VDDQ are less than 500 mV; VREF may be equal to or less than 300 mV.
4
VPP must be equal or greater than VDD/VDDQ at all times.
5
Overshoot area above 1.5V is specified in Section 4.3.5 and Section 4.3.6.
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8Gb x16 DDR4 SDRAM Datasheet
3.2
Recommended DC Operating Conditions
Table 3-1 Recommended DC Operating Conditions
Symbol
Parameter
VDD
VDDQ
VPP
Supply voltage
Supply voltage for output
Wordline supply voltage
Min
1.14
1.14
2.375
Rating
Typ.
1.2
1.2
2.5
Max
1.26
1.26
2.75
Note:
1
Under all conditions VDDQ must be less than or equal to VDD.
2
VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3
DC bandwidth is limited to 20MHz.
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Unit
Note
V
V
V
1,2,3
1,2,3
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8Gb x16 DDR4 SDRAM Datasheet
3.3
DRAM Component Operating Temperature Range
Table 3-2 Operating Temperature Range
Symbol
TOPER
Parameter
Rating
Unit
Note
Normal Temperature Range
0 ~ 85
o
C
1,2
Extended Temperature Range
85 ~ 95
o
C
1,3
Note:
1
Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For
measurement conditions, please refer to the JEDEC document JESD51-2.
2
The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating
conditions.
3
Some applications require operation of the DRAM in the Extended Temperature Range between 85 oC and 95
oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions
apply:
• Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 μs.
It is also possible to specify a component with 1X refresh (tREFI to 7.8μs) in the Extended Temperature
Range. Please refer to the DIMM SPD for option availability.
• If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0 and MR2 A7 = 1)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1 and MR2 A7 = 1).
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4. AC & DC Input Measurement Levels
This chapter mainly defines voltage tolerance limits and AC&DC logic input levels for input signals
to ensure the normal operation of DDR4 SDRAM.
•
AC and DC Logic Input Levels for Single-ended Signals on Page 22
•
AC and DC Input Measurement Levels: Vref Tolerances on Page 23
•
AC and DC Logic Input Levels for CK Differential Signals on Page 24
•
Slew Rate Definitions for CK Differential Input Signals on Page 31
•
CK Differential Input Cross Point Voltage on Page 34
•
CMOS rail to rail Input Levels on Page 36
•
AC&DC Logic input levels for DQS Signals on Page 37
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4.1
AC and DC Logic Input Levels for Single-ended Signals
Table 4-1 Single-ended AC and DC Input Levels for Command and Address
Symbol
Parameter
VIH.CA(DC75)
DDR4-3200
Unit
Note
Min
Max
DC input logic high
-
-
V
VIL.CA(DC75)
DC input logic low
-
-
V
VIH.CA(DC65)
DC input logic high
VREFCA + 0.065
VDD
V
VIL.CA(DC65)
DC input logic low
VSS
VREFCA - 0.065
V
VIH.CA(AC100)
AC input logic high
-
-
V
1
VIL.CA(AC100)
AC input logic low
-
-
V
1
VIH.CA(AC90)
AC input logic high
VREF + 0.09
Note 2
V
1
VIL.CA(AC90)
AC input logic low
Note 2
VREF - 0.09
V
1
VREFCA(DC)
Reference voltage for
ADD, CMD inputs
0.49*VDD
0.51*VDD
V
2,3
Note:
1
See “Overshoot and Undershoot Specifications”
2
The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1%
VDD (for reference :approx. ± 12mV)
3
For reference : approx. VDD/2 ± 12 mV
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4.2
AC and DC Input Measurement Levels: Vref Tolerances
The DC-tolerance limits and AC-noise limits for the reference voltages VrefCA is illustrated in
Figure 4-1 below. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for
VrefCA).
Vref(DC) is the linear average of Vref(t) over a very long period of time (for example, 1 second).
This average has to meet the min/max requirement in Table 4-1. Furthermore Vref(t) may
temporarily deviate from Vref(DC) by no more than ± 1% VDD.
Voltage
VDD
VRef(t)
Vref AC-noise
Vref(DC)max
Vref(DC)
VDD/2
Vref(DC)min
VSS
Time
Figure 4-1
Illustration of Vref(DC) Tolerance and Vref AC-noise Limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and
VIL(DC) are dependent on Vref.
“Vref” should be understood as Vref(DC).
This clarifies that DC-variations of Vref affect the absolute voltage a signal has to reach to
achieve a valid high or low level, and therefore the time to which setup and hold is measured.
System timing and voltage budgets need to account for Vref(DC) deviations from the optimum
position within the data-eye of the input signals.
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This also clarifies that the DRAM setup/hold specification and derating values need to include
time and voltage associated with Vref AC-noise. Timing and voltage effects due to AC-noise on
Vref up to the specified limit ( ± 1% of VDD) are included in DRAM timings and their associated
deratings.
4.3
AC and DC Logic Input Levels for Differential Signals
4.3.1
Differential Signal Definition
tDVAC
Differential Input Voltage(CK_t, CK_c)
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
half cycle
0.0
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
Time
Figure 4-2
Definition of Differential AC-Swing and “Time above AC-Level” tDVAC
Note:
1
Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.
2
Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.
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4.3.2
Differential Swing Requirements for Clock (CK_t - CK_c)
Table 4-2 Differential Input Levels Requirements for CK_t - CK_c
Symbol
Parameter
VIHdiff
VILdiff
DDR4-3200
Unit
Note
V
V
1
1
Note 3
V
2
2 x (VIL(AC) - VREF)
V
2
differential input high
differential input low
Min
+ 0.110
Note 3
Max
Note 3
- 0.110
VIHdiff(AC)
differential input high ac
2 x (VIH(AC) - VREF)
VILdiff(AC)
differential input low ac
Note 3
Note:
1
Used to define a differential signal slew-rate.
2
for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA;
3
These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective
limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and
undershoot.
Table 4-3 Allowed Time before Ringback (tDVAC) for CK_t - CK_c
tDVAC [ps] @ |VIH/Ldiff(AC)| = 200mV tDVAC [ps] @ |VIH/Ldiff(AC)| = TBDmV
Slew Rate [V/ns]
Min
Max
Min
Max
> 4.0
120
-
TBD
-
4.0
115
-
TBD
-
3.0
110
-
TBD
-
2.0
105
-
TBD
-
1.8
100
-
TBD
-
1.6
95
-
TBD
-
1.4
90
-
TBD
-
1.2
85
-
TBD
-
1.0
80
-
TBD
-
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