74LVC1G240GM,115

74LVC1G240 Single inverting buffer/line driver; 3-state Rev. 2 — 25 August 2023 Product data sheet 1. General description The 74LVC1G240 is a 1-bit inverting buffer/line driver with 3-state output. The device features an output enable OE. A HIGH on OE causes the output to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • • • • Wide supply voltage range from 1.65 V to 5.5 V Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation IOFF circuitry provides partial Power-down mode operation ±24 mA output drive (VCC = 3.0 V) Latch-up performance exceeds 250 mA Direct interface with TTL levels Complies with JEDEC standard: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8C (2.7 V to 3.6 V) • JESD36 (4.5 V to 5.5 V) ESD protection: • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G240GM -40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74LVC1G240GS -40 °C to +125 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm SOT1202 74LVC1G240GX -40 °C to +125 °C X2SON5 plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 × 0.8 × 0.32 mm SOT1226-3 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state 4. Marking Table 2. Marking codes Type number Marking code [1] 74LVC1G240GM V2 74LVC1G240GS V2 74LVC1G240GX V2 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 2 A Y 1 OE 2 4 OE 001aac528 Fig. 1. A 4 1 OE 001aac527 Logic symbol Fig. 2. Y IEC logic symbol Fig. 3. 001aac526 Logic diagram 6. Pinning information 6.1. Pinning GM package SOT886 (XSON6) OE 1 6 VCC A 2 5 n.c. GND 3 4 Y GX package SOT1226-3 (X2SON5) GS package SOT1202 (XSON6) OE 1 6 VCC A 2 5 n.c. GND 3 4 Y OE A Transparent top view Transparent top view 5 VCC 4 Y 3 GND aaa-035709 aaa-035707 1 2 aaa-035710 Transparent top view 6.2. Pin description Table 3. Pin description Symbol Pin Description SOT886 and SOT1202 SOT1226-3 OE 1 1 output enable input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. 5 - not connected VCC 6 5 supply voltage 74LVC1G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 2 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level; X = Don’t care; Z = high-impedance OFF-state. Output Input OE A Y L L H L H L H X Z 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V - ±50 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO > VCC or VO < 0 V VO output voltage Active mode [1] -0.5 Power-down mode; VCC = 0 V [1] -0.5 +6.5 V IO output current - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Ptot total power dissipation - 250 mW Tstg storage temperature -65 +150 °C [1] [2] VI < 0 V [1] VO = 0 V to VCC Tamb = -40 °C to +125 °C [2] mA VCC + 0.5 V The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT886 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT1202 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C. For SOT1226-3 (X2SON5) package: Ptot derates linearly with 3.0 mW/K above 67 °C. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate 74LVC1G240 Product data sheet Conditions Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V Active mode 0 - VCC V Power-down mode; VCC = 0 V 0 - 5.5 V °C -40 - +125 VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 3 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ [1] Max Unit 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - VCC = 2.7 V to 3.6 V - - VCC = 4.5 V to 5.5 V - - VCC = 1.65 V to 5.5 V; IO = 100 μA - - 0.1 V VCC = 1.65 V; IO = 4 mA - - 0.45 V VCC = 2.3 V; IO = 8 mA - - 0.3 V VCC = 2.7 V; IO = 12 mA - - 0.4 V VCC = 3.0 V; IO = 24 mA - - 0.55 V VCC = 4.5 V; IO = 32 mA - - 0.55 V Tamb = -40 °C to +85 °C VIH VIL VOL VOH HIGH-level input voltage LOW-level input voltage LOW-level output voltage HIGH-level output voltage VCC = 1.65 V to 1.95 V 0.35 × VCC V 0.7 V 0.8 V 0.3 × VCC V VI = VIH or VIL VI = VIH or VIL VCC = 1.65 V to 5.5 V; IO = -100 μA VCC - 0.1 - - V VCC = 1.65 V; IO = -4 mA 1.2 - - V VCC = 2.3 V; IO = -8 mA 1.9 - - V VCC = 2.7 V; IO = -12 mA 2.2 - - V VCC = 3.0 V; IO = -24 mA 2.3 - - V VCC = 4.5 V; IO = -32 mA 3.8 - - V II input leakage current VCC = 0 V to 5.5 V; VI = 5.5 V or GND - ±0.1 ±1 μA IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL; VO = 5.5 V or GND - ±0.1 ±2 μA IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - ±0.1 ±2 μA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 4 μA ΔICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V; IO = 0 A - 5 500 μA CI input capacitance - 5 - pF 74LVC1G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 4 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state Symbol Parameter Conditions Min Typ [1] Max Unit 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - VCC = 2.7 V to 3.6 V - - VCC = 4.5 V to 5.5 V - - VCC = 1.65 V to 5.5 V; IO = 100 μA - - 0.1 V VCC = 1.65 V; IO = 4 mA - - 0.70 V VCC = 2.3 V; IO = 8 mA - - 0.45 V VCC = 2.7 V; IO = 12 mA - - 0.60 V VCC = 3.0 V; IO = 24 mA - - 0.80 V VCC = 4.5 V; IO = 32 mA - - 0.80 V Tamb = -40 °C to +125 °C VIH HIGH-level input voltage VIL LOW-level input voltage VOL LOW-level output voltage VOH HIGH-level output voltage VCC = 1.65 V to 1.95 V 0.35 × VCC V 0.7 V 0.8 V 0.3 × VCC V VI = VIH or VIL VI = VIH or VIL VCC = 1.65 V to 5.5 V; IO = -100 μA VCC - 0.1 - - V VCC = 1.65 V; IO = -4 mA 0.95 - - V VCC = 2.3 V; IO = -8 mA 1.7 - - V VCC = 2.7 V; IO = -12 mA 1.9 - - V VCC = 3.0 V; IO = -24 mA 2.0 - - V VCC = 4.5 V; IO = -32 mA 3.4 - - V II input leakage current VCC = 0 V to 5.5 V; VI = 5.5 V or GND - - ±1 μA IOZ OFF-state output current VCC = 3.6 V; VI = VIH or VIL; VO = 5.5 V or GND - - ±2 μA IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - - ±2 μA ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 4 μA ΔICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V; IO = 0 A - - 500 μA [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 74LVC1G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 5 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 6. Symbol Parameter Conditions -40 °C to +85 °C Min [2] propagation A to Y; see Fig. 4 delay VCC = 1.65 V to 1.95 V; CL = 15 pF; RL = 1 MΩ 1.0 tpd enable time 3.8 6.9 1.0 8.7 ns 2.4 4.6 0.5 5.8 ns VCC = 3.0 V to 3.6 V; CL = 15 pF; RL = 1 MΩ 0.5 1.9 3.7 0.5 4.6 ns VCC = 4.5 V to 5.5 V; CL = 15 pF; RL = 1 MΩ 0.5 1.6 3.4 0.5 4.2 ns VCC = 1.65 V to 1.95 V; CL = 30 pF; RL = 1 kΩ 1.0 3.3 8.0 1.0 10.5 ns VCC = 2.3 V to 2.7 V; CL = 30 pF; RL = 500 Ω 0.5 2.2 5.5 0.5 7 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 0.5 2.5 5.5 0.5 7 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω 0.5 2.1 4.5 0.5 6 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; RL = 500 Ω 0.5 1.7 4.0 0.5 5.5 ns VCC = 1.65 V to 1.95 V; CL = 30 pF; RL = 1 kΩ 1.0 4.1 9.4 1.0 12 ns VCC = 2.3 V to 2.7 V; CL = 30 pF; RL = 500 Ω 0.5 2.8 6.6 0.5 8.5 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 0.5 3.3 6.6 0.5 8.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω 0.5 2.4 5.3 0.5 7 ns 0.5 2.1 5.0 0.5 6.5 ns VCC = 1.65 V to 1.95 V; CL = 30 pF; RL = 1 kΩ 1.0 4.3 9.2 1.0 12 ns VCC = 2.3 V to 2.7 V; CL = 30 pF; RL = 500 Ω 0.5 2.7 5.0 0.5 6.5 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 0.5 3.0 5.0 0.5 6.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF; RL = 500 Ω 0.5 3.1 5.0 0.5 6.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF; RL = 500 Ω 0.5 2.2 4.2 0.5 5.5 ns - 25 - - - pF - 6 - - - pF [2] OE to Y; see Fig. 5 [3] VCC = 4.5 V to 5.5 V; CL = 50 pF; RL = 500 Ω [1] [2] [3] [4] [5] [4] VI = GND to VCC; fi = 10 MHz power dissipation output enabled capacitance output disabled CPD Max 0.5 disable time OE to Y; see Fig. 5 tdis Min VCC = 2.3 V to 2.7 V; CL = 15 pF; RL = 1 MΩ A to Y; see Fig. 4 ten Typ[1] Max -40 °C to +125 °C Unit [5] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. tpd is the same as tPLH and tPHL ten is the same as tPZH and tPZL tdis is the same as tPLZ and tPHZ CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL × VCC × fo) = sum of outputs. 74LVC1G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 6 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state 11.1. Waveforms and test circuit VI VM A input GND t PHL t PLH VOH VM Y output VOL mna640 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig. 4. The data input (A) to output (Y) propagation delays VI OE input VM GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPHZ VOH output HIGH-to-OFF OFF-to-HIGH tPZH VY VM GND outputs enabled outputs disabled outputs enabled mna644 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. 3-state enable and disable times Table 9. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 1.95 V 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 4.5 V to 5.5 V 0.5VCC 0.5VCC VOL + 0.3 V VOH - 0.3 V 74LVC1G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 7 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state VEXT VCC G VI RL VO DUT RT CL RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to the output impedance Zo of the pulse generator; VEXT = External voltage for measuring switching times. Fig. 6. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VCC VI tr, tf tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC ≤ 2.0 ns open GND 2VCC 2.3 V to 2.7 V VCC ≤ 2.0 ns open GND 2VCC 2.7 V 2.7 V ≤ 2.5 ns open GND 6V 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns open GND 6V 4.5 V to 5.5 V VCC ≤ 2.5 ns open GND 2VCC 74LVC1G240 Product data sheet VEXT All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 8 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state 12. Package outline SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 Fig. 7. sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Package outline SOT886 (XSON6) 74LVC1G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 9 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit mm 1 mm scale A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1202_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1202 Fig. 8. Package outline SOT1202 (XSON6) 74LVC1G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 10 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 x 0.8 x 0.32 mm SOT1226-3 C Seating Plane X 5x y C D A B E A A3 pin 1 index area A1 pin 1 index area e 1 2 b (4x) v w y1 C C A B C L (4x) 3 k D h (6x) x) (4 5 4 0 1 mm scale Dimensions (mm are the original dimensions) Unit mm A A1 A3 D Dh E b e K L max 0.35 0.04 0.85 0.30 0.85 0.25 0.27 0.10 0.80 0.25 0.80 0.20 0.50 0.22 nom 0.32 0.02 (Typ.) min 0.30 0.00 0.75 0.20 0.75 0.15 0.20 0.17 v 0.1 w y y1 0.05 0.05 0.05 sot1226-3_po Outline version SOT1226-3 Fig. 9. References IEC JEDEC EIAJ European projection Issue date 19-11-06 19-11-07 --- Package outline SOT1226-3 (X2SON5) 74LVC1G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 11 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC1G240 v.2 20230825 Product data sheet - Modifications: • 74LVC1G240 v.1 20220309 74LVC1G240 Product data sheet 74LVC1G240 v.1 Section 2: ESD specification updated according to the latest JEDEC standard. Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 - © Nexperia B.V. 2023. All rights reserved 12 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74LVC1G240 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 13 / 14 74LVC1G240 Nexperia Single inverting buffer/line driver; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description............................................................. 2 7. Functional description................................................. 3 8. Limiting values............................................................. 3 9. Recommended operating conditions..........................3 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................6 11.1. Waveforms and test circuit........................................ 7 12. Package outline.......................................................... 9 13. Abbreviations............................................................ 12 14. Revision history........................................................12 15. Legal information......................................................13 © Nexperia B.V. 2023. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 25 August 2023 74LVC1G240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 25 August 2023 © Nexperia B.V. 2023. All rights reserved 14 / 14