ZDV4256M16A-13IPH

  ZDV4(5)256M16 ZDV4(5)256M16 4Gb DDR3(L) SDRAM Datasheet * Information furnished is believed to be accurate and reliable. However, Zetta assumes no responsibility for the consequences of use of such information or  for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any  patent rights of Zetta. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all  information previously supplied. Zetta products are not authorized for use as critical components in life support devices or systems without express written  approval of Zetta. The Zetta logo is a registered trademark of Zetta Device Technology Limited. All other names are the property of their respective own.    ZDV4(5)256M16         4GBIT DDR3 DRAM         Key Features  BL switch on the fly VDD=VDDQ=1.35V(1.28V~1.45V)，backward  compatible to 1.5V applications.  Driver strength selected by MRS Dynamic On Die Termination Asynchronous RESET pin Internal (self) calibration: Internal self calibration through ZQ pin (RZQ: 240 ohm ± 1%) VDD=VDDQ=1.5V(1.425V~1.575V)    8 banks 8n-bit prefetch architecture Fully differential clock inputs (CK,CK) operation ————  Bi-directional differential data strobe (DQS,DQS)   On chip DLL align DQ, DQS and DQS transition TDQS (Termination Data Strobe) supported (x8 only)  Write leveling Self refresh temperature (SRT) Automatic self refresh (ASR) JEDEC standard package - 96ball FBGA(x16)    ———— With CK transition   DM masks write data-in at the both rising and falling edges of the data strobe   All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock   Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 supported   Programmable additive latency 0, CL-1, and CL-2 supported  Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9, 10  Programmable burst length 4/8 with both nibble sequential and interleave mode   Lead free & RoHS compliant JEDEC compliant Operating Temperature (Tcase) - Commercial -C (0°C ≤ TC ≤ 85°C) - Industrial -I (-40°C ≤ TC ≤ 85°C)       1600 1866 2133 11-11-11 13-13-13 14-14-14 tCK(min) 1.25 1.071 0.938 ns CAS Latency 11 13 14 nCK tRCD(min) 13.75 13.91 13.09 ns tRP(min) 13.75 13.91 13.09 ns tRAS(min) 35 34 33 ns tRC(min) 48.75 47.91 46.09 ns Speed Unit   Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.   Rev 1.0 2   ZDV4(5)256M16 Descriptions   The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM. It is internally configured as an octal-bank DRAM.   The 4Gb chip is organized as 32Mbit x16 I/O x 8 banks. These synchronous devices achieve high speed double-data-rate transfer rates of up to 2133 Mb/sec/pin for general applications.   The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross ____ point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.   These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in BGA packages.       Addressing   Configuration 512Mb x 8 256Mb x 16 Number of Bank 8 8 Bank address BA0-BA2 BA0-BA2 Autoprecharge A10/AP A10/AP Row address A0-A15 A0-A14 Column address A0-A9 A0-A9 BC switch on the fly A12/BC A12/BC Page Size 1KB   2KB tREFI Tc ≦ 85°C : 7.8μs, 85°C < Tc ≦ 105°C : 3.9μs tRFC 260ns       Package   Dimension (mm) 4Gb (Org. / Package) Ball pitch (mm) 512Mbx8 78-ball FBGA 9 x 10.6 0.80 256Mbx16 96-ball FBGA 9 x 13 0.80   Rev 1.0 3   ZDV4(5)256M16 Ordering Information       Organization Speed Part No.    Clock (MHz) Data Rate (Mb/s)   CL-TRCD-TRP Package DDR3(L) Commercial Grade (-C, 0C ~ 85C)           256Mx16 ZDV4256M16A-14DPH 1066 DDR3L-2133 14-14-14 ZDV4256M16A-13DPH 933 DDR3L-1866 13-13-13 ZDV4256M16A-11DPH 800 DDR3L-1600 11-11-11 ZDV5256M16A-14DPH 1066 DDR3-2133 14-14-14 ZDV5256M16A-13DPH 933 DDR3-1866 13-13-13 ZDV5256M16A-11DPH 800 DDR3-1600 11-11-11           96-ball DDR3(L) Industrial Grade (-I, -40C ~ 85C)           256Mx16 ZDV4256M16A-14IPH 1066 DDR3L-2133 14-14-14 ZDV4256M16A-13IPH 933 DDR3L-1866 13-13-13 ZDV4256M16A-11IPH 800 DDR3L-1600 11-11-11 ZDV5256M16A-14IPH 1066 DDR3-2133 14-14-14 ZDV5256M16A-13IPH 933 DDR3-1866 13-13-13 ZDV5256M16A-11IPH 800 DDR3-1600 11-11-11     Rev 1.0 4           96-ball   ZDV4(5)256M16 X16 Package Ballout (Top View): 96ball FBGA Package     A   B C D E F G H J K L M N P R T     1 2 VDDQ DQU5 VSSQ VDD   VDDQ   DQU3 VSS VDDQ VSSQ VDDQ DQL2 VSSQ DQL6             NC ODT NC 9 DQU4 VDDQ VSS A DQSU DQU6 VSSQ B DQU1 DQSU DQU2 VDDQ C DMU DQU0 VSSQ VDD D DQL0 DML VSSQ VDDQ E DQSL DQL1 DQL3 VSSQ F DQSL VDD VSS VSSQ G DQL4 DQL7 DQL5 VDDQ H CK VSS NC J CK VDD CKE K A10/AP ZQ NC L NC VREFCA VSS M DQU7 ___________ VSS ________ VSS RAS ________ VDD ——— CAS _____ ———— CS WE VDD VSS BA0 A3 A5     8   VSS   7 __________ VDDQ     6   VREFDQ   5   VSSQ     4       3 BA2     ——— A0 A12/BC BA1 VDD N A2 A1 A4 VSS P A9 A11 A6 VDD R A14 A8 VSS T 7 8 9   VDD A7 VSS ——————— RESET A13 1 2 3     4 5 6     Top View: See the balls through the Package       Rev 1.0 5   ZDV4(5)256M16   Packge Dimensions – 96 balls BGA Package (x16)         Rev 1.0 6   ZDV4(5)256M16 Pin Functions   Symbol Type   ——— CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK ——— and negative edge of CK                             CKE Function ——— Input Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper selfrefresh entry and exit, VREF must maintain to this input. CKE must be maintained high throughout read and write accesses. Input buffers, ——— excluding CK, CK , ODT and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during Self-Refresh.     Input  ____ CS  ____ Chip Select: All commands are masked when CS is registered high. provides for external rank selection on systems with multiple memory ___ ranks. CS is considered part of the command code. _________ ________ ________ Input RAS, CAS, WE   DM, (DMU, DML)           BA0 ~ BA2                 A10 / AP A0 ~ A15     ———— A12, BC       ODT   Rev 1.0       ____ RAS , CAS , WE (along with CS) define the command being Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. Input Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. Input Auto-Precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. Address Inputs: Provide the row address for Activate commands and the column address for Read/Write commands to select one location       Input _________ ________ ________ Input _____ out of the memory array in the respective bank. (A10/AP and A12, BC have additional function as below.) The address inputs also provide the op-code during Mode Register Set commands. ——— Input Burst Chop: A12, BC is sampled during Read and Write commands to determine if burst chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped). On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is _______ Input __________ __________ applied to each DQ, DQS, DQS and DM, TDQS, NU, TDQS (when TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT. 7   ZDV4(5)256M16     Symbol ____________ RESET   DQ DQL, DQU, ________ DQS, (DQS） Type         __________ DQSL, (DQSL), ___________ DQSU, (DQSU )   ____________ Active Low Asynchronous Reset: Reset is active when RESET is LOW, ____________ ____________ Input _________ TDQS,(TDQS) normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V   Input/Output Data Inputs/Output: Bi-directional data bus. Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. The data strobes DQS, _______ _________ __________ DQSL, DQSU are paired with differential signals DQS, DQSL, DQSU, Input/Output respectively, to provide differential pair signaling to the system during both reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. _________       ___________ and inactive when RESET is HIGH. RESET must be HIGH during       Function TDQS and TDQS is applicable for ×8 configuration only. When enabled via mode register A11 = 1 in MR1, DRAM will enable the same Output __________ termination resistance function on TDQS, TDQS as is applied to DQS, DQS. When disabled via mode register A11 = 0 in MR1, DM/TDQS will __________ provide the data mask function and TDQS is not used. NC - No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.35V -0.067V/+0.1V or 1.5V ± 0.075V VDD Supply Power Supply: 1.35V -0.067V/+0.1V or 1.5V ± 0.075V VSSQ Supply DQ Ground VSS Supply Ground VREFCA Supply Reference voltage for CA VREFDQ Supply Reference voltage for DQ ZQ Supply Reference pin for ZQ calibration. _______ _______ ______ _____ ____________ Note: Input only pins (BA0-BA2, A0-A14, RAS, CAS, WE, CS, CKE, ODT, and RESET do not supply termination.   Rev 1.0 8   ZDV4(5)256M16 Absolute Maximum Ratings   Absolute Maximum DC Ratings       Symbol   Rating VDD   Voltage on VDD pin relative to VSS -0.4 ~ 1.8 VDDQ -0.4 ~ 1.8 TSTG 1,3   Voltage on input/output pin relative to VSS     V   VIN, VOUT 1,3   Voltage on VDDQ pin relative to VSS Storage Temperature Note   V       Unit         Parameters -0.4 ~ 1.8   V   -55 ~ 100 1   °C 1,2 Notes:   1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.   2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.   3. VDD and VDDQ must be within 300mV of each other at all times; and Vref must be not greater than 0.6VDDQ, when VDD and VDDQ are less than 500mV; Vref may be equal to or less than 300mV.     Refresh parameters by device density         Parameter Symbol 1Gb 4Gb REF command to ACT or REF command time tRFC 110 160 Rev 1.0 9     4Gb 260     8Gb Unit 350 ns   ZDV4(5)256M16 Temperature Range   Symbol     Commercial (-C) Industrial (-I) Parameters Rating Unit Note Normal Operating Temperature Range 0 ≤ TOPER ≤ 85 °C 1 Extended Temperature Range 85 < TOPER ≤ 95 °C 1,2 Normal Operating Temperature Range -40 ≤ TOPER ≤ 85 °C 1 Extended Temperature Range 85 < TOPER ≤ 95 °C 1,2 Notes:     1. Operating Temperature Toper is the case surface temperature on the center/top side of the DRAM. 2. Some applications require operation of the DRAM in the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the following additional apply:     a) Refresh commands must be doubled in frequency, therefore, reducing the Refresh interval tREFI to 3.9us. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual SelfRefresh mode with Extended Temperature Range capability (MR2 A6=0 and MR2 A7=1) or enable the optional Auto Self-Refresh mode (MR2 A6=1 and MR2 A7=0).   Rev 1.0 10   ZDV4(5)256M16 AC & DC Operating Conditions   Recommended DC Operating Conditions           Symbol         VDD     Parameters     Min. Typ. Max. 1.425 1.5 1.575   Supply Voltage   VDDQ   Rating DDR3 DDR3L 1.283 1.35 Supply Voltage for Output   1.45 DDR3 1.425 1.5 1.575   DDR3L 1.283 1.35 1.45 Unit         Note   V       1,2   3,4,5,6   V 1,2   3,4,5,6 Notes: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together 3. Maximum DC value may not be great than 1.425V. The DC value is the linear average of VDD/ VDDQ(t) over a very long period of time (e.g., 1 sec). 4. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 5. Under these supply voltages, the device operates to this DDR3L specification. 6. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation. 7. VDD= VDDQ= 1.35V (1.283–1.45V) Backward compatible to VDD= VDDQ= 1.5V ±0.075V Supports DDR3L devices to be backward com-partible in 1.5V applications.   Rev 1.0 11   ZDV4(5)256M16 IDD Specifications and Measurement Conditions   IDD Specifications (DDR3L)                                     Symbol   Parameter IDD0 Operating Current 0 One Bank Activate -> Precharge IDD1 Operating Current 1 One Bank Activate -> Read -> Precharge Width DDR3L-1600 11-11-11 DDR3L-1866 13-13-13 DDR3L-2133 14-14-14 Units x8 100 120 130 mA x16 110 130 150 mA x8 110 125 135 mA x16 120 135 155 mA x8 20 20 20 mA x16 22 22 22 mA IDD2P0 Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 IDD2P1 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 x8 43 45 47 mA x16 45 47 49 mA   x8 58 63 68 mA x16 60 65 70 mA x8 61 66 71 mA x16 63 68 73 mA x8 83 90 96 mA x16 85 92 96 mA x8 88 96 100 mA x16 90 100 105 mA IDD2Q IDD2N IDD2NT IDD3N IDD3P IDD4R IDD4W IDD5B Precharge Quiet Standby Current   Precharge Standby Current   Precharge Standby ODT Current   Active Standby Current Active Power-Down Current Always Fast Exit x8 68 77 82 mA x16 70 80 85 mA   x8 180 210 230 mA x16 190 220 240 mA x8 200 240 265 mA x16 210 250 280 mA x8 170 185 200 mA x16 180 195 210 mA x8 25 25 25 mA x16 25 25 25 mA x8 28 28 28 mA Operating Current Burst Read   Operating Current Burst Write   Burst Refresh Current IDD6 1 Self-Refresh Current Normal IDD6ET 2 Self-Refresh Current Extended x16 28 28 28 mA   x8 220 255 275 mA x16 240 270 290 mA x8 21 21 22 mA x16 23 23 24 mA IDD7 IDD8 All Bank Interleave Read Current   RESET Low Current Notes 1. TC = 85°C; SRT and ASR are disabled. 2. Enabling ASR could increase IDDx by up to an additional 2mA. 3. Restricted to TC (MAX) = 85°C. 4. TC = 85°C; ASR and ODT are disabled; SRT is enabled.   Rev 1.0 12   ZDV4(5)256M16 IDD Specifications and Measurement Conditions   IDD Specifications (DDR3)                                       Symbol   Parameter IDD0 Operating Current 0 One Bank Activate -> Precharge IDD1 Operating Current 1 One Bank Activate -> Read >Precharge Width DDR3-1600 11-11-11 DDR3-1866 13-13-13 DDR3-2133 14-14-14 Unit x8 100 120 130 mA x16 110 130 150 mA x8 110 125 135 135 mA 155 mA x16 120 x8 20 20 20 mA x16 22 22 22 mA IDD2P0 Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 IDD2P1 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 x8 43 45 47 mA x16 45 47 49 mA   x8 58 63 68 mA x16 60 65 70 mA x8 61 66 71 mA x16 63 68 73 mA x8 83 90 96 mA x16 85 92 98 mA IDD2Q IDD2N Precharge Quiet Standby Current   Precharge Standby Current   IDD2NT Precharge Standby ODT Current IDD3N IDD3P IDD4R IDD4W IDD5B   Active Standby Current x8 88 96 100 mA x16 90 100 105 mA Active Power-Down Current Always Fast Exit x8 68 77 82 mA x16 70 80 85 mA   x8 180 210 230 mA x16 190 220 240 mA x8 200 240 265 mA x16 210 250 280 mA x8 170 185 200 mA x16 180 195 210 mA x8 25 25 25 mA x16 25 25 25 mA Operating Current Burst Read   Operating Current Burst Write   Burst Refresh Current IDD6 1 Self-Refresh Current Normal IDD6ET 2 Self-Refresh Current Extended x8 28 28 28 mA x16 28 28 28 mA   x8 220 255 275 mA x16 240 270 290 mA x8 21 21 22 mA x16 23 23 24 mA IDD7 IDD8 All Bank Interleave Read Current   RESET Low Current Notes 1. TC = 85°C; SRT and ASR are disabled. 2. Enabling ASR could increase IDDx by up to an additional 2mA. 3. Restricted to TC (MAX) = 85°C. 4. TC = 85°C; ASR and ODT are disabled; SRT is enabled.     Rev 1.0 13   ZDV4(5)256M16 Revision History   Revision     0.1 1.0 Date     Nov., 2020 Dec., 2020 Page     12~13 Notes Preliminary IDDx value updated     Rev 1.0 14