RK3568J Datasheet
Rev 1.0
Rockchip
RK3568J
Datasheet
Revision History
Date
Revision
2022-03-04
1.0
Description
Initial release
Copyright 2022 © Rockchip Electronics Co., Ltd.
1
RK3568J Datasheet
Rev 1.0
Table of Content
Table of Content ...................................................................................................... 2
Figure Index ........................................................................................................... 3
Table Index............................................................................................................. 4
Warranty Disclaimer ................................................................................................. 5
Chapter 1 Introduction ..................................................................................... 6
1.1 Overview ............................................................................................... 6
1.2 Features ................................................................................................ 6
1.3 Block Diagram ...................................................................................... 18
Chapter 2 Package Information.........................................................................19
2.1 Order Information ................................................................................. 19
2.2 Top Marking ......................................................................................... 19
2.3 FCCSP636L Dimension ........................................................................... 19
2.4 Ball Map .............................................................................................. 22
2.5 Pin Number List .................................................................................... 22
2.6 Power/Ground IO Description .................................................................. 29
2.7 Function IO Description .......................................................................... 32
2.8 IO Pin Name Description ........................................................................ 41
Chapter 3 Electrical Specification ......................................................................53
3.1 Absolute Ratings ................................................................................... 53
3.2 Recommended Operating Condition ......................................................... 54
3.3 DC Characteristics ................................................................................. 55
3.4 Electrical Characteristics for General IO .................................................... 57
3.5 Electrical Characteristics for PLL .............................................................. 57
3.6 Electrical Characteristics for USB 2.0 Interface .......................................... 58
3.7 Electrical Characteristics for DDR IO......................................................... 59
3.8 Electrical Characteristics for TSADC.......................................................... 60
3.9 Electrical Characteristics for MIPI DSI....................................................... 60
3.10 Electrical Characteristics for MIPI CSI ..................................................... 60
3.11 Electrical Characteristics for HDMI.......................................................... 60
3.12 Electrical Characteristics for multi-PHY.................................................... 61
Chapter 4 Thermal Management .......................................................................62
4.1 Overview ............................................................................................. 62
4.2 Package Thermal Characteristics ............................................................. 62
Copyright 2022 © Rockchip Electronics Co., Ltd.
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RK3568J Datasheet
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Figure Index
Fig.1-1
Fig.2-1
Fig.2-2
Fig.2-3
Fig.2-4
Fig.2-5
Fig.2-6
Block Diagram ....................................................................................... 18
Package definition .................................................................................. 19
Package Top View .................................................................................. 19
Package bottom view.............................................................................. 20
Package side view .................................................................................. 20
Package dimension................................................................................. 21
Ball Map ............................................................................................... 22
Copyright 2022 © Rockchip Electronics Co., Ltd.
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RK3568J Datasheet
Rev 1.0
Table Index
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
2-1 Pin Number List Information ................................................................... 22
2-2 Power/Ground IO information ................................................................. 29
2-3 Function IO description .......................................................................... 32
2-4 IO function description list ..................................................................... 41
3-1 Absolute ratings.................................................................................... 53
3-2 Recommended operating condition .......................................................... 54
3-3 DC Characteristics................................................................................. 55
3-4 Electrical Characteristics for Digital General IO .......................................... 57
3-5 Electrical Characteristics for Frac PLL ....................................................... 57
3-6 Electrical Characteristics for Int-PLL ......................................................... 57
3-7 Electrical Characteristics for USB 2.0 Interface .......................................... 58
3-8 Electrical Characteristics for DDR IO ........................................................ 59
3-9 Electrical Characteristics for TSADC ......................................................... 60
3-10 Electrical Characteristics for MIPI DSI .................................................... 60
3-11 Electrical Characteristics for MIPI CSI ..................................................... 60
3-12 Electrical Characteristics for HDMI ......................................................... 60
3-13 Electrical Characteristics for PCIe PHY .................................................... 61
4-1 Thermal Resistance Characteristics .......................................................... 62
Copyright 2022 © Rockchip Electronics Co., Ltd.
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RK3568J Datasheet
Rev 1.0
Warranty Disclaimer
Rockchip Electronics Co., Ltd makes no warranty, representation or guarantee (expressed, implied, statutory, or otherwise)
by or with respect to anything in this document, and shall not be liable for any implied warranties of non-infringement,
merchantability or fitness for a particular purpose or for any indirect, special or consequential damages.
Information furnished is believed to be accurate and reliable. However, Rockchip Electronics Co., Ltd assumes no
responsibility for the consequences of use of such information or for any infringement of patents or other rights of third
parties that may result from its use.
Rockchip Electronics Co., Ltd’s products are not designed, intended, or authorized for using as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Rockchip Electronics Co., Ltd’s product could create a situation where personal injury or
death may occur, should buyer purchase or use Rockchip Electronics Co., Ltd’s products for any such unintended or
unauthorized application, buyers shall indemnify and hold Rockchip Electronics Co., Ltd and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees
arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended
or unauthorized use, even if such claim alleges that Rockchip Electronics Co., Ltd was negligent regarding the design or
manufacture of the part.
Copyright and Patent Right
Information in this document is provided solely to enable system and software implementers to use Rockchip Electronics Co.,
Ltd ’s products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Rockchip Electronics Co., Ltd does not convey any license under its patent rights nor the
rights of others.
All copyright and patent rights referenced in this document belong to their respective owners
and shall be subject to corresponding copyright and patent licensing requirements.
Trademarks
Rockchip and RockchipTM logo and the name of Rockchip Electronics Co., Ltd’s products are trademarks of Rockchip
Electronics Co., Ltd. and are exclusively owned by Rockchip Electronics Co., Ltd. References to other companies and their
products use trademarks owned by the respective companies and are for reference purpose only.
Confidentiality
The information contained herein (including any attachments) is confidential. The recipient hereby acknowledges the
confidentiality of this document, and except for the specific purpose, this document shall not be disclosed to any third party.
Reverse engineering or disassembly is prohibited.
ROCKCHIP ELECTRONICS CO.,LTD. RESERVES THE RIGHT TO MAKE CHANGES IN ITS PRODUCTS OR PRODUCT
SPECIFICATIONS WITH THE INTENT TO IMPROVE FUNCTION OR DESIGN AT ANY TIME AND WITHOUT NOTICE
AND IS NOT REQUIRED TO UNDATE THIS DOCUMENTATION TO REFLECT SUCH CHANGES.
Copyright © 2022 Rockchip Electronics Co., Ltd.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or
by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Rockchip
Electronics Co., Ltd.
Copyright 2022 © Rockchip Electronics Co., Ltd.
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RK3568J Datasheet
Rev 1.0
Chapter 1 Introduction
1.1 Overview
RK3568J is a high-performance and low power quad-core application processor designed
for intelligent hardware and industrial applications.
Many embedded powerful hardware engines are provided to optimize performance for highend application. RK3568J supports almost full-format H.264 decoder by 4K@60fps, H.265
decoder by 4K@60fps, also support H.264/H.265 encoder by 1080p@60fps, high-quality
JPEG encoder/decoder.
Embedded 3D GPU makes RK3568J completely compatible with OpenGL ES 1.1/2.0/3.2,
OpenCL 2.0 and Vulkan 1.1. Special 2D hardware engine will maximize display performance
and provide very smoothly operation.
The build-in NPU supports INT8/INT16/FP16/BFP16 hybrid operation. In addition, with its
strong compatibility, network models based on a series of frameworks such as
TensorFlow/MXNet/PyTorch/Caffe can be easily converted.
RK3568J has high-performance external memory interface(DDR3/DDR3L/DDR4
/LPDDR3/LPDDR4/LPDDR4X) capable of sustaining demanding memory bandwidths.
1.2 Features
The features listed below which may or may not be present in actual product, may be
subject to the third party licensing requirements. Please contact Rockchip for actual product
feature configurations and licensing requirements.
1.2.1 Microprocessor
Quad-core ARM Cortex-A55 CPU
ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated
media and signal processing computation
Include VFP hardware to support single and double-precision operations
ARMv8 Cryptography Extensions
Integrated 32KB L1 instruction cache, 32KB L1 data cache with ECC
512KB unified system L3 cache with ECC
TrustZone technology support
Separate power domains for CPU core system to support internal power switch and
externally turn on/off based on different application scenario
PD_A55_0: 1st Cortex-A55 + Neon + FPU + L1 I/D Cache
PD_A55_1: 2nd Cortex-A55 + Neon + FPU + L1 I/D Cache
PD_A55_2: 3rd Cortex-A55 + Neon + FPU + L1 I/D Cache
PD_A55_3: 4th Cortex-A55 + Neon + FPU + L1 I/D Cache
One isolated voltage domain
1.2.2 Neural Process Unit
Neural network acceleration engine with processing performance up to 1 TOPS
Support INT8/INT16/FP16/BFP16 MAC hybrid operation
Support deep-learning frameworks: TensorFlow, TF-lite, Pytorch, Caffe, ONNX, MXNet,
Keras, Darknet
One isolated voltage domain
1.2.3 Memory Organization
Internal on-chip memory
BootROM
SYSTEM_SRAM in the voltage domain of VD_LOGIC
PMU_SRAM in the voltage domain of VD_PMU for low power application
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External off-chip memory
①
DDR3/DDR3L/DDR4/LPDDR3/LPDDR4/LPDDR4X
SPI Nor/Nand Flash
eMMC
SD_Card
8bits Async Nand Flash
8bits toggle Nand Flash
8bits ONFI Nand Flash
1.2.4 Internal Memory
Internal BootRom
Support system boot from the following device:
SPI Flash interface
Nand Flash
eMMC interface
SDMMC interface
Support system code download by the following interface:
USB OTG interface (Device mode)
SYSTEM_SRAM
Size: 64KB
PMU_SRAM
Size: 8KB
1.2.5 External Memory or Storage device
Dynamic Memory Interface (DDR3/DDR3L/DDR4/LPDDR2/LPDDR3/LPDDR4/LPDDR4X)
Compatible with JEDEC standards
Compatible with DDR3-2133/DDR3L-2133/LPDDR3-2133/DDR4-3200/LPDDR43200/LPDDR4X-3200
Support 32bits data width, 2 ranks (chip selects), total addressing space is
8GB(max) for DDR3/DDR3L/DDR4
Support 32bits data width, 4 ranks (chip selects), total addressing space is
8GB(max) for LPDDR3/LPDDR4/LPDDR4X
Low power modes, such as power-down and self-refresh for SDRAM
Compensation for board delays and variable latencies through programmable
pipelines
Support 8bits ECC for DDR3/DDR3L/DDR4
Programmable output and ODT impedance with dynamic PVT compensation
eMMC Interface
Compatible with standard iNAND interface
Compatible with eMMC specification 4.41, 4.51, 5.0 and 5.1
Support three data bus width: 1bit, 4bits or 8bits
Support HS200;
Support CMD Queue
SD/MMC Interface
Compatible with SD3.0, MMC ver4.51
Data bus width is 4bits
Nand Flash Interface
Support async nand flash, each channel 8bits, up to 4 banks
Support ONFI Synchronous Flash Interface, each channel 8bits, up to 4 banks
Support Toggle Flash Interface, each channel 8bits, up to 4 banks
Support sync DDR nand flash, each channel 8bits, up to 4 banks
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Support LBA nand flash in async or sync mode
Up to 70bits/1KB hardware ECC
For DDR nand flash, support DLL bypass and 1/4 or 1/8 clock adjust, maximum
clock rate is 75MHz
For async nand flash, support configurable interface timing , maximum data rate is
16bits/cycle
SPI Flash Interface
Support Serial NOR Flash, NAND Flash, pSRAM and SRAM
Support SDR mode
Support 1bit/2bit/4bit data width
1.2.6 System Component
CRU (clock & reset unit)
Support clock gating control for individual components
One oscillator with 24MHz clock input
Support global soft-reset control for whole chip, also individual soft-reset for each
component
MCU
32bits microcontroller core
Harvard architecture separate Instruction and Data memories
Integrated Programmable Interrupt Controller (IPIC)
Integrated Debug Controller with JTAG interface
PMU(power management unit)
5 separate voltage domains(VD_CORE/VD_LOGIC/VD_NPU/VD_GPU/VD_PMU)
15 separate power domains, which can be power up/down by software based on
different application scenes
Multiple configurable work modes to save power by different frequency or
automatic clock gating control or power domain on/off control
Timer
Six 64bits timers with interrupt-based operation for non-secure application
Two 64bits timers with interrupt-based operation for secure application
Support two operation modes: free-running and user-defined count
Support timer work state checkable
Watchdog
32bits watchdog counter
Counter counts down from a preset value to 0 to indicate the occurrence of a
timeout
WDT can perform two types of operations when timeout occurs:
Generate a system reset
First generate an interrupt and if this is not cleared by the service routine by
the time a second timeout occurs then generate a system reset
Programmable reset pulse length
Totally 16 defined-ranges of main timeout period
One Watchdog for non-secure application
One Watchdog for secure application
Interrupt Controller
Support 3 PPI interrupt sources and 256 SPI interrupt sources input from different
components
Support 16 software-triggered interrupts
Two interrupt outputs (nFIQ and nIRQ) separately for each Cortex-A55, both are
low-level sensitive
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RK3568J Datasheet
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Support different interrupt priority for each interrupt source, and they are always
software-programmable
Mailbox
One Mailbox in SoC to service Cortex-A55 and MCU communication
Support four mailbox elements per mailbox, each element includes one data word,
one command word register and one flag bit that can represent one interrupt
Provide 32 lock registers for software to use to indicate whether mailbox is
occupied
DMAC
Two identical DMAC blocks supported(DMAC0/DMAC1)
Micro-code programming based DMA
The specific instruction set provides flexibility for programming DMA transfers
Linked list DMA function is supported to complete scatter-gather transfer
Support internal instruction cache
Embedded DMA manager thread
Support data transfer types with memory-to-memory, memory-to-peripheral,
peripheral-to-memory
Signals the occurrence of various DMA events using the interrupt output signals
Mapping relationship between each channel and different interrupt outputs is
software-programmable
One embedded DMA controller for system
DMAC features:
8 channels totally
32 hardware request from peripherals
2 interrupt outputs
Trust Execution Environment system
Support TrustZone technology for the following components
Cortex-A55, support security and non-security mode, switch by software
System general DMAC, support some dedicated channels work only in security
mode
Secure OTP, only can be accessed by Cortex-A55 in secure mode and secure
key reader block
SYSTEM_SRAM, part of space is addressed only in security mode, detailed size
is software-programmable together with TZMA (TrustZone memory adapter)
Cipher engine
Support SHA-1, SHA-256/224, SHA-512/384, MD5 with hardware padding
Support HMAC of SHA-1, SHA-256, SHA-512, MD5 with hardware padding
Support AES-128, AES-192, AES-256 encrypt & decrypt cipher
Support DES & TDES cipher
Support AES ECB/CBC/OFB/CFB/CTR/CTS/XTS/CCM/GCM/CBC-MAC/CMAC
mode
Support DES/TDES ECB/CBC/OFB/CFB mode
Support up to 4096 bits PKA mathematical operations for RSA/ECC
Support data scrambling for DDR SDRAM device
Support up to 256 bits TRNG Output
Support secure OTP
Support secure boot
Support secure debug
Support secure OS
1.2.7 Video CODEC
Video Decoder
H.265 HEVC/MVC Main10 Profile yuv420@L5.1 up to 4096x2304@60fps
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H.264 AVC/MVC Main10 Profile yuv400/yuv420/yuv422/@L5.1 up to
4096x2304@60fps
VP9 Profile0/2 yuv420@L5.1 up to 4096x2304@60fps
VP8 verision2,up to 1920x1088@60fps
VC1 Simple Profile@low, medium, high levels, Main Profile@low, medium, high
levels, Advanced Profile@level0~3,up to 1920x1088@60fps
MPEG-4 Simple Profile@L0~6,Advanced Simple Profile@L0~5,up to
1920x1088@60fps
MPEG-2 Main Profile, low, medium and high levels, up to 1920x1088@60fps
MPEG-1 Main Profile, low, medium and high levels, up to 1920x1088@60fps
H.263 Profile0,levels 10-70,up to 720x576@60fps
Video Encoder
H.264/AVC BP/MP/HP@level4.2，up to 1920x1080@60fps
H.265/HEVC MP@level4.1, up to 1920x1080@60fps (4096x4096@10fps with TILE)
Support YUV/RGB video source with rotation and mirror
1.2.8 JPEG CODEC
JPEG decoder
JPEG Baseline interleaved, max resolution up to 8176x8176，
performance up to 76 million pixels per second
JPEG encoder
Baseline Non-progressive
up to 8192x8192
up to 90 million pixels per second
1.2.9 Image Enhancement (IEP module)
Image format support
Input data: YUV420/YUV422 ; semi-planar/planar; UV swap
Output data: YUV420/YUV422 ; semi-planar; UV swap; Tile mode
YUV down sampling conversion from 422 to 420
Max resolution for dynamic image up to 1920x1080
De-interlace
I5O2: Input 5 Fields Output 2 frames mode
I5O1T: Input 5 Fields Output 1 Top frame mode
I5O1B: Input 5 Fields Output 1 Bottom frame mode
I2O2: Input 2 Fields Output 2 frames mode
I1O1T: Input 1 Field Output 1 Top frame mode
I1O1B: Input 1 Field Output 1 Bottom frame mode
PULLDOWN_REC: Pull down Recovery mode
DETECT_ONLY: Detect Only mode
MVHIST: De-interlace MV Histogram
MD: Motion Detection
ME: Motion Estimate
MC: Motion Compensation
EEDI: Enhanced Edge based Interpolation
OSD DETECT: On-Screen Display Detection
FF DETECT: Frame Field Detection
FO DETECT: Field Order Detection
PD DETECT: Pull down Detection
CC: Combining Check
1.2.10 Graphics Engine
3D Graphics Engine:
Mali-G52 1-Core-2EE
Copyright 2022 © Rockchip Electronics Co., Ltd.
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RK3568J Datasheet
Support
Support
Support
Support
Support
Rev 1.0
OpenGL ES 1.1, 2.0, and 3.2
Vulkan 1.0 and 1.1
OpenCL 2.0 Full Profile
1600Mpix/s fill rate when 800MHz clock frequency
38.4GLOPs when 800MHz clock frequency
2D Graphics Engine:
Data format
Support input of
ARGB/RGB888/RGB565/RGB4444/RGB5551/YUV420/YUV422/YUYV；
Support input of YUV422SP10bit/YUV420SP10bit(YUV-8bits out)
Support output of
ARGB/RGB888/RGB565/RGB4444/RGB5551/YUV420/YUV422/YUYV；
Pixel Format conversion, BT.601/BT.709
Dither operation, Y dither update;
Max resolution: 8192x8192 source, 4096x4096 destination
Scaling
Down-scaling: Average filter
Up-scaling: Bi-cubic filter(source>2048 would use Bi-linear)
Arbitrary non-integer scaling ratio，from 1/16 to 16
Rotation
0, 90, 180, 270 degree rotation
x-mirror, y-mirror& rotation operation
BitBLT
Block transfer
Color palette/Color fill, support with alpha
Transparency mode (color keying/stencil test, specified value/value range)
Two source BitBLT:
A+B=B only BitBLT, A support rotate&scale when B fixed
A+B=C second source (B) has same attribute with (C) plus rotation function
Alpha Blending
New comprehensive per-pixel alpha(color/alpha channel separately)
Fading
SRC1(R2Y)&&SRC0(YUV)—alpha->DST(YUV)
1.2.11 Video input interface
Interface and video input processor
Support up to 16bit DVP interface (digital parallel input)
Support MIPI CSI RX interface
Support VICAP block(Video Input Processor)
Support video data from DVP
Support video data from MIPI CSI
Support DVP and MIPI CSI simultaneously
Support ISP block(Image Signal Processor)
Support video data from DVP
Support video data from MIPI CSI
DVP Interface
Support 8bits/10bits/12bits/16bits input
Support up to 150MHz input data
MIPI CSI RX Interface
Compatible with the MIPI Alliance Interface specification v1.2
Up to 4 data lanes, 2.5Gbps maximum data rate per lane
Support MIPI-HS, MIPI-LP mode
Support two mode
One interface with 1 clock lane and 4 data lanes
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Two interface, each with 1 clock lane and 2 data lanes
VICAP
Support
Support
Support
Support
Support
Support
Support
Support
Support
Support
Support
Support
ISP
DVP input: ITU-R BT601/656/1120 with raw8/raw10/raw12/raw16, YUV422
MIPI input: RX data lane x1/x2/x4, raw8/raw10/raw12, YUV422
3A: include AE/Histogram, AF, AWB statistics output
FPN: Fixed Pattern Noise removal
BLC: Black Level Correction
DPCC: Static/Dynamic defect pixel cluster correction
LSC: Lens shading correction
Bayer-2DNR: Bayer-raw De-noising, 2DNR
Bayer-3DNR: Bayer-raw De-noising, 3DNR
HDR: 2-Frame Merge into High-Dynamic Range
DRC: 2-Frame Merge Video Tone mapping
Debayer: Advanced Adaptive Demosaic with Chromatic Aberration Correction
CCM/CSM: Color correction matrix; RGB2YUV etc.
Gamma: Gamma out correction
Dehaze/Enhance: Automatic Dehaze and edge enhancement
3DLUT: 3D-Lut Color Palette for Customer
LDCH: Lens-distortion in the horizontal direction
2DNR: Advanced Spatial Noise reduce in YUV
Sharp: Picture Sharpening & Edge Enhance in YUV
CGC: Color Gamut Compression, YUV full range/limit range convert
Output Scale*2
Maximum resolution is 4096x2304
BT601 YCbCr 422 8bits input、RAW 8/10/12bits input
BT656 YCbCr 422 8bits input
BT1120 YCbCr 422 8/10/12/16bits input, single/dual-edge sampling
2/4 mixed BT656/BT1120 YCbCr 422 8bit input
YUYV sequence configurable
the polarity of pixel_clk, hsync and vsync configurable
receiving CSI2 protocol data(up to four IDs)
receiving DSI protocol data(Video mode/Command mode)
window cropping
virtual stride when write to DDR
NV16/NV12 output for YUV data
compact/ non-compact output for RAW data
1.2.12 Display interface
Display interface
Support RGB Parallel Display interface
Support BT656/BT1120 interface
Support MIPI_DSI interface
Support LVDS interface
Support HDMI interface
Support eDP interface
Support EBC inteface
Support three simultaneous displays in the following interfaces
RGB/BT1120
BT656
MIPI_DSI_TX
LVDS
HDMI
eDP
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RGB/BT1120 video output interface
Support up to 1920x1080@60Hz
Support RGB(up to 8bit) format
Up to 150MHz data rate
BT656 video output interface
Support PAL and NTSC
MIPI DSI TX interface
Compatible with MIPI Alliance Interface specification v1.2
Support 2 channel DSI
Support 4 data lanes per channel
Support 2.5Gbps maximum data rate per lane
Up to 1920x1080@60Hz display output for single MIPI mode and 2560*1440@60Hz
for dual-MIPI mode
Support RGB(up to 8bit) format
LVDS interface
Compliant with the TIA/EIA-644-A LVDS specification
Support RGB888 and RGB666 input for LVDS interface
Support VESA/JEIDA LVDS data format transfer
HDMI TX interface
Single Physical Layer PHY with support for HDMI1.4 and HDMI2.0 operation
For HDMI operation, support for the following:
Up to 10 bits Deep Color modes
Up to 1080p@120Hz and 4096x2304@60Hz
3-D video formats
Support RGB/YUV(up to 10bit) format
Support HDCP1.4/2.2
eDP interface
Support 1 eDP 1.3 interface
Up to 4 physical lanes of 2.7Gbps/lane
Supports Panel Self Refresh(PSR)
Support up to 2560x1600@60Hz
Support RGB(up to 10bit) format
EBC interface
E-ink EPD compatible
Support up to 2200x1650
Support 16bit data
Up to 16 level gray scale
Up to 256 frames every scanning
1.2.13 Video Output Processor
Video inputs
Support 2 cluster layer
Support up to 4096x2160 input resolution
Support afbcd
Support RGB/YUV/YUYV format
Support scale up/down ratio 4~1/4
Support rotation
Support 2 esmart layer
Support up to 4096x2160 input resolution
Support RGB/YUV/YUYV format
Support scale up/down ratio 4~1/4
Support 4 regions
Support 2 smart layer
Support up to 4096x2160 input resolution
Support RGB format
Support 4 regions
Overlay
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Support MAX 6 layers overlay: 2 Cluster/2 ESMART/2 SMART
Support RGB/YUV domain overlay
Post process
HDR
HDR10/HDR HLG
HDR2SDR/SDR2HDR
3D-LUT/P2I/CSC/BCSH/DITHER/CABC/GAMMA/COLORBAR
Write back
Format: ARGB8888/RGB888/RGB565/YUV420
Max resolution: 1920x1080
Video outputs
Video output0, up to 4096x2304@60Hz resolution
Video output1, up to 2048x1536@60Hz resolution
Video output2, up to 1920x1080@60Hz resolution
1.2.14 Audio Interface
I2S0 with 8 channel
Up to 8 channels TX and 8 channels RX path
Audio resolution from 16bits to 32bits
Sample rate up to 192KHz
Provides master and slave work mode, software configurable
Support 3 I2S formats (normal, left-justified, right-justified)
Only for HDMI
I2S1 with 8 channel
Up to 8 channels TX and 8 channels RX path
Audio resolution from 16bits to 32bits
Sample rate up to 192KHz
Provides master and slave work mode, software configurable
Support 3 I2S formats (normal, left-justified, right-justified)
Support 4 PCM formats (early, late1, late2, late3)
I2S and PCM mode cannot be used at the same time
I2S2/I2S3 with 2 channel
Up to 2 channels for TX and 2 channels RX path
Audio resolution from 16bits to 32bits
Sample rate up to 192KHz
Provides master and slave work mode, software configurable
Support 3 I2S formats (normal, left-justified, right-justified)
Support 4 PCM formats (early, late1, late2, late3)
I2S and PCM cannot be used at the same time
PDM
Up to 8 channels
Audio resolution from 16bits to 24bits
Sample rate up to 192KHz
Support PDM master receive mode
TDM
supports up to 8 channels for TX and 8 channels RX path
Audio resolution from 16bits to 32bits
Sample rate up to 192KHz
Provides master and slave work mode, software configurable
Support 3 I2S formats (normal, left-justified, right-justified)
Support 4 PCM formats (early, late1, late2, late3)
Digital Audio Codec
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Support 3 channels digital ADC
Support 2 channels digital DAC
Support I2S/PCM interface
Support I2S/PCM master and slave mode
Support 4 channels audio transmitting in I2S mode
Support 2 channels audio receiving in I2S mode
Support 2 channels audio transmitting or receiving in PCM mode
Support 16~24 bits sample resolution for both digital ADC and digital DAC
Both digital ADC and digital DAC support three groups of sample rates. Group 0 are
8KHz/16KHz/32KHz/64KHz/128KHz, group 1 are
11.025KHz/22.05KHz/44.1KHz/88.2KHz/176.4KHz and group 2 are
12KHz/24KHz/48KHz/96KHz/192KHz
Voice Activity Detection(VAD)
Support read voice data from I2S/PDM
Support voice amplitude detection
Support Multi-Mic array data storing
Support a level combined interrupt
1.2.15 Connectivity
SDIO interface
Compatible with SDIO3.0 protocol
4bits data bus widths
MAC 10/100/1000 Ethernet Controller
Support two identical Ethernet controllers
Support 10/100/1000 Mbps data transfer rates with the RGMII interfaces
Support 10/100 Mbps data transfer rates with the RMII interfaces
Support both full-duplex and half-duplex operation
Supports IEEE 802.1Q VLAN tag detection for reception frames
Support detection of LAN wake-up frames and AMD Magic Packet frames
Support checking IPv4 header checksum and TCP, UDP, or ICMP checksum
encapsulated in IPv4 or IPv6 datagram
Support for TCP Segmentation Offload (TSO) and UDP Fragmentation Offload (UFO)
USB 2.0 Host
Support two USB2.0 Host
Compatible with USB 2.0 specification
Supports high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
Support Enhanced Host Controller Interface Specification (EHCI), Revision 1.0
Support Open Host Controller Interface Specification (OHCI), Revision 1.0a
Multi-PHY Interface
Support three multi-PHYs with PCIe2.1/SATA3.0/USB3.0/QSGMII controller
Up to one USB3 Host controller
Up to one USB3 OTG controller
Up to one PCIe2.1 controller
Up to three SATA controller
Up to one QSGMII or SGMII PCS controller
Multi-PHY0 support one of the following interfaces
USB3.0 OTG
SATA0
Multi-PHY1 support one of the following interfaces
USB3.0 Host
SATA1
QSGMII/SGMII
Multi-PHY2 support one of the following interfaces
PCIe2.1
SATA2
Copyright 2022 © Rockchip Electronics Co., Ltd.
15
RK3568J Datasheet
Rev 1.0
QSGMII/SGMII
USB 3.0 xHCI Host Controller
Support 1 USB2.0 port and 1 Super-Speed port
Concurrent USB3.0/USB2.0 traffic, up to 8.48Gbps bandwidth
Support standard or open-source xHCI and class driver
USB 3.0 Dual-Role Device (DRD) Controller
Static USB3.0 Device
Static USB3.0 xHCI host
USB3.0/USB2.0 OTG A device and B device basing on ID
PCIe2.1 interface
Compatible with PCI Express Base Specification Revision 3.0
Support Root Complex(RC) mode
Support 2.5Gbps and 5.0Gbps serial data transmission rate per lane per
direction
Support one lane
SATA interface
Compatible with Serial ATA 3.3 and AHCI Revision 1.3.1
Support eSATA
Support 1.5Gb/s, 3.0Gb/s, 6.0Gb/s
Support 3 SATA controller
QSGMII/SGMII interface
Support one QSGMII, only two GMII controller supported
Support SGMII mode with 1000Mbps
PCIe3.0 PHY Interface
Support PCIe3.1(8Gbps) protocol and backward compatible with the PCIe2.1 and
PCIe1.1 protocol
Support two lane
Support two PCIe controller with x1 mode or one PCIe controller with x2 mode
Two lane PCIe3.0 controller
Compatible with PCI Express Base Specification Revision 3.0
Dual operation mode: Root Complex(RC)and End Point(EP)
Support 2.5Gbps, 5.0Gbps and 8.0Gbps serial data transmission rate per lane
per direction
Support two lanes
One lane PCIe3.0 controller
Compatible with PCI Express Base Specification Revision 3.0
Support Root Complex(RC) mode
Support 2.5Gbbps, 5.0Gbps and 8.0Gbps serial data transmission rate per lane
per direction
Support one lane
SPI interface
Support four SPI Controller
Support one chip-select output and the other support two chip-select output
Support serial-master and serial-slave mode, software-configurable
I2C interface
Support six I2C interface
Support 7bits and 10bits address mode
Software programmable clock frequency
Data on the I2C-bus can be transferred at rates of up to 100Kbit/s in the Standardmode, up to 400Kbit/s in the Fast-mode or up to 1 Mbit/s in Fast-mode Plus.
UART Controller
Support ten UART interfaces
Embedded two 64-byte FIFO for TX and RX operation respectively
Copyright 2022 © Rockchip Electronics Co., Ltd.
16
RK3568J Datasheet
Rev 1.0
Support 5bits,6bits,7bits,8bits serial data transmit or receive
Standard asynchronous communication bits such as start, stop and parity
Support different input clock for UART operation to get up to 4Mbps baud rate
Support auto flow control mode for UART0/UART1/UART3/UART4/UART5
Smart Card
Support ISO-7816
support card activation and deactivation
support cold/warm reset
support Answer to Reset(ATR) response reception
support T0 for asynchronous half-duplex character transmission
support T1 for asynchronous half-duplex block transmission
support automatic operating voltage class selection
support adjustable clock rate and bit (baud) rate
support configurable automatic byte repetition
PWM
Sixteen on-chip PWMs(PWM0~PWM15) with interrupt-based operation
Programmable pre-scaled operation to bus clock and then further scaled
Embedded 32bits timer/counter facility
Support capture mode
Support continuous mode or one-shot mode
Provides reference mode and output various duty-cycle waveform
Optimized for IR application for PWM3,PWM7,PWM11 and PWM15
1.2.16 Others
Multiple group of GPIO
All of GPIOs can be used to generate interrupt to CPU
Support level trigger and edge trigger interrupt
Support configurable polarity of level trigger interrupt
Support configurable rising edge, falling edge and both edge trigger interrupt
Temperature Sensor(TSADC)
Up to 50KS/s sampling rate
Support two temperature sensor
-20~120℃ temperature range and 5℃ temperature resolution
Support two channels
Successive Approximation ADC (SARADC)
10bits resolution
Up to 1MS/s sampling rate
8 single-ended input channels
OTP
Support 8K bits Size, 7K bits for secure application
Support Program/Read/Idle mode
Package Type
FCCSP636L (body: 19mm x 19mm; ball size: 0.35mm; ball pitch: 0.65mm)
Notes:
DDR3/DDR3L/DDR4/LPDDR3/LPDDR4/LPDDR4X are not used simultaneously
LVDS interface can not be used when dual-mipi mode enable
Copyright 2022 © Rockchip Electronics Co., Ltd.
17
RK3568J Datasheet
Rev 1.0
1.3 Block Diagram
The following diagram shows the basic block diagram.
Clock & Reset
RK3568J
WDT
Cortex-A55 Quad-Core
System
PLL x9
Timer x6
Secure Timer x2
PMU
Connectivity
PCIe3.0 1x2/2x1 Lane
Core0
32KB L1 I-Cache
Core1
32KB L1 I-Cache
32KB L1 D-Cache with ECC
32KB L1 D-Cache with ECC
NOEN/FPU/Crypto
NOEN/FPU/Crypto
PCIe2.1 x1/SATA3.0 x3
/USB3 HOST x1/USB3
OTG x1/QSGMII x1,
Share 3 Serdes Lanes
USB2.0 HOSTx2
Crypto
Core2
32KB L1 I-Cache
Core3
32KB L1 I-Cache
I2S/TDM(8ch) x2, one
for HDMI
Interrupt Controller
32KB L1 D-Cache with ECC
32KB L1 D-Cache with ECC
I2S/PCM(2ch) x2
NOEN/FPU/Crypto
NOEN/FPU/Crypto
DMAC x2
SARADC x8
512KB L3-Cache with ECC
Audio PWM
TSADC
MCU
VOP
(Three Display Port,
2HD for LCD/HDMI,
1SD for BT656 to CVBS)
Digital Acodec
NPU
VAD
Multi-Media Processor
Mailbox
Multi-Media Interface
PDM(8ch)
SPDIF(8ch)
ISO7816
4K Video Decoder
GPU Mali-G52-2EE
1080p Video Encoder
2D Graphics Engine
JPEG Codec
IEP
8M ISP
UART x10
SPI x4
SDIO 3.0
Ethernet GMAC x2
(10/100/1000M)
HDMI2.0a
I2C x6
eDP1.3
CAN x3
Single LVDS/
Dual MIPI-DSI_TX
Parallel RGB Interface
E-Ink Interface
16bits Camera I/F
MIPI-CSI_RX 4 Lane
External Memory Interface
eMMC 5.1
Nor Flash /Async SRAM
SD3.0/MMC4.51
SDR/DDR/LBA Nand Flash
32Bit DDR Controller
(DDR3/DDR3L/DDR4 with ECC)
(LPDDR3/LPDDR4/LPDDR4X)
PWM x16
GPIO x152
Embedded Memory
SRAM (64KB)
ROM (32KB)
OTP(8K bit)
Fig.1-1 Block Diagram
Copyright 2022 © Rockchip Electronics Co., Ltd.
18
RK3568J Datasheet
Rev 1.0
Chapter 2 Package Information
2.1 Order Information
Orderable
Device
RoHS
status
Package
Package QTY
Device Feature
RK3568J
RoHS
FCCSP636L
700 pcs
Quad core application processor
2.2 Top Marking
Rockchip : Brand Name
RKXXXX : Part Number
ABC
: Internal Control Code
XXXXXX : Die Lot NO # maybe
letter
YYWW : Date Code
NXXXXXX FXX: Sub-lot info in
OSAT
The first pin
Fig.2-1 Package definition
2.3 FCCSP636L Dimension
Fig.2-2 Package Top View
Copyright 2022 © Rockchip Electronics Co., Ltd.
19
RK3568J Datasheet
Rev 1.0
Fig.2-3 Package bottom view
Fig.2-4 Package side view
Copyright 2022 © Rockchip Electronics Co., Ltd.
20
RK3568J Datasheet
Rev 1.0
Fig.2-5 Package dimension
Copyright 2022 © Rockchip Electronics Co., Ltd.
21
RK3568J Datasheet
Rev 1.0
2.4 Ball Map
A
1
2
VSS_1
DDR4_CS0n/LPDDR
4_CS0n_A/DDR3_O
DT1/LPDDR3_ODT0/
AC25
3
VSS_2
4
B
DDR4_CS1n/LPDDR DDR4_CKE/LPDDR DDR4_CLKP/LPDD
DDR4_A2/LPDDR4_
4_CS1n_A/DDR3_C 4_CKE0_A/DDR3_C R4_CLKP_A/DDR3_
A1_A/DDR3_A4/LP
S1n/LPDDR3_ODT1/ KE/LPDDR3_CKE/A CLKP/LPDDR3_CLK
DDR3_A6/AC2
AC26
C22
P/AC23
C
DDR4_A8/LPDDR4_
DDR4_A11/LPDDR4
ODT0_CA_A/DDR3_
_A0_A/DDR3_A7/LP
A6/LPDDR3_A9/AC
DDR3_A8/AC11
8
VSS_14
D
DDR_DQ3_A/DDR4_
DQL6_A/LPDDR4_D
Q3_A/DDR3_DQ3/L
PDDR3_DQ9
VSS_26
E
F
VSS_25
DDR_DQ1_A/DDR4_ DDR_DQ2_A/DDR4_
DQL2_A/LPDDR4_D DQL4_A/LPDDR4_D
Q1_A/DDR3_DQ1/L Q2_A/DDR3_DQ2/L
PDDR3_DQ14
PDDR3_DQ10
DDR_DQ0_A/DDR4_
DQL0_A/LPDDR4_D
Q0_A/DDR3_DQ0/L
PDDR3_DQ15
VSS_31
G
DDR_DQS0P_A/DD DDR_DQS0N_A/DD
R4_DQSL_P_A/LPD R4_DQSL_N_A/LPD
DR4_DQS0P_A/DD DR4_DQS0N_A/DD
R3_DQS0P/LPDDR3 R3_DQS0N/LPDDR3
_DQS1P
_DQS1N
H
DDR_DQ6_A/DDR4_
DQL3_A/LPDDR4_D
Q6_A/DDR3_DQ6/L
PDDR3_DQ8
J
DDR_DQ4_A/DDR4_ DDR_DQ5_A/DDR4_
DQL7_A/LPDDR4_D DQL5_A/LPDDR4_D
Q4_A/DDR3_DQ4/L Q5_A/DDR3_DQ5/L
PDDR3_DQ13
PDDR3_DQ12
K
L
VSS_59
VSS_49
DDR_DQ12_A/DDR4
_DQU2_A/LPDDR4_
DQ12_A/DDR3_DQ1
2/LPDDR3_DQ26
DDR_DQS1N_A/DD DDR_DQS1P_A/DD
R4_DQSU_N_A/LPD R4_DQSU_P_A/LPD
DR4_DQS1N_A/DD DR4_DQS1P_A/DD
R3_DQS1N/LPDDR3 R3_DQS1P/LPDDR3
_DQS3N
_DQS3P
5
DDR4_CLKN/LPDD
DDR4_A9/LPDDR4_
R4_CLKN_A/DDR3_
CLKN_B/DDR3_A5/CLKN/LPDDR3_CLK
/AC9
N/AC24
VSS_8
DDR4_A14_WEn/LP
DDR4_A12/LPDDR4
DDR4_A4_A/DDR3_
_A3_A/DDR3_BA2/A15/LPDDR3_A5/A
/AC12
C14
NP
6
VSS_3
7
DDR4_A0/LPDDR4_ DDR4_A5/LPDDR4_ DDR4_A13/LPDDR4
CLKP_B/DDR3_A9/- A5_B/DDR3_A11/LP _A0_B/DDR3_A14/L
/AC0
DDR3_A2/AC5
PDDR3_A0/AC13
VSS_15
DDR4_A16_RASn/L
DDR4_A10/LPDDR4
PDDR4_A5_A/DDR3
_CKE0_B/DDR3_A1
_RASn/LPDDR3_A7
0/-/AC10
/AC16
NP
NP
VSS_29
DDR4_A15_CASn/L
PDDR4_A2_A/DDR3
_A0/-/AC15
NP
DDR4_ACTn/LPDDR
4_CKE1_B/DDR3_C
ASn/-/AC17
VSS_32
DDR4_A3/LPDDR4_
CKE1_A/DDR3_A3//AC3
DDR4_A1//DDR3_A2/-/AC1
NP
NP
NP
VSS_38
VSS_39
NP
VSS_51
DDR_RZQ
VSS_50
DDR_DQ7_A/DDR4_ DDR_DM0_A/DDR4
DQL1_A/LPDDR4_D _DML_A/LPDDR4_D
Q7_A/DDR3_DQ7/L M0_A/DDR3_DM0/L
PDDR3_DQ11
PDDR3_DM1
VSS_52
DDR_DM1_A/DDR4
_DMU_A/LPDDR4_
DM1_A/DDR3_DM1/
LPDDR3_DM3
VSS_53
NP
NP
NP
VSS_65
DDR_DQ15_A/DDR4
_DQU0_A/LPDDR4_
DQ15_A/DDR3_DQ1
5/LPDDR3_DQ27
VSS_66
8
VSS_30
VSS_16
10
NP
DDR_DQ11_A/DDR4 DDR_DQ10_A/DDR4
_DQU5_A/LPDDR4_ _DQU7_A/LPDDR4_
DQ11_A/DDR3_DQ1 DQ10_A/DDR3_DQ1
1/LPDDR3_DQ29
0/LPDDR3_DQ28
VSS_9
VSS_17
DDR4_ODT1/LPDDR
DDR4_A4/LPDDR4_
4_CS0n_B/DDR3_C
A3_B/DDR3_BA1/L
S0n/LPDDR3_CS0n/
PDDR3_A3/AC4
AC28
VSS_4
11
12
13
14
DDR_DQS0P_B/DD
DDR_DQ4_B/DDR4_ DDR_DQ13_B/DDR4
R4_DQSU_P_B/LPD
DQU0_B/LPDDR4_D _DQL5_B/LPDDR4_
DR4_DQS0P_B/DD
Q4_B/DDR3_DQ20/ DQ13_B/DDR3_DQ2
R3_DQS2P/LPDDR3
LPDDR3_DQ2
9/LPDDR3_DQ17
_DQS0P
DDR_DQS0N_B/DD
DDR_DQ0_B/DDR4_
R4_DQSU_N_B/LPD
DQU7_B/LPDDR4_D
DR4_DQS0N_B/DD
Q0_B/DDR3_DQ16/
R3_DQS2N/LPDDR3
LPDDR3_DQ1
_DQS0N
VSS_5
15
16
DDR_DQS1P_B/DD
DDR_DQ12_B/DDR4 DDR_DQ15_B/DDR4
R4_DQSL_P_B/LPD
_DQL7_B/LPDDR4_ _DQL3_B/LPDDR4_
DR4_DQS1P_B/DD
DQ12_B/DDR3_DQ2 DQ15_B/DDR3_DQ3
R3_DQS3P/LPDDR3
8/LPDDR3_DQ16
1/LPDDR3_DQ21
_DQS2P
VSS_10
NP
VSS_18
VSS_19
NP
NP
VSS_27
DDR_DQ2_B/DDR4_
DQU3_B/LPDDR4_D
Q2_B/DDR3_DQ18/
LPDDR3_DQ6
NP
VSS_20
17
DDR_DQS1N_B/DD
DDR_DQ8_B/DDR4_ DDR_DQ10_B/DDR4
R4_DQSL_N_B/LPD
DQL0_B/LPDDR4_D _DQL4_B/LPDDR4_
DR4_DQS1N_B/DD
Q8_B/DDR3_DQ24/ DQ10_B/DDR3_DQ2
R3_DQS3N/LPDDR3
LPDDR3_DQ18
6/LPDDR3_DQ22
_DQS2N
VSS_21
VSS_11
NP
VSS_6
19
20
21
22
23
24
VSS_12
EMMC_D2/FLASH_ EMMC_D7/FLASH_
D2/GPIO1_B6_u
D7/GPIO1_C3_u
NP
I2S1_LRCK_RX_M0/
UART4_TX_M0/PDM
EMMC_D1/FLASH_
_CLK0_M0/AUDIOP
D1/GPIO1_B5_u
WM_ROUT_P/GPIO
1_A6_d
NP
FSPI_CS0n/FLASH_ FSPI_D0/FLASH_R
CS0n/GPIO1_D3_u
DY/GPIO1_D1_u
NP
I2S1_SDO1_M0/I2S
1_SDI3_M0/PDM_S
DI3_M0/PCIE20_CL EMMC_D3/FLASH_
KREQn_M2/ACODE D3/GPIO1_B7_u
C_DAC_DATAR/GPI
O1_B0_d
NP
FSPI_D1/FLASH_R
Dn/GPIO1_D2_u
I2C3_SCL_M0/UART
DDR_DM1_B/DDR4
3_TX_M0/CAN1_TX_
_DML_B/LPDDR4_D
M0/AUDIOPWM_LO
M1_B/DDR3_DM3/L
UT_N/ACODEC_AD
PDDR3_DM2
C_CLK/GPIO1_A1_u
VSS_22
VSS_23
I2C3_SDA_M0/UAR
DDR_DQ14_B/DDR4 T3_RX_M0/CAN1_R
_DQL1_B/LPDDR4_ X_M0/AUDIOPWM_
DQ14_B/DDR3_DQ3 LOUT_P/ACODEC_
0/LPDDR3_DQ20 ADC_DATA/GPIO1_
A0_u
SARADC_VIN2
NP
DDR_DQ3_B/DDR4_
DDR4_BA0/LPDDR4
DQU1_B/LPDDR4_D
_A2_B/DDR3_A1/Q3_B/DDR3_DQ19/
/AC18
LPDDR3_DQ4
NP
VSS_33
NP
DDR4_RESETn/LPD
DR4_RESETn/DDR3
_RESETn/AC29
VSS_34
NP
VSS_35
VSS_36
NP
VSS_37
I2S1_SCLK_RX_M0/
UART4_RX_M0/PD
M_CLK1_M0/SPDIF
_TX_M0/GPIO1_A4_
d
NP
EMMC_RSTn/FSPI_
D2/FLASH_WPn/GP
IO1_C7_d
SARADC_VIN7
SARADC_VIN5
NP
VSS_40
VSS_41
NP
VSS_42
VSS_43
NP
VSS_44
VSS_45
NP
VSS_46
VSS_47
NP
SARADC_VIN6
SARADC_VIN4
NP
I2S2_MCLK_M0/ET
H0_REFCLKO_25M/
UART7_RTSn_M0/S
PI2_CLK_M0/GPIO2
_C1_d
NP
DDRPHY_VDDQ_1
NP
DDRPHY_VDDQ_2
DDRPHY_VDDQ_3
NP
DDRPHY_VDDQ_4
DDRPHY_VDDQ_5
NP
VCCIO1
VCCIO2
NP
OTP_VCC18
NP
DDR_AVSS
DDRPHY_VDDQ_6
NP
DDRPHY_VDDQL_1 DDRPHY_VDDQL_2
NP
DDRPHY_VDDQL_3
VDD_CPU_1
NP
VSS_54
VSS_55
NP
VSS_56
VCCIO4
VSS_57
NP
NP
DDRPHY_VDDQL_4
VSS_60
VSS_61
VSS_62
VSS_63
VDD_CPU_2
VDD_CPU_3
VDD_CPU_4
VDD_CPU_5
VSS_64
NP
NP
NP
NP
NP
DDRPHY_VDDQ_7 DDRPHY_VDDQL_5
VSS_68
VDD_LOGIC_1
VSS_69
VSS_70
VDD_CPU_6
VDD_CPU_7
VDD_CPU_8
VDD_CPU_9
VSS_71
VSS_72
VSS_73
VCCIO3
USB3_OTG0_ID
AVSS_2
DDR4_ODT0/LPDDR
DDR4_BA1/LPDDR4
4_CS1n_B/DDR3_O
_A4_B/DDR3_A12/L
DT0/LPDDR3_CS1n/
PDDR3_A4/AC19
AC27
VSS_67
NP
DDR_DQ7_B/DDR4_ DDR_DQ6_B/DDR4_
DQU2_B/LPDDR4_D DQU4_B/LPDDR4_D
Q7_B/DDR3_DQ23/ Q6_B/DDR3_DQ22/
LPDDR3_DQ0
LPDDR3_DQ7
NP
25
26
27
I2S1_LRCK_TX_M0/
I2S1_MCLK_M0/UA
I2S1_SDO3_M0/I2S
UART4_RTSn_M0/S
EMMC_DATA_STR
RT3_RTSn_M0/SCR
1_SDI1_M0/PDM_S
EMMC_CLKOUT/FL
CR_RST/PCIE30X1_
FSPI_CLK/FLASH_
EMMC_D0/FLASH_ EMMC_D4/FLASH_ OBE/FSPI_CS1n/FL FSPI_D3/FLASH_C
_CLK/PCIE30X1_PE
DI1_M0/PCIE20_PE
ASH_DQS/GPIO1_C
CLKREQn_M2/ACO
ALE/GPIO1_D0_d
D0/GPIO1_B4_u
D4/GPIO1_C0_u
ASH_CLE/GPIO1_C S1n/GPIO1_D4_u
RSTn_M2/GPIO1_A
RSTn_M2/GPIO1_B
5_d
DEC_DAC_SYNC/G
6_d
2_d
2_d
PIO1_A5_d
I2S1_SCLK_TX_M0/ I2S1_SDO0_M0/UA
DDR_DQ9_B/DDR4_ DDR_DQ11_B/DDR4 UART3_CTSn_M0/S RT4_CTSn_M0/SCR
I2S1_SDI0_M0/PDM EMMC_CMD/FLAS
DQL2_B/LPDDR4_D _DQL6_B/LPDDR4_ CR_IO/PCIE30X1_W _DET/AUDIOPWM_
_SDI0_M0/GPIO1_B H_WRn/GPIO1_C4_
Q9_B/DDR3_DQ25/ DQ11_B/DDR3_DQ2 AKEn_M2/ACODEC ROUT_N/ACODEC_
3_d
u
LPDDR3_DQ19
7/LPDDR3_DQ23 _DAC_CLK/GPIO1_ DAC_DATAL/GPIO1
A3_d
_A7_d
NP
DDR_DM0_B/DDR4 DDR_DQ5_B/DDR4_
_DMU_B/LPDDR4_ DQU6_B/LPDDR4_D
DM0_B/DDR3_DM2/ Q5_B/DDR3_DQ21/
LPDDR3_DM0
LPDDR3_DQ3
18
I2S1_SDO2_M0/I2S
1_SDI2_M0/PDM_S
DI2_M0/PCIE20_WA EMMC_D5/FLASH_ EMMC_D6/FLASH_
KEn_M2/ACODEC_ D5/GPIO1_C1_u
D6/GPIO1_C2_u
ADC_SYNC/GPIO1_
B1_d
DDR4_BG1/LPDDR4 DDR4_BG0/LPDDR4
_ODT1_CA_A/DDR3 _ODT1_CA_B/DDR3
_BA0/-/AC21
_WEn/-/AC20
DDR_DQ13_A/DDR4 DDR_DQ14_A/DDR4
_DQU4_A/LPDDR4_ _DQU6_A/LPDDR4_
DQ13_A/DDR3_DQ1 DQ14_A/DDR3_DQ1
3/LPDDR3_DQ31
4/LPDDR3_DQ30
NP
9
DDR_DQ1_B/DDR4_
DDR4_A6/LPDDR4_ DDR4_A7/LPDDR4_
DQU5_B/LPDDR4_D
A1_B/DDR3_A13/LP ODT0_CA_B/DDR3_
Q1_B/DDR3_DQ17/
DDR3_A1/AC6
A8/-/AC7
LPDDR3_DQ5
SARADC_VIN3
NP
VSS_24
NP
VSS_13
SARADC_VIN1
28
A
VSS_7
SDMMC1_D2/GMA
C0_RXCLK/UART7_
RX_M0/GPIO2_A5_u
B
SDMMC1_D3/GMA SDMMC1_CMD/GM
C0_TXD2/UART7_TX AC0_TXD3/UART9_
_M0/GPIO2_A6_u RX_M0/GPIO2_A7_u
C
SARADC_VIN0
SDMMC1_PWREN/I SDMMC1_CLK/GM
2C4_SDA_M1/UART AC0_TXCLK/UART9
8_RTSn_M0/CAN2_ _TX_M0/GPIO2_B0_
RX_M1/GPIO2_B1_d
d
D
VSS_28
SDMMC1_DET/I2C4
CLK32K_OUT1/UAR SDMMC1_D0/GMA SDMMC1_D1/GMA
_SCL_M1/UART8_C
T8_RX_M0/SPI1_CS C0_RXD2/UART6_R C0_RXD3/UART6_TX
TSn_M0/CAN2_TX_
1_M0/GPIO2_C6_d X_M0/GPIO2_A3_u _M0/GPIO2_A4_u
M1/GPIO2_B2_u
E
I2S2_LRCK_RX_M0/ I2S2_SCLK_TX_M0/
I2S2_SDI_M0/GMA GMAC0_RXD0/UAR
GMAC0_RXDV_CRS GMAC0_MCLKINOU
GMAC0_TXD0/UART
C0_RXER/UART8_T T1_CTSn_M0/SPI1_
/UART6_CTSn_M0/ T/UART7_CTSn_M0/
1_RX_M0/GPIO2_B3
X_M0/SPI2_CS1_M0 MISO_M0/GPIO2_B
SPI1_CS0_M0/GPIO SPI2_MISO_M0/GPI
_u
/GPIO2_C5_d
6_u
2_C0_d
O2_C2_d
F
GMAC0_TXEN/UAR
GMAC0_TXD1/UART
T1_RTSn_M0/SPI1_
1_TX_M0/GPIO2_B4
CLK_M0/GPIO2_B5
_u
_u
G
I2S2_LRCK_TX_M0/ I2S2_SCLK_RX_M0/
I2S2_SDO_M0/GMA
SDMMC0_D2/ARMJ SDMMC0_CMD/PW SDMMC0_CLK/TES
GMAC0_MDC/UART GMAC0_RXD1/UAR
SARADC_AVDD_1V C0_MDIO/UART9_C
TAG_TCK/UART5_C M10_M1/UART5_RX T_CLKOUT/UART5_
9_RTSn_M0/SPI2_M T6_RTSn_M0/SPI1_
8
TSn_M0/SPI2_CS0_
TSn_M0/GPIO1_D7_ _M0/CAN0_TX_M1/ TX_M0/CAN0_RX_M
OSI_M0/GPIO2_C3_ MOSI_M0/GPIO2_B
M0/GPIO2_C4_d
u
GPIO2_A1_u
1/GPIO2_A2_d
d
7_d
H
VSS_48
NP
SDMMC0_D3/ARMJ SDMMC0_D1/UART SDMMC0_D0/UART
TAG_TMS/UART5_R 2_RX_M1/UART6_R 2_TX_M1/UART6_TX
TSn_M0/GPIO2_A0_ X_M1/PWM9_M1/G _M1/PWM8_M1/GPI
u
PIO1_D6_u
O1_D5_u
NP
VSS_58
AVSS_1
EDP_TX_D0P
J
NP
NP
EDP_TX_D0N
EDP_TX_D1P
K
EDP_TX_AUXP
AVSS_3
EDP_TX_D1N
EDP_TX_D2P
L
M
DDR_DQ8_A/DDR4_
DQU3_A/LPDDR4_D
Q8_A/DDR3_DQ8/L
PDDR3_DQ25
VSS_74
VSS_75
DDR_ECC_DQ1
DDR_ECC_DQ2
VSS_76
DDR_ECC_DQ4
VSS_77
VSS_78
VDD_LOGIC_2
VSS_79
VSS_80
VDD_CPU_COM
VSS_81
VDD_CPU_10
VSS_82
VDD_NPU_1
EDP_TX_AVDD_0V9
AVSS_4
EDP_TX_AUXN
AVSS_5
EDP_TX_D2N
EDP_TX_D3P
M
N
VSS_83
DDR_DQ9_A/DDR4_
DQU1_A/LPDDR4_D
Q9_A/DDR3_DQ9/L
PDDR3_DQ24
NP
NP
NP
NP
NP
NP
NP
SYSPLL_AVDD_1V
8
SYSPLL_AVSS
VSS_84
VDD_LOGIC_3
VSS_85
VSS_86
VDD_LOGIC_4
VSS_87
VSS_88
VDD_NPU_2
NP
NP
NP
NP
NP
NP
NP
EDP_TX_D3N
AVSS_6
N
P
DDR_ECC_DQS_N
DDR_ECC_DQS_P
VSS_89
DDR_ECC_DQ6
DDR_ECC_DQ0
VSS_90
DDR_ECC_DM
DDR_VREFOUT
USB2_AVDD_1V8
USB2_AVDD_3V3
SYSPLL_AVDD_0V
9
VSS_91
VDD_LOGIC_5
VSS_92
VSS_93
VDD_LOGIC_6
VSS_94
VDD_NPU_3
VDD_NPU_4
VDD_NPU_5
AVSS_7
USB3_AVDD_0V9
USB3_AVDD_1V8
USB3_HOST1_DP
USB3_HOST1_DM
AVSS_8
USB3_OTG0_DP
USB3_OTG0_DM
P
DDRPHY_VDDQ_8 DDRPHY_VDDQL_6
R
USB2_HOST2_DM
USB2_HOST2_DP
VSS_95
DDR_ECC_DQ7
DDR_ECC_DQ3
VSS_96
DDR_ECC_DQ5
USB2_AVDD_0V9
VCCIO6_1
VSS_97
VSS_98
VDD_LOGIC_7
VDD_GPU_1
VSS_99
VSS_100
VDD_LOGIC_8
VSS_101
VSS_102
VSS_103
T
USB2_HOST3_DM
USB2_HOST3_DP
NP
NP
NP
NP
NP
NP
NP
VSS_104
VSS_105
VDD_LOGIC_9
VDD_GPU_2
VSS_106
VSS_107
VDD_LOGIC_10
VSS_108
VSS_109
VSS_110
U
VSS_111
VSS_112
VSS_113
VSS_114
VCCIO6_2
VSS_115
VDD_GPU_3
VDD_GPU_4
VDD_GPU_5
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
PCIE30_RESREF
VSS_122
VSS_123
VCCIO5_1
VCCIO5_2
VCCIO7
VSS_124
AVSS_13
AVSS_14
AVSS_15
CIF_CLKIN/EBC_SD
CIF_HREF/EBC_SD
CLK/GMAC1_MCLKI
CIF_VSYNC/EBC_S
CIF_CLKOUT/EBC_
LE/GMAC1_MDC_M
NOUT_M1/UART1_C
DOE/GMAC1_MDIO
GDCLK/PWM11_IR_
1/UART1_RTSn_M1/
TSn_M1/I2S2_SCLK
_M1/I2S2_SCLK_TX
M1/GPIO4_C0_d
I2S2_MCLK_M1/GPI
_RX_M1/GPIO4_C1_
_M1/GPIO4_B7_d
O4_B6_d
d
V
I2C4_SCL_M0/EBC_ ISP_PRELIGHT_TRI
GDOE/ETH1_REFC G/EBC_SDCE3/GM
LKO_25M_M1/SPI3 AC1_RXDV_CRS_M
_CLK_M0/I2S2_SD 1/I2S1_SDO2_M1/G
O_M1/GPIO4_B3_d
PIO4_B1_d
W
ISP_FLASHTRIGOU
CAM_CLKOUT0/EB
T/EBC_SDCE0/GM
C_SDCE1/GMAC1_
AC1_TXEN_M1/SPI3
RXD0_M1/SPI3_CS1
_CS0_M0/I2S1_SCL
_M0/I2S1_LRCK_RX
K_RX_M1/GPIO4_A
_M1/GPIO4_A7_d
6_d
Y
VSS_121
NP
I2C4_SDA_M0/EBC
I2C2_SDA_M1/EBC CAM_CLKOUT1/EB
I2C2_SCL_M1/EBC_
_VCOM/GMAC1_RX
_GDSP/CAN2_RX_ C_SDCE2/GMAC1_
SDSHR/CAN2_TX_
ER_M1/SPI3_MOSI
M0/ISP_FLASH_TRI RXD1_M1/SPI3_MIS
M0/I2S1_SDO3_M1/
_M0/I2S2_SDI_M1/
GIN/VOP_BT656_CL O_M0/I2S1_SDO1_
GPIO4_B5_d
GPIO4_B2_d
K_M1/GPIO4_B4_d
M1/GPIO4_B0_d
NP
NP
AA
CIF_D6/EBC_SDDO
CIF_D11/EBC_SDD CIF_D10/EBC_SDD
6/SDMMC2_DET_M
O11/GMAC1_RXD2_ O10/GMAC1_TXCLK
0/I2S1_SDI2_M1/VO
M1/PDM_SDI1_M1/ _M1/PDM_CLK1_M
P_BT656_D6_M1/G
GPIO4_A1_d
1/GPIO4_A0_d
PIO3_D4_d
AB
CIF_D3/EBC_SDDO
3/SDMMC2_D3_M0/
I2S1_SDO0_M1/VO
P_BT656_D3_M1/G
PIO3_D1_d
AC
CIF_D5/EBC_SDDO PWM15_IR_M0/SP PWM14_M0/VOP_P LCDC_DEN/VOP_B CIF_D0/EBC_SDDO
5/SDMMC2_CLK_M DIF_TX_M1/GMAC1 WM_M1/GMAC1_M T1120_D15/SPI1_CL 0/SDMMC2_D0_M0/
0/I2S1_SDI1_M1/VO _MDIO_M0/UART7_ DC_M0/UART7_TX_ K_M1/UART5_RX_M I2S1_MCLK_M1/VO
P_BT656_D5_M1/G RX_M1/I2S1_LRCK_ M1/PDM_CLK1_M2/ 1/I2S1_SCLK_RX_M P_BT656_D0_M1/G
PIO3_D3_d
RX_M2/GPIO3_C5_d
GPIO3_C4_d
2/GPIO3_C3_d
PIO3_C6_d
AD
LCDC_HSYNC/VOP
LCDC_D23/PWM13
_BT1120_D13/SPI1_
_M0/GMAC1_MCLKI
MOSI_M1/PCIE20_
NOUT_M0/UART3_R
PERSTn_M1/I2S1_S
X_M1/PDM_SDI3_M
DO2_M2/GPIO3_C1
2/GPIO3_C0_d
_d
AE
LCDC_D19/VOP_BT LCDC_D20/VOP_BT LCDC_D21/VOP_BT
1120_D10/GMAC1_ 1120_D11/GMAC1_ 1120_D12/GMAC1_
RXER_M0/I2C5_SD TXD0_M0/I2C3_SCL TXD1_M0/I2C3_SDA
A_M0/PDM_SDI1_M _M1/PWM10_M0/G _M1/PWM11_IR_M0
2/GPIO3_B4_d
PIO3_B5_d
/GPIO3_B6_d
AF
LCDC_D18/VOP_BT LCDC_D17/VOP_BT
1120_D9/GMAC1_R 1120_D8/GMAC1_R
XDV_CRS_M0/I2C5_ XD1_M0/UART4_TX_
SCL_M0/PDM_SDI0 M1/PWM9_M0/GPI
_M2/GPIO3_B3_d
O3_B2_d
AG
LCDC_D16/VOP_BT LCDC_D15/VOP_BT LCDC_D13/VOP_BT LCDC_D10/VOP_BT
1120_D7/GMAC1_R 1120_D6/ETH1_REF 1120_CLK/GMAC1_ 1120_D2/GMAC1_T
XD0_M0/UART4_RX CLKO_25M_M0/SD TXCLK_M0/I2S3_SD XD3_M0/I2S3_SCLK
_M1/PWM8_M0/GPI MMC2_PWREN_M1 I_M0/SDMMC2_CLK _M0/SDMMC2_D2_
O3_B1_d
/GPIO3_B0_d
_M1/GPIO3_A6_d
M1/GPIO3_A3_d
AH
NP
NP
CIF_D15/EBC_SDD CIF_D14/EBC_SDD CIF_D13/EBC_SDD CIF_D12/EBC_SDD CIF_D9/EBC_SDDO CIF_D8/EBC_SDDO CIF_D4/EBC_SDDO
O15/GMAC1_TXD1_ O14/GMAC1_TXD0_ O13/GMAC1_RXCL O12/GMAC1_RXD3_ 9/GMAC1_TXD3_M1 8/GMAC1_TXD2_M1 4/SDMMC2_CMD_M
M1/UART9_RX_M2/I M1/UART9_TX_M2/I K_M1/UART7_RX_M M1/UART7_TX_M2/ /UART1_RX_M1/PD /UART1_TX_M1/PD 0/I2S1_SDI0_M1/VO
2S2_LRCK_RX_M1/ 2S2_LRCK_TX_M1/ 2/PDM_SDI3_M1/G PDM_SDI2_M1/GPI M_SDI0_M1/GPIO3_ M_CLK0_M1/GPIO3 P_BT656_D4_M1/G
GPIO4_A5_d
GPIO4_A4_d
PIO4_A3_d
O4_A2_d
D7_d
_D6_d
PIO3_D2_d
VSS_144
1
VSS_136
NP
VSS_138
VSS_141
VSS_133
NP
CIF_D7/EBC_SDDO CIF_D1/EBC_SDDO LCDC_VSYNC/VOP
7/SDMMC2_PWRE 1/SDMMC2_D1_M0/ _BT1120_D14/SPI1_
N_M0/I2S1_SDI3_M I2S1_SCLK_TX_M1/ MISO_M1/UART5_T
1/VOP_BT656_D7_ VOP_BT656_D1_M1 X_M1/I2S1_SDO3_
M1/GPIO3_D5_d
/GPIO3_C7_d
M2/GPIO3_C2_d
CIF_D2/EBC_SDDO
2/SDMMC2_D2_M0/
I2S1_LRCK_TX_M1/
VOP_BT656_D2_M1
/GPIO3_D0_d
LCDC_D22/PWM12
_M0/GMAC1_TXEN_
M0/UART3_TX_M1/
PDM_SDI2_M2/GPI
O3_B7_d
NP
NP
LCDC_D9/VOP_BT1
120_D1/GMAC1_TX
D2_M0/I2S3_MCLK_
M0/SDMMC2_D1_M
1/GPIO3_A2_d
VSS_137
NP
3
4
5
VSS_125
VSS_126
VSS_127
VSS_128
NP
VSS_131
VSS_132
NP
NP
PWM15_IR_M1/SPI
3_MOSI_M1/CAN1_
TX_M1/PCIE30X2_W
AKEn_M2/I2S3_SCL
K_M1/GPIO4_C3_d
NP
LCDC_D8/VOP_BT1
120_D0/SPI1_CS0_
M1/PCIE30X1_PER
STn_M1/SDMMC2_
D0_M1/GPIO3_A1_d
LCDC_D2/VOP_BT6
LCDC_D3/VOP_BT6
56_D2_M0/SPI0_CS
56_D3_M0/SPI0_CL
0_M1/PCIE30X1_CL
K_M1/PCIE30X1_W
KREQn_M1/I2S1_L
AKEn_M1/I2S1_SDI
RCK_TX_M2/GPIO2
0_M2/GPIO2_D3_d
_D2_d
VSS_134
VSS_139
AVSS_11
PMUPLL_AVDD_0V
9
AVSS_17
PMUPLL_AVSS
AVSS_19
PMUIO2
NP
MIPI_DSI_TX0/LVDS
_TX0_AVDD_1V8
AVSS_20
NP
PMUIO1
NP
I2C2_SDA_M0/SPI0
_MOSI_M0/PCIE20_
PERSTn_M0/PWM2
_M1/GPIO0_B6_u
AVSS_27
HDMI_TX_REXT
NP
PCIE30_AVDD_0V9 PCIE30_AVDD_0V9
PCIE30_AVDD_1V8
_2
_1
HDMI_TX_AVDD_1V
8
NP
AVSS_9
NP
AVSS_16
AVSS_29
NP
GPIO0_D4_d
TVSS
NP
NP
NP
GPIO0_D6_d
AVSS_40
AVSS_41
NP
GPIO0_D5_d
AVSS_42
NP
AVSS_34
HDMI_TX_HPDIN
NP
MIPI_DSI_TX1_D1N
AVSS_39
NP
I2C2_SCL_M0/SPI0
PWM6/SPI0_MISO_
UART2_RX_M0/GPI
_CLK_M0/PCIE20_
M0/PCIE30X2_WAK
O0_D0_u
WAKEn_M0/PWM1
En_M0/GPIO0_C5_d
_M1/GPIO0_B5_u
NP
MIPI_CSI_RX_D2N
MIPI_DSI_TX1_D3P
NP
MIPI_DSI_TX1_D2P
MIPI_DSI_TX1_CLK
P
NP
MIPI_DSI_TX1_D1P MIPI_DSI_TX1_D0P
NP
PWM7_IR/SPI0_CS
CLK32K_IN/CLK32K
PWM5/SPI0_CS1_ PWM1_M0/GPUAV
0_M0/PCIE30X2_PE
_OUT0/PCIE30X2_B
M0/UART0_RTSn/G S/UART0_RX/GPIO0
RSTn_M0/GPIO0_C
UTTONRSTn/GPIO0
PIO0_C4_d
_C0_d
6_d
_B0_u
AVSS_48
NP
MIPI_CSI_RX_CLK1 MIPI_CSI_RX_CLK0
N
N
9
10
NP
PWM4/VOP_PWM_
GPU_PWREN/SAT
M0/PCIE30X1_PER
A_CP_POD/PCIE30
STn_M0/MCU_JTAG
X2_CLKREQn_M0/G
_TRSTn/GPIO0_C3_
PIO0_A6_d
d
PWM2_M0/NPUAV
SDMMC0_PWREN/
S/UART0_TX/MCU_J I2C0_SCL/GPIO0_B SATA_MP_SWITCH
TAG_TDI/GPIO0_C1
1_u
/PCIE20_CLKREQn
_d
_M0/GPIO0_A5_d
AVSS_49
AVSS_50
AVSS_54
NP
AVSS_55
AVSS_56
NP
MIPI_CSI_RX_D1P
MIPI_CSI_RX_D0P
MIPI_DSI_TX0_D3N/ MIPI_DSI_TX0_D2N/ MIPI_DSI_TX0_CLK MIPI_DSI_TX0_D1N/ MIPI_DSI_TX0_D0N/
LVDS_TX0_D3N
LVDS_TX0_D2N
N/LVDS_TX0_CLKN
LVDS_TX0_D1N
LVDS_TX0_D0N
AVSS_57
HDMI_TX_CLKN
HDMI_TX_D0P
HDMI_TX_D1P
HDMI_TX_D2P
MIPI_CSI_RX_D1N
MIPI_CSI_RX_D0N
MIPI_DSI_TX0_D3P/ MIPI_DSI_TX0_D2P/ MIPI_DSI_TX0_CLK MIPI_DSI_TX0_D1P/ MIPI_DSI_TX0_D0P/
LVDS_TX0_D3P
LVDS_TX0_D2P
P/LVDS_TX0_CLKP
LVDS_TX0_D1P
LVDS_TX0_D0P
AVSS_58
HDMI_TX_CLKP
HDMI_TX_D0N
HDMI_TX_D1N
HDMI_TX_D2N
AVSS_59
11
12
18
19
20
21
22
23
NP
13
AVSS_51
14
AVSS_52
15
NP
16
AVSS_53
17
Y
PCIE30_REFCLKN_I
N
NP
VSS_140
W
AVSS_28
NP
AVSS_45
V
VSS_135
AVSS_38
NP
USB3_HOST1_SST USB3_HOST1_SST
XN/SATA1_TXN/QS XP/SATA1_TXP/QS
GMII_TXN_M0
GMII_TXP_M0
GPIO0_A3_u
AVSS_33
MIPI_DSI_TX1_D0N
AVSS_18
PCIE20_RXP/SATA2 PCIE20_RXN/SATA2
_RXP/QSGMII_RXP_ _RXN/QSGMII_RXN_
M1
M1
AVSS_32
AVSS_44
U
NP
MIPI_DSI_TX1_D2N
NP
USB3_HOST1_SSR USB3_HOST1_SSR
XN/SATA1_RXN/QS XP/SATA1_RXP/QS
GMII_RXN_M0
GMII_RXP_M0
AVSS_23
NP
MIPI_DSI_TX1_CLK
N
T
AVSS_12
NP
NP
AVSS_43
PCIE20_REFCLKN
USB3_OTG0_SSTX USB3_OTG0_SSTX
N/SATA0_TXN
P/SATA0_TXP
PCIE30_REFCLKP_I
N
AVSS_37
NP
PCIE20_REFCLKP
NP
NP
AVSS_31
MIPI_DSI_TX1_D3N
MULTI_PHY1_REFC MULTI_PHY1_REFC
LKN
LKP
AVSS_10
AVSS_22
AVSS_36
MIPI_CSI_RX_D2P
NP
NP
AVSS_30
NP
NP
USB3_OTG0_SSRX USB3_OTG0_SSRX
N/SATA0_RXN
P/SATA0_RXP
AVSS_21
NP
SDMMC0_DET/SAT
PMUPLL_AVDD_1V A_CP_DET/PCIE30X
8
1_CLKREQn_M0/G
PIO0_A4_u
NP
MULTI_PHY0_REFC MULTI_PHY0_REFC
LKP
LKN
PCIE20_TXP/SATA2 PCIE20_TXN/SATA2
_TXP/QSGMII_TXP_ _TXN/QSGMII_TXN_
M1
M1
NP
NP
8
AVSS_26
NP
NP
PWM14_M1/SPI3_C
LK_M1/CAN1_RX_M
1/PCIE30X2_CLKRE
Qn_M2/I2S3_MCLK
_M1/GPIO4_C2_d
7
AVSS_25
NP
NP
AVSS_35
LCDC_D0/VOP_BT6
56_D0_M0/SPI0_MI
HDMITX_SDA/I2C5_ HDMITX_SCL/I2C5_
SO_M1/PCIE20_CL
MIPI_CSI_RX_CLK1 MIPI_CSI_RX_CLK0
SDA_M1/GPIO4_D0 SCL_M1/GPIO4_C7
KREQn_M1/I2S1_M
P
P
_u
_u
CLK_M2/GPIO2_D0
_d
6
NP
MIPI_CSI_RX_AVDD MIPI_DSI_TX1_AVD
_1V8
D_1V8
NP
GPIO4_D2_d
NP
VSS_145
AVSS_24
MIPI_CSI_RX_AVDD MIPI_DSI_TX1_AVD MIPI_DSI_TX0/LVDS
_0V9
D_0V9
_TX0_AVDD_0V9
MULTI_PHY_AVDD_ MULTI_PHY_AVDD_ MULTI_PHY_AVDD_
0V9_1
0V9_2
1V8
I2C1_SDA/CAN0_RX
_M0/PCIE20_BUTT
I2C0_SDA/GPIO0_B
ONRSTn/MCU_JTA
2_u
G_TCK/GPIO0_B4_
u
PWM13_M1/SPI3_C
S0_M1/SATA0_ACT
_LED/UART9_RX_M MIPI_CSI_RX_D3N
1/I2S3_SDI_M1/GPI
O4_C6_d
EDP_HPDIN_M0/SP
LCDC_D14/VOP_BT LCDC_D12/VOP_BT LCDC_CLK/VOP_BT LCDC_D7/VOP_BT6
DIF_TX_M2/SATA2_
1120_D5/GMAC1_R 1120_D4/GMAC1_R 656_CLK_M0/SPI2_ 56_D7_M0/SPI2_MI HDMITX_CEC_M0/S
ACT_LED/PCIE30X2
XCLK_M0/SDMMC2 XD3_M0/I2S3_SDO_ CLK_M1/UART8_RX SO_M1/UART8_TX_ PI3_CS1_M1/GPIO4
_PERSTn_M2/I2S3_
_DET_M1/GPIO3_A M0/SDMMC2_CMD_ _M1/I2S1_SDO1_M M1/I2S1_SDO0_M2/
_D1_u
LRCK_M1/GPIO4_C
7_d
M1/GPIO3_A5_d
2/GPIO3_A0_d
GPIO2_D7_d
4_d
2
NP
VSS_130
LCDC_D6/VOP_BT6 LCDC_D1/VOP_BT6
PWM12_M1/SPI3_
56_D6_M0/SPI2_M 56_D1_M0/SPI0_M
MISO_M1/SATA1_A
OSI_M1/PCIE30X2_ OSI_M1/PCIE20_W
CT_LED/UART9_TX_ MIPI_CSI_RX_D3P
PERSTn_M1/I2S1_S AKEn_M1/I2S1_SCL
M1/I2S3_SDO_M1/
DI3_M2/GPIO2_D6_ K_TX_M2/GPIO2_D1
GPIO4_C5_d
d
_d
LCDC_D4/VOP_BT6
LCDC_D11/VOP_BT
LCDC_D5/VOP_BT6
56_D4_M0/SPI2_CS
1120_D3/GMAC1_R
56_D5_M0/SPI2_CS
1_M1/PCIE30X2_CL
XD2_M0/I2S3_LRCK
0_M1/PCIE30X2_W
KREQn_M1/I2S1_S
_M0/SDMMC2_D3_
AKEn_M1/I2S1_SDI
DI1_M2/GPIO2_D4_
M1/GPIO3_A4_d
2_M2/GPIO2_D5_d
d
VSS_143
NP
NP
VSS_129
HDMI_TX_AVDD_0V HDMI_TX_AVDD_0V PMU_VDD_LOGIC_
9_1
9_2
0V9
USB3_OTG0_VBUS
EDP_TX_AVDD_1V8 USB3_AVDD_3V3
DET
R
PCIE30_TX0P
AA
PCIE30_TX1N
PCIE30_TX1P
AB
PCIE30_RX0N
PCIE30_RX0P
AC
PCIE30_RX1N
PCIE30_RX1P
AD
GPIO0_D3_d
AVSS_46
AVSS_47
AE
VSS_142
XOUT24M
XIN24M
PCIE30_TX0N
AF
PWM3_IR/EDP_HP I2C1_SCL/CAN0_TX
DIN_M1/PCIE30X1_ _M0/PCIE30X1_BUT
TSADC_SHUT_M0/T
PMIC_SLEEP/TSAD
FLASH_VOL_SEL/G
REFCLK_OUT/GPIO
WAKEn_M0/MCU_J TONRSTn/MCU_JTA
SADC_SHUT_ORG/
C_SHUT_M1/GPIO0
PIO0_A7_u
0_A0_d
TAG_TMS/GPIO0_C G_TDO/GPIO0_B3_
GPIO0_A1_z
_A2_d
2_d
u
HDMITX_CEC_M1/P
UART2_TX_M0/GPI
PWM0_M0/CPUAV
WM0_M1/UART0_C
O0_D1_u
S/GPIO0_B7_d
TSn/GPIO0_C7_d
24
25
26
nPOR_u
VSS_146
27
28
AG
AH
Fig.2-6 Ball Map
2.5 Pin Number List
Table 2-1 Pin Number List Information
Pin Name
VSS_1
DDR4_CS0n/LPDDR4_CS0n_A/DDR3_ODT1/LPDDR3_
ODT0/AC25
Pin
A1
VSS_2
A3
DDR4_CLKN/LPDDR4_CLKN_A/DDR3_CLKN/LPDDR3_C
LKN/AC24
A4
DDR4_A9/LPDDR4_CLKN_B/DDR3_A5/-/AC9
A5
VSS_3
A6
DDR4_A6/LPDDR4_A1_B/DDR3_A13/LPDDR3_A1/AC6
A7
DDR4_A7/LPDDR4_ODT0_CA_B/DDR3_A8/-/AC7
A8
DDR_DQ1_B/DDR4_DQU5_B/LPDDR4_DQ1_B/DDR3_
DQ17/LPDDR3_DQ5
VSS_4
DDR_DQS0P_B/DDR4_DQSU_P_B/LPDDR4_DQS0P_B/
DDR3_DQS2P/LPDDR3_DQS0P
Copyright 2022 © Rockchip Electronics Co., Ltd.
Pin Name
SARADC_VIN5
I2S2_LRCK_RX_M0/GMAC0_RXDV_CRS/UART6_C
TSn_M0/SPI1_CS0_M0/GPIO2_C0_d
I2S2_SCLK_TX_M0/GMAC0_MCLKINOUT/UART7_
CTSn_M0/SPI2_MISO_M0/GPIO2_C2_d
I2S2_SDI_M0/GMAC0_RXER/UART8_TX_M0/SPI2
_CS1_M0/GPIO2_C5_d
GMAC0_RXD0/UART1_CTSn_M0/SPI1_MISO_M0/
GPIO2_B6_u
GMAC0_TXD0/UART1_RX_M0/GPIO2_B3_u
DDR_DQS0P_A/DDR4_DQSL_P_A/LPDDR4_DQS0
P_A/DDR3_DQS0P/LPDDR3_DQS1P
DDR_DQS0N_A/DDR4_DQSL_N_A/LPDDR4_DQS0
N_A/DDR3_DQS0N/LPDDR3_DQS1N
Pin
F22
A9
VSS_38
G5
A10
VSS_39
G6
A11
VSS_40
G8
A2
F24
F25
F26
F27
F28
G1
G2
22
RK3568J Datasheet
Rev 1.0
Pin Name
DDR_DQ4_B/DDR4_DQU0_B/LPDDR4_DQ4_B/DDR3_
DQ20/LPDDR3_DQ2
DDR_DQ13_B/DDR4_DQL5_B/LPDDR4_DQ13_B/DDR3
_DQ29/LPDDR3_DQ17
VSS_5
DDR_DQS1N_B/DDR4_DQSL_N_B/LPDDR4_DQS1N_B/
DDR3_DQS3N/LPDDR3_DQS2N
DDR_DQ8_B/DDR4_DQL0_B/LPDDR4_DQ8_B/DDR3_D
Q24/LPDDR3_DQ18
DDR_DQ10_B/DDR4_DQL4_B/LPDDR4_DQ10_B/DDR3
_DQ26/LPDDR3_DQ22
VSS_6
I2S1_MCLK_M0/UART3_RTSn_M0/SCR_CLK/PCIE30X1
_PERSTn_M2/GPIO1_A2_d
I2S1_LRCK_TX_M0/UART4_RTSn_M0/SCR_RST/PCIE3
0X1_CLKREQn_M2/ACODEC_DAC_SYNC/GPIO1_A5_d
I2S1_SDO3_M0/I2S1_SDI1_M0/PDM_SDI1_M0/PCIE2
0_PERSTn_M2/GPIO1_B2_d
FSPI_CLK/FLASH_ALE/GPIO1_D0_d
EMMC_CLKOUT/FLASH_DQS/GPIO1_C5_d
Pin
Pin Name
Pin
A12
VSS_41
G9
A13
VSS_42
G11
A14
VSS_43
G12
A15
VSS_44
G14
A16
VSS_45
G15
A17
VSS_46
G17
A18
VSS_47
G18
A19
SARADC_VIN6
G20
A20
SARADC_VIN4
G21
EMMC_D0/FLASH_D0/GPIO1_B4_u
A24
EMMC_D4/FLASH_D4/GPIO1_C0_u
A25
EMMC_DATA_STROBE/FSPI_CS1n/FLASH_CLE/GPIO1_
C6_d
FSPI_D3/FLASH_CS1n/GPIO1_D4_u
VSS_7
CIF_D6/EBC_SDDO6/SDMMC2_DET_M0/I2S1_SDI2_M
1/VOP_BT656_D6_M1/GPIO3_D4_d
CIF_D11/EBC_SDDO11/GMAC1_RXD2_M1/PDM_SDI1
_M1/GPIO4_A1_d
CIF_D10/EBC_SDDO10/GMAC1_TXCLK_M1/PDM_CLK1
_M1/GPIO4_A0_d
VSS_133
CIF_D7/EBC_SDDO7/SDMMC2_PWREN_M0/I2S1_SDI3
_M1/VOP_BT656_D7_M1/GPIO3_D5_d
CIF_D1/EBC_SDDO1/SDMMC2_D1_M0/I2S1_SCLK_TX
_M1/VOP_BT656_D1_M1/GPIO3_C7_d
LCDC_VSYNC/VOP_BT1120_D14/SPI1_MISO_M1/UAR
T5_TX_M1/I2S1_SDO3_M2/GPIO3_C2_d
VSS_134
PWM15_IR_M1/SPI3_MOSI_M1/CAN1_TX_M1/PCIE30
X2_WAKEn_M2/I2S3_SCLK_M1/GPIO4_C3_d
AVSS_24
AVSS_25
AVSS_26
A21
A22
A23
G28
H1
H2
A27
VSS_50
DDR_DQ7_A/DDR4_DQL1_A/LPDDR4_DQ7_A/DD
R3_DQ7/LPDDR3_DQ11
DDR_DM0_A/DDR4_DML_A/LPDDR4_DM0_A/DDR
3_DM0/LPDDR3_DM1
H3
AA2
VSS_51
H6
AA3
DDR_RZQ
H7
AA4
DDRPHY_VDDQ_1
H9
AA5
DDRPHY_VDDQ_2
H11
AA6
DDRPHY_VDDQ_3
H12
AA7
DDRPHY_VDDQ_4
H14
AA9
DDRPHY_VDDQ_5
H15
AA11
VCCIO1
H17
AA12
AA14
AA15
VCCIO2
OTP_VCC18
SARADC_AVDD_1V8
I2S2_SDO_M0/GMAC0_MDIO/UART9_CTSn_M0/S
PI2_CS0_M0/GPIO2_C4_d
I2S2_LRCK_TX_M0/GMAC0_MDC/UART9_RTSn_M
0/SPI2_MOSI_M0/GPIO2_C3_d
I2S2_SCLK_RX_M0/GMAC0_RXD1/UART6_RTSn_
M0/SPI1_MOSI_M0/GPIO2_B7_d
SDMMC0_D2/ARMJTAG_TCK/UART5_CTSn_M0/GP
IO1_D7_u
SDMMC0_CMD/PWM10_M1/UART5_RX_M0/CAN0_
TX_M1/GPIO2_A1_u
SDMMC0_CLK/TEST_CLKOUT/UART5_TX_M0/CAN
0_RX_M1/GPIO2_A2_d
DDR_DQ4_A/DDR4_DQL7_A/LPDDR4_DQ4_A/DD
R3_DQ4/LPDDR3_DQ13
DDR_DQ5_A/DDR4_DQL5_A/LPDDR4_DQ5_A/DD
R3_DQ5/LPDDR3_DQ12
VSS_52
DDR_DM1_A/DDR4_DMU_A/LPDDR4_DM1_A/DDR
3_DM1/LPDDR3_DM3
H18
H20
H22
VSS_53
J5
A28
AA1
HDMI_TX_REXT
AA18
I2C2_SDA_M0/SPI0_MOSI_M0/PCIE20_PERSTn_M0/P
WM2_M1/GPIO0_B6_u
AA20
GPIO0_A3_u
AA22
VSS_135
AA23
AVSS_28
AA24
PCIE30_REFCLKN_IN
AA25
AVSS_29
AA26
PCIE30_TX0N
AA27
PCIE30_TX0P
AA28
CIF_D3/EBC_SDDO3/SDMMC2_D3_M0/I2S1_SDO0_M
1/VOP_BT656_D3_M1/GPIO3_D1_d
AB1
Copyright 2022 © Rockchip Electronics Co., Ltd.
G24
G27
VSS_49
AA17
CIF_D2/EBC_SDDO2/SDMMC2_D2_M0/I2S1_LRCK_TX
_M1/VOP_BT656_D2_M1/GPIO3_D0_d
VSS_137
G23
A26
AVSS_27
VSS_136
I2S2_MCLK_M0/ETH0_REFCLKO_25M/UART7_RTS
n_M0/SPI2_CLK_M0/GPIO2_C1_d
VSS_48
GMAC0_TXD1/UART1_TX_M0/GPIO2_B4_u
GMAC0_TXEN/UART1_RTSn_M0/SPI1_CLK_M0/GP
IO2_B5_u
DDR_DQ6_A/DDR4_DQL3_A/LPDDR4_DQ6_A/DD
R3_DQ6/LPDDR3_DQ8
AB2
AB5
AB6
DDR_DQ13_A/DDR4_DQU4_A/LPDDR4_DQ13_A/
DDR3_DQ13/LPDDR3_DQ31
DDR_DQ14_A/DDR4_DQU6_A/LPDDR4_DQ14_A/
DDR3_DQ14/LPDDR3_DQ30
DDR_AVSS
H4
H5
H23
H24
H25
H26
H27
H28
J1
J2
J3
J4
J6
J7
J8
23
RK3568J Datasheet
Rev 1.0
Pin Name
LCDC_D8/VOP_BT1120_D0/SPI1_CS0_M1/PCIE30X1_
PERSTn_M1/SDMMC2_D0_M1/GPIO3_A1_d
GPIO4_D2_d
AVSS_30
AVSS_31
AVSS_32
AVSS_33
AVSS_34
HDMI_TX_HPDIN
I2C1_SDA/CAN0_RX_M0/PCIE20_BUTTONRSTn/MCU_J
TAG_TCK/GPIO0_B4_u
I2C0_SDA/GPIO0_B2_u
Pin
Pin Name
Pin
AB8
DDRPHY_VDDQ_6
J9
AB9
AB11
AB12
AB14
AB15
AB17
AB18
DDRPHY_VDDQL_1
DDRPHY_VDDQL_2
DDRPHY_VDDQL_3
VDD_CPU_1
VSS_54
VSS_55
VSS_56
J11
J12
J14
J15
J17
J18
J20
AB20
VCCIO4
J21
AB21
J22
GPIO0_D4_d
AB23
TVSS
AB24
PCIE30_TX1N
AB27
PCIE30_TX1P
CIF_D5/EBC_SDDO5/SDMMC2_CLK_M0/I2S1_SDI1_M
1/VOP_BT656_D5_M1/GPIO3_D3_d
PWM15_IR_M0/SPDIF_TX_M1/GMAC1_MDIO_M0/UAR
T7_RX_M1/I2S1_LRCK_RX_M2/GPIO3_C5_d
PWM14_M0/VOP_PWM_M1/GMAC1_MDC_M0/UART7_T
X_M1/PDM_CLK1_M2/GPIO3_C4_d
LCDC_DEN/VOP_BT1120_D15/SPI1_CLK_M1/UART5_R
X_M1/I2S1_SCLK_RX_M2/GPIO3_C3_d
CIF_D0/EBC_SDDO0/SDMMC2_D0_M0/I2S1_MCLK_M
1/VOP_BT656_D0_M1/GPIO3_C6_d
LCDC_D3/VOP_BT656_D3_M0/SPI0_CLK_M1/PCIE30X
1_WAKEn_M1/I2S1_SDI0_M2/GPIO2_D3_d
LCDC_D2/VOP_BT656_D2_M0/SPI0_CS0_M1/PCIE30X
1_CLKREQn_M1/I2S1_LRCK_TX_M2/GPIO2_D2_d
AVSS_35
AVSS_36
AVSS_37
MIPI_DSI_TX1_D2N
AVSS_38
MIPI_DSI_TX1_D1N
AVSS_39
UART2_RX_M0/GPIO0_D0_u
PWM6/SPI0_MISO_M0/PCIE30X2_WAKEn_M0/GPIO0_
C5_d
I2C2_SCL_M0/SPI0_CLK_M0/PCIE20_WAKEn_M0/PW
M1_M1/GPIO0_B5_u
AB28
VSS_57
SDMMC0_D3/ARMJTAG_TMS/UART5_RTSn_M0/GP
IO2_A0_u
SDMMC0_D1/UART2_RX_M1/UART6_RX_M1/PWM
9_M1/GPIO1_D6_u
SDMMC0_D0/UART2_TX_M1/UART6_TX_M1/PWM
8_M1/GPIO1_D5_u
VSS_58
AC1
AVSS_1
J27
AC2
EDP_TX_D0P
J28
AC3
VSS_59
K1
AC4
DDR_DQ12_A/DDR4_DQU2_A/LPDDR4_DQ12_A/
DDR3_DQ12/LPDDR3_DQ26
K2
AC5
DDRPHY_VDDQL_4
K10
AC7
VSS_60
K11
AC8
VSS_61
K12
AC9
AC11
AC12
AC14
AC15
AC17
AC18
AC20
VSS_62
VSS_63
VDD_CPU_2
VDD_CPU_3
VDD_CPU_4
VDD_CPU_5
VSS_64
EDP_TX_D0N
K13
K14
K15
K16
K17
K18
K19
K27
AC21
EDP_TX_D1P
K28
GPIO0_D6_d
AC24
AVSS_40
AC25
AVSS_41
AC26
PCIE30_RX0N
AC27
PCIE30_RX0P
AC28
LCDC_HSYNC/VOP_BT1120_D13/SPI1_MOSI_M1/PCIE
20_PERSTn_M1/I2S1_SDO2_M2/GPIO3_C1_d
LCDC_D23/PWM13_M0/GMAC1_MCLKINOUT_M0/UART
3_RX_M1/PDM_SDI3_M2/GPIO3_C0_d
VSS_138
LCDC_D22/PWM12_M0/GMAC1_TXEN_M0/UART3_TX_
M1/PDM_SDI2_M2/GPIO3_B7_d
LCDC_D6/VOP_BT656_D6_M0/SPI2_MOSI_M1/PCIE30
X2_PERSTn_M1/I2S1_SDI3_M2/GPIO2_D6_d
LCDC_D1/VOP_BT656_D1_M0/SPI0_MOSI_M1/PCIE20
_WAKEn_M1/I2S1_SCLK_TX_M2/GPIO2_D1_d
PWM12_M1/SPI3_MISO_M1/SATA1_ACT_LED/UART9_
TX_M1/I2S3_SDO_M1/GPIO4_C5_d
MIPI_CSI_RX_D3P
MIPI_CSI_RX_D2N
MIPI_DSI_TX1_D3P
MIPI_DSI_TX1_D2P
MIPI_DSI_TX1_CLKP
MIPI_DSI_TX1_D1P
MIPI_DSI_TX1_D0P
Copyright 2022 © Rockchip Electronics Co., Ltd.
AC22
AD1
DDR_DQS1N_A/DDR4_DQSU_N_A/LPDDR4_DQS1
N_A/DDR3_DQS1N/LPDDR3_DQS3N
DDR_DQS1P_A/DDR4_DQSU_P_A/LPDDR4_DQS1
P_A/DDR3_DQS1P/LPDDR3_DQS3P
VSS_65
DDR_DQ15_A/DDR4_DQU0_A/LPDDR4_DQ15_A/
DDR3_DQ15/LPDDR3_DQ27
VSS_66
DDR_DQ11_A/DDR4_DQU5_A/LPDDR4_DQ11_A/
DDR3_DQ11/LPDDR3_DQ29
DDR_DQ10_A/DDR4_DQU7_A/LPDDR4_DQ10_A/
DDR3_DQ10/LPDDR3_DQ28
J23
J24
J25
J26
L1
L2
L3
L4
L5
L6
L7
AD2
VSS_67
L8
AD3
DDRPHY_VDDQ_7
L9
AD4
DDRPHY_VDDQL_5
L10
AD6
VSS_68
L11
AD7
VDD_LOGIC_1
L12
AD8
VSS_69
L13
AD9
AD11
AD12
AD14
AD15
AD17
AD18
VSS_70
VDD_CPU_6
VDD_CPU_7
VDD_CPU_8
VDD_CPU_9
VSS_71
VSS_72
L14
L15
L16
L17
L18
L19
L20
24
RK3568J Datasheet
Rev 1.0
Pin Name
PWM7_IR/SPI0_CS0_M0/PCIE30X2_PERSTn_M0/GPIO
0_C6_d
PWM5/SPI0_CS1_M0/UART0_RTSn/GPIO0_C4_d
PWM1_M0/GPUAVS/UART0_RX/GPIO0_C0_d
CLK32K_IN/CLK32K_OUT0/PCIE30X2_BUTTONRSTn/G
PIO0_B0_u
GPIO0_D5_d
AVSS_42
PCIE30_RX1N
PCIE30_RX1P
LCDC_D19/VOP_BT1120_D10/GMAC1_RXER_M0/I2C5
_SDA_M0/PDM_SDI1_M2/GPIO3_B4_d
LCDC_D20/VOP_BT1120_D11/GMAC1_TXD0_M0/I2C3
_SCL_M1/PWM10_M0/GPIO3_B5_d
LCDC_D21/VOP_BT1120_D12/GMAC1_TXD1_M0/I2C3
_SDA_M1/PWM11_IR_M0/GPIO3_B6_d
LCDC_D9/VOP_BT1120_D1/GMAC1_TXD2_M0/I2S3_M
CLK_M0/SDMMC2_D1_M1/GPIO3_A2_d
VSS_139
PWM13_M1/SPI3_CS0_M1/SATA0_ACT_LED/UART9_R
X_M1/I2S3_SDI_M1/GPIO4_C6_d
MIPI_CSI_RX_D3N
MIPI_CSI_RX_D2P
MIPI_DSI_TX1_D3N
AVSS_43
MIPI_DSI_TX1_CLKN
AVSS_44
MIPI_DSI_TX1_D0N
AVSS_45
VSS_140
PWM4/VOP_PWM_M0/PCIE30X1_PERSTn_M0/MCU_JT
AG_TRSTn/GPIO0_C3_d
GPU_PWREN/SATA_CP_POD/PCIE30X2_CLKREQn_M0/
GPIO0_A6_d
GPIO0_D3_d
AVSS_46
AVSS_47
LCDC_D18/VOP_BT1120_D9/GMAC1_RXDV_CRS_M0/I
2C5_SCL_M0/PDM_SDI0_M2/GPIO3_B3_d
LCDC_D17/VOP_BT1120_D8/GMAC1_RXD1_M0/UART4
_TX_M1/PWM9_M0/GPIO3_B2_d
VSS_141
LCDC_D11/VOP_BT1120_D3/GMAC1_RXD2_M0/I2S3_
LRCK_M0/SDMMC2_D3_M1/GPIO3_A4_d
LCDC_D4/VOP_BT656_D4_M0/SPI2_CS1_M1/PCIE30X
2_CLKREQn_M1/I2S1_SDI1_M2/GPIO2_D4_d
LCDC_D5/VOP_BT656_D5_M0/SPI2_CS0_M1/PCIE30X
2_WAKEn_M1/I2S1_SDI2_M2/GPIO2_D5_d
PWM14_M1/SPI3_CLK_M1/CAN1_RX_M1/PCIE30X2_C
LKREQn_M2/I2S3_MCLK_M1/GPIO4_C2_d
AVSS_48
AVSS_49
Pin
Pin Name
Pin
AD20
VSS_73
L21
AD21
AD22
VCCIO3
USB3_OTG0_ID
L22
L23
AD23
AVSS_2
L24
AD25
AD26
AD27
AD28
EDP_TX_AUXP
AVSS_3
EDP_TX_D1N
EDP_TX_D2P
DDR_DQ8_A/DDR4_DQU3_A/LPDDR4_DQ8_A/DD
R3_DQ8/LPDDR3_DQ25
L25
L26
L27
L28
AE2
VSS_74
M2
AE3
VSS_75
M3
AE5
DDR_ECC_DQ1
M4
AE6
DDR_ECC_DQ2
M5
AE8
VSS_76
M6
AE9
AE11
AE12
AE14
AE15
AE17
AE18
AE20
AE21
DDR_ECC_DQ4
VSS_77
DDRPHY_VDDQ_8
DDRPHY_VDDQL_6
VSS_78
VDD_LOGIC_2
VSS_79
VSS_80
VDD_CPU_COM
M7
M8
M9
M10
M11
M12
M13
M14
M15
AE23
VSS_81
M16
AE24
VDD_CPU_10
M17
AE26
AE27
AE28
VSS_82
VDD_NPU_1
EDP_TX_AVDD_0V9
M18
M19
M20
AF1
AVSS_4
M21
AF2
EDP_TX_AVDD_1V8
M22
AF3
USB3_AVDD_3V3
M23
AF4
USB3_OTG0_VBUSDET
M24
AF5
EDP_TX_AUXN
M25
AF6
AVSS_5
M26
AF8
EDP_TX_D2N
M27
AF9
AF11
M28
N1
AVSS_50
AF12
AVSS_51
AVSS_52
AVSS_53
AVSS_54
AVSS_55
AVSS_56
PWM2_M0/NPUAVS/UART0_TX/MCU_JTAG_TDI/GPIO0
_C1_d
I2C0_SCL/GPIO0_B1_u
SDMMC0_PWREN/SATA_MP_SWITCH/PCIE20_CLKREQ
n_M0/GPIO0_A5_d
VSS_142
XOUT24M
XIN24M
LCDC_D16/VOP_BT1120_D7/GMAC1_RXD0_M0/UART4
_RX_M1/PWM8_M0/GPIO3_B1_d
LCDC_D15/VOP_BT1120_D6/ETH1_REFCLKO_25M_M0
/SDMMC2_PWREN_M1/GPIO3_B0_d
AF14
AF15
AF17
AF18
AF20
AF21
EDP_TX_D3P
VSS_83
DDR_DQ9_A/DDR4_DQU1_A/LPDDR4_DQ9_A/DD
R3_DQ9/LPDDR3_DQ24
SYSPLL_AVDD_1V8
SYSPLL_AVSS
VSS_84
VDD_LOGIC_3
VSS_85
VSS_86
AF23
VDD_LOGIC_4
N16
AF24
VSS_87
N17
AF25
VSS_88
N18
AF26
AF27
AF28
VDD_NPU_2
EDP_TX_D3N
AVSS_6
N19
N27
N28
AG1
DDR_ECC_DQS_N
P1
AG2
DDR_ECC_DQS_P
P2
Copyright 2022 © Rockchip Electronics Co., Ltd.
AE1
M1
N2
N10
N11
N12
N13
N14
N15
25
RK3568J Datasheet
Pin Name
LCDC_D13/VOP_BT1120_CLK/GMAC1_TXCLK_M0/I2S
3_SDI_M0/SDMMC2_CLK_M1/GPIO3_A6_d
LCDC_D10/VOP_BT1120_D2/GMAC1_TXD3_M0/I2S3_
SCLK_M0/SDMMC2_D2_M1/GPIO3_A3_d
VSS_143
LCDC_D0/VOP_BT656_D0_M0/SPI0_MISO_M1/PCIE20
_CLKREQn_M1/I2S1_MCLK_M2/GPIO2_D0_d
HDMITX_SDA/I2C5_SDA_M1/GPIO4_D0_u
HDMITX_SCL/I2C5_SCL_M1/GPIO4_C7_u
MIPI_CSI_RX_CLK1P
MIPI_CSI_RX_CLK0P
MIPI_CSI_RX_D1P
MIPI_CSI_RX_D0P
MIPI_DSI_TX0_D3N/LVDS_TX0_D3N
MIPI_DSI_TX0_D2N/LVDS_TX0_D2N
MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN
MIPI_DSI_TX0_D1N/LVDS_TX0_D1N
MIPI_DSI_TX0_D0N/LVDS_TX0_D0N
AVSS_57
HDMI_TX_CLKN
HDMI_TX_D0P
HDMI_TX_D1P
HDMI_TX_D2P
PWM3_IR/EDP_HPDIN_M1/PCIE30X1_WAKEn_M0/MCU
_JTAG_TMS/GPIO0_C2_d
I2C1_SCL/CAN0_TX_M0/PCIE30X1_BUTTONRSTn/MCU
_JTAG_TDO/GPIO0_B3_u
FLASH_VOL_SEL/GPIO0_A7_u
TSADC_SHUT_M0/TSADC_SHUT_ORG/GPIO0_A1_z
REFCLK_OUT/GPIO0_A0_d
PMIC_SLEEP/TSADC_SHUT_M1/GPIO0_A2_d
VSS_144
LCDC_D14/VOP_BT1120_D5/GMAC1_RXCLK_M0/SDM
MC2_DET_M1/GPIO3_A7_d
LCDC_D12/VOP_BT1120_D4/GMAC1_RXD3_M0/I2S3_
SDO_M0/SDMMC2_CMD_M1/GPIO3_A5_d
LCDC_CLK/VOP_BT656_CLK_M0/SPI2_CLK_M1/UART8
_RX_M1/I2S1_SDO1_M2/GPIO3_A0_d
LCDC_D7/VOP_BT656_D7_M0/SPI2_MISO_M1/UART8
_TX_M1/I2S1_SDO0_M2/GPIO2_D7_d
HDMITX_CEC_M0/SPI3_CS1_M1/GPIO4_D1_u
EDP_HPDIN_M0/SPDIF_TX_M2/SATA2_ACT_LED/PCIE
30X2_PERSTn_M2/I2S3_LRCK_M1/GPIO4_C4_d
VSS_145
MIPI_CSI_RX_CLK1N
MIPI_CSI_RX_CLK0N
MIPI_CSI_RX_D1N
MIPI_CSI_RX_D0N
MIPI_DSI_TX0_D3P/LVDS_TX0_D3P
MIPI_DSI_TX0_D2P/LVDS_TX0_D2P
MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP
MIPI_DSI_TX0_D1P/LVDS_TX0_D1P
MIPI_DSI_TX0_D0P/LVDS_TX0_D0P
AVSS_58
HDMI_TX_CLKP
HDMI_TX_D0N
HDMI_TX_D1N
HDMI_TX_D2N
AVSS_59
UART2_TX_M0/GPIO0_D1_u
HDMITX_CEC_M1/PWM0_M1/UART0_CTSn/GPIO0_C7
_d
PWM0_M0/CPUAVS/GPIO0_B7_d
nPOR_u
VSS_146
DDR4_A2/LPDDR4_A1_A/DDR3_A4/LPDDR3_A6/AC2
DDR4_CS1n/LPDDR4_CS1n_A/DDR3_CS1n/LPDDR3_O
DT1/AC26
DDR4_CKE/LPDDR4_CKE0_A/DDR3_CKE/LPDDR3_CKE
/AC22
Copyright 2022 © Rockchip Electronics Co., Ltd.
Rev 1.0
Pin
Pin Name
Pin
AG3
VSS_89
P3
AG4
DDR_ECC_DQ6
P4
AG5
DDR_ECC_DQ0
P5
AG6
VSS_90
P6
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
DDR_ECC_DM
DDR_VREFOUT
USB2_AVDD_1V8
USB2_AVDD_3V3
SYSPLL_AVDD_0V9
VSS_91
VDD_LOGIC_5
VSS_92
VSS_93
VDD_LOGIC_6
VSS_94
VDD_NPU_3
VDD_NPU_4
VDD_NPU_5
AVSS_7
USB3_AVDD_0V9
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
AG23
USB3_AVDD_1V8
P23
AG24
USB3_HOST1_DP
P24
AG25
AG26
AG27
AG28
AH1
USB3_HOST1_DM
AVSS_8
USB3_OTG0_DP
USB3_OTG0_DM
USB2_HOST2_DM
P25
P26
P27
P28
R1
AH2
USB2_HOST2_DP
R2
AH3
VSS_95
R3
AH4
DDR_ECC_DQ7
R4
AH5
DDR_ECC_DQ3
R5
AH6
VSS_96
R6
AH7
DDR_ECC_DQ5
R7
AH8
AH9
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
USB2_AVDD_0V9
VCCIO6_1
VSS_97
VSS_98
VDD_LOGIC_7
VDD_GPU_1
VSS_99
VSS_100
VDD_LOGIC_8
VSS_101
VSS_102
VSS_103
MULTI_PHY_AVDD_0V9_1
MULTI_PHY_AVDD_0V9_2
MULTI_PHY_AVDD_1V8
AVSS_9
MULTI_PHY0_REFCLKP
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
AH25
MULTI_PHY0_REFCLKN
R25
AH26
AH27
AH28
B1
AVSS_10
USB3_OTG0_SSRXN/SATA0_RXN
USB3_OTG0_SSRXP/SATA0_RXP
USB2_HOST3_DM
R26
R27
R28
T1
B2
USB2_HOST3_DP
T2
B3
VSS_104
T10
26
RK3568J Datasheet
Rev 1.0
Pin Name
DDR4_CLKP/LPDDR4_CLKP_A/DDR3_CLKP/LPDDR3_C
LKP/AC23
VSS_8
DDR4_A0/LPDDR4_CLKP_B/DDR3_A9/-/AC0
DDR4_A5/LPDDR4_A5_B/DDR3_A11/LPDDR3_A2/AC5
DDR4_A13/LPDDR4_A0_B/DDR3_A14/LPDDR3_A0/AC
13
VSS_9
DDR_DQ0_B/DDR4_DQU7_B/LPDDR4_DQ0_B/DDR3_
DQ16/LPDDR3_DQ1
DDR_DQS0N_B/DDR4_DQSU_N_B/LPDDR4_DQS0N_B
/DDR3_DQS2N/LPDDR3_DQS0N
VSS_10
DDR_DQ12_B/DDR4_DQL7_B/LPDDR4_DQ12_B/DDR3
_DQ28/LPDDR3_DQ16
DDR_DQ15_B/DDR4_DQL3_B/LPDDR4_DQ15_B/DDR3
_DQ31/LPDDR3_DQ21
DDR_DQS1P_B/DDR4_DQSL_P_B/LPDDR4_DQS1P_B/
DDR3_DQS3P/LPDDR3_DQS2P
Pin
Pin Name
Pin
B4
VSS_105
T11
B5
B6
B7
VDD_LOGIC_9
VDD_GPU_2
VSS_106
T12
T13
T14
B8
VSS_107
T15
B9
VDD_LOGIC_10
T16
B10
VSS_108
T17
B11
VSS_109
T18
B12
VSS_110
T19
B13
USB3_OTG0_SSTXN/SATA0_TXN
T27
B14
USB3_OTG0_SSTXP/SATA0_TXP
T28
B15
VSS_111
U1
VSS_11
B16
DDR_DQ9_B/DDR4_DQL2_B/LPDDR4_DQ9_B/DDR3_D
Q25/LPDDR3_DQ19
DDR_DQ11_B/DDR4_DQL6_B/LPDDR4_DQ11_B/DDR3
_DQ27/LPDDR3_DQ23
I2S1_SCLK_TX_M0/UART3_CTSn_M0/SCR_IO/PCIE30
X1_WAKEn_M2/ACODEC_DAC_CLK/GPIO1_A3_d
I2S1_SDO0_M0/UART4_CTSn_M0/SCR_DET/AUDIOPW
M_ROUT_N/ACODEC_DAC_DATAL/GPIO1_A7_d
I2S1_SDI0_M0/PDM_SDI0_M0/GPIO1_B3_d
EMMC_CMD/FLASH_WRn/GPIO1_C4_u
VSS_12
EMMC_D2/FLASH_D2/GPIO1_B6_u
EMMC_D7/FLASH_D7/GPIO1_C3_u
VSS_13
SARADC_VIN0
SDMMC1_D2/GMAC0_RXCLK/UART7_RX_M0/GPIO2_A
5_u
DDR4_A8/LPDDR4_ODT0_CA_A/DDR3_A6/LPDDR3_A9
/AC8
DDR4_A11/LPDDR4_A0_A/DDR3_A7/LPDDR3_A8/AC1
1
VSS_14
DDR4_A12/LPDDR4_A3_A/DDR3_BA2/-/AC12
DDR4_A14_WEn/LPDDR4_A4_A/DDR3_A15/LPDDR3_
A5/AC14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
B17
B18
B19
U3
U4
U5
VSS_112
U6
B21
B22
B23
B24
B25
B26
B27
VSS_113
VSS_114
VCCIO6_2
VSS_115
VDD_GPU_3
VDD_GPU_4
VDD_GPU_5
U7
U8
U9
U10
U11
U12
U13
B28
VSS_116
U14
C1
VSS_117
U15
C2
VSS_118
U16
C3
C4
VSS_119
VSS_120
U17
U18
C5
PCIE30_RESREF
U19
C6
C8
C9
C11
C12
C14
C15
PCIE30_AVDD_0V9_2
PCIE30_AVDD_0V9_1
PCIE30_AVDD_1V8
AVSS_11
MULTI_PHY1_REFCLKN
MULTI_PHY1_REFCLKP
AVSS_12
USB3_HOST1_SSRXN/SATA1_RXN/QSGMII_RXN_
M0
USB3_HOST1_SSRXP/SATA1_RXP/QSGMII_RXP_
M0
I2C4_SCL_M0/EBC_GDOE/ETH1_REFCLKO_25M_
M1/SPI3_CLK_M0/I2S2_SDO_M1/GPIO4_B3_d
ISP_PRELIGHT_TRIG/EBC_SDCE3/GMAC1_RXDV_
CRS_M1/I2S1_SDO2_M1/GPIO4_B1_d
VSS_121
I2C4_SDA_M0/EBC_VCOM/GMAC1_RXER_M1/SPI
3_MOSI_M0/I2S2_SDI_M1/GPIO4_B2_d
I2C2_SCL_M1/EBC_SDSHR/CAN2_TX_M0/I2S1_S
DO3_M1/GPIO4_B5_d
I2C2_SDA_M1/EBC_GDSP/CAN2_RX_M0/ISP_FLA
SH_TRIGIN/VOP_BT656_CLK_M1/GPIO4_B4_d
CAM_CLKOUT1/EBC_SDCE2/GMAC1_RXD1_M1/SP
I3_MISO_M0/I2S1_SDO1_M1/GPIO4_B0_d
U20
U21
U22
U23
U24
U25
U26
VSS_122
V8
C17
VSS_23
C18
I2S1_LRCK_RX_M0/UART4_TX_M0/PDM_CLK0_M0/AU
DIOPWM_ROUT_P/GPIO1_A6_d
C20
EMMC_D1/FLASH_D1/GPIO1_B5_u
C21
FSPI_CS0n/FLASH_CS0n/GPIO1_D3_u
C23
FSPI_D0/FLASH_RDY/GPIO1_D1_u
C24
VSS_24
C25
SARADC_VIN1
C26
Copyright 2022 © Rockchip Electronics Co., Ltd.
U2
B20
VSS_22
SDMMC1_D3/GMAC0_TXD2/UART7_TX_M0/GPIO2_A6
_u
SDMMC1_CMD/GMAC0_TXD3/UART9_RX_M0/GPIO2_A
7_u
CIF_CLKIN/EBC_SDCLK/GMAC1_MCLKINOUT_M1/
UART1_CTSn_M1/I2S2_SCLK_RX_M1/GPIO4_C1_
d
CIF_CLKOUT/EBC_GDCLK/PWM11_IR_M1/GPIO4_
C0_d
CIF_VSYNC/EBC_SDOE/GMAC1_MDIO_M1/I2S2_
SCLK_TX_M1/GPIO4_B7_d
CIF_HREF/EBC_SDLE/GMAC1_MDC_M1/UART1_R
TSn_M1/I2S2_MCLK_M1/GPIO4_B6_d
C27
C28
U27
U28
V1
V2
V3
V4
V5
V6
V7
27
RK3568J Datasheet
Rev 1.0
Pin Name
DDR_DQ3_A/DDR4_DQL6_A/LPDDR4_DQ3_A/DDR3_D
Q3/LPDDR3_DQ9
VSS_25
VSS_26
DDR4_A16_RASn/LPDDR4_A5_A/DDR3_RASn/LPDDR3
_A7/AC16
DDR4_A10/LPDDR4_CKE0_B/DDR3_A10/-/AC10
DDR4_ODT1/LPDDR4_CS0n_B/DDR3_CS0n/LPDDR3_C
S0n/AC28
DDR4_A4/LPDDR4_A3_B/DDR3_BA1/LPDDR3_A3/AC4
VSS_27
DDR_DQ2_B/DDR4_DQU3_B/LPDDR4_DQ2_B/DDR3_
DQ18/LPDDR3_DQ6
DDR_DM0_B/DDR4_DMU_B/LPDDR4_DM0_B/DDR3_D
M2/LPDDR3_DM0
DDR_DQ5_B/DDR4_DQU6_B/LPDDR4_DQ5_B/DDR3_
DQ21/LPDDR3_DQ3
DDR_DQ14_B/DDR4_DQL1_B/LPDDR4_DQ14_B/DDR3
_DQ30/LPDDR3_DQ20
I2C3_SDA_M0/UART3_RX_M0/CAN1_RX_M0/AUDIOP
WM_LOUT_P/ACODEC_ADC_DATA/GPIO1_A0_u
I2S1_SDO1_M0/I2S1_SDI3_M0/PDM_SDI3_M0/PCIE2
0_CLKREQn_M2/ACODEC_DAC_DATAR/GPIO1_B0_d
EMMC_D3/FLASH_D3/GPIO1_B7_u
FSPI_D1/FLASH_RDn/GPIO1_D2_u
SARADC_VIN2
SDMMC1_PWREN/I2C4_SDA_M1/UART8_RTSn_M0/CA
N2_RX_M1/GPIO2_B1_d
SDMMC1_CLK/GMAC0_TXCLK/UART9_TX_M0/GPIO2_
B0_d
Pin
Pin Name
Pin
D1
VSS_123
V9
D2
D3
VCCIO5_1
VCCIO5_2
V10
V11
D5
VCCIO7
V12
D6
VSS_124
V13
D8
AVSS_13
V14
D9
D11
AVSS_14
AVSS_15
V15
V16
D12
HDMI_TX_AVDD_0V9_1
V17
D14
HDMI_TX_AVDD_0V9_2
V18
D15
PMU_VDD_LOGIC_0V9
V19
D17
PMUPLL_AVSS
V20
D18
PMUPLL_AVDD_0V9
V21
D20
AVSS_16
V22
D21
D23
D24
AVSS_17
PCIE20_REFCLKP
PCIE20_REFCLKN
V23
V24
V25
D26
AVSS_18
V26
VSS_28
D28
DDR_DQ1_A/DDR4_DQL2_A/LPDDR4_DQ1_A/DDR3_D
Q1/LPDDR3_DQ14
E1
DDR_DQ2_A/DDR4_DQL4_A/LPDDR4_DQ2_A/DDR3_D
Q2/LPDDR3_DQ10
E2
VSS_29
DDR4_A15_CASn/LPDDR4_A2_A/DDR3_A0/-/AC15
DDR4_ACTn/LPDDR4_CKE1_B/DDR3_CASn/-/AC17
VSS_30
DDR4_ODT0/LPDDR4_CS1n_B/DDR3_ODT0/LPDDR3_
CS1n/AC27
DDR4_BA1/LPDDR4_A4_B/DDR3_A12/LPDDR3_A4/AC
19
DDR4_BA0/LPDDR4_A2_B/DDR3_A1/-/AC18
DDR_DQ3_B/DDR4_DQU1_B/LPDDR4_DQ3_B/DDR3_
DQ19/LPDDR3_DQ4
DDR_DQ7_B/DDR4_DQU2_B/LPDDR4_DQ7_B/DDR3_
DQ23/LPDDR3_DQ0
DDR_DQ6_B/DDR4_DQU4_B/LPDDR4_DQ6_B/DDR3_
DQ22/LPDDR3_DQ7
DDR_DM1_B/DDR4_DML_B/LPDDR4_DM1_B/DDR3_D
M3/LPDDR3_DM2
I2C3_SCL_M0/UART3_TX_M0/CAN1_TX_M0/AUDIOPW
M_LOUT_N/ACODEC_ADC_CLK/GPIO1_A1_u
I2S1_SDO2_M0/I2S1_SDI2_M0/PDM_SDI2_M0/PCIE2
0_WAKEn_M2/ACODEC_ADC_SYNC/GPIO1_B1_d
E3
E4
E6
E7
USB3_HOST1_SSTXN/SATA1_TXN/QSGMII_TXN_
M0
USB3_HOST1_SSTXP/SATA1_TXP/QSGMII_TXP_M
0
CAM_CLKOUT0/EBC_SDCE1/GMAC1_RXD0_M1/SP
I3_CS1_M0/I2S1_LRCK_RX_M1/GPIO4_A7_d
ISP_FLASHTRIGOUT/EBC_SDCE0/GMAC1_TXEN_
M1/SPI3_CS0_M0/I2S1_SCLK_RX_M1/GPIO4_A6
_d
VSS_125
VSS_126
VSS_127
VSS_128
E8
MIPI_CSI_RX_AVDD_0V9
W14
E9
MIPI_DSI_TX1_AVDD_0V9
W15
E11
MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9
W16
E12
AVSS_19
W17
E14
HDMI_TX_AVDD_1V8
W18
E15
PMUIO2
W19
E17
PCIE20_TXP/SATA2_TXP/QSGMII_TXP_M1
W27
E18
PCIE20_TXN/SATA2_TXN/QSGMII_TXN_M1
W28
EMMC_D5/FLASH_D5/GPIO1_C1_u
E21
EMMC_D6/FLASH_D6/GPIO1_C2_u
E22
SARADC_VIN3
E23
SDMMC1_DET/I2C4_SCL_M1/UART8_CTSn_M0/CAN2_
TX_M1/GPIO2_B2_u
CLK32K_OUT1/UART8_RX_M0/SPI1_CS1_M0/GPIO2_C
6_d
SDMMC1_D0/GMAC0_RXD2/UART6_RX_M0/GPIO2_A3
_u
SDMMC1_D1/GMAC0_RXD3/UART6_TX_M0/GPIO2_A4
_u
VSS_31
DDR_DQ0_A/DDR4_DQL0_A/LPDDR4_DQ0_A/DDR3_D
Q0/LPDDR3_DQ15
Copyright 2022 © Rockchip Electronics Co., Ltd.
D27
E20
E25
E26
E27
CIF_D15/EBC_SDDO15/GMAC1_TXD1_M1/UART9
_RX_M2/I2S2_LRCK_RX_M1/GPIO4_A5_d
CIF_D14/EBC_SDDO14/GMAC1_TXD0_M1/UART9
_TX_M2/I2S2_LRCK_TX_M1/GPIO4_A4_d
CIF_D13/EBC_SDDO13/GMAC1_RXCLK_M1/UART
7_RX_M2/PDM_SDI3_M1/GPIO4_A3_d
CIF_D12/EBC_SDDO12/GMAC1_RXD3_M1/UART7
_TX_M2/PDM_SDI2_M1/GPIO4_A2_d
CIF_D9/EBC_SDDO9/GMAC1_TXD3_M1/UART1_R
X_M1/PDM_SDI0_M1/GPIO3_D7_d
CIF_D8/EBC_SDDO8/GMAC1_TXD2_M1/UART1_T
X_M1/PDM_CLK0_M1/GPIO3_D6_d
CIF_D4/EBC_SDDO4/SDMMC2_CMD_M0/I2S1_SD
I0_M1/VOP_BT656_D4_M1/GPIO3_D2_d
V27
V28
W1
W2
W10
W11
W12
W13
Y1
Y2
Y3
Y4
Y5
Y6
Y7
E28
VSS_129
Y8
F1
VSS_130
Y9
F2
VSS_131
Y11
28
RK3568J Datasheet
Rev 1.0
Pin Name
VSS_32
DDR4_A3/LPDDR4_CKE1_A/DDR3_A3/-/AC3
DDR4_A1/-/DDR3_A2/-/AC1
DDR4_BG1/LPDDR4_ODT1_CA_A/DDR3_BA0/-/AC21
DDR4_BG0/LPDDR4_ODT1_CA_B/DDR3_WEn/-/AC20
VSS_33
DDR4_RESETn/LPDDR4_RESETn/DDR3_RESETn/AC29
Pin
F3
F4
F5
F7
F8
F9
F11
Pin
Y12
Y14
Y15
Y17
Y18
Y20
Y21
F14
F15
F17
Pin Name
VSS_132
MIPI_CSI_RX_AVDD_1V8
MIPI_DSI_TX1_AVDD_1V8
MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8
AVSS_20
PMUIO1
PMUPLL_AVDD_1V8
SDMMC0_DET/SATA_CP_DET/PCIE30X1_CLKREQn
_M0/GPIO0_A4_u
AVSS_21
AVSS_22
PCIE30_REFCLKP_IN
VSS_34
F12
VSS_35
VSS_36
VSS_37
I2S1_SCLK_RX_M0/UART4_RX_M0/PDM_CLK1_M0/SP
DIF_TX_M0/GPIO1_A4_d
EMMC_RSTn/FSPI_D2/FLASH_WPn/GPIO1_C7_d
SARADC_VIN7
F18
AVSS_23
Y26
F20
F21
PCIE20_RXP/SATA2_RXP/QSGMII_RXP_M1
PCIE20_RXN/SATA2_RXN/QSGMII_RXN_M1
Y27
Y28
Y22
Y23
Y24
Y25
2.6 Power/Ground IO Description
Table 2-2 Power/Ground IO information
Group
Ball#
Descriptions
A1 A3 A6 A10 A14 A18 A28 AA4 AA9
AA23 AB2 AB6 AD3 AE6 AE21 AF3 AF26
AG5 AH1 AH8 AH28 B5 B9 B12 B16 B23
B26 C3 C6 C8 C9 C11 C12 C14 C15 C17
C18 C25 D2 D3 D11 D28 E3 E7 F1 F3 F9
F12 F14 F15 F17 G5 G6 G8 G9 G11 G12
G14 G15 G17 G18 G24 H2 H3 H6 J3 J5
VSS
J17 J18 J20 J22 J26 K1 K11 K12 K13
K14 K19 L3 L5 L8 L11 L13 L14 L19 L20
Internal Core Ground,
Digital IO Ground,
L21 M2 M3 M6 M8 M11 M13 M14 M16
M18 N1 N12 N14 N15 N17 N18 P3 P6
P12 P14 P15 P17 R3 R6 R10 R11 R14
R15 R17 R18 R19 T10 T11 T14 T15 T17
T18 T19 U1 U6 U7 U8 U10 U14 U15 U16
U17 U18 V3 V8 V9 V13 W10 W11 W12
W13 Y8 Y9 Y11 Y12
AA12 AA14 AA15 AA17 AA24 AA26 AB11
AB12 AB14 AB15 AB17 AC9 AC11 AC12
AC15 AC18 AC25 AC26 AD26 AE14 AE17
AVSS
AE20 AE27 AE28 AF9 AF11 AF12 AF14
AF15 AF17 AF18 AF20 AF21 AG18 AH18
Analog Ground
AH23 J27 L24 L26 M21 M26 N28 P21
P26 R23 R26 U23 U26 V14 V15 V16 V22
V23 V26 W17 Y18 Y23 Y24 Y26
DDR_AVSS
J8
Analog Ground
PMUPLL_VSS
V20
Analog Ground
SYSPLL_VSS
N11
Analog Ground
VDD_CPU
J15 K15 K16 K17 K18 L15 L16 L17 L18
Copyright 2022 © Rockchip Electronics Co., Ltd.
M17
CPU Core Power
29
RK3568J Datasheet
Rev 1.0
Group
Ball#
VDD_CPU_CORE
M15
VDD_GPU
R13 T13 U11 U12 U13
GPU Core Power
VDD_NPU
M19 N19 P18 P19 P20
NPU Core Power
VDD_LOGIC
L12 M12 N13 N16 P13 P16 R12 R16 T12
T16
Descriptions
CPU Core Power feedback
Logic Power
PMU_VDD_LOGIC_0V9
V19
PMU digital Power
VCCIO1
H17
VCCIO1 Power Domain Power
VCCIO2
H18
VCCIO2 Power Domain Power
VCCIO3
L22
VCCIO3 Power Domain Power
VCCIO4
J21
VCCIO4 Power Domain Power
VCCIO5
V10
VCCIO5 Power Domain Power
VCCIO6
V11
VCCIO6 Power Domain Power
VCCIO7
R9
VCCIO7 Power Domain Power
Y20
PMU VCCIO1 Power Domain
PMUIO1
Power
W19
PMUIO2
PMU VCCIO2 Power Domain
Power
DDRPHY _VDDQ
H9 H11 H12 H14 H15 J9 L9 M9
DDR PHY Power
DDRPHY_VDDQL
J11 J12 J14 K10 L10 M10
DDR PHY Power
PMUPLL_AVDD_0V9
V21
PLL Analog Power
PMUPLL_AVDD_1V8
Y21
PLL Analog Power
SYSPLL_AVDD_0V9
P11
PLL Analog Power
SYSPLL_AVDD_1V8
N10
PLL Analog Power
USB2_AVDD_0V9
R8
USB2.0 analog Power
USB2_AVDD_1V8
P9
USB2.0 analog Power
USB2_AVDD_3V3
P10
USB2.0 analog Power
USB3_AVDD_0V9
P22
USB3.0 analog Power
USB3_AVDD_1V8
P23
USB3.0 analog Power
USB3_AVDD_3V3
M23
USB3.0 analog Power
MULTI_PHY_AVDD_0V9
R20 R21
Multi-Phy analog Power
MULTI_PHY_AVDD_1V8
R22
Multi-Phy analog Power
PCIE30_AVDD_0V9
U21
PCIe3.0 analog Power
PCIE30_AVDD_1V8
U22
PCIe3.0 analog Power
MIPI_CSI_RX_AVDD_0V9
W14
MIPI CSI RX Analog Power
MIPI_CSI_RX_AVDD_1V8
Y14
MIPI CSI RX Analog Power
Copyright 2022 © Rockchip Electronics Co., Ltd.
30
RK3568J Datasheet
Group
Rev 1.0
Ball#
Descriptions
MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9
W16
MIPI DSI TX0 Analog Power
MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8
Y17
MIPI DSI TX0 Analog Power
MIPI_DSI_TX1/LVDS_TX1_AVDD_0V9
W15
MIPI DSI TX1 Analog Power
MIPI_DSI_TX1/LVDS_TX1_AVDD_1V8
Y15
MIPI DSI TX1 Analog Power
EDP_TX_AVDD_0V9
M20
EDP Analog Power
EDP_TX_AVDD_1V8
M22
EDP Analog Power
HDMI_TX_AVDD_0V9
V17 V18
HDMI PHY analog Power
HDMI_TX_AVDD_1V8
W18
HDMI PHY analog Power
SARADC_AVDD_1V8
H22
SARADC Analog Power
OTP_VCC_1V8
H20
OTP Analog Power
Copyright 2022 © Rockchip Electronics Co., Ltd.
31
RK3568J Datasheet
Rev 1.0
2.7 Function IO Description
Table 2-3 Function IO description
PIN
PIN Name
Func1
AF28
XIN24M
XIN24M
AF27
XOUT24M
XOUT24M
Func2
Func3
Func4
AE26
GPIO0_D3_d
GPIO0_D3_d
AB23
GPIO0_D4_d
GPIO0_D4_d
AD25
GPIO0_D5_d
GPIO0_D5_d
AC24
GPIO0_D6_d
GPIO0_D6_d
AB24
TVSS
TVSS
AH27
nPOR_u
nPOR_u
AG27
REFCLK_OUT/GPIO0_A0_d
GPIO0_A0_d
REFCLK_OUT
AG26
TSADC_SHUT_M0/TSADC_SHUT_ORG/GPIO0_A1_z
GPIO0_A1_z
TSADC_SHUT_M0
AG28
PMIC_SLEEP/TSADC_SHUT_M1/GPIO0_A2_d
GPIO0_A2_d
PMIC_SLEEP
TSADC_SHUT_OR
G
TSADC_SHUT_M1
AA22
GPIO0_A3_u
GPIO0_A3_u
Y22
SDMMC0_DET/SATA_CP_DET/PCIE30X1_CLKREQn_M0/GPIO0_A4_u
GPIO0_A4_u
SDMMC0_DET
SATA_CP_DET
PCIE30X1_CLKREQn_
M0
AF25
SDMMC0_PWREN/SATA_MP_SWITCH/PCIE20_CLKREQn_M0/GPIO0_A5_d
GPIO0_A5_d
SDMMC0_PWREN
SATA_MP_SWITC
H
PCIE20_CLKREQn_M
0
AE24
GPU_PWREN/SATA_CP_POD/PCIE30X2_CLKREQn_M0/GPIO0_A6_d
GPIO0_A6_d
GPU_PWREN
SATA_CP_POD
PCIE30X2_CLKREQn_
M0
AG25
FLASH_VOL_SEL/GPIO0_A7_u
GPIO0_A7_u
FLASH_VOL_SEL
AD23
CLK32K_IN/CLK32K_OUT0/PCIE30X2_BUTTONRSTn/GPIO0_B0_u
GPIO0_B0_u
CLK32K_IN
CLK32K_OUT0
PCIE30X2_BUTTONR
STn
Func5
Die Power
Domain
PMUIO0
PMUIO1
AF24
I2C0_SCL/GPIO0_B1_u
GPIO0_B1_u
I2C0_SCL
AB21
I2C0_SDA/GPIO0_B2_u
GPIO0_B2_u
I2C0_SDA
AG24
I2C1_SCL/CAN0_TX_M0/PCIE30X1_BUTTONRSTn/MCU_JTAG_TDO/GPIO0_B3_u
GPIO0_B3_u
I2C1_SCL
CAN0_TX_M0
PCIE30X1_BUTTONR
STn
MCU_JTAG_TDO
AB20
I2C1_SDA/CAN0_RX_M0/PCIE20_BUTTONRSTn/MCU_JTAG_TCK/GPIO0_B4_u
GPIO0_B4_u
I2C1_SDA
CAN0_RX_M0
PCIE20_BUTTONRST
n
MCU_JTAG_TCK
AC22
I2C2_SCL_M0/SPI0_CLK_M0/PCIE20_WAKEn_M0/PWM1_M1/GPIO0_B5_u
GPIO0_B5_u
I2C2_SCL_M0
SPI0_CLK_M0
PCIE20_WAKEn_M0
PWM1_M1
AA20
I2C2_SDA_M0/SPI0_MOSI_M0/PCIE20_PERSTn_M0/PWM2_M1/GPIO0_B6_u
GPIO0_B6_u
I2C2_SDA_M0
SPI0_MOSI_M0
PCIE20_PERSTn_M0
PWM2_M1
AH26
PWM0_M0/CPUAVS/GPIO0_B7_d
GPIO0_B7_d
PWM0_M0
CPUAVS
AD22
PWM1_M0/GPUAVS/UART0_RX/GPIO0_C0_d
GPIO0_C0_d
PWM1_M0
GPUAVS
UART0_RX
AF23
PWM2_M0/NPUAVS/UART0_TX/MCU_JTAG_TDI/GPIO0_C1_d
GPIO0_C1_d
PWM2_M0
NPUAVS
UART0_TX
MCU_JTAG_TDI
AG23
PWM3_IR/EDP_HPDIN_M1/PCIE30X1_WAKEn_M0/MCU_JTAG_TMS/GPIO0_C2_d
GPIO0_C2_d
PWM3_IR
EDP_HPDIN_M1
PCIE30X1_WAKEn_M
0
MCU_JTAG_TMS
PCIE30X1_PERSTn_M
0
MCU_JTAG_TRSTn
AE23
PWM4/VOP_PWM_M0/PCIE30X1_PERSTn_M0/MCU_JTAG_TRSTn/GPIO0_C3_d
GPIO0_C3_d
PWM4
VOP_PWM_M0
AD21
PWM5/SPI0_CS1_M0/UART0_RTSn/GPIO0_C4_d
GPIO0_C4_d
PWM5
SPI0_CS1_M0
AC21
PWM6/SPI0_MISO_M0/PCIE30X2_WAKEn_M0/GPIO0_C5_d
GPIO0_C5_d
PWM6
SPI0_MISO_M0
AD20
PWM7_IR/SPI0_CS0_M0/PCIE30X2_PERSTn_M0/GPIO0_C6_d
GPIO0_C6_d
PWM7_IR
SPI0_CS0_M0
AH25
HDMITX_CEC_M1/PWM0_M1/UART0_CTSn/GPIO0_C7_d
GPIO0_C7_d
HDMITX_CEC_M1
PWM0_M1
UART0_RTSn
PCIE30X2_WAKEn_M
0
PCIE30X2_PERSTn_M
0
UART0_CTSn
AC20
UART2_RX_M0/GPIO0_D0_u
GPIO0_D0_u
UART2_RX_M0
AH24
UART2_TX_M0/GPIO0_D1_u
GPIO0_D1_u
UART2_TX_M0
D18
I2C3_SDA_M0/UART3_RX_M0/CAN1_RX_M0/AUDIOPWM_LOUT_P/ACODEC_ADC_DATA/GPI
O1_A0_u
GPIO1_A0_u
I2C3_SDA_M0
UART3_RX_M0
CAN1_RX_M0
Copyright 2022© Rockchip Electronics Co., Ltd.
Func6
PMUIO2
AUDIOPWM_LOUT_P
ACODEC_ADC_DA
TA
VCCIO1
32
RK3568J Datasheet
Rev 1.0
PIN
PIN Name
Func1
Func2
Func3
Func4
Func5
Func6
E18
I2C3_SCL_M0/UART3_TX_M0/CAN1_TX_M0/AUDIOPWM_LOUT_N/ACODEC_ADC_CLK/GPIO
1_A1_u
GPIO1_A1_u
I2C3_SCL_M0
UART3_TX_M0
CAN1_TX_M0
AUDIOPWM_LOUT_N
ACODEC_ADC_CL
K
A19
I2S1_MCLK_M0/UART3_RTSn_M0/SCR_CLK/PCIE30X1_PERSTn_M2/GPIO1_A2_d
GPIO1_A2_d
I2S1_MCLK_M0
UART3_RTSn_M0
SCR_CLK
PCIE30X1_PERSTn_
M2
B19
I2S1_SCLK_TX_M0/UART3_CTSn_M0/SCR_IO/PCIE30X1_WAKEn_M2/ACODEC_DAC_CLK/GP
IO1_A3_d
GPIO1_A3_d
I2S1_SCLK_TX_M
0
UART3_CTSn_M0
SCR_IO
PCIE30X1_WAKEn_
M2
F18
I2S1_SCLK_RX_M0/UART4_RX_M0/PDM_CLK1_M0/SPDIF_TX_M0/GPIO1_A4_d
GPIO1_A4_d
I2S1_SCLK_RX_M
0
UART4_RX_M0
PDM_CLK1_M0
SPDIF_TX_M0
A20
I2S1_LRCK_TX_M0/UART4_RTSn_M0/SCR_RST/PCIE30X1_CLKREQn_M2/ACODEC_DAC_SY
NC/GPIO1_A5_d
GPIO1_A5_d
I2S1_LRCK_TX_M
0
UART4_RTSn_M0
SCR_RST
PCIE30X1_CLKREQn
_M2
C20
I2S1_LRCK_RX_M0/UART4_TX_M0/PDM_CLK0_M0/AUDIOPWM_ROUT_P/GPIO1_A6_d
GPIO1_A6_d
I2S1_LRCK_RX_M
0
UART4_TX_M0
PDM_CLK0_M0
AUDIOPWM_ROUT_P
B20
I2S1_SDO0_M0/UART4_CTSn_M0/SCR_DET/AUDIOPWM_ROUT_N/ACODEC_DAC_DATAL/GP
IO1_A7_d
GPIO1_A7_d
I2S1_SDO0_M0
UART4_CTSn_M0
SCR_DET
AUDIOPWM_ROUT_
N
ACODEC_DAC_DA
TAL
D20
I2S1_SDO1_M0/I2S1_SDI3_M0/PDM_SDI3_M0/PCIE20_CLKREQn_M2/ACODEC_DAC_DATA
R/GPIO1_B0_d
GPIO1_B0_d
I2S1_SDO1_M0
I2S1_SDI3_M0
PDM_SDI3_M0
PCIE20_CLKREQn_M
2
ACODEC_DAC_DA
TAR
E20
I2S1_SDO2_M0/I2S1_SDI2_M0/PDM_SDI2_M0/PCIE20_WAKEn_M2/ACODEC_ADC_SYNC/G
PIO1_B1_d
GPIO1_B1_d
I2S1_SDO2_M0
I2S1_SDI2_M0
PDM_SDI2_M0
PCIE20_WAKEn_M2
ACODEC_ADC_SY
NC
A21
I2S1_SDO3_M0/I2S1_SDI1_M0/PDM_SDI1_M0/PCIE20_PERSTn_M2/GPIO1_B2_d
GPIO1_B2_d
I2S1_SDO3_M0
I2S1_SDI1_M0
PDM_SDI1_M0
PCIE20_PERSTn_M2
B21
I2S1_SDI0_M0/PDM_SDI0_M0/GPIO1_B3_d
GPIO1_B3_d
I2S1_SDI0_M0
PDM_SDI0_M0
A24
EMMC_D0/FLASH_D0/GPIO1_B4_u
GPIO1_B4_u
EMMC_D0
FLASH_D0
C21
EMMC_D1/FLASH_D1/GPIO1_B5_u
GPIO1_B5_u
EMMC_D1
FLASH_D1
B24
EMMC_D2/FLASH_D2/GPIO1_B6_u
GPIO1_B6_u
EMMC_D2
FLASH_D2
D21
EMMC_D3/FLASH_D3/GPIO1_B7_u
GPIO1_B7_u
EMMC_D3
FLASH_D3
A25
EMMC_D4/FLASH_D4/GPIO1_C0_u
GPIO1_C0_u
EMMC_D4
FLASH_D4
E21
EMMC_D5/FLASH_D5/GPIO1_C1_u
GPIO1_C1_u
EMMC_D5
FLASH_D5
E22
EMMC_D6/FLASH_D6/GPIO1_C2_u
GPIO1_C2_u
EMMC_D6
FLASH_D6
B25
EMMC_D7/FLASH_D7/GPIO1_C3_u
GPIO1_C3_u
EMMC_D7
FLASH_D7
B22
EMMC_CMD/FLASH_WRn/GPIO1_C4_u
GPIO1_C4_u
EMMC_CMD
FLASH_WRn
A23
EMMC_CLKOUT/FLASH_DQS/GPIO1_C5_d
GPIO1_C5_d
EMMC_CLKOUT
FLASH_DQS
A26
EMMC_DATA_STROBE/FSPI_CS1n/FLASH_CLE/GPIO1_C6_d
GPIO1_C6_d
EMMC_DATA_STR
OBE
FSPI_CS1n
FLASH_CLE
F20
EMMC_RSTn/FSPI_D2/FLASH_WPn/GPIO1_C7_d
GPIO1_C7_d
EMMC_RSTn
FSPI_D2
FLASH_WPn
A22
FSPI_CLK/FLASH_ALE/GPIO1_D0_d
GPIO1_D0_d
FSPI_CLK
FLASH_ALE
C24
FSPI_D0/FLASH_RDY/GPIO1_D1_u
GPIO1_D1_u
FSPI_D0
FLASH_RDY
D23
FSPI_D1/FLASH_RDn/GPIO1_D2_u
GPIO1_D2_u
FSPI_D1
FLASH_RDn
C23
FSPI_CS0n/FLASH_CS0n/GPIO1_D3_u
GPIO1_D3_u
FSPI_CS0n
FLASH_CS0n
A27
FSPI_D3/FLASH_CS1n/GPIO1_D4_u
GPIO1_D4_u
FSPI_D3
FLASH_CS1n
J25
SDMMC0_D0/UART2_TX_M1/UART6_TX_M1/PWM8_M1/GPIO1_D5_u
GPIO1_D5_u
SDMMC0_D0
UART2_TX_M1
UART6_TX_M1
PWM8_M1
J24
SDMMC0_D1/UART2_RX_M1/UART6_RX_M1/PWM9_M1/GPIO1_D6_u
GPIO1_D6_u
SDMMC0_D1
UART2_RX_M1
UART6_RX_M1
PWM9_M1
H26
SDMMC0_D2/ARMJTAG_TCK/UART5_CTSn_M0/GPIO1_D7_u
GPIO1_D7_u
SDMMC0_D2
ARMJTAG_TCK
UART5_CTSn_M0
ACODEC_DAC_CL
K
ACODEC_DAC_SY
NC
VCCIO2
VCCIO3
J23
SDMMC0_D3/ARMJTAG_TMS/UART5_RTSn_M0/GPIO2_A0_u
GPIO2_A0_u
SDMMC0_D3
ARMJTAG_TMS
UART5_RTSn_M0
H27
SDMMC0_CMD/PWM10_M1/UART5_RX_M0/CAN0_TX_M1/GPIO2_A1_u
GPIO2_A1_u
SDMMC0_CMD
PWM10_M1
UART5_RX_M0
CAN0_TX_M1
H28
SDMMC0_CLK/TEST_CLKOUT/UART5_TX_M0/CAN0_RX_M1/GPIO2_A2_d
GPIO2_A2_d
SDMMC0_CLK
TEST_CLKOUT
UART5_TX_M0
CAN0_RX_M1
E27
SDMMC1_D0/GMAC0_RXD2/UART6_RX_M0/GPIO2_A3_u
GPIO2_A3_u
SDMMC1_D0
GMAC0_RXD2
UART6_RX_M0
E28
SDMMC1_D1/GMAC0_RXD3/UART6_TX_M0/GPIO2_A4_u
GPIO2_A4_u
SDMMC1_D1
GMAC0_RXD3
UART6_TX_M0
B28
SDMMC1_D2/GMAC0_RXCLK/UART7_RX_M0/GPIO2_A5_u
GPIO2_A5_u
SDMMC1_D2
GMAC0_RXCLK
UART7_RX_M0
C27
SDMMC1_D3/GMAC0_TXD2/UART7_TX_M0/GPIO2_A6_u
GPIO2_A6_u
SDMMC1_D3
GMAC0_TXD2
UART7_TX_M0
C28
SDMMC1_CMD/GMAC0_TXD3/UART9_RX_M0/GPIO2_A7_u
GPIO2_A7_u
SDMMC1_CMD
GMAC0_TXD3
UART9_RX_M0
D27
SDMMC1_CLK/GMAC0_TXCLK/UART9_TX_M0/GPIO2_B0_d
GPIO2_B0_d
SDMMC1_CLK
GMAC0_TXCLK
UART9_TX_M0
D26
SDMMC1_PWREN/I2C4_SDA_M1/UART8_RTSn_M0/CAN2_RX_M1/GPIO2_B1_d
GPIO2_B1_d
SDMMC1_PWREN
I2C4_SDA_M1
UART8_RTSn_M0
CAN2_RX_M1
E25
SDMMC1_DET/I2C4_SCL_M1/UART8_CTSn_M0/CAN2_TX_M1/GPIO2_B2_u
GPIO2_B2_u
SDMMC1_DET
I2C4_SCL_M1
UART8_CTSn_M0
CAN2_TX_M1
Copyright 2022© Rockchip Electronics Co., Ltd.
Die Power
Domain
VCCIO4
33
RK3568J Datasheet
Rev 1.0
PIN
PIN Name
Func1
Func2
Func3
UART1_RX_M0
Func4
Func5
F28
GMAC0_TXD0/UART1_RX_M0/GPIO2_B3_u
GPIO2_B3_u
GMAC0_TXD0
G27
GMAC0_TXD1/UART1_TX_M0/GPIO2_B4_u
GPIO2_B4_u
GMAC0_TXD1
UART1_TX_M0
G28
GMAC0_TXEN/UART1_RTSn_M0/SPI1_CLK_M0/GPIO2_B5_u
GPIO2_B5_u
GMAC0_TXEN
UART1_RTSn_M0
SPI1_CLK_M0
F27
GMAC0_RXD0/UART1_CTSn_M0/SPI1_MISO_M0/GPIO2_B6_u
GPIO2_B6_u
GMAC0_RXD0
UART1_CTSn_M0
SPI1_MISO_M0
H25
I2S2_SCLK_RX_M0/GMAC0_RXD1/UART6_RTSn_M0/SPI1_MOSI_M0/GPIO2_B7_d
GPIO2_B7_d
GMAC0_RXD1
UART6_RTSn_M0
SPI1_MOSI_M0
UART6_CTSn_M0
SPI1_CS0_M0
UART7_RTSn_M0
SPI2_CLK_M0
F24
I2S2_LRCK_RX_M0/GMAC0_RXDV_CRS/UART6_CTSn_M0/SPI1_CS0_M0/GPIO2_C0_d
GPIO2_C0_d
G23
I2S2_MCLK_M0/ETH0_REFCLKO_25M/UART7_RTSn_M0/SPI2_CLK_M0/GPIO2_C1_d
GPIO2_C1_d
F25
I2S2_SCLK_TX_M0/GMAC0_MCLKINOUT/UART7_CTSn_M0/SPI2_MISO_M0/GPIO2_C2_d
GPIO2_C2_d
H24
I2S2_LRCK_TX_M0/GMAC0_MDC/UART9_RTSn_M0/SPI2_MOSI_M0/GPIO2_C3_d
GPIO2_C3_d
H23
I2S2_SDO_M0/GMAC0_MDIO/UART9_CTSn_M0/SPI2_CS0_M0/GPIO2_C4_d
GPIO2_C4_d
F26
I2S2_SDI_M0/GMAC0_RXER/UART8_TX_M0/SPI2_CS1_M0/GPIO2_C5_d
E26
CLK32K_OUT1/UART8_RX_M0/SPI1_CS1_M0/GPIO2_C6_d
AG6
AD7
AC8
AC7
AF5
AF6
AD6
AH5
AH4
AB8
AE5
AG4
AF4
AH3
AG3
LCDC_D0/VOP_BT656_D0_M0/SPI0_MISO_M1/PCIE20_CLKREQn_M1/I2S1_MCLK_M2/GPIO
2_D0_d
LCDC_D1/VOP_BT656_D1_M0/SPI0_MOSI_M1/PCIE20_WAKEn_M1/I2S1_SCLK_TX_M2/GPI
O2_D1_d
LCDC_D2/VOP_BT656_D2_M0/SPI0_CS0_M1/PCIE30X1_CLKREQn_M1/I2S1_LRCK_TX_M2/
GPIO2_D2_d
LCDC_D3/VOP_BT656_D3_M0/SPI0_CLK_M1/PCIE30X1_WAKEn_M1/I2S1_SDI0_M2/GPIO2_
D3_d
LCDC_D4/VOP_BT656_D4_M0/SPI2_CS1_M1/PCIE30X2_CLKREQn_M1/I2S1_SDI1_M2/GPIO
2_D4_d
LCDC_D5/VOP_BT656_D5_M0/SPI2_CS0_M1/PCIE30X2_WAKEn_M1/I2S1_SDI2_M2/GPIO2
_D5_d
LCDC_D6/VOP_BT656_D6_M0/SPI2_MOSI_M1/PCIE30X2_PERSTn_M1/I2S1_SDI3_M2/GPIO
2_D6_d
LCDC_D7/VOP_BT656_D7_M0/SPI2_MISO_M1/UART8_TX_M1/I2S1_SDO0_M2/GPIO2_D7_d
LCDC_CLK/VOP_BT656_CLK_M0/SPI2_CLK_M1/UART8_RX_M1/I2S1_SDO1_M2/GPIO3_A0_
d
LCDC_D8/VOP_BT1120_D0/SPI1_CS0_M1/PCIE30X1_PERSTn_M1/SDMMC2_D0_M1/GPIO3_
A1_d
LCDC_D9/VOP_BT1120_D1/GMAC1_TXD2_M0/I2S3_MCLK_M0/SDMMC2_D1_M1/GPIO3_A2
_d
LCDC_D10/VOP_BT1120_D2/GMAC1_TXD3_M0/I2S3_SCLK_M0/SDMMC2_D2_M1/GPIO3_A3
_d
LCDC_D11/VOP_BT1120_D3/GMAC1_RXD2_M0/I2S3_LRCK_M0/SDMMC2_D3_M1/GPIO3_A
4_d
LCDC_D12/VOP_BT1120_D4/GMAC1_RXD3_M0/I2S3_SDO_M0/SDMMC2_CMD_M1/GPIO3_A
5_d
LCDC_D13/VOP_BT1120_CLK/GMAC1_TXCLK_M0/I2S3_SDI_M0/SDMMC2_CLK_M1/GPIO3_
A6_d
I2S2_SCLK_RX_M
0
I2S2_LRCK_RX_M
0
I2S2_MCLK_M0
I2S2_SCLK_TX_M
0
I2S2_LRCK_TX_M
0
GMAC0_RXDV_CR
S
ETH0_REFCLKO_
25M
GMAC0_MCLKINO
UT
UART7_CTSn_M0
SPI2_MISO_M0
GMAC0_MDC
UART9_RTSn_M0
SPI2_MOSI_M0
I2S2_SDO_M0
GMAC0_MDIO
UART9_CTSn_M0
SPI2_CS0_M0
GPIO2_C5_d
I2S2_SDI_M0
GMAC0_RXER
UART8_TX_M0
SPI2_CS1_M0
GPIO2_C6_d
CLK32K_OUT1
UART8_RX_M0
SPI1_CS1_M0
GPIO2_D0_d
LCDC_D0
GPIO2_D1_d
LCDC_D1
GPIO2_D2_d
LCDC_D2
GPIO2_D3_d
LCDC_D3
GPIO2_D4_d
LCDC_D4
GPIO2_D5_d
LCDC_D5
GPIO2_D6_d
LCDC_D6
GPIO2_D7_d
LCDC_D7
GPIO3_A0_d
LCDC_CLK
VOP_BT656_D0_
M0
VOP_BT656_D1_
M0
VOP_BT656_D2_
M0
VOP_BT656_D3_
M0
VOP_BT656_D4_
M0
VOP_BT656_D5_
M0
VOP_BT656_D6_
M0
VOP_BT656_D7_
M0
VOP_BT656_CLK_
M0
SPI0_MISO_M1
PCIE20_CLKREQn_M
1
SPI0_MOSI_M1
PCIE20_WAKEn_M1
SPI0_CS0_M1
SPI0_CLK_M1
SPI2_CS1_M1
SPI2_CS0_M1
SPI2_MOSI_M1
SPI2_MISO_M1
PCIE30X1_CLKREQn
_M1
PCIE30X1_WAKEn_
M1
PCIE30X2_CLKREQn
_M1
PCIE30X2_WAKEn_
M1
PCIE30X2_PERSTn_
M1
Func6
I2S1_MCLK_M2
I2S1_SCLK_TX_M
2
I2S1_LRCK_TX_M
2
I2S1_SDI0_M2
I2S1_SDI1_M2
I2S1_SDI2_M2
I2S1_SDI3_M2
UART8_TX_M1
I2S1_SDO0_M2
SPI2_CLK_M1
UART8_RX_M1
I2S1_SDO1_M2
SDMMC2_D0_M1
GPIO3_A1_d
LCDC_D8
VOP_BT1120_D0
SPI1_CS0_M1
PCIE30X1_PERSTn_
M1
GPIO3_A2_d
LCDC_D9
VOP_BT1120_D1
GMAC1_TXD2_M0
I2S3_MCLK_M0
SDMMC2_D1_M1
GPIO3_A3_d
LCDC_D10
VOP_BT1120_D2
GMAC1_TXD3_M0
I2S3_SCLK_M0
SDMMC2_D2_M1
GPIO3_A4_d
LCDC_D11
VOP_BT1120_D3
GMAC1_RXD2_M0
I2S3_LRCK_M0
SDMMC2_D3_M1
GPIO3_A5_d
LCDC_D12
VOP_BT1120_D4
GMAC1_RXD3_M0
I2S3_SDO_M0
SDMMC2_CMD_M
1
SDMMC2_CLK_M1
GPIO3_A6_d
LCDC_D13
VOP_BT1120_CLK
GMAC1_TXCLK_M0
I2S3_SDI_M0
AH2
LCDC_D14/VOP_BT1120_D5/GMAC1_RXCLK_M0/SDMMC2_DET_M1/GPIO3_A7_d
GPIO3_A7_d
LCDC_D14
VOP_BT1120_D5
GMAC1_RXCLK_M0
SDMMC2_DET_M1
AG2
LCDC_D15/VOP_BT1120_D6/ETH1_REFCLKO_25M_M0/SDMMC2_PWREN_M1/GPIO3_B0_d
GPIO3_B0_d
LCDC_D15
VOP_BT1120_D6
ETH1_REFCLKO_25M
_M0
SDMMC2_PWREN_M
1
AG1
LCDC_D16/VOP_BT1120_D7/GMAC1_RXD0_M0/UART4_RX_M1/PWM8_M0/GPIO3_B1_d
GPIO3_B1_d
LCDC_D16
VOP_BT1120_D7
GMAC1_RXD0_M0
UART4_RX_M1
AF2
LCDC_D17/VOP_BT1120_D8/GMAC1_RXD1_M0/UART4_TX_M1/PWM9_M0/GPIO3_B2_d
LCDC_D18/VOP_BT1120_D9/GMAC1_RXDV_CRS_M0/I2C5_SCL_M0/PDM_SDI0_M2/GPIO3_
B3_d
LCDC_D19/VOP_BT1120_D10/GMAC1_RXER_M0/I2C5_SDA_M0/PDM_SDI1_M2/GPIO3_B4_
d
GPIO3_B2_d
LCDC_D17
VOP_BT1120_D8
UART4_TX_M1
PWM9_M0
GPIO3_B3_d
LCDC_D18
VOP_BT1120_D9
GMAC1_RXD1_M0
GMAC1_RXDV_CRS_
M0
I2C5_SCL_M0
PDM_SDI0_M2
GPIO3_B4_d
LCDC_D19
GMAC1_RXER_M0
I2C5_SDA_M0
PDM_SDI1_M2
LCDC_D20/VOP_BT1120_D11/GMAC1_TXD0_M0/I2C3_SCL_M1/PWM10_M0/GPIO3_B5_d
GPIO3_B5_d
LCDC_D20
GMAC1_TXD0_M0
I2C3_SCL_M1
PWM10_M0
GPIO3_B6_d
LCDC_D21
GMAC1_TXD1_M0
I2C3_SDA_M1
PWM11_IR_M0
GPIO3_B7_d
LCDC_D22
VOP_BT1120_D1
0
VOP_BT1120_D1
1
VOP_BT1120_D1
2
PWM12_M0
GMAC1_TXEN_M0
UART3_TX_M1
PDM_SDI2_M2
GPIO3_C0_d
LCDC_D23
PWM13_M0
GMAC1_MCLKINOUT
_M0
UART3_RX_M1
PDM_SDI3_M2
AF1
AE1
AE2
AE3
AD4
AD2
LCDC_D21/VOP_BT1120_D12/GMAC1_TXD1_M0/I2C3_SDA_M1/PWM11_IR_M0/GPIO3_B6_
d
LCDC_D22/PWM12_M0/GMAC1_TXEN_M0/UART3_TX_M1/PDM_SDI2_M2/GPIO3_B7_d
LCDC_D23/PWM13_M0/GMAC1_MCLKINOUT_M0/UART3_RX_M1/PDM_SDI3_M2/GPIO3_C0_
d
Copyright 2022© Rockchip Electronics Co., Ltd.
Die Power
Domain
VCCIO5
PWM8_M0
34
RK3568J Datasheet
PIN
AD1
AA7
AC4
AC3
AC2
AC5
AA6
AB5
Rev 1.0
PIN Name
LCDC_HSYNC/VOP_BT1120_D13/SPI1_MOSI_M1/PCIE20_PERSTn_M1/I2S1_SDO2_M2/GPI
O3_C1_d
LCDC_VSYNC/VOP_BT1120_D14/SPI1_MISO_M1/UART5_TX_M1/I2S1_SDO3_M2/GPIO3_C2
_d
LCDC_DEN/VOP_BT1120_D15/SPI1_CLK_M1/UART5_RX_M1/I2S1_SCLK_RX_M2/GPIO3_C3
_d
Func1
Func2
GPIO3_C1_d
LCDC_HSYNC
GPIO3_C2_d
LCDC_VSYNC
Func3
VOP_BT1120_D1
3
VOP_BT1120_D1
4
VOP_BT1120_D1
5
Func4
Func5
Func6
SPI1_MOSI_M1
PCIE20_PERSTn_M1
I2S1_SDO2_M2
SPI1_MISO_M1
UART5_TX_M1
I2S1_SDO3_M2
UART5_RX_M1
I2S1_SCLK_RX_M
2
GPIO3_C3_d
LCDC_DEN
PWM14_M0/VOP_PWM_M1/GMAC1_MDC_M0/UART7_TX_M1/PDM_CLK1_M2/GPIO3_C4_d
PWM15_IR_M0/SPDIF_TX_M1/GMAC1_MDIO_M0/UART7_RX_M1/I2S1_LRCK_RX_M2/GPIO3
_C5_d
GPIO3_C4_d
PWM14_M0
VOP_PWM_M1
GMAC1_MDC_M0
UART7_TX_M1
GPIO3_C5_d
PWM15_IR_M0
SPDIF_TX_M1
GMAC1_MDIO_M0
UART7_RX_M1
CIF_D0/EBC_SDDO0/SDMMC2_D0_M0/I2S1_MCLK_M1/VOP_BT656_D0_M1/GPIO3_C6_d
GPIO3_C6_d
CIF_D0
EBC_SDDO0
SDMMC2_D0_M0
I2S1_MCLK_M1
GPIO3_C7_d
CIF_D1
EBC_SDDO1
SDMMC2_D1_M0
I2S1_SCLK_TX_M1
CIF_D1/EBC_SDDO1/SDMMC2_D1_M0/I2S1_SCLK_TX_M1/VOP_BT656_D1_M1/GPIO3_C7_
d
CIF_D2/EBC_SDDO2/SDMMC2_D2_M0/I2S1_LRCK_TX_M1/VOP_BT656_D2_M1/GPIO3_D0_
d
SPI1_CLK_M1
PDM_CLK1_M2
I2S1_LRCK_RX_M
2
VOP_BT656_D0_M
1
VOP_BT656_D1_M
1
VOP_BT656_D2_M
1
VOP_BT656_D3_M
1
VOP_BT656_D4_M
1
VOP_BT656_D5_M
1
VOP_BT656_D6_M
1
VOP_BT656_D7_M
1
GPIO3_D0_d
CIF_D2
EBC_SDDO2
SDMMC2_D2_M0
I2S1_LRCK_TX_M1
AB1
CIF_D3/EBC_SDDO3/SDMMC2_D3_M0/I2S1_SDO0_M1/VOP_BT656_D3_M1/GPIO3_D1_d
GPIO3_D1_d
CIF_D3
EBC_SDDO3
SDMMC2_D3_M0
I2S1_SDO0_M1
Y7
CIF_D4/EBC_SDDO4/SDMMC2_CMD_M0/I2S1_SDI0_M1/VOP_BT656_D4_M1/GPIO3_D2_d
GPIO3_D2_d
CIF_D4
EBC_SDDO4
SDMMC2_CMD_M0
I2S1_SDI0_M1
AC1
CIF_D5/EBC_SDDO5/SDMMC2_CLK_M0/I2S1_SDI1_M1/VOP_BT656_D5_M1/GPIO3_D3_d
GPIO3_D3_d
CIF_D5
EBC_SDDO5
SDMMC2_CLK_M0
I2S1_SDI1_M1
AA1
CIF_D6/EBC_SDDO6/SDMMC2_DET_M0/I2S1_SDI2_M1/VOP_BT656_D6_M1/GPIO3_D4_d
GPIO3_D4_d
CIF_D6
EBC_SDDO6
SDMMC2_DET_M0
I2S1_SDI2_M1
AA5
CIF_D7/EBC_SDDO7/SDMMC2_PWREN_M0/I2S1_SDI3_M1/VOP_BT656_D7_M1/GPIO3_D5_
d
GPIO3_D5_d
CIF_D7
EBC_SDDO7
SDMMC2_PWREN_M0
I2S1_SDI3_M1
Y6
CIF_D8/EBC_SDDO8/GMAC1_TXD2_M1/UART1_TX_M1/PDM_CLK0_M1/GPIO3_D6_d
GPIO3_D6_d
CIF_D8
EBC_SDDO8
GMAC1_TXD2_M1
UART1_TX_M1
PDM_CLK0_M1
Y5
CIF_D9/EBC_SDDO9/GMAC1_TXD3_M1/UART1_RX_M1/PDM_SDI0_M1/GPIO3_D7_d
GPIO3_D7_d
CIF_D9
EBC_SDDO9
GMAC1_TXD3_M1
UART1_RX_M1
PDM_SDI0_M1
AA3
CIF_D10/EBC_SDDO10/GMAC1_TXCLK_M1/PDM_CLK1_M1/GPIO4_A0_d
GPIO4_A0_d
CIF_D10
EBC_SDDO10
GMAC1_TXCLK_M1
PDM_CLK1_M1
AA2
CIF_D11/EBC_SDDO11/GMAC1_RXD2_M1/PDM_SDI1_M1/GPIO4_A1_d
GPIO4_A1_d
CIF_D11
EBC_SDDO11
GMAC1_RXD2_M1
PDM_SDI1_M1
Y4
CIF_D12/EBC_SDDO12/GMAC1_RXD3_M1/UART7_TX_M2/PDM_SDI2_M1/GPIO4_A2_d
GPIO4_A2_d
CIF_D12
EBC_SDDO12
GMAC1_RXD3_M1
UART7_TX_M2
Y3
CIF_D13/EBC_SDDO13/GMAC1_RXCLK_M1/UART7_RX_M2/PDM_SDI3_M1/GPIO4_A3_d
GPIO4_A3_d
CIF_D13
EBC_SDDO13
GMAC1_RXCLK_M1
UART7_RX_M2
Y2
CIF_D14/EBC_SDDO14/GMAC1_TXD0_M1/UART9_TX_M2/I2S2_LRCK_TX_M1/GPIO4_A4_d
GPIO4_A4_d
CIF_D14
EBC_SDDO14
GMAC1_TXD0_M1
UART9_TX_M2
Y1
CIF_D15/EBC_SDDO15/GMAC1_TXD1_M1/UART9_RX_M2/I2S2_LRCK_RX_M1/GPIO4_A5_d
GPIO4_A5_d
CIF_D15
EBC_SDDO15
GMAC1_TXD1_M1
UART9_RX_M2
GPIO4_A6_d
ISP_FLASHTRIGO
UT
EBC_SDCE0
GMAC1_TXEN_M1
SPI3_CS0_M0
GPIO4_A7_d
CAM_CLKOUT0
EBC_SDCE1
GMAC1_RXD0_M1
SPI3_CS1_M0
W2
W1
V7
ISP_FLASHTRIGOUT/EBC_SDCE0/GMAC1_TXEN_M1/SPI3_CS0_M0/I2S1_SCLK_RX_M1/GPI
O4_A6_d
CAM_CLKOUT0/EBC_SDCE1/GMAC1_RXD0_M1/SPI3_CS1_M0/I2S1_LRCK_RX_M1/GPIO4_A
7_d
CAM_CLKOUT1/EBC_SDCE2/GMAC1_RXD1_M1/SPI3_MISO_M0/I2S1_SDO1_M1/GPIO4_B0_
d
GPIO4_B0_d
CAM_CLKOUT1
EBC_SDCE2
GMAC1_RXD1_M1
SPI3_MISO_M0
V2
ISP_PRELIGHT_TRIG/EBC_SDCE3/GMAC1_RXDV_CRS_M1/I2S1_SDO2_M1/GPIO4_B1_d
GPIO4_B1_d
ISP_PRELIGHT_TR
IG
EBC_SDCE3
GMAC1_RXDV_CRS_
M1
I2S1_SDO2_M1
V4
I2C4_SDA_M0/EBC_VCOM/GMAC1_RXER_M1/SPI3_MOSI_M0/I2S2_SDI_M1/GPIO4_B2_d
I2C4_SCL_M0/EBC_GDOE/ETH1_REFCLKO_25M_M1/SPI3_CLK_M0/I2S2_SDO_M1/GPIO4_B
3_d
I2C2_SDA_M1/EBC_GDSP/CAN2_RX_M0/ISP_FLASH_TRIGIN/VOP_BT656_CLK_M1/GPIO4_
B4_d
GPIO4_B2_d
I2C4_SDA_M0
EBC_VCOM
GPIO4_B3_d
I2C4_SCL_M0
EBC_GDOE
GPIO4_B4_d
I2C2_SDA_M1
EBC_GDSP
V1
V6
I2S2_SDI_M1
I2S2_SDO_M1
CAN2_RX_M0
ISP_FLASH_TRIGIN
VOP_BT656_CLK_
M1
I2C2_SCL_M1/EBC_SDSHR/CAN2_TX_M0/I2S1_SDO3_M1/GPIO4_B5_d
GPIO4_B5_d
I2C2_SCL_M1
EBC_SDSHR
CAN2_TX_M0
I2S1_SDO3_M1
GPIO4_B6_d
CIF_HREF
EBC_SDLE
GMAC1_MDC_M1
UART1_RTSn_M1
U4
CIF_VSYNC/EBC_SDOE/GMAC1_MDIO_M1/I2S2_SCLK_TX_M1/GPIO4_B7_d
GPIO4_B7_d
CIF_VSYNC
EBC_SDOE
GMAC1_MDIO_M1
I2S2_SCLK_TX_M1
CIF_CLKOUT/EBC_GDCLK/PWM11_IR_M1/GPIO4_C0_d
GPIO4_C0_d
CIF_CLKOUT
EBC_GDCLK
PWM11_IR_M1
GPIO4_C1_d
CIF_CLKIN
EBC_SDCLK
GMAC1_MCLKINOUT
_M1
AF8
AA11
AH7
CIF_CLKIN/EBC_SDCLK/GMAC1_MCLKINOUT_M1/UART1_CTSn_M1/I2S2_SCLK_RX_M1/GPI
O4_C1_d
PWM14_M1/SPI3_CLK_M1/CAN1_RX_M1/PCIE30X2_CLKREQn_M2/I2S3_MCLK_M1/GPIO4_C
2_d
PWM15_IR_M1/SPI3_MOSI_M1/CAN1_TX_M1/PCIE30X2_WAKEn_M2/I2S3_SCLK_M1/GPIO4
_C3_d
EDP_HPDIN_M0/SPDIF_TX_M2/SATA2_ACT_LED/PCIE30X2_PERSTn_M2/I2S3_LRCK_M1/GP
IO4_C4_d
GPIO4_C2_d
PWM14_M1
SPI3_CLK_M1
CAN1_RX_M1
GPIO4_C3_d
PWM15_IR_M1
SPI3_MOSI_M1
CAN1_TX_M1
GPIO4_C4_d
EDP_HPDIN_M0
SPDIF_TX_M2
SATA2_ACT_LED
UART1_CTSn_M1
PCIE30X2_CLKREQn
_M2
PCIE30X2_WAKEn_
M2
PCIE30X2_PERSTn_
M2
I2S2_MCLK_M1
I2S2_SCLK_RX_M
1
I2S3_MCLK_M1
I2S3_SCLK_M1
I2S3_LRCK_M1
AD8
PWM12_M1/SPI3_MISO_M1/SATA1_ACT_LED/UART9_TX_M1/I2S3_SDO_M1/GPIO4_C5_d
GPIO4_C5_d
PWM12_M1
SPI3_MISO_M1
SATA1_ACT_LED
UART9_TX_M1
I2S3_SDO_M1
AE8
PWM13_M1/SPI3_CS0_M1/SATA0_ACT_LED/UART9_RX_M1/I2S3_SDI_M1/GPIO4_C6_d
GPIO4_C6_d
PWM13_M1
SPI3_CS0_M1
SATA0_ACT_LED
UART9_RX_M1
I2S3_SDI_M1
Copyright 2022© Rockchip Electronics Co., Ltd.
VCCIO6
I2S1_SDO1_M1
SPI3_CLK_M0
CIF_HREF/EBC_SDLE/GMAC1_MDC_M1/UART1_RTSn_M1/I2S2_MCLK_M1/GPIO4_B6_d
U2
PDM_SDI3_M1
I2S2_LRCK_TX_M
1
I2S2_LRCK_RX_M
1
I2S1_SCLK_RX_M
1
I2S1_LRCK_RX_M
1
SPI3_MOSI_M0
V5
U3
PDM_SDI2_M1
GMAC1_RXER_M1
ETH1_REFCLKO_25M
_M1
U5
Die Power
Domain
VCCIO7
35
RK3568J Datasheet
PIN
Rev 1.0
PIN Name
Func1
Func2
Func3
AG8
HDMITX_SCL/I2C5_SCL_M1/GPIO4_C7_u
GPIO4_C7_u
HDMITX_SCL
I2C5_SCL_M1
AG7
HDMITX_SDA/I2C5_SDA_M1/GPIO4_D0_u
GPIO4_D0_u
HDMITX_SDA
I2C5_SDA_M1
AH6
HDMITX_CEC_M0/SPI3_CS1_M1/GPIO4_D1_u
GPIO4_D1_u
HDMITX_CEC_M0
SPI3_CS1_M1
AB9
GPIO4_D2_d
GPIO4_D2_d
AG19
HDMI_TX_CLKN
HDMI_TX_CLKN
AH19
HDMI_TX_CLKP
HDMI_TX_CLKP
AH20
HDMI_TX_D0N
HDMI_TX_D0N
AG20
HDMI_TX_D0P
HDMI_TX_D0P
AH21
HDMI_TX_D1N
HDMI_TX_D1N
AG21
HDMI_TX_D1P
HDMI_TX_D1P
AH22
HDMI_TX_D2N
HDMI_TX_D2N
AG22
HDMI_TX_D2P
HDMI_TX_D2P
AB18
HDMI_TX_HPDIN
HDMI_TX_HPDIN
AA18
HDMI_TX_REXT
AH10
MIPI_CSI_RX_CLK0N
AG10
MIPI_CSI_RX_CLK0P
MIPI_CSI_RX_CLK1N
MIPI_CSI_RX_CLK1P
AH12
MIPI_CSI_RX_D0N
MIPI_CSI_RX_D0N
AG12
MIPI_CSI_RX_D0P
MIPI_CSI_RX_D0P
AH11
MIPI_CSI_RX_D1N
MIPI_CSI_RX_D1N
AG11
MIPI_CSI_RX_D1P
MIPI_CSI_RX_D1P
AD11
MIPI_CSI_RX_D2N
MIPI_CSI_RX_D2N
AE11
MIPI_CSI_RX_D2P
MIPI_CSI_RX_D2P
AE9
MIPI_CSI_RX_D3N
MIPI_CSI_RX_D3N
MIPI_CSI_RX_D3P
MIPI_CSI_RX_D3P
MIPI_DSI_TX0_CLKN/LVDS_TX0_CLKN
AH15
MIPI_DSI_TX0_CLKP/LVDS_TX0_CLKP
AG17
MIPI_DSI_TX0_D0N/LVDS_TX0_D0N
AH17
MIPI_DSI_TX0_D0P/LVDS_TX0_D0P
AG16
MIPI_DSI_TX0_D1N/LVDS_TX0_D1N
AH16
MIPI_DSI_TX0_D1P/LVDS_TX0_D1P
AG14
MIPI_DSI_TX0_D2N/LVDS_TX0_D2N
AH14
MIPI_DSI_TX0_D2P/LVDS_TX0_D2P
AG13
MIPI_DSI_TX0_D3N/LVDS_TX0_D3N
AH13
MIPI_DSI_TX0_D3P/LVDS_TX0_D3P
AE15
MIPI_DSI_TX1_CLKN
AD15
MIPI_DSI_TX1_CLKP
AE18
MIPI_DSI_TX1_D0N
AD18
MIPI_DSI_TX1_D0P
AC17
MIPI_DSI_TX1_D1N
Copyright 2022© Rockchip Electronics Co., Ltd.
Func6
Die Power
Domain
HDMI
HDMI_TX_REXT
AH9
AD9
Func5
MIPI_CSI_RX_CLK
0N
MIPI_CSI_RX_CLK
0P
MIPI_CSI_RX_CLK
1N
MIPI_CSI_RX_CLK
1P
AG9
AG15
Func4
MIPI_DSI_TX0_CL
KN
MIPI_DSI_TX0_CL
KP
MIPI_DSI_TX0_D0
N
MIPI_DSI_TX0_D0
P
MIPI_DSI_TX0_D1
N
MIPI_DSI_TX0_D1
P
MIPI_DSI_TX0_D2
N
MIPI_DSI_TX0_D2
P
MIPI_DSI_TX0_D3
N
MIPI_DSI_TX0_D3
P
MIPI_DSI_TX1_CL
KN
MIPI_DSI_TX1_CL
KP
MIPI_DSI_TX1_D0
N
MIPI_DSI_TX1_D0
P
MIPI_DSI_TX1_D1
N
MIPI_CSI_R
X
LVDS_TX0_CLKN
LVDS_TX0_CLKP
LVDS_TX0_D0N
LVDS_TX0_D0P
LVDS_TX0_D1N
LVDS_TX0_D1P
MIPI_DSI_T
X0
LVDS_TX0_D2N
LVDS_TX0_D2P
LVDS_TX0_D3N
LVDS_TX0_D3P
MIPI_DSI_T
X1
36
RK3568J Datasheet
Rev 1.0
PIN
PIN Name
AD17
MIPI_DSI_TX1_D1P
AC14
MIPI_DSI_TX1_D2N
Func1
Func2
Func3
MIPI_DSI_TX1_D2P
AE12
MIPI_DSI_TX1_D3N
AD12
MIPI_DSI_TX1_D3P
M25
EDP_TX_AUXN
EDP_TX_AUXN
L25
EDP_TX_AUXP
EDP_TX_AUXP
K27
EDP_TX_D0N
EDP_TX_D0N
J28
EDP_TX_D0P
EDP_TX_D0P
L27
EDP_TX_D1N
EDP_TX_D1N
K28
EDP_TX_D1P
EDP_TX_D1P
M27
EDP_TX_D2N
EDP_TX_D2N
L28
EDP_TX_D2P
EDP_TX_D2P
N27
EDP_TX_D3N
EDP_TX_D3N
M28
EDP_TX_D3P
R25
MULTI_PHY0_REFCLKN
R24
MULTI_PHY0_REFCLKP
U24
MULTI_PHY1_REFCLKN
U25
MULTI_PHY1_REFCLKP
V25
PCIE20_REFCLKN
PCIE20_REFCLKN
V24
PCIE20_REFCLKP
PCIE20_REFCLKP
Y28
PCIE20_RXN/SATA2_RXN/QSGMII_RXN_M1
PCIE20_RXN
SATA2_RXN
Y27
PCIE20_RXP/SATA2_RXP/QSGMII_RXP_M1
PCIE20_RXP
SATA2_RXP
QSGMII_RXP_M1
W28
PCIE20_TXN/SATA2_TXN/QSGMII_TXN_M1
PCIE20_TXN
SATA2_TXN
QSGMII_TXN_M1
PCIE20_TXP
PCIE30_REFCLKN_I
N
PCIE30_REFCLKP_I
N
SATA2_TXP
QSGMII_TXP_M1
W27
PCIE20_TXP/SATA2_TXP/QSGMII_TXP_M1
PCIE30_REFCLKN_IN
Func6
Die Power
Domain
EDP_TX_D3P
MULTI_PHY0_REFC
LKN
MULTI_PHY0_REFC
LKP
MULTI_PHY1_REFC
LKN
MULTI_PHY1_REFC
LKP
Y25
PCIE30_REFCLKP_IN
U19
PCIE30_RESREF
PCIE30_RESREF
AC27
PCIE30_RX0N
PCIE30_RX0N
AC28
PCIE30_RX0P
PCIE30_RX0P
AD27
PCIE30_RX1N
PCIE30_RX1N
AD28
PCIE30_RX1P
PCIE30_RX1P
AA27
PCIE30_TX0N
PCIE30_TX0N
AA28
PCIE30_TX0P
PCIE30_TX0P
AB27
PCIE30_TX1N
PCIE30_TX1N
AB28
PCIE30_TX1P
PCIE30_TX1P
B27
SARADC_VIN0
SARADC_VIN0
C26
SARADC_VIN1
SARADC_VIN1
D24
SARADC_VIN2
SARADC_VIN2
E23
SARADC_VIN3
SARADC_VIN3
G21
SARADC_VIN4
SARADC_VIN4
F22
SARADC_VIN5
SARADC_VIN5
G20
SARADC_VIN6
SARADC_VIN6
F21
SARADC_VIN7
SARADC_VIN7
Copyright 2022© Rockchip Electronics Co., Ltd.
Func5
MIPI_DSI_TX1_D1
P
MIPI_DSI_TX1_D2
N
MIPI_DSI_TX1_D2
P
MIPI_DSI_TX1_D3
N
MIPI_DSI_TX1_D3
P
AD14
AA25
Func4
EDP
QSGMII_RXN_M1
MUlTI_PHY
MULTI_PHY0
PCIE30
37
RK3568J Datasheet
Rev 1.0
PIN
PIN Name
Func1
R1
USB2_HOST2_DM
USB2_HOST2_DM
R2
USB2_HOST2_DP
USB2_HOST2_DP
T1
USB2_HOST3_DM
USB2_HOST3_DM
T2
USB2_HOST3_DP
USB2_HOST3_DP
P25
USB3_HOST1_DM
USB3_HOST1_DM
USB3_HOST1_DP
USB3_HOST1_SSR
XN
USB3_HOST1_SSR
XP
USB3_HOST1_SST
XN
USB3_HOST1_SST
XP
P24
USB3_HOST1_DP
U27
USB3_HOST1_SSRXN/SATA1_RXN/QSGMII_RXN_M0
U28
USB3_HOST1_SSRXP/SATA1_RXP/QSGMII_RXP_M0
V27
USB3_HOST1_SSTXN/SATA1_TXN/QSGMII_TXN_M0
V28
USB3_HOST1_SSTXP/SATA1_TXP/QSGMII_TXP_M0
P28
USB3_OTG0_DM
USB3_OTG0_DM
P27
USB3_OTG0_DP
USB3_OTG0_DP
L23
USB3_OTG0_ID
R27
USB3_OTG0_SSRXN/SATA0_RXN
R28
USB3_OTG0_SSRXP/SATA0_RXP
T27
USB3_OTG0_SSTXN/SATA0_TXN
T28
USB3_OTG0_SSTXP/SATA0_TXP
M24
USB3_OTG0_VBUSDET
Func2
Func3
SATA1_RXN
QSGMII_RXN_M0
SATA1_RXP
QSGMII_RXP_M0
SATA1_TXN
QSGMII_TXN_M0
SATA1_TXP
QSGMII_TXP_M0
Func4
Func6
Die Power
Domain
SARADC
USB2
USB3_OTG0_ID
USB3_OTG0_SSRX
N
USB3_OTG0_SSRX
P
USB3_OTG0_SSTX
N
USB3_OTG0_SSTX
P
USB3_OTG0_VBUS
DET
SATA0_RXN
SATA0_RXP
SATA0_TXN
SATA0_TXP
USB3
H5
DDR_DM0_A/DDR4_DML_A/LPDDR4_DM0_A/DDR3_DM0/LPDDR3_DM1
DDR4_DML_A
LPDDR4_DM0_A
DDR3_DM0
LPDDR3_DM1
D14
DDR_DM0_B/DDR4_DMU_B/LPDDR4_DM0_B/DDR3_DM2/LPDDR3_DM0
DDR4_DMU_B
LPDDR4_DM0_B
DDR3_DM2
LPDDR3_DM0
J4
DDR_DM1_A/DDR4_DMU_A/LPDDR4_DM1_A/DDR3_DM1/LPDDR3_DM3
DDR4_DMU_A
LPDDR4_DM1_A
DDR3_DM1
LPDDR3_DM3
E17
DDR_DM1_B/DDR4_DML_B/LPDDR4_DM1_B/DDR3_DM3/LPDDR3_DM2
DDR4_DML_B
LPDDR4_DM1_B
DDR3_DM3
LPDDR3_DM2
F2
DDR_DQ0_A/DDR4_DQL0_A/LPDDR4_DQ0_A/DDR3_DQ0/LPDDR3_DQ15
DDR4_DQL0_A
LPDDR4_DQ0_A
DDR3_DQ0
LPDDR3_DQ15
B10
DDR_DQ0_B/DDR4_DQU7_B/LPDDR4_DQ0_B/DDR3_DQ16/LPDDR3_DQ1
DDR4_DQU7_B
LPDDR4_DQ0_B
DDR3_DQ16
LPDDR3_DQ1
E1
DDR_DQ1_A/DDR4_DQL2_A/LPDDR4_DQ1_A/DDR3_DQ1/LPDDR3_DQ14
DDR4_DQL2_A
LPDDR4_DQ1_A
DDR3_DQ1
LPDDR3_DQ14
A9
DDR_DQ1_B/DDR4_DQU5_B/LPDDR4_DQ1_B/DDR3_DQ17/LPDDR3_DQ5
DDR4_DQU5_B
LPDDR4_DQ1_B
DDR3_DQ17
LPDDR3_DQ5
L7
DDR_DQ10_A/DDR4_DQU7_A/LPDDR4_DQ10_A/DDR3_DQ10/LPDDR3_DQ28
DDR4_DQU7_A
LPDDR4_DQ10_A
DDR3_DQ10
LPDDR3_DQ28
A17
DDR_DQ10_B/DDR4_DQL4_B/LPDDR4_DQ10_B/DDR3_DQ26/LPDDR3_DQ22
DDR4_DQL4_B
LPDDR4_DQ10_B
DDR3_DQ26
LPDDR3_DQ22
L6
DDR_DQ11_A/DDR4_DQU5_A/LPDDR4_DQ11_A/DDR3_DQ11/LPDDR3_DQ29
DDR4_DQU5_A
LPDDR4_DQ11_A
DDR3_DQ11
LPDDR3_DQ29
B18
DDR_DQ11_B/DDR4_DQL6_B/LPDDR4_DQ11_B/DDR3_DQ27/LPDDR3_DQ23
DDR4_DQL6_B
LPDDR4_DQ11_B
DDR3_DQ27
LPDDR3_DQ23
K2
DDR_DQ12_A/DDR4_DQU2_A/LPDDR4_DQ12_A/DDR3_DQ12/LPDDR3_DQ26
DDR4_DQU2_A
LPDDR4_DQ12_A
DDR3_DQ12
LPDDR3_DQ26
B13
DDR_DQ12_B/DDR4_DQL7_B/LPDDR4_DQ12_B/DDR3_DQ28/LPDDR3_DQ16
DDR4_DQL7_B
LPDDR4_DQ12_B
DDR3_DQ28
LPDDR3_DQ16
J6
DDR_DQ13_A/DDR4_DQU4_A/LPDDR4_DQ13_A/DDR3_DQ13/LPDDR3_DQ31
DDR4_DQU4_A
LPDDR4_DQ13_A
DDR3_DQ13
LPDDR3_DQ31
A13
DDR_DQ13_B/DDR4_DQL5_B/LPDDR4_DQ13_B/DDR3_DQ29/LPDDR3_DQ17
DDR4_DQL5_B
LPDDR4_DQ13_B
DDR3_DQ29
LPDDR3_DQ17
J7
DDR_DQ14_A/DDR4_DQU6_A/LPDDR4_DQ14_A/DDR3_DQ14/LPDDR3_DQ30
DDR4_DQU6_A
LPDDR4_DQ14_A
DDR3_DQ14
LPDDR3_DQ30
D17
DDR_DQ14_B/DDR4_DQL1_B/LPDDR4_DQ14_B/DDR3_DQ30/LPDDR3_DQ20
DDR4_DQL1_B
LPDDR4_DQ14_B
DDR3_DQ30
LPDDR3_DQ20
L4
DDR_DQ15_A/DDR4_DQU0_A/LPDDR4_DQ15_A/DDR3_DQ15/LPDDR3_DQ27
DDR4_DQU0_A
LPDDR4_DQ15_A
DDR3_DQ15
LPDDR3_DQ27
B14
DDR_DQ15_B/DDR4_DQL3_B/LPDDR4_DQ15_B/DDR3_DQ31/LPDDR3_DQ21
DDR4_DQL3_B
LPDDR4_DQ15_B
DDR3_DQ31
LPDDR3_DQ21
E2
DDR_DQ2_A/DDR4_DQL4_A/LPDDR4_DQ2_A/DDR3_DQ2/LPDDR3_DQ10
DDR4_DQL4_A
LPDDR4_DQ2_A
DDR3_DQ2
LPDDR3_DQ10
Copyright 2022© Rockchip Electronics Co., Ltd.
Func5
38
RK3568J Datasheet
Rev 1.0
PIN
PIN Name
Func1
Func2
Func3
Func4
D12
DDR_DQ2_B/DDR4_DQU3_B/LPDDR4_DQ2_B/DDR3_DQ18/LPDDR3_DQ6
DDR4_DQU3_B
LPDDR4_DQ2_B
DDR3_DQ18
LPDDR3_DQ6
D1
DDR_DQ3_A/DDR4_DQL6_A/LPDDR4_DQ3_A/DDR3_DQ3/LPDDR3_DQ9
DDR4_DQL6_A
LPDDR4_DQ3_A
DDR3_DQ3
LPDDR3_DQ9
E12
DDR_DQ3_B/DDR4_DQU1_B/LPDDR4_DQ3_B/DDR3_DQ19/LPDDR3_DQ4
DDR4_DQU1_B
LPDDR4_DQ3_B
DDR3_DQ19
LPDDR3_DQ4
J1
DDR_DQ4_A/DDR4_DQL7_A/LPDDR4_DQ4_A/DDR3_DQ4/LPDDR3_DQ13
DDR4_DQL7_A
LPDDR4_DQ4_A
DDR3_DQ4
LPDDR3_DQ13
A12
DDR_DQ4_B/DDR4_DQU0_B/LPDDR4_DQ4_B/DDR3_DQ20/LPDDR3_DQ2
DDR4_DQU0_B
LPDDR4_DQ4_B
DDR3_DQ20
LPDDR3_DQ2
J2
DDR_DQ5_A/DDR4_DQL5_A/LPDDR4_DQ5_A/DDR3_DQ5/LPDDR3_DQ12
DDR4_DQL5_A
LPDDR4_DQ5_A
DDR3_DQ5
LPDDR3_DQ12
D15
DDR_DQ5_B/DDR4_DQU6_B/LPDDR4_DQ5_B/DDR3_DQ21/LPDDR3_DQ3
DDR4_DQU6_B
LPDDR4_DQ5_B
DDR3_DQ21
LPDDR3_DQ3
H1
DDR_DQ6_A/DDR4_DQL3_A/LPDDR4_DQ6_A/DDR3_DQ6/LPDDR3_DQ8
DDR4_DQL3_A
LPDDR4_DQ6_A
DDR3_DQ6
LPDDR3_DQ8
E15
DDR_DQ6_B/DDR4_DQU4_B/LPDDR4_DQ6_B/DDR3_DQ22/LPDDR3_DQ7
DDR4_DQU4_B
LPDDR4_DQ6_B
DDR3_DQ22
LPDDR3_DQ7
H4
DDR_DQ7_A/DDR4_DQL1_A/LPDDR4_DQ7_A/DDR3_DQ7/LPDDR3_DQ11
DDR4_DQL1_A
LPDDR4_DQ7_A
DDR3_DQ7
LPDDR3_DQ11
E14
DDR_DQ7_B/DDR4_DQU2_B/LPDDR4_DQ7_B/DDR3_DQ23/LPDDR3_DQ0
DDR4_DQU2_B
LPDDR4_DQ7_B
DDR3_DQ23
LPDDR3_DQ0
M1
DDR_DQ8_A/DDR4_DQU3_A/LPDDR4_DQ8_A/DDR3_DQ8/LPDDR3_DQ25
DDR4_DQU3_A
LPDDR4_DQ8_A
DDR3_DQ8
LPDDR3_DQ25
A16
DDR_DQ8_B/DDR4_DQL0_B/LPDDR4_DQ8_B/DDR3_DQ24/LPDDR3_DQ18
DDR4_DQL0_B
LPDDR4_DQ8_B
DDR3_DQ24
LPDDR3_DQ18
N2
DDR_DQ9_A/DDR4_DQU1_A/LPDDR4_DQ9_A/DDR3_DQ9/LPDDR3_DQ24
DDR4_DQU1_A
LPDDR4_DQ9_A
DDR3_DQ9
LPDDR3_DQ24
B17
DDR_DQ9_B/DDR4_DQL2_B/LPDDR4_DQ9_B/DDR3_DQ25/LPDDR3_DQ19
DDR4_DQL2_B
LPDDR4_DQ9_B
DDR3_DQ25
LPDDR3_DQ19
G2
DDR_DQS0N_A/DDR4_DQSL_N_A/LPDDR4_DQS0N_A/DDR3_DQS0N/LPDDR3_DQS1N
DDR4_DQSL_N_A
DDR3_DQS0N
LPDDR3_DQS1N
B11
DDR_DQS0N_B/DDR4_DQSU_N_B/LPDDR4_DQS0N_B/DDR3_DQS2N/LPDDR3_DQS0N
DDR4_DQSU_N_B
DDR3_DQS2N
LPDDR3_DQS0N
G1
DDR_DQS0P_A/DDR4_DQSL_P_A/LPDDR4_DQS0P_A/DDR3_DQS0P/LPDDR3_DQS1P
DDR4_DQSL_P_A
LPDDR4_DQS0P_A
DDR3_DQS0P
LPDDR3_DQS1P
A11
DDR_DQS0P_B/DDR4_DQSU_P_B/LPDDR4_DQS0P_B/DDR3_DQS2P/LPDDR3_DQS0P
DDR4_DQSU_P_B
DDR3_DQS2P
LPDDR3_DQS0P
L1
DDR_DQS1N_A/DDR4_DQSU_N_A/LPDDR4_DQS1N_A/DDR3_DQS1N/LPDDR3_DQS3N
DDR4_DQSU_N_A
DDR3_DQS1N
LPDDR3_DQS3N
A15
DDR_DQS1N_B/DDR4_DQSL_N_B/LPDDR4_DQS1N_B/DDR3_DQS3N/LPDDR3_DQS2N
DDR4_DQSL_N_B
LPDDR4_DQS0P_B
LPDDR4_DQS1N_
A
LPDDR4_DQS1N_
B
DDR3_DQS3N
LPDDR3_DQS2N
L2
DDR_DQS1P_A/DDR4_DQSU_P_A/LPDDR4_DQS1P_A/DDR3_DQS1P/LPDDR3_DQS3P
DDR4_DQSU_P_A
LPDDR4_DQS1P_A
DDR3_DQS1P
LPDDR3_DQS3P
B15
DDR_DQS1P_B/DDR4_DQSL_P_B/LPDDR4_DQS1P_B/DDR3_DQS3P/LPDDR3_DQS2P
DDR4_DQSL_P_B
LPDDR4_DQS1P_B
DDR3_DQS3P
LPDDR3_DQS2P
B6
DDR4_A0/LPDDR4_CLKP_B/DDR3_A9/-/AC0
DDR4_A0
LPDDR4_CLKP_B
DDR3_A9
-
F5
DDR4_A1/-/DDR3_A2/-/AC1
DDR4_A1
-
DDR3_A2
-
B1
DDR4_A2/LPDDR4_A1_A/DDR3_A4/LPDDR3_A6/AC2
DDR4_A2
LPDDR4_A1_A
DDR3_A4
LPDDR3_A6
LPDDR4_DQS0N_
A
LPDDR4_DQS0N_
B
F4
DDR4_A3/LPDDR4_CKE1_A/DDR3_A3/-/AC3
DDR4_A3
LPDDR4_CKE1_A
DDR3_A3
-
D9
DDR4_A4/LPDDR4_A3_B/DDR3_BA1/LPDDR3_A3/AC4
DDR4_A4
LPDDR4_A3_B
DDR3_BA1
LPDDR3_A3
B7
DDR4_A5/LPDDR4_A5_B/DDR3_A11/LPDDR3_A2/AC5
DDR4_A5
LPDDR4_A5_B
DDR3_A11
LPDDR3_A2
A7
DDR4_A6/LPDDR4_A1_B/DDR3_A13/LPDDR3_A1/AC6
DDR4_A6
LPDDR4_A1_B
DDR3_A13
LPDDR3_A1
A8
DDR4_A7/LPDDR4_ODT0_CA_B/DDR3_A8/-/AC7
DDR4_A7
DDR3_A8
-
C1
DDR4_A8/LPDDR4_ODT0_CA_A/DDR3_A6/LPDDR3_A9/AC8
DDR4_A8
DDR3_A6
LPDDR3_A9
A5
DDR4_A9/LPDDR4_CLKN_B/DDR3_A5/-/AC9
DDR4_A9
LPDDR4_CLKN_B
DDR3_A5
-
D6
DDR4_A10/LPDDR4_CKE0_B/DDR3_A10/-/AC10
DDR4_A10
LPDDR4_CKE0_B
DDR3_A10
-
C2
DDR4_A11/LPDDR4_A0_A/DDR3_A7/LPDDR3_A8/AC11
DDR4_A11
LPDDR4_A0_A
DDR3_A7
LPDDR3_A8
C4
DDR4_A12/LPDDR4_A3_A/DDR3_BA2/-/AC12
DDR4_A12
LPDDR4_A3_A
DDR3_BA2
-
B8
DDR4_A13/LPDDR4_A0_B/DDR3_A14/LPDDR3_A0/AC13
DDR4_A13
LPDDR4_A0_B
DDR3_A14
LPDDR3_A0
C5
DDR4_A14_WEn/LPDDR4_A4_A/DDR3_A15/LPDDR3_A5/AC14
DDR4_A14_WEn
LPDDR4_A4_A
DDR3_A15
LPDDR3_A5
E4
DDR4_A15_CASn/LPDDR4_A2_A/DDR3_A0/-/AC15
DDR4_A15_CASn
LPDDR4_A2_A
DDR3_A0
-
D5
DDR4_A16_RASn/LPDDR4_A5_A/DDR3_RASn/LPDDR3_A7/AC16
DDR4_A16_RASn
LPDDR4_A5_A
DDR3_RASn
LPDDR3_A7
-
LPDDR4_ODT0_CA
_B
LPDDR4_ODT0_CA
_A
E6
DDR4_ACTn/LPDDR4_CKE1_B/DDR3_CASn/-/AC17
DDR4_ACTn
LPDDR4_CKE1_B
DDR3_CASn
E11
DDR4_BA0/LPDDR4_A2_B/DDR3_A1/-/AC18
DDR4_BA0
LPDDR4_A2_B
DDR3_A1
-
E9
DDR4_BA1/LPDDR4_A4_B/DDR3_A12/LPDDR3_A4/AC19
DDR4_BA1
LPDDR4_A4_B
DDR3_A12
LPDDR3_A4
F8
DDR4_BG0/LPDDR4_ODT1_CA_B/DDR3_WEn/-/AC20
DDR4_BG0
DDR3_WEn
-
F7
DDR4_BG1/LPDDR4_ODT1_CA_A/DDR3_BA0/-/AC21
DDR4_BG1
B3
DDR4_CKE/LPDDR4_CKE0_A/DDR3_CKE/LPDDR3_CKE/AC22
DDR4_CKE
Copyright 2022© Rockchip Electronics Co., Ltd.
LPDDR4_ODT1_CA
_B
LPDDR4_ODT1_CA
_A
LPDDR4_CKE0_A
DDR3_BA0
-
DDR3_CKE
LPDDR3_CKE
Func5
Func6
Die Power
Domain
39
RK3568J Datasheet
Rev 1.0
PIN
PIN Name
Func1
Func2
Func3
Func4
A4
DDR4_CLKN/LPDDR4_CLKN_A/DDR3_CLKN/LPDDR3_CLKN/AC24
DDR4_CLKN
LPDDR4_CLKN_A
DDR3_CLKN
LPDDR3_CLKN
B4
DDR4_CLKP/LPDDR4_CLKP_A/DDR3_CLKP/LPDDR3_CLKP/AC23
DDR4_CLKP
LPDDR4_CLKP_A
DDR3_CLKP
LPDDR3_CLKP
A2
DDR4_CS0n/LPDDR4_CS0n_A/DDR3_ODT1/LPDDR3_ODT0/AC25
DDR4_CS0n
LPDDR4_CS0n_A
DDR3_ODT1
LPDDR3_ODT0
B2
DDR4_CS1n/LPDDR4_CS1n_A/DDR3_CS1n/LPDDR3_ODT1/AC26
DDR4_CS1n
LPDDR4_CS1n_A
DDR3_CS1n
LPDDR3_ODT1
E8
DDR4_ODT0/LPDDR4_CS1n_B/DDR3_ODT0/LPDDR3_CS1n/AC27
DDR4_ODT0
LPDDR4_CS1n_B
DDR3_ODT0
LPDDR3_CS1n
D8
DDR4_ODT1/LPDDR4_CS0n_B/DDR3_CS0n/LPDDR3_CS0n/AC28
DDR4_ODT1
LPDDR4_CS0n_B
DDR3_CS0n
LPDDR3_CS0n
P7
DDR_ECC_DM
DDR_ECC_DM
LPDDR4_RESETn
DDR3_RESETn
P5
DDR_ECC_DQ0
DDR_ECC_DQ0
M4
DDR_ECC_DQ1
DDR_ECC_DQ1
M5
DDR_ECC_DQ2
DDR_ECC_DQ2
R5
DDR_ECC_DQ3
DDR_ECC_DQ3
M7
DDR_ECC_DQ4
DDR_ECC_DQ4
R7
DDR_ECC_DQ5
DDR_ECC_DQ5
P4
DDR_ECC_DQ6
DDR_ECC_DQ6
R4
DDR_ECC_DQ7
DDR_ECC_DQ7
P1
DDR_ECC_DQS_N
DDR_ECC_DQS_N
P2
DDR_ECC_DQS_P
DDR_ECC_DQS_P
F11
DDR4_RESETn/LPDDR4_RESETn/DDR3_RESETn/AC29
DDR4_RESETn
H7
DDR_RZQ
DDR_RZQ
P8
DDR_VREFOUT
DDR_VREFOUT
Copyright 2022© Rockchip Electronics Co., Ltd.
Func5
Func6
Die Power
Domain
40
RK3568J Datasheet
Rev 1.0
2.8 IO Pin Name Description
This sub-chapter will focus on the detailed function description of every pins based on
different interface.
Table 2-4 IO function description list
Interface
Misc
Interface
SWJ-DP
Interface
MCU_JTAG
Interface
SD/MMC
Host
Controller
Pin Name
I
Clock input of 24MHz crystal
XOUT24M
O
Clock output of 24MHz crystal
NPOR
I
Chip hardware reset
CLK32K_IN
I
32K clock input
CLK32K_OUT
O
32K clock output
Pin Name
Interface
Interface
Nand Flash
Interface
Dir.
Description
ARMJTAG_TCK
I
SWD interface clock input
ARMJTAG_TMS
I/O
SWD interface data inout
Pin Name
Dir.
Description
MCU_JTAGTCK
I
JTAG interface clock input
MCU_JTAGTRST
I
JTAG interface reset input
MCU_JTAGTMS
I
JTAG interface TMS input
MCU_JTAGTDO
O
JTAG interface TDO
MCU_JTAGTDI
I
JTAG interface TDI
Pin Name
Dir.
Description
SDMMC[i]_CLK(i=0~2)
O
SDMMC[i]_CMD(i=0~2)
I/O
sdmmc card command output and response input
I/O
sdmmc card data input and output
SDMMC[i] _D[j](i=0~2)
(j=0~3)
Pin Name
EMMC_CLKOUT
eMMC
Description
XIN24M
SDMMC[i]_DETN(i=0~2)
Interface
Dir.
I
sdmmc card clock
sdmmc card detect signal, 0 represents presence
of card
Dir.
O
Description
emmc card clock
EMMC_CMD
I/O
emmc card command output and response input
EMMC_D[i](i=0~7)
I/O
emmc card data input and output
Pin Name
Dir.
Description
FLASH_ALE
O
Flash address latch enable signal
FLASH_CLE
O
Flash command latch enable signal
FLASH_WRN
O
Flash write enable and clock signal
FLASH_RDN
O
Flash read enable and write/read signal
FLASH_D[i] (i=0~7)
I/O
Flash data inputs/outputs signal
FLASHx_DQS
I/O
Flash data strobe signal
FLASHx_RDY
I
Flash ready/busy signal
Copyright 2022© Rockchip Electronics Co., Ltd.
41
RK3568J Datasheet
Interface
Pin Name
FLASHx_CSN[i]=0~1)
Interface
FSPI
Controller
Pin Name
LCDC
Interface
BT1120
Interface
BT656
Interface
EBC
Interface
O
Description
Flash chip enable signal for chip i, i=0~7
Dir.
Description
I/O
FSPI serial clock
FSPI_CSN[i] (i=0)
I/O
FSPI chip select signal, low active
Pin Name
O
FSPI serial data inout
Dir.
Description
LCDC_DCLK
O
LCDC RGB interface display clock out
LCDC_VSYNC
O
LCDC RGB interface vertical sync pulse
LDCD_HSYNC
O
LCDC RGB interface horizontal sync pulse
LCDC_DEN
O
LCDC RGB interface data enable
LCDC_D[i] (i=0~23)
O
LCDC data output/input
Pin Name
Dir.
Description
BT1120_CLK
O
BT1120 interface display clock out
BT1120_D[i] (i=0~15)
O
BT1120 data output
Pin Name
Dir.
Description
BT656_CLK
O
BT656 interface display clock out
BT656_D[i] (i=0~7)
O
BT656 data output
Pin Name
Dir.
Description
EBC_SDCLK
O
EBC source clock
EBC_GDCLK
O
EBC gate clock
EBC_SDOE
O
EBC source data enable
EBC_SDLE
O
EBC source latch enable
EBC_SDSHR
O
EBC source scan Dir.
EBC_GDSP
O
EBC gate start pulse
EBC_GDOE
O
EBC gate output enable
EBC_VCOM
O
EBC VCOM enable
EBC_SDCE i(i=0~3)
O
EBC Source chip slelect
EBC_SDDO i(i=0~15)
O
EBC source data output
Pin Name
I2S1_MCLK
I2S1/PCM
Dir.
FSPI_CLK
FSPI_SIO[i] (i=0,3)
Interface
Rev 1.0
Dir.
O
Description
I2S/PCM clock source
I2S1_SCLKTX
I/O
I2S/PCM serial clock for transmit data
I2S1_SCLKRX
I/O
I2S/PCM serial clock for receive data
I2S1_LRCKRX
I/O
I2S1_LRCKTX
I/O
Controller
Copyright 2022© Rockchip Electronics Co., Ltd.
I2S/PCM left & right channel signal for receiving
serial data, synchronous left & right channel in
I2S mode and the beginning of a group of left &
right channels in PCM mode
I2S/PCM left & right channel signal for
transmitting serial data, synchronous left & right
42
RK3568J Datasheet
Interface
Rev 1.0
Pin Name
Dir.
Description
channel in I2S mode and the beginning of a
group of left & right channels in PCM mode
Interface
I2S1_SDI[i](i=1~3)
I
I2S/PCM serial data input
I2S1_SDO[i](i=1~3)
O
I2S/PCM serial data output
Pin Name
Dir.
I2S2_MCLK
I2S2/PCM
O
I/O
I2S/PCM serial clock for receive data
I2S2_SCLKTX
I/O
I2S/PCM serial clock for transmit data
I/O
I2S/PCM left & right channel signal for receiving
serial data, synchronous left & right channel in
I2S mode and the beginning of a group of left &
right channels in PCM mode
I/O
I2S/PCM left & right channel signal for
transmitting serial data, synchronous left & right
channel in I2S mode and the beginning of a
group of left & right channels in PCM mode
I2S2_LRCKRX
I2S2_LRCKTX
I2S3/PCM
I2S2_SDI
I
I2S/PCM serial data input
I2S2_SDO
O
I2S/PCM serial data output
Pin Name
Dir.
SPDIF
Interface
Description
I2S3_MCLK
O
I2S3_SCLK
I/O
I2S/PCM serial clock
I2S3_LRCK
I/O
I2S/PCM left & right channel clock, synchronous
left & right channel in I2S mode and the
beginning of a group of left & right channels in
PCM mode
Controller
Interface
I2S/PCM clock source
I2S2_SCLKRX
Controller
Interface
Description
I2S/PCM clock source
I2S3_SDI
I
I2S/PCM serial data input
I2S3_SDO
O
I2S/PCM serial data output
Pin Name
Dir.
SPDIF_TX
O
Pin Name
Description
S/PDIF data output
Dir.
Description
PDM_CLK
O
PDM sampling clock
PDM_SDI[i](i=0~3)
I
PDM data
PDM
Interface
Pin Name
Dir.
Description
CAN_RXD
I
CAN receive data
CAN_TXD
O
CAN transmit data
Pin Name
Dir.
Description
AUDPWM_L
O
Audio PWM left channel data
AUDPWM_R
O
Audio PWM right channel data
Interface
Pin Name
Dir.
Description
Digital
ACODEC_DAC_CLK
O
CODEC DAC clock output signal
Audio
ACODEC_ADC_CLK
O
CODEC ADC clock output signal
CODEC
ACODEC_DAC_SYNC
O
CODEC DAC synchronous signal
CAN
Interface
Audio PWM
Copyright 2022© Rockchip Electronics Co., Ltd.
43
RK3568J Datasheet
Interface
Rev 1.0
Pin Name
Dir.
Description
ACODEC_ADC_SYNC
O
CODEC ADC synchronous signal
ACODEC_DAC_DATAR
O
CODEC DAC right channel data
ACODEC_DAC_DATAL
O
CODEC DAC left channel data
ACODEC_ADC_DATA
I
CODEC ADC data
Interface
Pin Name
Dir.
Description
SCR_CLK
O
Smart Card clock
SCR_RST
O
Smart Card reset
SCR_DET
I
Smart Card detect
Smart Card
SCR_IO
Interface
I/O
Pin Name
Smart Card data
Dir.
Description
SPI0_CLK
I/O
SPI serial clock
SPI0_CSN[i](i=0)
I/O
SPI chip select signal, low active
SPI0_MOSI
I/O
SPI serial data
SPI0_MISO
I/O
SPI serial data
SPI0
Interface
SPI1
Pin Name
Description
SPI1_CLK
I/O
SPI serial clock
SPI1_CSN[i](i=0,1)
I/O
SPI chip select signal, low active
SPI1_MOSI
I/O
SPI serial data
SPI1_MISO
I/O
SPI serial data
Interface
SPI2
Dir.
Pin Name
Dir.
Description
SPI2_CLK
I/O
SPI serial clock
SPI2_CSN[i](i=0,1)
I/O
SPI chip select signal, low active
SPI2_MOSI
I/O
SPI serial data
SPI2_MISO
I/O
SPI serial data
Interface
Pin Name
Dir.
Description
SPI3_CLK
I/O
SPI serial clock
SPI3_CSN[i](i=0,1)
I/O
SPI chip select signal, low active
SPI3_MOSI
I/O
SPI serial data
SPI3_MISO
I/O
SPI serial data
SPI3
Interface
PWM
Pin Name
Dir.
Description
PWM0
I/O
Pulse Width Modulation input and output
PWM1
I/O
Pulse Width Modulation input and output
PWM2
I/O
Pulse Width Modulation input and output
Copyright 2022© Rockchip Electronics Co., Ltd.
44
RK3568J Datasheet
Interface
Pin Name
PWM3_IR
I/O
Pulse Width Modulation input and output, used for
IR application recommended
Pulse Width Modulation input and output
PWM5
I/O
Pulse Width Modulation input and output
PWM6
I/O
Pulse Width Modulation input and output
I/O
Pulse Width Modulation input and output, used for
IR application recommended
PWM8
I/O
Pulse Width Modulation input and output
PWM9
I/O
Pulse Width Modulation input and output
PWM10
I/O
Pulse Width Modulation input and output
I/O
Pulse Width Modulation input and output, used for
IR application recommended
PWM12
I/O
Pulse Width Modulation input and output
PWM13
I/O
Pulse Width Modulation input and output
PWM14
I/O
Pulse Width Modulation input and output
I/O
Pulse Width Modulation input and output, used for
PWM15_IR
Interface
IR application recommended
Pin Name
Dir.
I2C[i]_SDA(i=0,1,2,3,4,5)
I/O
I2C data
I2C[i]_SCL(i=0,1,2,3,4,5)
I/O
I2C clock
Pin Name
Dir.
Interface
Description
Description
UART[i]_RX(i=1~9)
I
UART serial data input
UART[i]_TX(i=1~9)
O
UART serial data output
UART[i]_CTS(i=1~9)
I
UART clear to send modem status input
UART[i]_RTS(i=1~9)
O
UART modem control request to send output
Interface
Pin Name
GMAC[i]_CLK(i=0,1)
GMAC
Description
I/O
PWM11_IR
UART
Dir.
PWM4
PWM7_IR
I2C
Rev 1.0
Dir.
I/O
Description
RMII REC_CLK output or GMAC external clock
input
GMAC[i]_TXCLK(i=0,1)
O
RGMII TX clock output
GMAC[i]_RXCLK(i=0,1)
I
RGMII RX clock input
GMAC[i]_MDC(i=0,1)
O
GMAC management interface clock
GMAC[i]_MDIO(i=0,1)
I/O
GMAC management interface data
GMAC[i]_TXDi(j=0~3)
O
GMAC TX data
I
GMAC RX data
GMAC[i]_TXEN(i=0,1)
O
GMAC TX data enable
GMAC[i]_RXDV(i=0,1)
I
GMAC RX data valid signal
GMAC[i]_RXER(i=0,1)
I
GMAC RX error signal
(i=0,1)
GMAC[i]_RXD[j](j=0~3)
(i=0,1)
Copyright 2022© Rockchip Electronics Co., Ltd.
45
RK3568J Datasheet
Interface
Rev 1.0
Pin Name
Dir.
MIPI_DSI_TX0_D[i]N
O
(i=0~3)
MIPI_DSI_TX0_D[i]P
MIPI_DSI0
Interface
O
(i=0~3)
MIPI_DSI_TX0_CLKP
O
MIPI_DSI_TX0_CLKN
O
Pin Name
O
(i=0~3)
MIPI_DSI_TX1_D[i]P
Interface
O
(i=0~3)
MIPI_DSI_TX1_CLKP
O
MIPI_DSI_TX1_CLKN
O
Pin Name
LVDS_TX0_D[i]N(i=0~3)
O
LVDS_TX0_D[i]P(i=0~3)
O
LVDS_TX0_CLKP
O
LVDS_TX0_CLKN
O
Pin Name
MIPI_CSI_DN[i] (i=0~3)
I
MIPI_CSI_DP[i] (i=0~3)
I
MIPI_CSI_CLK[i]P(i=0~1)
I
MIPI_CSI_CLK[i]N(i=0~1)
I
Camera
Interface
Pin Name
MIPI DSI positive differential data line transceiver
output
MIPI DSI positive differential clock line
transceiver output
MIPI DSI negative differential clock line
transceiver output
Description
MIPI DSI negative differential data line
transceiver output
MIPI DSI positive differential data line transceiver
output
MIPI DSI positive differential clock line
transceiver output
MIPI DSI negative differential clock line
transceiver output
Description
LVDS negative differential data line transceiver
output
LVDS positive differential data line transceiver
output
LVDS positive differential clock line transceiver
output
LVDS negative differential clock line transceiver
output
Dir.
MIPI_CSI
Interface
transceiver output
Dir.
LVDS0
Interface
MIPI DSI negative differential data line
Dir.
MIPI_DSI_TX1_D[i]N
MIPI_DSI1
Description
Dir.
Description
MIPI CSI negative differential data line
transceiver output
MIPI CSI positive differential data line transceiver
output
MIPI CSI positive differential clock line transceiver
output
MIPI CSI negative differential clock line
transceiver output
Description
CIF_CLKIN
I
Camera interface input pixel clock
CAM_CLKOUT0
O
Camera interface output work clock
CAM_CLKOUT1
O
Camera interface output work clock
CIF_VSYNC
I
Camera interface vertical sync signal
CIF_HREF
I
Camera interfacehorizontal sync signal
CIF_D[i] (i=0~15)
I
Camera interface input pixel data
Copyright 2022© Rockchip Electronics Co., Ltd.
46
RK3568J Datasheet
Interface
Pin Name
PCIE20_REFCLKN
PCIE20_REFCLKP
Rev 1.0
Dir.
I/O
PCIE20_TXN
PCIE20_TXP
PCIe2
PCIE20_RXN
PCIE20_RXP
PCIE20_BUTTONRSTN
Interface
O
PCIe differential data output signals
I
PCIe differential data input signals
I
PCIe Reset request
PCIE20_CLKREQN
I
PCIe clock request from PCIe peripheral
Pin Name
PCIE30_TX[i]N (i=0~1)
PCIE30_RX[i]P (i=0~1)
Description
100MHz differential reference clock out for PCIe
peripheral
I
PCIe reference resistor connection
O
PCIe differential data output signals
I
PCIe differential data input signals
Pin Name
Dir.
PCIE30X1_BUTTONRSTN
I
Description
PCIe Reset request
PCIE30X1_WAKEN
I/O
PCIE30X1_PERSTN
I
PCIe warm reset request
PCIE30X1_CLKREQN
I
PCIe clock request from PCIe peripheral
PCIE30X2_BUTTONRSTN
I
PCIe Reset request
PCIe wake up
PCIE30X2_WAKEN
I/O
PCIE30X2_PERSTN
I
PCIe warm reset request
PCIE30X2_CLKREQN
I
PCIe clock request from PCIe peripheral
Pin Name
Dir.
PCIe
PCIe wake up
Dir.
I
for
peripheral
PCIe warm reset request
PCIE30_RX[i]N (i=0~1)
Interface
clock
I
PCIE30_TX[i]P (i=0~1)
Misc Signal
reference
PCIE20_PERSTNM0
PCIE30_RESREF
PCIe3
differential
I/O
PCIE30_REFCLKP
Interface
100MHz
PCIE20_WAKENM0
PCIE30_REFCLKN
PCIe3
Description
PCIe wake up
Description
USB_HOST2_DP
I/O
USB 2.0 Data signal DP
USB_HOST2_DM
I/O
USB 2.0 Data signal DM
USB_HOST3_DP
I/O
USB 2.0 Data signal DP
USB_HOST3_DM
I/O
USB 2.0 Data signal DM
USB 2.0
Interface
Pin Name
Dir.
USB3_OTG0_SSTXP
USB3_ OTG0_SSTXN
USB3 OTG
USB3_OTG0_SSRXP
USB3_OTG0_SSRXN
USB3_OTG0_DP
O
USB 3.0 transmission signal DP/DM,
I
USB 3.0 receive signal DP/DM
I/O
Copyright 2022© Rockchip Electronics Co., Ltd.
Description
USB 2.0 Data signal DP
47
RK3568J Datasheet
Interface
Pin Name
USB3_OTG0_DM
Rev 1.0
Dir.
I/O
USB 2.0 Data signal DM
USB3_OTG0_VBUSDET
I
Insert detect when act as USB device
USB3_OTG0_ID
I
USB Mini-Receptacle Identifier
Interface
Pin Name
Dir.
USB3_HOST1_SSTXP
USB3 Host
Description
USB3_ HOST1_SSTXN
USB3_HOST1_SSRXP
USB3_HOST1_SSRXN
Interface
Pin Name
O
USB 3.0 transmission signal DP/DM,
I
USB 3.0 receive signal DP/DM
Dir.
SATA[i]_TXN
O
SATA[i]_TXP(i=0~2)
SATA[i]_RXN
Description
Description
SATA transmission signal DP/DM
I/O
SATA receive signal DP/DM
SATA_CPDET
I
SATA cold presence detect
SATA_MPSWITCH
I
SATA mechanical presence switch
SATA_CPPOD
O
SATA presence power on device
SATA[i]_ACTLED(i=0~2
O
SATA[i]_RXP(i=0~2)
SATA
)
Interface
Pin Name
Dir.
QSGMII_TXN
QSMII/
QSGMII_TXP
SGMII
QSGMII_RXN
GSGMII_RXP
Interface
eDP
Interface
Pin Name
SATA active LED
O
I/O
Description
SGMII/QSGMII transmission signal DP/DM
SGMII/QSGMII receive signal DP/DM
Dir.
Description
EDP_TX[i]P(i=0~3)
O
eDP data lane positive output
EDP_TX[i]N(i=0~3)
O
eDP data lane negative output
EDP_AUXP
I/O
eDP CH-AUX positive differential output
EDP_AUXN
I/O
eDP CH-AUX negative differential output
Pin Name
Dir.
HDMI_TX_D[i]N(i=0~2)
O
HDMI_X_D[i]P(i=0~2)
O
HDMI_TX_CLKN
O
HDMI_TX_CLKP
O
HDMI
Copyright 2022© Rockchip Electronics Co., Ltd.
Description
HDMI negative TMDS differential line driver data
output
HDMI positive TMDS differential line driver data
output
HDMI negative TMDS differential line driver clock
output
HDMI positive TMDS differential line driver clock
output
48
RK3568J Datasheet
Interface
Pin Name
DDR3
Interface
HDMI reference resistor connection
HDMI_TX_HPDIN
I/O
HDMI hot plug detect signal
HDMITX_SDA
I/O
I2C data line for HDMI
HDMITX_SCL
I/O
I2C clock line for HDMI
HDMITX_CEC
I/O
HDMI CEC signal
Pin Name
Dir.
Description
ISP_FLASHTRIGOUT
O
Hold signal for flash light
ISP_PRELIGHTTRIG
O
Hold signal for prelight
ISP_FLASHTRIGIN
I
External flash trigger pulse
Pin Name
Dir.
Description
DDR3_CLKP
O
Active-high clock signal to the memory device.
DDR3_CLKN
O
Active-low clock signal to the memory device.
DDR3_CKE
O
DDR3_CSN[i] (i=0,1)
O
DDR3_RASn
O
DDR3_CASn
O
DDR3_WEn
O
DDR3_BA[i] (i=0,1,2)
O
Bank address signal to the memory device.
DDR3_A[i] (i=0~15)
O
Address signal to the memory device.
DDR3_DQS[i]_P
(i=0~3)
DDR3_DQS[i]_N
(i=0~3)
I/O
I/O
I/O
DDR3_DM[i] (i=0~3)
O
DDR3_ODT[i] (i=0,1)
O
DDR3_RESETn
O
Pin Name
Active-high clock enable signal to the memory
device
Active-low chip select signal to the memory device.
Active-low row address strobe to the memory
device.
Active-low column address strobe to the memory
device.
Active-low write enable strobe to the memory
device.
BiDir.al data line to the memory device.
Active-high biDir.al data strobes to the memory
device.
Active-low biDir.al data strobes to the memory
device.
Active-low data mask signal to the memory device.
On-Die Termination output signal for two chip
select.
Reset signal to the memory device
Dir.
Description
DDR4_CLKP
O
Active-high clock signal to the memory device.
DDR4_CLKN
O
Active-low clock signal to the memory device.
DDR4_CKE
O
DDR4_CS[i]n (i=0,1)
O
DDR4_BA[i] (i=0,1)
O
Bank address signal to the memory device.
DDR4_BG[i] (i=0,1)
O
Bank address signal to the memory device.
DDR4_A[i] (i=0~13)
O
Address signal to the memory device.
DDR4
Interface
Description
I/O
DDR3_DQ[i] (i=0~31)
Interface
Dir.
HDMI_TX_REXT
Interface
Interface
Rev 1.0
Copyright 2022© Rockchip Electronics Co., Ltd.
Active-high clock enable signal to the memory
device
Active-low chip select signal to the memory device.
A
49
RK3568J Datasheet
Interface
Interface
LPDDR3
Interface
Pin Name
Rev 1.0
Dir.
DDR4_A14_Wen
O
DDR4_A15_CASn
O
DDR4_A16_RASn
O
Description
Address signal to the memory device/Active-low
write enable strobe to the memory device.
Address signal to the memory device/Active-low
column address strobe to the memory device.
Address signal to the memory device/Active-low
row address strobe to the memory device.
DDR4_DQL_A[i] (i=0~7)
I/O
BiDir.al data line to the memory device.
DDR4_DQH_A[i] (i=0~7)
I/O
BiDir.al data line to the memory device.
DDR4_DQSL_P_A
I/O
DDR4_DQSL_N_A
I/O
DDR4_DQSH_P_A
I/O
DDR4_DQSH_N_A
I/O
Active-high biDir.al data strobes to the memory
device.
Active-low biDir.al data strobes to the memory
device.
Active-high biDir.al data strobes to the memory
device.
Active-low biDir.al data strobes to the memory
device.
DDR4_DML_A
O
Active-low data mask signal to the memory device.
DDR4_DMH_A
O
Active-low data mask signal to the memory device.
DDR4_DQL_B[i] (i=0~7)
I/O
BiDir.al data line to the memory device.
DDR4_DQH_B[i] (i=0~7)
I/O
BiDir.al data line to the memory device.
DDR4_DQSL_P_B
I/O
DDR4_DQSL_N_B
I/O
DDR4_DQSH_P_B
I/O
DDR4_DQSH_N_B
I/O
Active-high biDir.al data strobes to the memory
device.
Active-low biDir.al data strobes to the memory
device.
Active-high biDir.al data strobes to the memory
device.
Active-low biDir.al data strobes to the memory
device.
DDR4_DML_B
O
Active-low data mask signal to the memory device.
DDR4_DMH_B
O
Active-low data mask signal to the memory device.
DDR4_ODT[i] (i=0,1)
O
DDR4_RESETn
O
Pin Name
On-Die Termination output signal for two chip
select.
Reset signal to the memory device
Dir.
Description
LPDDR3_CLKP
O
Active-high clock signal to the memory device.
LPDDR3_CLKN
O
Active-low clock signal to the memory device.
LPDDR3_CKE
O
LPDDR3_CS[i]n (i=0,1)
O
LPDDR3_A[i] (i=0~9)
O
LPDDR3_DQ[i] (i=0~31)
I/O
Copyright 2022© Rockchip Electronics Co., Ltd.
Active-high clock enable signal to the memory
device
Active-low chip select signal to the memory device.
AThere are two chip select.
Address signal to the memory device.
BiDir.al data line to the memory device.
50
RK3568J Datasheet
Interface
Pin Name
LPDDR3_DQS[i]_P
(i=0~3)
LPDDR3_DQS[i]_N
(i=0~3)
Rev 1.0
Dir.
I/O
I/O
LPDDR3_DM[i] (i=0~3)
O
LPDDR3_ODT[i] (i=0,1)
O
Interface
Pin Name
Active-low biDir.al data strobes to the memory
device.
Active-low data mask signal to the memory device.
On-Die Termination output signal for two chip
select.
Dir.
Description
Active-high clock signal to the memory device.
LPDDR4_CLKN_A
O
Active-low clock signal to the memory device.
LPDDR4_CKE0_A
O
LPDDR4_CKE1_A
O
LPDDR4_CS[i]n_A (i=0,1)
O
LPDDR4_A[i] (i=0~15)
O
LPDDR4_DQS[i]P_A
(i=0,1)
LPDDR4_DQS[i]N_A
(i=0,1)
I/O
I/O
I/O
LPDDR4_DM[i] (i=0~3)
Interface
device.
O
(i=0~15)
/LPDDR4X
Active-high biDir.al data strobes to the memory
LPDDR4_CLKP_A
LPDDR4_DQ[i]_A
LPDDR4
Description
O
LPDDR4_ODT[i]_CA_A
O
(i=0,1)
Active-high clock enable signal to the memory
device
Active-high clock enable signal to the memory
device
Active-low chip select signal to the memory device.
AThere are two chip select.
Address signal to the memory device.
BiDir.al data line to the memory device.
Active-high biDir.al data strobes to the memory
device.
Active-low biDir.al data strobes to the memory
device.
Active-low data mask signal to the memory device.
On-Die Termination output signal for two chip
select.
LPDDR4_CLKP_B
O
Active-high clock signal to the memory device.
LPDDR4_CLKN_B
O
Active-low clock signal to the memory device.
LPDDR4_CKE0_B
O
LPDDR4_CKE1_B
O
LPDDR4_CS[i]n_B (i=0,1)
O
LPDDR4_B[i] (i=0~15)
O
LPDDR4_DQ[i]_B
(i=0~15)
LPDDR4_DQS[i]P_B
(i=0,1)
LPDDR4_DQS[i]N_B
(i=0,1)
I/O
I/O
I/O
LPDDR4_DM[i] (i=0~3)
Copyright 2022© Rockchip Electronics Co., Ltd.
O
Active-high clock enable signal to the memory
device
Active-high clock enable signal to the memory
device
Active-low chip select signal to the memory device.
AThere are two chip select.
Address signal to the memory device.
BiDir.al data line to the memory device.
Active-high biDir.al data strobes to the memory
device.
Active-low biDir.al data strobes to the memory
device.
Active-low data mask signal to the memory device.
51
RK3568J Datasheet
Interface
Pin Name
Rev 1.0
Dir.
LPDDR4_ODT[i]_CA_B
(i=0,1)
LPDDR4_RESETn
Copyright 2022© Rockchip Electronics Co., Ltd.
O
O
Description
On-Die Termination output signal for two chip
select.
Reset signal to the memory device
52
RK3568J Datasheet
Rev 1.0
Chapter 3 Electrical Specification
3.1 Absolute Ratings
The below table provides the absolute ratings.
Absolute maximum ratings specify the values beyond which the device may be damaged
permanently. Long-term exposure to absolute maximum ratings conditions may affect
device reliability.
Absolute minimum ratings specify the values beyond which the device may be damaged
permanently. Long-term exposure to absolute minimum ratings conditions may affect
device reliability.
Table 3-1 Absolute ratings
Parameters
Related Power Group
Min
Max
Unit
Supply voltage for CPU
VDD_CPU
-0.3
1.1
V
Supply voltage for GPU
VDD_GPU
-0.3
1.1
V
Supply voltage for NPU
VDD_NPU
-0.3
1.1
V
VDD_LOGIC
-0.3
1.1
V
-0.3
1.1
V
-0.3
1.98
V
-0.3
3.63
V
DDRPHY_VDDQ
-0.3
1.65
V
Tstg
-40
125
℃
Tj
NA
125
℃
Supply voltage for core logic
PMU_VDD_LOGIC_0V9
PMUPLL_AVDD_0V9
USB2_AVDD_0V9
USB3_AVDD_0V9
MULTI_PHY_AVDD_0V9
0.9V supply voltage
PCIE30_AVDD_0V9
MIPI_CSI_RX_AVDD_0V9
MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9
MIPI_DSI_TX1_AVDD_0V9
EDP/DP_TX_AVDD_0V9
HDMI_TX_AVDD_0V9
PMUPLL_AVDD_1V8
SYSPLL_AVDD_1V8
MULTI_PHY_AVDD_1V8
USB2_AVDD_1V8
USB3_AVDD_1V8
MULTI_PHY_AVDD_1V8
1.8V supply voltage
PCIE30_AVDD_1V8
MIPI_CSI_RX_AVDD_1V8
MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8
MIPI_DSI_TX1_AVDD_1V8
EDP/DP_TX_AVDD_1V8
HDMI_TX_AVDD_1V8
OTP_VCC_1V8
3.3V supply voltage
Supply voltage for DDR IO
Storage Temperature
Max Conjunction Temperature
Copyright 2022© Rockchip Electronics Co., Ltd.
USB2_AVDD_3V3
USB3_AVDD_3V3
53
RK3568J Datasheet
Rev 1.0
3.2 Recommended Operating Condition
Following table describes the recommended operating condition.
Table 3-2 Recommended operating condition
Parameters
Symbol
Min
Typ
Max
Unit
VDD_CPU normal, CPU 1.4GHz
0.8
0.9
1
V
VDD_CPU overdrive, CPU 1.8GHz
0.95
1.05
1.15
V
VDD_GPU normal, GPU 550MHz
0.8
0.9
1
V
VDD_GPU overdrive, GPU 800MHz
0.9
0.95
1.1
V
VDD_NPU normal, NPU 600MHz
0.8
0.9
0.99
V
VDD_NPU overdrive, NPU 1GHz
0.9
0.95
1.1
V
VDD_LOGIC
0.81
0.9
0.99
V
PMU_VDD_LOGIC_0V9
0.81
0.9
0.99
V
PMUIO1
2.97
3.3
3.63
V
2.97
3.3
3.63
1.62
1.8
1.98
DDRPHY_VDDQ/DDRPHY_VDDQL
1.425
1.5
1.575
V
DDRPHY_VDDQ/DDRPHY_VDDQL
1.283
1.35
1.417
V
DDRPHY_VDDQ/DDRPHY_VDDQL
0.994
1.2
1.3
V
DDRPHY_VDDQ/DDRPHY_VDDQL
0.994
1.2
1.3
V
DDRPHY_VDDQ/DDRPHY_VDDQL
1.0
1.1
1.21
V
LPDDR4X IO VDDQ Power
DDRPHY_VDDQ
1.0
1.1
1.21
V
LPDDR4X IO VDDQL Power
DDRPHY_VDDQL
0.54
0.6
0.66
V
PMU PLL Analog Power(0.9V)
PMUPLL_AVDD_0V9
0.81
0.9
0.99
V
PMU PLL Analog Power(1.8V)
PMUPLL_AVDD_1V8
1.62
1.8
1.98
V
SYSPLL_AVDD_0V9
0.81
0.9
0.99
V
SYSPLL_AVDD_1V8
1.62
1.8
1.98
V
USB 2.0 Analog Power (0.9V)
USB2_AVDD_0V9
0.81
0.9
0.99
V
USB 2.0 Analog Power (1.8V)
USB2_AVDD_1V8
1.62
1.8
1.98
V
USB 2.0 Analog Power (3.3V)
USB2_AVDD_3V3
2.97
3.3
3.63
V
USB 3.0 Analog Power (0.9V)
USB3_AVDD_0V9
0.81
0.9
0.99
V
USB 3.0 Analog Power (1.8V)
USB3_AVDD_1V8
1.62
1.8
1.98
V
USB 3.0 Analog Power (3.3V)
USB3_AVDD_3V3
2.97
3.3
3.63
V
Multi-phy Analog Power(0.9V)
MULTI_PHY_AVDD_0V9
0.81
0.9
0.99
V
Multi-phy Analog Power(1.8V)
MULTI_PHY_AVDD_1V8
1.62
1.8
1.98
V
PCIe30 Analog Power(0.9V)
PCIE30_AVDD_0V9
0.81
0.9
0.99
V
PCIe30 Analog Power(1.8V)
PCIE30_AVDD_1V8
1.62
1.8
1.98
V
Voltage for CPU
Voltage for GPU
Voltage for NPU
Voltage for core logic
Voltage for PMU
PMUIO1 GPIO Power
Digital GPIO Power
(3.3V/1.8V)
DDR3 IO VDDQ/VDDQL power
DDR3L IO VDDQ/VDDQL
Power
LPDDR3 IO VDDQ/VDDQL
Power
DDR4 IO VDDQ/VDDQL Power
LPDDR4 IO VDDQ/VDDQL
Power
System PLL Analog
Power(0.9V)
System PLL Analog
Power(1.8V)
VCCIO1,VCCIO2, VCCIO3,
VCCIO4VCCIO5, VCCIO6, VCCIO7,
PMUIO2
V
MIPI CSI Analog Power(0.9V)
MIPI_CSI_RX_AVDD_0V9
0.81
0.9
0.99
V
MIPI CSI Analog Power(1.8V)
MIPI_CSI_RX_AVDD_1V8
1.62
1.8
1.98
V
MIPI DSI Analog Power(0.9V)
MIPI_DSI_TX0/LVDS_TX0_AVDD_0V9
0.81
0.9
0.99
V
Copyright 2022© Rockchip Electronics Co., Ltd.
54
RK3568J Datasheet
Rev 1.0
Parameters
Min
Typ
Max
Unit
MIPI DSI Analog Power (1.8V)
MIPI_DSI_TX0/LVDS_TX0_AVDD_1V8
Symbol
1.62
1.8
1.98
V
MIPI DSI Analog Power(0.9V)
MIPI_DSI_TX1_AVDD_0V9
0.81
0.9
0.99
V
MIPI DSI Analog Power (1.8V)
MIPI_DSI_TX1_AVDD_1V8
1.62
1.8
1.98
V
eDP Analog Power(0.9V)
EDP/DP_TX_AVDD_0V9
0.81
0.9
0.99
V
eDP Analog Power (1.8V)
EDP/DP_TX_AVDD_1V8
1.62
1.8
1.98
V
HDMI Analog Power(0.9V)
HDMI_TX_AVDD_0V9
0.81
0.9
0.99
V
HDMI Analog Power (1.8V)
HDMI_TX_AVDD_1V8
1.62
1.8
1.98
V
SARADC Analog Power(1.8V)
SARADC_AVDD_1V8
1.62
1.8
1.98
V
OTP_VCC_1V8
1.62
1.8
1.98
V
OSC input clock frequency
NA
24
NA
MHz
Max CPU frequency normal
NA
NA
1.4
GHz
NA
1.8
GHz
NA
550
MHz
NA
800
MHz
NA
600
MHz
NA
1000
MHz
NA
85
℃
OTP Analog Power(1.8V)
mode
②
Max CPU frequency overdrive
mode
NA
③
Max GPU frequency normal
mode
NA
②
Max GPU frequency overdrive
mode
NA
③
Max NPU frequency normal
mode
NA
②
Max NPU frequency overdrive
mode
NA
③
Ambient Operating
Temperature
Notes:
①
②
③
-40
TA
Symbol name is same as the pin name in the io descriptions
For the industrial operating environment, under normal mode, the lifetime is reasonably
guaranteed.
Overdrive mode brings higher frequency, and the voltage will increase accordingly. Under the
overdrive mode for a long time, the chipset may shorten the lifetime, especially in high temperature
condition.
3.3 DC Characteristics
Table 3-3 DC Characteristics
Parameters
Input Low Voltage
Input High Voltage
Digital GPIO
@3.3V
Output Low Voltage
Output High Voltage
Pullup Resistor
Pulldown Resistor
Input Low Voltage
Input High Voltage
Digital GPIO
@1.8V
Output Low Voltage
Output High Voltage
Symbol
Vil
Vih
Vol
Voh
Rpu
Rpd
Vil
Vih
Vol
Voh
Min
Typ
Max
Unit
-0.3
NA
0.8
V
2.0
NA
VCC+0.3
V
-0.3
NA
0.4
V
2.4
NA
VCC+0.3
V
16
NA
43
Kohm
16
NA
43
Kohm
-0.3
NA
0.35*VCC
V
0.65*VCC
NA
VCC+0.3
V
-0.3
NA
0.4
V
1.4
NA
VCC+0.3
V
43
Kohm
43
Kohm
Pullup Resistor
Rpu
16
NA
Pulldown Resistor
Rpd
16
NA
Copyright 2022© Rockchip Electronics Co., Ltd.
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RK3568J Datasheet
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Parameters
Symbol
Min
Typ
Max
DDRPHY_VDD
Input High Voltage
Vih_ddr
Vref+0.1
NA
Input Low Voltage
Vil_ddr
VSSQ
NA
Vref-0.1
V
output impedence
Rtt
20
NA
60
Ohm
Input High Voltage
Vih_ddr
Vref+0.1
NA
Input Low Voltage
Vil_ddr
VSSQ
NA
Vref-0.1
V
output impedence
Rtt
20
NA
60
Ohm
Input High Voltage
Vih_ddr
Vref+0.1
NA
Input Low Voltage
Vil_ddr
VSSQ
NA
output impedence
Rtt
20
Q
DDR IO
@DDR3 mode
DDRPHY_VDD
Q
DDR IO
@DDR3L mode
DDR IO
@DDR4 mode
Unit
DDRPHY_VDD
Q
V
V
V
Vref-0.1
V
NA
60
Ohm
V
Input High Voltage
Vih_ddr
Vref+0.1
NA
DDRPHY_VDD
Q
Input Low Voltage
Vil_ddr
VSSQ
NA
Vref-0.1
V
output impedence
Rtt
20
NA
60
Ohm
DDR IO
Input High Voltage
Vih_ddr
Vref+0.1
NA
DDRPHY_VDD
Q
V
@LPDDR4 mode
Input Low Voltage
Vil_ddr
VSSQ
NA
Vref-0.1
V
output impedence
Rtt
20
NA
60
Ohm
Input High Voltage
Vih_ddr
Vref+0.1
NA
Input Low Voltage
Vil_ddr
VSSQ
NA
Vref-0.1
V
output impedence
Rtt
20
NA
60
Ohm
DDR IO @
LPDDR3 mode
DDR IO
@LPDDR4X
mode
Parameters
MIPI_LVDS
Combo IO@LVDS
mode
MIPI_LVDS
Combo IO@MIPI
mode
Symbol
Min
DDRPHY_VDD
QL
Typ
V
Max
Unit
1.475
V
Output High Voltage
Voh
Output Low Voltage
Vol
925
NA
Output differential voltage
|VOD|
250
NA
400
mV
Output offset voltage
Vos
1125
NA
1275
mV
Output impedance, single ended
Ro
40
NA
140
Ω
Ro mismatch between A & B
ΔRo
NA
NA
10
%
Change in |Vod| between 0 and 1
|ΔVod|
NA
NA
25
mV
Change in Vod between 0 and 1
ΔVos
NA
NA
25
mV
Output High Voltage
Voh
1.08
1.2
1.32
V
Output Low Voltage
Vol
-50
NA
50
mV
HS TX static Common-mode voltage
VCMTX
150
200
250
mV
|ΔVCMTX(1,0)|
NA
NA
5
mV
|VOD|
140
200
270
mV
|ΔVOD|
NA
NA
14
mV
VOHHS
NA
NA
360
mV
VCMTX mismatch when output is Differential-1
mV
or Differential-0
HS transmit differential voltage
VOD mismatch when output is Differential-1 or
Differential-0
HS output high voltage
Copyright 2022© Rockchip Electronics Co., Ltd.
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RK3568J Datasheet
Rev 1.0
Parameters
Symbol
Min
Typ
Max
Unit
Single ended output impedance
ZOS
40
50
62.5
Ω
Single ended output impedance mismatch
ΔZOS
NA
NA
10
%
3.4 Electrical Characteristics for General IO
Table 3-4 Electrical Characteristics for Digital General IO
Parameters
Symbol
Input leakage current
Ii
Tri-state output leakage current
Ioz
Test condition
Min
Typ
Max
Unit
Vin = 3.3V or 0V
NA
NA
10
uA
Vout = 3.3V or 0V
NA
NA
10
uA
NA
NA
10
uA
NA
NA
10
uA
NA
NA
10
uA
NA
NA
10
uA
Vin = 1.8V or 0V
NA
NA
10
uA
Vout = 1.8V or 0V
NA
NA
10
uA
NA
NA
10
uA
NA
NA
10
uA
NA
NA
10
uA
NA
NA
10
uA
Vin = 3.3V, pulldown
Digital
disabled
High level input current
Iih
GPIO
Vin = 3.3V, pulldown
enabled
@3.3V
Vin = 0V, pullup
Low level input current
Iil
disabled
Vin = 0V, pullup
enabled
Input leakage current
Ii
Tri-state output leakage current
Ioz
Vin = 1.8V, pulldown
Digital
High level input current
Iih
disabled
GPIO
Vin = 1.8V, pulldown
@1.8V
enabled
Vin = 0V, pullup
Low level input current
Iil
disabled
Vin = 0V, pullup
enabled
3.5 Electrical Characteristics for PLL
Table 3-5 Electrical Characteristics for Frac PLL
Parameters
Symbol
Input clock
frequency(Frac)
Frac PLL
Fin
VCO operating range
Fvco
Output clock frequency
Fout
Lock time
Tlt
Test condition
Fin = FREF
@1.8V/0.99V
Fvco = Fref * FBDIV
@3.3V/0.99V
Fout = Fvco/POSTDIV
@3.3V/0.99V
@ 3.3V/0.99V,
FREF=24M,REFDIV=1
Min
Typ
Max
Unit
1
NA
1200
MHz
950
NA
3800
MHz
19
NA
3800
MHz
NA
250
500
Input
clock
cycles
Table 3-6 Electrical Characteristics for Int-PLL
Copyright 2022© Rockchip Electronics Co., Ltd.
57
RK3568J Datasheet
Rev 1.0
Parameters
Symbol
Input clock
Int PLL
Fin = FREF
Fin
frequency(Frac)
VCO operating range
Fvco
Output clock frequency
Fout
Lock time
Test condition
@1.8V/0.99V
Fvco = Fref * FBDIV
@3.3V/0.99V
Fout = Fvco/POSTDIV
@3.3V/0.99V
@ 3.3V/0.99V,
Tlt
FREF=24M,REFDIV=1
Min
Typ
Max
Unit
10
NA
800
MHz
475
NA
1900
MHz
9
NA
1900
MHz
Input
NA
1000
1500
clock
cycles
Notes:
①
REFDIV is the input divider value;
②
FBDIV is the feedback divider value;
③ POSTDIV is the output divider value
3.6 Electrical Characteristics for USB 2.0 Interface
Table 3-7 Electrical Characteristics for USB 2.0 Interface
Parameters
Symbol
Test condition
Min
Typ
Max
Unit
40.5
45
49.5
ohm
40.5
45
49.5
ohm
NA
NA
3
pF
1.45
1.65
1.85
V
0.175
0.2
0.225
V
Classic (LS/FS); Io=0mA
2.97
3.3
3.63
V
Classic (LS/FS); Io=6mA
2.2
NA
NA
V
HS mode; Io=0mA
360
400
440
mV
Classic (LS/FS); Io=0mA
-0.33
0
0.33
V
Classic (LS/FS); Io=6mA
NA
0.3
0.8
V
HS mode; Io=0mA
-40
0
40
mV
Classic mode
NA
+-250
NA
mV
HS mode
NA
+-25
NA
mV
Classic mode
0.8
1.65
2.5
V
0.1
0.2
0.3
V
0.5
0.6
0.7
V
NA
NA
3
pF
Squelch threshold
100
112
150
mV
Disconnect threshold
570
590
625
mV
Transmitter
Classic mode (Vout = 0 or
Output resistance
ROUT
3.3V)
HS mode (Vout = 0 to 800mV)
Output Capacitance
COUT
Output Common Mode Voltage
VM
Differential output signal high
Differential output signal low
VOH
VOL
seen from D+ or DClassic (LS/FS) mode
HS mode
Receiver
Receiver sensitivity
RSENS
HS mode (differential and
Receiver common mode
RCM
squelch comparator)
HS mode (disconnect
comparator)
Input capacitance (seen at D+ or
D-)
High input level
VIH
0.6
NA
NA
V
Low input level
VIL
NA
NA
0.2
V
Copyright 2022© Rockchip Electronics Co., Ltd.
58
RK3568J Datasheet
Rev 1.0
3.7 Electrical Characteristics for DDR IO
Table 3-8 Electrical Characteristics for DDR IO
Parameters
Symbol
Test condition
Min
Typ
Max
6
Unit
DDR IO @DDR3 mode
Input leakage current
@ 1.5V , 125℃
-80
NA
DDR IO @DDR3L mode
Input leakage current
@ 1.35V , 125℃
-65
NA
5
uA
DDR IO @DDR4 mode
Input leakage current
@ 1.2V , 125℃
-50
NA
4
uA
DDR IO @LPDDR3 mode
Input leakage current
@ 1.2V , 125℃
-50
NA
4
uA
DDR IO @LPDDR4 mode
Input leakage current
@ 1.1V , 125℃
-45
NA
3.5
uA
DDR IO @LPDDR4X mode
Input leakage current
@ 0.6V , 125℃
-20
NA
1.5
uA
Copyright 2022© Rockchip Electronics Co., Ltd.
uA
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RK3568J Datasheet
Rev 1.0
3.8 Electrical Characteristics for TSADC
Table 3-9 Electrical Characteristics for TSADC
Parameters
Symbol
Test condition
Min
Typ
Max
Unit
Temperature Resolution
NA
±5
NA
℃
Temperature Range
-20
NA
120
℃
3.9 Electrical Characteristics for MIPI DSI
Table 3-10 Electrical Characteristics for MIPI DSI
Parameters
Common-mode
450 MHz
Symbol
variations
above
Test condition
Min
Typ
Max
Units
ΔVcmtx(HF)
NA
NA
15
mVrms
Common-mode variations between
50MHz – 450MHz
ΔVcmtx(LF)
NA
NA
25
mVpeak
20%-80% rise time and fall time
Tr and Tf
NA
NA
0.3
UI
10
NA
NA
ps
Min
Typ
Max
Units
3.10 Electrical Characteristics for MIPI CSI
Table 3-11 Electrical Characteristics for MIPI CSI
Parameters
Symbol
Test condition
Common-mode interference beyond
450 MHz
ΔVcmrx(HF)
NA
NA
100
mV
Common-mode interference 50MHz450MHz
ΔVcmrx(LF)
NA
NA
50
mV
Common-mode termination
Ccm
NA
NA
60
pF
Input pulse rejection
Espike
NA
NA
300
V.ps
Minimum pulse width response
Tmin-rx
20
NA
NA
ns
Peak interference amplitude
Vint
NA
NA
200
mV
Interference frequency
Fint
450
NA
NA
MHz
3.11 Electrical Characteristics for HDMI
Table 3-12 Electrical Characteristics for HDMI
Parameters
Symbol
tR
Differential output signal rise time
tR_DATA
tR_CLOCK
tF
Differential output signal fall time
tF_DATA
tF_CLOCK
Copyright 2022© Rockchip Electronics Co., Ltd.
Test condition
20~80%
RL=50Ω
20~80%
RL=50Ω
20~80%
RL=50Ω
20~80%
RL=50Ω
20~80%
RL=50Ω
20~80%
RL=50Ω
Min
Typ
Max
Unit
75
NA
NA
ps
42.5
NA
NA
ps
75
NA
NA
ps
75
NA
NA
ps
42.5
NA
NA
ps
75
NA
NA
ps
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RK3568J Datasheet
Rev 1.0
3.12 Electrical Characteristics for multi-PHY
Table 3-13 Electrical Characteristics for PCIe PHY
Parameters
Symbol
Condition
Min
Typ
Max
Unit
VTX-DIFF-PP
0.8
NA
1.2
V
VTX-DIFF-PP-LOW
0.4
NA
1.2
V
RTX-DIFF-DC
80
NA
120
ohm
RTX-DC-OFFSET
NA
NA
5
%
VTX-RCV-DETECT
NA
NA
600
mV
Tr
25
NA
NA
ps
Tf
25
NA
NA
ps
CTX
75
NA
200
nF
AC Coupling Capacitor(SATA3.0)
CTX
6
NA
12
nF
Unit Interval
UI
399.88
NA
400.12
ps
Vrxdpp-c
250
NA
1200
mV
Rrxd-c
80
NA
120
ohm
Trxd-c-ms
NA
NA
5
%
Transmitter
Differential p-pTx voltage swing
Low power differential p-p Tx
voltage swing
Tx de-emphasis level ratio
Single Ended Output Resistance
Matching
The amount of voltage change
allowed during Receiver
Detection
Output rising time for 20% to
80%
Output falling time for 20% to
80%
AC Coupling
Capacitor(USB3.0/PCIE2.1)
Input Voltage Swing
Input differential impedance
Single Ended input Resistance
Matching
Copyright 2022© Rockchip Electronics Co., Ltd.
61
RK3568J Datasheet
Rev 1.0
Chapter 4 Thermal Management
4.1 Overview
For reliability and operability concerns, the absolute maximum junction temperature has to
be below 125℃.
4.2 Package Thermal Characteristics
Table 4-1 provides the thermal resistance characteristics for the package used on the SoC.
The resulting simulation data for reference only, please prevail in kind test.
Table 4-1 Thermal Resistance Characteristics
Parameter
Symbol
Typical
Unit
Junction-to-ambient thermal resistance
𝜽𝑱𝑨
15.5
(℃/𝑾)
Junction-to-board thermal resistance
𝜽𝑱𝑩
11.3
(℃/𝑾)
Junction-to-case thermal resistance
𝜽𝑱𝑪
2.43
(℃/𝑾)
Note: The testing PCB is 4 layers, 114.3mmx101.6mm, 1.6mm thickness, Ambient
temperature is 25℃.
Copyright 2022© Rockchip Electronics Co., Ltd.
62
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