Motorcomm
YT8531SH / YT8531SC
Datasheet
INTEGRATED 10/100/1000 GIGABIT ETHERNET TRANSCEIVER
VERSION DRAFT_04
DATE
2021-12-28
裕太微电子| Motorcomm
Motorcomm YT8531SH / YT8531SC Datasheet
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Disclaimer
This document only provides periodic information, and its contents will/may be updated from time to time
according to actual situation of Motorcomm’s products without further notice. Motorcomm will not take any
responsibility for any direct or indirect losses caused due to improper use of this document.
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Motorcomm YT8531SH / YT8531SC Datasheet
Revision History
Revision
Draft 01
Draft 02
Draft 03
Draft 04
Release Date
2021/07/12
2021/08/04
2021/08/30
2021/12/28
Summary
First version.
Add mechanical information.
Add register description.
1. Add section 8 power requirements.
2. Modify pin description of pin 45/46.
3. Add package version into ordering information.
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Motorcomm YT8531SH / YT8531SC Datasheet
Content
1. General Description ............................................................................................................................................... 1
1.1. TARGET APPLICATIONS ....................................................................................................................... 1
2. Features.................................................................................................................................................................. 2
3. Pin Assignment ...................................................................................................................................................... 4
3.1. YT8531S QFN48 6x6mm........................................................................................................................... 4
3.2. Pin Assignment ........................................................................................................................................... 5
3.3. Transceiver Interface .................................................................................................................................. 6
3.4. Clock........................................................................................................................................................... 6
3.5. RGMII ........................................................................................................................................................ 6
3.6. SerDes......................................................................................................................................................... 7
3.7. Reset ........................................................................................................................................................... 7
3.8. Mode Selection ........................................................................................................................................... 7
3.9. LED Default Settings .................................................................................................................................. 8
3.10. Regulator and Reference........................................................................................................................... 8
3.11. Power Related ........................................................................................................................................... 8
3.12. Management ............................................................................................................................................. 8
3.13. Miscellaneous Pins ................................................................................................................................... 9
4. Function Description ........................................................................................................................................... 10
4.1. Application Diagram ................................................................................................................................ 10
4.1.1. UTP (UTPRGMII / UTPSGMII) Application.................................................................... 10
4.1.2. Fiber (FIBERRGMII) Application........................................................................................... 10
4.1.3. UTP/Fiber to RGMII (UTP/FIBER Media Auto Detection RGMII) Application ......................... 10
4.1.4. SGMII to RGMII (SGMII RGMII Bridge Mode) Application ................................................ 11
4.1.5. Fiber to UTP (UTPFIBER Media Converter) Application ...................................................... 11
4.2. Transmit Functions ................................................................................................................................... 11
4.2.1. Transmit Encoder Modes ............................................................................................................... 11
4.3. Receive Functions ..................................................................................................................................... 12
4.3.1. Receive Decoder Modes ................................................................................................................ 12
4.4. Echo Canceller .......................................................................................................................................... 12
4.5. NEXT Canceller ....................................................................................................................................... 12
4.6. Baseline Wander Canceller ....................................................................................................................... 12
4.7. Digital Adaptive Equalizer ....................................................................................................................... 12
4.8. Management Interface .............................................................................................................................. 13
4.9. Auto-Negoitation ...................................................................................................................................... 13
4.10. Polarity Detection and Auto Correction ................................................................................................. 13
4.11. Loopback Mode ...................................................................................................................................... 13
4.11.1. Digital Loopback ......................................................................................................................... 13
4.11.2. External loopback ........................................................................................................................ 13
4.11.3. Remote PHY loopback ................................................................................................................ 14
4.12. Energy Efficient Ethernet (EEE) ............................................................................................................ 14
4.13. Synchronous Ethernet (Sync-E).............................................................................................................. 14
4.14. Wake-On-LAN (WOL)........................................................................................................................... 14
4.15. Link Down Power Saving (Sleep Mode) ................................................................................................ 15
4.16. Interrupt .................................................................................................................................................. 15
5. Operational Description ....................................................................................................................................... 16
5.1. Reset ......................................................................................................................................................... 16
5.2. PHY Address ............................................................................................................................................ 16
5.3. RGMII Interface ....................................................................................................................................... 16
5.4. LED .......................................................................................................................................................... 17
5.5. INT_N/PME_N Pin Usage ....................................................................................................................... 17
5.6. Power Supplies ......................................................................................................................................... 17
5.6.1. Internal Switch Regulator .............................................................................................................. 17
5.6.2. Internal LDO .................................................................................................................................. 17
6. Register Overview ............................................................................................................................................... 18
6.1. Common Register ..................................................................................................................................... 18
6.1.1. SMI_SDS_PHY (EXT_0xA000) ................................................................................................... 18
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Motorcomm YT8531SH / YT8531SC Datasheet
6.1.2. Chip_Config (EXT_0xA001) ........................................................................................................ 18
6.1.3. SDS_Config (EXT_0xA002) ......................................................................................................... 19
6.1.4. RGMII_Config1 (EXT_0xA003) .................................................................................................. 19
6.1.5. RGMII_Config2 (EXT_0xA004) .................................................................................................. 20
6.1.6. MDIO_Cfg_And_RGMII_OOB_Mon (EXT_0xA005) ................................................................ 20
6.1.7. Misc_Config (EXT_0xA006) ........................................................................................................ 21
6.1.8. MAC_Address_Cfg1 (EXT_0xA007) ........................................................................................... 21
6.1.9. MAC_Address_Cfg2 (EXT_0xA008) ........................................................................................... 21
6.1.10. MAC_Address_Cfg3 (EXT_0xA009) ......................................................................................... 21
6.1.11. WOL_Cfg (EXT_0xA00A) ......................................................................................................... 22
6.1.12. LED_GENERAL_CFG (EXT_0xA00B) .................................................................................... 22
6.1.13. LED0_CFG (EXT_0xA00C) ....................................................................................................... 23
6.1.14. LED1_CFG (EXT_0xA00D) ....................................................................................................... 24
6.1.15. LED2_CFG (EXT_0xA00E) ....................................................................................................... 24
6.1.16. LED_BLINK_CFG (EXT_0xA00F) ........................................................................................... 25
6.1.17. Pad Drive Strength Cfg (EXT_0xA010)...................................................................................... 25
6.1.18. SyncE_CFG (EXT_0xA012) ....................................................................................................... 26
6.2. UTP MII Register ..................................................................................................................................... 26
6.2.1. Basic Control Register (0x00) ....................................................................................................... 26
6.2.2. Basic Status Register (0x01) .......................................................................................................... 27
6.2.3. PHY Identification Register1 (0x02) ............................................................................................. 28
6.2.4. PHY Identification Register2 (0x03) ............................................................................................. 28
6.2.5. Auto-Negotiation Advertisement (0x04) ....................................................................................... 29
6.2.6. Auto-Negotiation Link Partner Ability (0x05) .............................................................................. 31
6.2.7. Auto-Negotiation Expansion Register (0x06)................................................................................ 32
6.2.8. Auto-Negotiation NEXT Page Register (0x07) ............................................................................. 32
6.2.9. Auto-Negotiation Link Partner Received NEXT Page Register (0x08) ........................................ 32
6.2.10. MASTER-SLAVE control register (0x09) .................................................................................. 33
6.2.11. MASTER-SLAVE Status Register (0x0A).................................................................................. 34
6.2.12. MMD Access Control Register (0x0D) ....................................................................................... 35
6.2.13. MMD Access Data Register (0x0E) ............................................................................................ 35
6.2.14. Extended status register (0x0F) ................................................................................................... 35
6.2.15. PHY Specific Function Control Register (0x10) ......................................................................... 36
6.2.16. PHY Specific Status Register (0x11)........................................................................................... 36
6.2.17. Interrupt Mask Register (0x12).................................................................................................... 38
6.2.18. Interrupt Status Register (0x13) ................................................................................................... 38
6.2.19. Speed Auto Downgrade Control Register (0x14) ........................................................................ 39
6.2.20. Rx Error Counter Register (0x15)................................................................................................ 39
6.2.21. Extended Register's Address Offset Register (0x1E) .................................................................. 39
6.2.22. Extended Register's Data Register (0x1F) ................................................................................... 40
6.3. UTP MMD Register ................................................................................................................................. 40
6.3.1. PCS Control 1 Register (MMD3, 0x0) .......................................................................................... 40
6.3.2. PCS Status 1 Register (MMD3, 0x1)............................................................................................. 40
6.3.3. EEE Control and Capability Register (MMD3, 0x14) ................................................................... 40
6.3.4. EEE Wake Error Counter (MMD3, 0x16) ..................................................................................... 41
6.3.5. Local Device EEE Ability (MMD7, 0x3C) ................................................................................... 41
6.3.6. Link Partner EEE Ability (MMD7, 0x3D) .................................................................................... 41
6.4. UTP EXT Register .................................................................................................................................... 41
6.4.1. Pkgen Cfg1 (EXT_0x38) ............................................................................................................... 41
6.4.2. Pkgen Cfg2 (0x39) ......................................................................................................................... 42
6.4.3. Pkgen Cfg3 (EXT_0x3A) .............................................................................................................. 42
6.4.4. Pkgen Cfg4 (0x3B) ........................................................................................................................ 42
6.4.5. Pkg Cfg0 (EXT_0xA0) .................................................................................................................. 42
6.4.6. Pkg Cfg1 (EXT_0xA1) .................................................................................................................. 43
6.4.7. Pkg Cfg2 (EXT_0xA2) .................................................................................................................. 43
6.4.8. Pkg Rx Valid0 (EXT_0xA3) ......................................................................................................... 43
6.4.9. Pkg Rx Valid1 (EXT_0xA4) ......................................................................................................... 43
6.4.10. Pkg Rx Os0 (EXT_0xA5) ............................................................................................................ 44
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Motorcomm YT8531SH / YT8531SC Datasheet
6.4.11. Pkg Rx Os1 (EXT_0xA6) ............................................................................................................ 44
6.4.12. Pkg Rx Us0 (EXT_0xA7) ............................................................................................................ 44
6.4.13. Pkg Rx Us1 (EXT_0xA8) ............................................................................................................ 44
6.4.14. Pkg Rx Err (EXT_0xA9) ............................................................................................................. 44
6.4.15. Pkg Rx Os Bad (EXT_0xAA)...................................................................................................... 44
6.4.16. Pkg Rx Fragment (EXT_0xAB) .................................................................................................. 45
6.4.17. Pkg Rx Nosfd (EXT_0xAC) ........................................................................................................ 45
6.4.18. Pkg Tx Valid0 (EXT_0xAD) ....................................................................................................... 45
6.4.19. Pkg Tx Valid1 (EXT_0xAE) ....................................................................................................... 45
6.4.20. Pkg Tx Os0 (EXT_0xAF) ............................................................................................................ 45
6.4.21. Pkg Tx Os1 (EXT_0xB0) ............................................................................................................ 45
6.4.22. Pkg Tx Us0 (EXT_0xB1) ............................................................................................................ 45
6.4.23. Pkg Tx Us1 (EXT_0xB2) ............................................................................................................ 46
6.4.24. Pkg Tx Err (EXT_0xB3).............................................................................................................. 46
6.4.25. Pkg Tx Os Bad (EXT_0xB4) ....................................................................................................... 46
6.4.26. Pkg Tx Fragment (EXT_0xB5) ................................................................................................... 46
6.4.27. Pkg Tx Nosfd (EXT_0xB6) ......................................................................................................... 46
6.5. SDS MII Register ..................................................................................................................................... 46
6.5.1. Basic Control Register (0x00) ....................................................................................................... 46
6.5.2. Basic Status Register (0x01) .......................................................................................................... 47
6.5.3. Sds Identification Register1 (0x02) ............................................................................................... 48
6.5.4. Sds Identification Register2 (0x03) ............................................................................................... 48
6.5.5. Auto-Negotiation Advertisement (0x04) ....................................................................................... 49
6.5.6. Auto-Negotiation Link Partner Ability (0x05) .............................................................................. 49
6.5.7. Auto-Negotiation Expansion Register (0x06)................................................................................ 49
6.5.8. Auto-Negotiation NEXT Page Register (0x07) ............................................................................. 49
6.5.9. Auto-Negotiation Link Partner Received NEXT Page Register (0x08) ........................................ 49
6.5.10. Extended status register (0x0F) ................................................................................................... 50
6.5.11. Sds Specific Status Register (0x11) ............................................................................................. 50
6.5.12. 100BASE-FX Cfg (0x14) ............................................................................................................ 51
6.5.13. Receive Err Counter (0x15) ......................................................................................................... 51
6.5.14. Link Fail Counter (0x16) ............................................................................................................. 51
6.5.15. Extended Register's Address Offset Register (0x1E) .................................................................. 51
6.5.16. Extended Register's Data Register (0x1F) ................................................................................... 51
6.6. SDS EXT Register .................................................................................................................................... 52
6.6.1. Pkgen Cfg1 (EXT_0x38) ............................................................................................................... 52
6.6.2. Pkgen Cfg2 (EXT_0x39) ............................................................................................................... 52
6.6.3. Pkgen Cfg3 (EXT_0x3A) .............................................................................................................. 52
6.6.4. Pkgen Cfg3 (EXT_0x3B) .............................................................................................................. 52
6.6.5. Pkg Cfg0 (EXT_0x1A0) ................................................................................................................ 53
6.6.6. Pkg Cfg1 (EXT_0x1A1) ................................................................................................................ 53
6.6.7. Pkg Cfg2 (EXT_0x1A2) ................................................................................................................ 53
6.6.8. Pkg Rx Valid0 (EXT_0x1A3) ....................................................................................................... 54
6.6.9. Pkg Rx Valid1 (EXT_0x1A4) ....................................................................................................... 54
6.6.10. Pkg Rx Os0 (EXT_0x1A5) .......................................................................................................... 54
6.6.11. Pkg Rx Os1 (EXT_0x1A6) .......................................................................................................... 54
6.6.12. Pkg Rx Us0 (EXT_0x1A7) .......................................................................................................... 54
6.6.13. Pkg Rx Us1 (EXT_0x1A8) .......................................................................................................... 54
6.6.14. Pkg Rx Err (EXT_0x1A9) ........................................................................................................... 55
6.6.15. Pkg Rx Os Bad (EXT_0x1AA).................................................................................................... 55
6.6.16. Pkg Rx Fragment (EXT_0x1AB) ................................................................................................ 55
6.6.17. Pkg Rx Nosfd (EXT_0x1AC) ...................................................................................................... 55
6.6.18. Pkg Tx Valid0 (EXT_0x1AD) ..................................................................................................... 55
6.6.19. Pkg Tx Valid1 (EXT_0x1AE) ..................................................................................................... 55
6.6.20. Pkg Tx Os0 (EXT_0x1AF) .......................................................................................................... 55
6.6.21. Pkg Tx Os1 (EXT_0x1B0) .......................................................................................................... 56
6.6.22. Pkg Tx Us0 (EXT_0x1B1) .......................................................................................................... 56
6.6.23. Pkg Tx Us1 (EXT_0x1B2) .......................................................................................................... 56
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Motorcomm YT8531SH / YT8531SC Datasheet
6.6.24. Pkg Tx Err (EXT_0x1B3)............................................................................................................ 56
6.6.25. Pkg Tx Os Bad (EXT_0x1B4) ..................................................................................................... 56
6.6.26. Pkg Tx Fragment (EXT_0x1B5) ................................................................................................. 56
6.6.27. Pkg Tx Nosfd (EXT_0x1B6) ....................................................................................................... 57
7. Timing and AC/DC Characteristics ..................................................................................................................... 58
7.1. DC Characteristics .................................................................................................................................... 58
7.2. AC Characteristics .................................................................................................................................... 58
7.2.1. SGMII Differential Transmitter Characteristics ............................................................................ 58
7.2.2. SGMII Differential Receiver Characteristics ................................................................................. 59
7.2.3. RGMII Timing w/o delay .............................................................................................................. 60
7.2.4. RGMII Timing with internal delay ................................................................................................ 61
7.2.5. SMI (MDC/MDIO) Interface Characteristics ................................................................................ 61
7.3. Crystal Requirement ................................................................................................................................. 61
7.4. Oscillator/External Clock Requirement .................................................................................................... 62
8. Power Requirements ............................................................................................................................................ 63
8.1. Absolute Maximum Ratings ..................................................................................................................... 63
8.2. Recommended Operating Conditions ....................................................................................................... 63
8.3. Power Sequence ........................................................................................................................................ 63
8.4. Power Consumption.................................................................................................................................. 64
8.4.1. UTP RGMII ............................................................................................................................ 64
8.4.2. FIBER RGMII ......................................................................................................................... 64
8.4.3. SGMII RGMII ........................................................................................................................ 64
8.4.4. UTP SGMII............................................................................................................................. 64
8.4.5. UTP FIBER .............................................................................................................................. 65
8.5. Maximum Power Consumption ................................................................................................................ 65
8.6. Power Noise .............................................................................................................................................. 65
9. Thermal Resistance.............................................................................................................................................. 66
10. Mechanical Information..................................................................................................................................... 67
11. Ordering Information ......................................................................................................................................... 68
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Motorcomm YT8531SH / YT8531SC Datasheet
List of Tables
Table 1. Pin Assignment .................................................................................................................................... 5
Table 2. Transceiver Interface ........................................................................................................................... 6
Table 3. Clock.................................................................................................................................................... 6
Table 4. RGMII ................................................................................................................................................. 6
Table 5. SerDes.................................................................................................................................................. 7
Table 6. Reset .................................................................................................................................................... 7
Table 7. Mode Selection .................................................................................................................................... 7
Table 8. LED Default Settings........................................................................................................................... 8
Table 9. Regulator and Reference...................................................................................................................... 8
Table 10. Power Related .................................................................................................................................... 8
Table 11. Management ...................................................................................................................................... 8
Table 12. Miscellaneous Pins ............................................................................................................................ 9
Table 13. Reset Timing Characteristics ........................................................................................................... 16
Table 14. CFG_LDO[1:0] Configuration ........................................................................................................ 17
Table 15. Register Access Types ..................................................................................................................... 18
Table 16. SMI_SDS_PHY (EXT_0xA000)..................................................................................................... 18
Table 17. Chip_Config (EXT_0xA001) .......................................................................................................... 18
Table 18. SDS_Config (EXT_0xA002)........................................................................................................... 19
Table 19. RGMII_Config1 (EXT_0xA003) .................................................................................................... 19
Table 20. RGMII_Config2 (EXT_0xA004) .................................................................................................... 20
Table 21. MDIO_Cfg_And_RGMII_OOB_Mon (EXT_0xA005) .................................................................. 20
Table 22. Misc_Config (EXT_0xA006) .......................................................................................................... 21
Table 23. MAC_Address_Cfg1 (EXT_0xA007) ............................................................................................. 21
Table 24. MAC_Address_Cfg2 (EXT_0xA008) ............................................................................................. 21
Table 25. MAC_Address_Cfg3 (EXT_0xA009) ............................................................................................. 21
Table 26. WOL_Cfg (EXT_0xA00A) ............................................................................................................. 22
Table 27. LED_GENERAL_CFG (EXT_0xA00B) ........................................................................................ 22
Table 28. LED0_CFG (EXT_0xA00C) ........................................................................................................... 23
Table 29. LED1_CFG (EXT_0xA00D)........................................................................................................... 24
Table 30. LED2_CFG (EXT_0xA00E) ........................................................................................................... 24
Table 31. LED_BLINK_CFG (EXT_0xA00F) ............................................................................................... 25
Table 32. Pad Drive Strength Cfg (EXT_0xA010) ......................................................................................... 25
Table 33. SyncE_CFG (EXT_0xA012) ........................................................................................................... 26
Table 34. Basic Control Register (0x00) ......................................................................................................... 26
Table 35. Basic Status Register (0x01) ............................................................................................................ 27
Table 36. PHY Identification Register1 (0x02) ............................................................................................... 28
Table 37. PHY Identification Register2 (0x03) ............................................................................................... 28
Table 38. Auto-Negotiation Advertisement (0x04) ......................................................................................... 29
Table 39. Auto-Negotiation Link Partner Ability (0x05) ................................................................................ 31
Table 40. Auto-Negotiation Expansion Register (0x06) ................................................................................. 32
Table 41. Auto-Negotiation NEXT Page Register (0x07) ............................................................................... 32
Table 42. Auto-Negotiation Link Partner Received NEXT Page Register (0x08) .......................................... 32
Table 43. MASTER-SLAVE control register (0x09) ...................................................................................... 33
Table 44. MASTER-SLAVE Status Register (0x0A) ..................................................................................... 34
Table 45. MMD Access Control Register (0x0D) ........................................................................................... 35
Table 46. MMD Access Data Register (0x0E) ................................................................................................ 35
Table 47. Extended status register (0x0F) ....................................................................................................... 35
Table 48. PHY Specific Function Control Register (0x10) ............................................................................. 36
Table 49. PHY Specific Status Register (0x11)............................................................................................... 36
Table 50. Interrupt Mask Register (0x12) ....................................................................................................... 38
Table 51. Interrupt Status Register (0x13)....................................................................................................... 38
Table 52. Speed Auto Downgrade Control Register (0x14) ............................................................................ 39
Table 53. Rx Error Counter Register (0x15) ................................................................................................... 39
Table 54. Extended Register's Address Offset Register (0x1E) ...................................................................... 39
Table 55. Extended Register's Data Register (0x1F) ....................................................................................... 40
Table 56. PCS Control 1 Register (MMD3, 0x0) ............................................................................................ 40
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Motorcomm YT8531SH / YT8531SC Datasheet
Table 57. PCS Status 1 Register (MMD3, 0x1)............................................................................................... 40
Table 58. EEE Control and Capability Register (MMD3, 0x14)..................................................................... 40
Table 59. EEE Wake Error Counter (MMD3, 0x16) ....................................................................................... 41
Table 60. Local Device EEE Ability (MMD7, 0x3C) ..................................................................................... 41
Table 61. Link Partner EEE Ability (MMD7, 0x3D) ...................................................................................... 41
Table 62. Pkgen Cfg1 (EXT_0x38) ................................................................................................................. 41
Table 63. Pkgen Cfg2 (EXT_0x39) ................................................................................................................. 42
Table 64. Pkgen Cfg3 (EXT_0x3A) ................................................................................................................ 42
Table 65. Pkgen Cfg4 (EXT_0x3B) ................................................................................................................ 42
Table 66. Pkg Cfg0 (EXT_0xA0) .................................................................................................................... 42
Table 67. Pkg Cfg1 (EXT_0xA1) .................................................................................................................... 43
Table 68. Pkg Cfg2 (EXT_0xA2) .................................................................................................................... 43
Table 69. Pkg Rx Valid0 (EXT_0xA3) ........................................................................................................... 43
Table 70. Pkg Rx Valid1 (EXT_0xA4) ........................................................................................................... 43
Table 71. Pkg Rx Os0 (EXT_0xA5)................................................................................................................ 44
Table 72. Pkg Rx Os1 (EXT_0xA6)................................................................................................................ 44
Table 73. Pkg Rx Us0 (EXT_0xA7)................................................................................................................ 44
Table 74. Pkg Rx Us1 (EXT_0xA8)................................................................................................................ 44
Table 75. Pkg Rx Err (EXT_0xA9) ................................................................................................................. 44
Table 76. Pkg Rx Os Bad (EXT_0xAA) ......................................................................................................... 44
Table 77. Pkg Rx Fragment (EXT_0xAB) ...................................................................................................... 45
Table 78. Pkg Rx Nosfd (EXT_0xAC) ............................................................................................................ 45
Table 79. Pkg Tx Valid0 (EXT_0xAD)........................................................................................................... 45
Table 80. Pkg Tx Valid1 (EXT_0xAE) ........................................................................................................... 45
Table 81. Pkg Tx Os0 (EXT_0xAF) ................................................................................................................ 45
Table 82. Pkg Tx Os1 (EXT_0xB0) ................................................................................................................ 45
Table 83. Pkg Tx Us0 (EXT_0xB1) ................................................................................................................ 45
Table 84. Pkg Tx Us1 (EXT_0xB2) ................................................................................................................ 46
Table 85. Pkg Tx Err (EXT_0xB3) ................................................................................................................. 46
Table 86. Pkg Tx Os Bad (EXT_0xB4) ........................................................................................................... 46
Table 87. Pkg Tx Fragment (EXT_0xB5) ....................................................................................................... 46
Table 88. Pkg Tx Nosfd (EXT_0xB6) ............................................................................................................. 46
Table 89. Basic Control Register (0x00) ......................................................................................................... 46
Table 90. Basic Status Register (0x01) ............................................................................................................ 47
Table 91. Sds Identification Register1 (0x02) ................................................................................................. 48
Table 92. Sds Identification Register2 (0x03) ................................................................................................. 48
Table 93. Auto-Negotiation Advertisement (0x04) ......................................................................................... 49
Table 94. Auto-Negotiation Link Partner Ability (0x05) ................................................................................ 49
Table 95. Auto-Negotiation Expansion Register (0x06) ................................................................................. 49
Table 96. Auto-Negotiation NEXT Page Register (0x07) ............................................................................... 49
Table 97. Auto-Negotiation Link Partner Received NEXT Page Register (0x08) .......................................... 49
Table 98. Extended status register (0x0F) ....................................................................................................... 50
Table 99. Sds Specific Status Register (0x11) ................................................................................................. 50
Table 100. 100BASE-FX Cfg (0x14) .............................................................................................................. 51
Table 101. Receive Err Counter (0x15) ........................................................................................................... 51
Table 102. Link Fail Counter (0x16) ............................................................................................................... 51
Table 103. Extended Register's Address Offset Register (0x1E) .................................................................... 51
Table 104. Extended Register's Data Register (0x1F) ..................................................................................... 51
Table 105. Pkgen Cfg1 (EXT_0x38) ............................................................................................................... 52
Table 106. Pkgen Cfg2 (EXT_0x39) ............................................................................................................... 52
Table 107. Pkgen Cfg3 (EXT_0x3A) .............................................................................................................. 52
Table 108. Pkgen Cfg3 (EXT_0x3B) .............................................................................................................. 52
Table 109. Pkg Cfg0 (EXT_0x1A0) ................................................................................................................ 53
Table 110. Pkg Cfg1 (EXT_0x1A1) ................................................................................................................ 53
Table 111. Pkg Cfg2 (EXT_0x1A2) ................................................................................................................ 53
Table 112. Pkg Rx Valid0 (EXT_0x1A3) ....................................................................................................... 54
Table 113. Pkg Rx Valid1 (EXT_0x1A4) ....................................................................................................... 54
Table 114. Pkg Rx Os0 (EXT_0x1A5) ............................................................................................................ 54
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Motorcomm YT8531SH / YT8531SC Datasheet
Table 115. Pkg Rx Os1 (EXT_0x1A6) ............................................................................................................ 54
Table 116. Pkg Rx Us0 (EXT_0x1A7) ............................................................................................................ 54
Table 117. Pkg Rx Us1 (EXT_0x1A8) ............................................................................................................ 54
Table 118. Pkg Rx Err (EXT_0x1A9) ............................................................................................................. 55
Table 119. Pkg Rx Os Bad (EXT_0x1AA) ..................................................................................................... 55
Table 120. Pkg Rx Fragment (EXT_0x1AB) .................................................................................................. 55
Table 121. Pkg Rx Nosfd (EXT_0x1AC) ........................................................................................................ 55
Table 122. Pkg Tx Valid0 (EXT_0x1AD)....................................................................................................... 55
Table 123. Pkg Tx Valid1 (EXT_0x1AE) ....................................................................................................... 55
Table 124. Pkg Tx Os0 (EXT_0x1AF) ............................................................................................................ 55
Table 125. Pkg Tx Os1 (EXT_0x1B0) ............................................................................................................ 56
Table 126. Pkg Tx Us0 (EXT_0x1B1) ............................................................................................................ 56
Table 127. Pkg Tx Us1 (EXT_0x1B2) ............................................................................................................ 56
Table 128. Pkg Tx Err (EXT_0x1B3) ............................................................................................................. 56
Table 129. Pkg Tx Os Bad (EXT_0x1B4) ....................................................................................................... 56
Table 130. Pkg Tx Fragment (EXT_0x1B5) ................................................................................................... 56
Table 131. Pkg Tx Nosfd (EXT_0x1B6) ......................................................................................................... 57
Table 132. DC Characteristics ......................................................................................................................... 58
Table 133. SGMII Differential Transmitter Characteristics ............................................................................ 58
Table 134. SGMII Differential Receiver Characteristics................................................................................. 59
Table 135. RGMII Timing w/o delay .............................................................................................................. 60
Table 136. RGMII Timing with internal delay ................................................................................................ 61
Table 137. SMI (MDC/MDIO) Interface Characteristics ................................................................................ 61
Table 138. Crystal Requirement ...................................................................................................................... 61
Table 139. Oscillator/External Clock Requirement ......................................................................................... 62
Table 140. Absolute Maximum Ratings .......................................................................................................... 63
Table 141. Recommended Operating Conditions ............................................................................................ 63
Table 142. Power Sequence Timing Parameters ............................................................................................. 63
Table 143. UTP RGMII Power Consumption .......................................................................................... 64
Table 144. FIBER RGMII Power Consumption ....................................................................................... 64
Table 145. SGMII RGMII Power Consumption ....................................................................................... 64
Table 146. UTP SGMII Power Consumption ........................................................................................... 64
Table 147. UTP FIBER Power Consumption ........................................................................................... 65
Table 148. Maximum Power Consumption ..................................................................................................... 65
Table 149. Thermal Resistance........................................................................................................................ 66
Table 150. Mechanical Dimensions................................................................................................................. 67
Table 151. Ordering Information ..................................................................................................................... 68
9
Motorcomm YT8531SH / YT8531SC Datasheet
List of Figures
Figure 1. Block Diagram ................................................................................................................................... 3
Figure 2. Pin Assignment Diagram.................................................................................................................... 4
Figure 3. UTP (UTPRGMII / UTPSGMII) Application ...................................................................... 10
Figure 4. Fiber (FIBERRGMII) Application ............................................................................................. 10
Figure 5. UTP/Fiber to RGMII Application .................................................................................................... 10
Figure 6. SGMII to RGMII Application .......................................................................................................... 11
Figure 7. Fiber to UTP Application ................................................................................................................. 11
Figure 8. Digital Loopback .............................................................................................................................. 13
Figure 9. External Loopback ........................................................................................................................... 14
Figure 10. Remote PHY Loopback.................................................................................................................. 14
Figure 11. Reset Timing Diagram ................................................................................................................... 16
Figure 12. Connection Diagram of RGMII...................................................................................................... 17
Figure 13. SGMII Differential Transmitter Eye Diagram ............................................................................... 59
Figure 14. SGMII Differential Receiver Eye Diagram .................................................................................... 60
Figure 15. RGMII Timing w/o delay ............................................................................................................... 60
Figure 16. RGMII Timing with internal delay................................................................................................. 61
Figure 17. SMI (MDC/MDIO) Timing............................................................................................................ 61
Figure 18. Power Sequence Diagram .............................................................................................................. 63
10
Motorcomm YT8531SH / YT8531SC Datasheet
1. General Description
The YT8531S is a highly integrated Ethernet transceiver that complies with 10BASE-Te, 100BASE-TX, and
1000BASE-T IEEE 802.3 standards. It provides all the necessary physical layer functions to transmit and receive
Ethernet packets over CAT.5E UTP cable.
The YT8531S uses state-of-the-art DSP technology and an Analog Front End (AFE) to enable high-speed data
transmission and reception over UTP cable. Functions such as Crossover Detection & Auto-Correction, polarity
correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction
are implemented in the YT8531S to provide robust transmission and reception capabilities at 10Mbps, 100Mbps,
or 1000Mbps.
Data transfer between MAC and PHY is via the Reduced Gigabit Media Independent Interface (RGMII), or Serial
Gigabit Media Independent Interface (SGMII) for 1000BASE-T, 100BASE-TX and 10BASE-Te. The YT8531S
supports various RGMII signaling voltages, including 3.3V, 2.5V, and 1.8V.
The YT8531S also supports a SerDes interface that can be configured as SGMII, 1000BASE-X or 100BASE-FX.
1.1. TARGET APPLICATIONS
DTV (Digital TV)
MAU (Media Access Unit)
CNR (Communication and Network Riser)
Game Console
Printer and Office Machine
DVD Player and Recorder
Ethernet Hub
Ethernet Switch
Base Stations and Controllers
Routers, DSLAMs, PON Equipment
Test and Measurement Systems
Industrial and Factory Automation Equipment
Multimedia synchronization and Real Time Networking
Any embedded system with an Ethernet MAC that needs a UTP physical connection.
1
Motorcomm YT8531SH / YT8531SC Datasheet
2. Features
1000BASE-T IEEE 802.3ab Compliant
100BASE-TX IEEE 802.3u Compliant
10BASE-Te IEEE 802.3 Compliant
Support 1000BASE-X / 100BASE-FX
Supports RGMII/SGMII MAC interface
Supports IEEE 802.3az-2010 (Energy Efficient Ethernet)
Supports Synchronous Ethernet (Sync-E)
Built-in Wake-on-LAN (WOL) over UTP/Fiber
Supports interrupt function over UTP/Fiber
Supports Parallel Detection
Crossover Detection & Auto-Correction
Automatic polarity correction
Baseline Wander Correction
Supports 120m for CAT.5E cable in 1000BASE-T
Selectable 3.3V/2.5V/1.8V signaling for RGMII.
Supports 25MHz external crystal or OSC
Provides 25MHz/125MHz clock source for MAC
Provides 3 network status LEDs
Supports Link Down Power Saving (Sleep Mode)
Supports SERDES (SGMII/1000BASE-X )
Supports 1000BASE-X/100FX unidirection
Supports Fiber-to-UTP Media Convertor mode or SGMII-to-RGMII Bridge mode
Supports UTP/Fiber Auto Detection
Supports 18k bytes jumbo frame for 1000BASE-T and 100BASE-TX, and 10k bytes for 10BASE-Te
Built-in Switching Regulator for core power 1.1V
Built-in LDO for RGMII IO power 2.5V/1.8V
Industrial grade manufacturing process for YT8531SH
3.3V and 1.1V power supply
48-pin QFN Green Package
2
Motorcomm YT8531SH / YT8531SC Datasheet
DAC
PCS TX
SerDes
Interface
MDIP/N[3:0]
Hybrid
Circuit
VDD33
Switching
Regulator
3.3V -> 1.1V
ADC
Feed
Forward
Equalizer
Phase
Selector
Decision
Feedback
Equalizer
PCS RX
TX_CTL
TXD[3:0]
TX_CLK
HSIP/HSIN
HSOP/HSON
RX_CTL
RXD[3:0]
RX_CLK
Timing
Recovery
Echo
Canceller
From Transmitters
Management
Interface
MDC
MDIO
INTB/
PMEB
PLL
Next
Canceller
BIAS
2.49k
resistor
From Transmitters
XTAL
Figure 1. Block Diagram
3
LED
ControlLer
LED0
LED1
LED2
Motorcomm YT8531SH / YT8531SC Datasheet
3. Pin Assignment
37
38
39
40
41
42
43
44
45
46
47
1
36
2
35
3
34
4
33
5
MOTORCOMM
32
6
31
7
30
YT8531
8
29
24
23
22
21
20
25
19
12
18
26
17
11
16
27
15
10
14
28
13
9
LED1/CFG_LDO0
LED0/PHYAD0
INT_N/PME_N
Reserved
LX
VDD33_LX
DVDD33
DVDD_RGMII
RX_CLK/PHYAD1
RX_CTL/PHYAD2
RXD0/RXDLY
RXD1/CFG_MODE0
RESET_N
MDC
MDIO
TXD3
TXD2
TXD1
TXD0
TX_CTL
TX_CLK
DVDDL
RXD3/CFG_MODE2
RXD2/CFG_MODE1
AVDD33
TRXP0
TRXN0
AVDDL
TRXP1
TRXN1
TRXP2
TRXN2
AVDDL
TRXP3
TRXN3
AVDD33
48
RBIAS
AVDDL
XTAL_O/XTAL_I*
XTAL_I/XTAL_O*
CLKOUT
Reserved
NC
HSON
HSOP
HSIN
HSIP
LED2/CFG_LDO1
3.1. YT8531S QFN48 6x6mm
*Note:
Pin 45 and 46 is related to package version. Please refer to ordering information to find more.
Figure 2. Pin Assignment Diagram
4
Motorcomm YT8531SH / YT8531SC Datasheet
3.2. Pin Assignment
Some pins have multiple functions.
Refer to the Pin Assignment figures for a graphical representation.
I: Input
O: Output
IO: Bidirectional Input and Output
LI: Latched Input During Power UP
P: Power
PU: Internal pull up
PD: Internal pull down
G: Ground
OD: Open Drain
XT: Crystal Related
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pin Name
AVDD33
TRXP0
TRXN0
AVDDL
TRXP1
TRXN1
TRXP2
TRXN2
AVDDL
TRXP3
TRXN3
AVDD33
RESET_N
MDC
MDIO
TXD3
TXD2
TXD1
TXD0
TX_CTL
TX_CLK
DVDDL
RXD3/CFG_MODE2
RXD2/CFG_MODE1
RXD1/CFG_MODE0
Table 1. Pin Assignment
Type
No.
P
26
IO
27
IO
28
P
29
IO
30
IO
31
IO
32
IO
33
P
34
IO
35
IO
36
P
37
I/PU
38
I/PD
39
IO/PU
40
I/PD
41
I/PD
42
I/PD
43
I/PD
44
I/PD
45
I/PD
46
P
47
O/LI/PD
48
O/LI/PD
49
O/LI/PD
5
Pin Name
RXD0/RXDLY
RX_CTL/PHYAD2
RX_CLK/PHYAD1
DVDD_RGMII
DVDD33
VDD33_LX
LX
Reserved
INT_N/PME_N
LED0/PHYAD0
LED1/CFG_LDO0
LED2/CFG_LDO1
HSIP
HSIN
HSOP
HSON
NC
Reserved
CLKOUT
XTAL_I/XTAL_O
XTAL_O/XTAL_I
AVDDL
RBIAS
GND
Type
O/LI/PU
O/LI/PD
O/LI/PD
P
P
P
P/O
IO/PD
O/OD
O/LI/PU
O/LI/PU
O/LI/PD
I
I
O
O
G
O
XT
XT
P
O
G
Motorcomm YT8531SH / YT8531SC Datasheet
3.3. Transceiver Interface
No.
2
3
5
6
7
8
10
11
Pin Name
TRXP0
TRXN0
TRXP1
TRXN1
TRXP2
TRXN2
TRXP3
TRXN3
Type
IO
IO
IO
IO
IO
IO
IO
IO
Table 2. Transceiver Interface
Description
Media-dependent interface 0, 100Ω transmission line
Media-dependent interface 0, 100Ω transmission line
Media-dependent interface 1, 100Ω transmission line
Media-dependent interface 1, 100Ω transmission line
Media-dependent interface 2, 100Ω transmission line
Media-dependent interface 2, 100Ω transmission line
Media-dependent interface 3, 100Ω transmission line
Media-dependent interface 3, 100Ω transmission line
3.4. Clock
No.
44
Pin Name
CLKOUT
Type
O
45
XTAL_I/
XTAL_O
XT
46
XTAL_O/
XTAL_I
XT
Table 3. Clock
Description
1. Reference Clock Generated from Internal PLL. This pin should be
kept floating if the clock is not used by the MAC.
2. UTP recovery receive clock for Sync Ethernet.
3. Fiber recovery receive clock for Sync Ethernet.
4. 25MHz reference clock.
For package version A, this pin is XTAL_I, means 25MHz Crystal Input
pin. But is XTAL_O for package version B, means 25MHz Crystal
Output pin.
If use external oscillator or clock from another device.
1. When connect an external 25MHz oscillator or clock from another
device to XTAL_O pin, XTAL_I must be shorted to GND.
2. When connect an external 25MHz oscillator or clock from another
device to XTAL_I pin, keep the XTAL_O floating.
For package version A, this pin is XTAL_O, means 25MHz Crystal
Output pin. But is XTAL_I for package version B, means 25MHz Crystal
Input pin.
If use external oscillator or clock from another device.
1. When connect an external 25MHz oscillator or clock from another
device to XTAL_O pin, XTAL_I must be shorted to GND.
2. When connect an external 25MHz oscillator or clock from another
device to XTAL_I pin, keep the XTAL_O floating.
3.5. RGMII
No.
16
17
18
19
20
21
Pin Name
TXD3
TXD2
TXD1
TXD0
TX_CTL
TX_CLK
Type
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
Table 4. RGMII
Description
Transmit Data.
Data is transmitted from MAC to PHY via TXD[3:0].
Transmit Control Signal from the MAC.
The transmit reference clock will be 125Mhz, 25MHz, or 2.5MHz
depending on speed.
6
Motorcomm YT8531SH / YT8531SC Datasheet
23
24
25
26
28
RXD3
RXD2
RXD1
RXD0
RX_CLK
O/LI/PD
O/LI/PD
O/LI/PD
O/LI/PU
O/LI/PD
27
RX_CTL
O/LI/PD
Receive Data.
Data is transmitted from PHY to MAC via RXD[3:0].
The continuous receive reference clock will be 125MHz, 25MHz, or
2.5MHz, and is derived from the received data stream.
Receive Control Signal to the MAC.
3.6. SerDes
No.
38
Pin Name
HSIP
Type
I
39
HSIN
I
40
HSOP
O
41
HSON
O
Table 5. SerDes
Description
SerDes Differential Input: 1.25GHz serial interfaces to receive data from
an External device that supports the SGMII interface.
The differential pair has an internal 100 ohm termination resistor.
SerDes Differential Output: 1.25GHz serial interfaces to transfer data
from an External device that supports the SGMII interface.
Both HSOP and HSON have an internal 50 ohm termination resistor to
AVDDL, which means the differential impedence is 100 ohm.
3.7. Reset
No.
13
Pin Name
RESET_N
Type
I/PU
Table 6. Reset
Description
Hardware reset, active low. Requires an external pull-up resistor
3.8. Mode Selection
No.
35
28
27
26
Name
PHYAD0
PHYAD1
PHYAD2
RXDLY
Type
O/LI/PU
O/LI/PD
O/LI/PD
O/LI/PU
36
CFG_LDO0
O/LI/PU
37
CFG_LDO1
O/LI/PD
25
CFG_MODE0
O/LI/PD
24
CFG_MODE1
O/LI/PD
23
CFG_MODE2
O/LI/PD
Table 7. Mode Selection
Description
PHYAD[2:0]. PHY address config
RGMII receiver clock timing control
Pull-up to add 2ns delay on RX_CLK when RX_CLK is 125MHz or,
to add 8ns delay on RX_CLK when RX_CLK is 25MHz/2.5MHz,
which shall be used to latch RXD.
CFG_LDO[1:0], Voltage selection for RGMII I/O pad
2’b00: 3.3V
2’b01: 2.5V
2’b10 or 2b'11: 1.8V
CFG_MODE[2:0]: Operation Mode Configuration.
3’b000: UTP RGMII
3’b001: FIBER RGMII
3’b010: UTP/FIBER RGMII (Media Auto Detection)
3’b011: UTP SGMII
3’b100: SGMII (PHY side) RGMII (MAC side),
3’b101: SGMII (MAC side) RGMII (PHY side)
3’b110: UTP FIBER (Media Conversion auto mode)
3’b111: UTP FIBER (Media Conversion force mode)
7
Motorcomm YT8531SH / YT8531SC Datasheet
3.9. LED Default Settings
No.
35
Pin Name
LED0
36
LED1
37
LED2
Table 8. LED Default Settings
Description
Light = Link up at 10Mbps
Blinking = Transiting or Receiving
O/LI/PU Light = Link up at 100Mbps
Blinking = Transiting or Receiving
O/LI/PD Light = Link up at 1000Mbps
Blinking = Transiting or Receiving
Type
O/LI/PU
3.10. Regulator and Reference
No.
48
Pin Name
RBIAS
Type
O
32
LX
P/O
Table 9. Regulator and Reference
Description
Bias Resistor.
An external 2.49 kΩ±1% resistor must be connected between the RBIAS
pin and GND
Switch regulator 1.1V output.
Connect to an external 2.2 uH power inductor directly
3.11. Power Related
No.
30
Pin Name
DVDD33
Type
P
31
29
VDD33_LX
DVDD_RGMII
P
P
22
1, 12
4, 9, 47
49
DVDDL
AVDD33
AVDDL
GND
P
P
P
G
Table 10. Power Related
Description
3.3V Power
Digital non-RGMII I/O power
3.3V power for switching regulator
Digital RGMII I/O, MDC/MDIO power, adjusted by CFG_LDO[1:0].
Note: When CFG_LDO[1:0] = 00, the I/O pad power is supplied from
the external 3.3V power connected to DVDD_RGMII pin. Otherwise, it is
supplied from the internal LDO.
No matter whether the I/O pad power form external or internal, a bulk
capacitor and a decoupling capacitor should be connected to this pin.
Digital power 1.1V
Analog Power 3.3V
Analog power 1.1V
Exposed PAD
3.12. Management
No.
14
15
Pin Name
MDC
MDIO
Type
I/PD
IO/PU
34
INT_N/PME_N
O/OD
Table 11. Management
Description
Management Data Clock.
Input/Output of Management Data.
Pull up 3.3V/2.5V/1.8V for 3.3V/2.5V/1.8V I/O respectively
This pin is shared by two functions, the default pin setting is INT_N.
Keep this pin floating if either of the functions is not used. The pin type
depends on function selected:
8
Motorcomm YT8531SH / YT8531SC Datasheet
1. Interrupt (should be 3.3V pulled up).
Set low if the specified events occurred; active low.
2. Power Management Event (should be 3.3V pulled up).
Set low if received a magic packet; active low.
Note 1: The behavior of INT_N is level-triggered, the behavior of
PME_N is level-triggered or pulse-triggered which is controled by
EXT 0xA00A bit[0].
Note 2: The function of INT_N/PME_N can be assigned by Ext
0xa00a bit[6].
1: Pin 34 functions as PME_N.
0: Pin 34 functions as INT_N (default).
3.13. Miscellaneous Pins
No.
33
Pin Name
Reserved
Type
IO/PD
42
43
NC
Reserved
G
Table 12. Miscellaneous Pins
Description
Reserved for internal use.
Keep floating or external pull down.
Should not external pull up.
NC, keep floating or connect to GND
Keep floating or connect to GND.
Should not connect to VDD or be pulled up.
9
Motorcomm YT8531SH / YT8531SC Datasheet
4. Function Description
4.1. Application Diagram
4.1.1. UTP (UTPRGMII / UTPSGMII) Application
Figure 3. UTP (UTPRGMII / UTPSGMII) Application
4.1.2. Fiber (FIBERRGMII) Application
Figure 4. Fiber (FIBERRGMII) Application
4.1.3. UTP/Fiber to RGMII (UTP/FIBER Media Auto Detection RGMII) Application
Figure 5. UTP/Fiber to RGMII Application
10
Motorcomm YT8531SH / YT8531SC Datasheet
4.1.4. SGMII to RGMII (SGMII RGMII Bridge Mode) Application
Figure 6. SGMII to RGMII Application
4.1.5. Fiber to UTP (UTPFIBER Media Converter) Application
Figure 7. Fiber to UTP Application
There are two modes for Fiber applications. Media Conversion auto mode and Media Conversion force mode.
In Media Conversion auto mode, SerDes can choose speed automaticly between 1000BASE-X and 100BASE-FX
based on signal received and type of fiber module. Then UTP will choose the speed witch is matched with SerDes
automaticly.
In Media Conversion force mode, UTP only has 1000BASET ability and SerDes is configured as 1000BASE-X
by default. To manually choose UTP speed, please configure UTP MII register 0x4 and 0x9. To manually choose
SerDes speed, please configure common EXT_Reg_0xA006 bit[0].
In FIBER RGMII, UTP/FIBER to RGMII and UTP FIBER (Media Conversion auto mode) mode, fiber
works in Media Conversion auto mode. In UTP FIBER (Media Conversion force mode) mode, fiber works in
Media Conversion force mode.
4.2. Transmit Functions
4.2.1. Transmit Encoder Modes
4.2.1.1. 1000BASE-T
In 1000BASE-T mode, the YT8531S scrambles transmit data bytes from the MAC interfaces to 9-bit symbols and
encodes them into 4D five-level PAM signals over the four pairs of CAT.5E UTP cable.
11
Motorcomm YT8531SH / YT8531SC Datasheet
4.2.1.2. 100BASE-TX
In 100BASE-TX mode, 4-bit data from the MII is 4B/5B serialized, scrambled, and encoded to a three-level
MLT3 sequence transmitted by the PMA.
4.2.1.3. 10BASE-Te
In 10BASE-Te mode, the YT8531S transmits and receives Manchester-encoded data.
4.3. Receive Functions
4.3.1. Receive Decoder Modes
4.3.1.1. 1000BASE-T
In 1000BASE-T mode, the PMA recovers the 4D PAM signals after accounting for the cabling conditions such as
skew among the four pairs, the pair swap order, and the polarity of the pairs. The resulting code group is decoded
into 8-bit data values. Data stream delimiters are translated appropriately and data is output to the MAC
interfaces.
4.3.1.2. 100BASE-TX
In 100BASE-TX mode, the receive data stream is recovered and descrambled to align to the symbol boundaries.
The aligned data is then parallelized and 5B/ 4B decoded to 4-bit data. This output runs to MAC interfaces after
data stream delimiters have been translated.
4.3.1.3. 10BASE-Te
In 10BASE-Te mode, the recovered 10BASE-Te signal is decoded from Manchester then aligned.
4.4. Echo Canceller
A hybrid circuit is used to transmit and receive simultaneously on each pair. A signal reflects back as an echo if
the transmitter is not perfectly matched to the line. Other connector or cable imperfections, such as patch panel
discontinuity and variations in cable impedance along the twisted pair cable, also result in drastic SNR
degradation on the receive signal. The YT8531S device implements a digital echo canceller to adjust for echo and
is adaptive to compensate for the varied channel conditions.
4.5. NEXT Canceller
The 1000BASE-T physical layer uses all four pairs of wires to transmit data. Because the four twisted pairs are
bundled together, significant high frequency crosstalk occurs between adjacent pairs in the bundle. The YT8531S
device uses three parallel NEXT cancellers on each receive channel to cancel high frequency crosstalk. The
YT8531S cancels NEXT by subtracting an estimate of these signals from the equalizer output.
4.6. Baseline Wander Canceller
Baseline wander results from Ethernet links that AC-couple to the transceivers and from AC coupling that cannot
maintain voltage levels for longer than a short time. As a result, transmitted pulses are distorted, resulting in
erroneous sampled values for affected pulses. Baseline wander is more problematic in the 1000BASE-T
environment than in 100BASE-TX due to the DC baseline shift in the transmit and receive signals. The YT8531S
device uses an advanced baseline wander cancellation circuit that continuously monitors and compensates for this
effect, minimizing the impact of DC baseline shift on the overall error rate.
4.7. Digital Adaptive Equalizer
The digital adaptive equalizer removes inter- symbol interference at the receiver. The digital adaptive equalizer
takes unequalized signals from ADC output and uses a combination of feedforward equalizer (FFE) and decision
feedback equalizer (DFE) for the best optimized signal-to-noise (SNR) ratio.
12
Motorcomm YT8531SH / YT8531SC Datasheet
4.8. Management Interface
The Status and Control registers of the device are accessible through the MDIO and MDC serial interface. The
functional and electrical properties of this management interface comply with IEEE 802.3, Section 22 and also
support MDC clock rates up to 12.5 MHz.
4.9. Auto-Negoitation
The YT8531S negotiates its operation mode using the auto negotiation mechanism according to IEEE 802.3
clause 28 over the copper media. Auto negotiation supports choosing the mode of operation automatically by
comparing its own abilities and received abilities from link partner. The advertised abilities include:
Speed: 10/100/1000Mbps
Duplex mode: full duplex and/or half duplex
Auto negotiation is initialized when the following scenarios happen:
Power-up/Hardware/Software reset
Auto negotiation restart
Transition from power down to power up
Link down
Auto negotiation is enabled for YT8531S by default, and can be disabled by software control.
4.10. Polarity Detection and Auto Correction
YT8531S can detect and correct two types of cable errors: swapping of pairs within the UTP cable (swapping
between pair 0 and pair 1, and(or) swapping between pair 2 and pair 3) and swapping of wires within a pair.
4.11. Loopback Mode
There are three loopback modes in YT8531S
4.11.1. Digital Loopback
Digital loopback provides the ability to loop transmitted data back to the receiver using digital circuitry in
YT8531S.
Figure 8. Digital Loopback
4.11.2. External loopback
External cable loopback loops Tx to Rx through a complete digital and analog path and an external cable, thus
testing all the digital data paths and all the analog circuits. Figure shows a block diagram of external cable
loopback.
13
Motorcomm YT8531SH / YT8531SC Datasheet
Figure 9. External Loopback
4.11.3. Remote PHY loopback
The Remote loopback connects the MDI receive path to the MDI transmit path, near the RGMII interface, thus the
remote link partner can detect the connectivity in the resulting loop. Figure below, shows the path of the remote
loopback.
Figure 10. Remote PHY Loopback
4.12. Energy Efficient Ethernet (EEE)
EEE is IEEE 802.3az, an extension of the IEEE 802.3 standard. EEE defines support for the PHY to operate in
Low Power Idle (LPI) mode which, when enabled, supports QUIET times during low link utilization allowing
both link partners to disable portions of each PHY's circuitry and save power.
4.13. Synchronous Ethernet (Sync-E)
YT8531S provides Synchronous Ethernet (Sync-E) support when the device is operating in 1000BASE-T,
100BASE-TX, 1000BASE-X and 100BASE-FX on the transmission media. The CLKOUT pin can be assigned to
output the recovered clock.
The recovery clock for Sync-E can be either a 125MHz or 25MHz clock.
If the CLKOUT pin is assigned to output the recovered clock from PHY and PHY is working at 1000BASE-T
mode, when the PHY is in SLAVE mode, the CLKOUT will output the recoverd clock from the MDI. If the
device is in MASTER mode, the CLKOUT will output the clock based on the local free run PLL.
4.14. Wake-On-LAN (WOL)
Wake-on-LAN (WOL) is a mechanism to manage and regulate the total network power consumption. YT8531S
supports automatic detection of a specific frame and notification via dedicated hardware interrupt pin. The
specific frame contains a specific data sequence located anywhere inside the packet. The data sequence consists of
6 bytes of consecutive 1 (0xFFFFFFFFFFFF), followed by 16 repetitions of the MAC address of the computer to
be waked up. The 48-bit MAC address can be set in MAC_Address_Cfg1~3 common registers.
14
Motorcomm YT8531SH / YT8531SC Datasheet
4.15. Link Down Power Saving (Sleep Mode)
YT8531S supports link down power saving, also called sleep mode. When UTP port link down and no signals
over UTP cable for 40 seconds, YT8531S will enter sleep mode.
For most of time in sleep mode, YT8531S will disable almost all the circuits except crystal clock and comparators
for channel 0/1 of 10BASE-Te. Access by MDC/MDIO interface is available.
At a time interval in sleep mode, YT8531S will wake to transmit signals over TRXP1/TRXN1. The time interval
is a random value around 2.7s.
Once detecting signals over UTP cable, YT8531S will exit sleep mode.
4.16. Interrupt
YT8531S provides an active low interrupt output pin (INT_N) based on change of the PHY status. Every interrupt
condition is represented by the read-only general interrupt status register (section 6.2.18. Interrupt Status Register
(UTP MII register 0x13)).
The interrupts can be individually enable or disable by setting or clearing bits in the interrupt enable register
(section 6.2.17. Interrupt Mask Register (UTP MII register 0x12)).
Note 1: The interrupt of the YT8531S is a level-triggered mechanism.
Note 2: The INT_N and PME_N functions share the same pin (pin 34). Refer to section 5.5. INT_N/PME_N Pin
Usage.
15
Motorcomm YT8531SH / YT8531SC Datasheet
5. Operational Description
5.1. Reset
YT8531S have a hardware reset pin(RESET_N) which is low active. RESET_N should be active for at least 10ms
to make sure all internal logic is reset to a known state. Hardware reset should be applied after power up.
RESET_N is also used for power on strapping. After RESET_N is released, YT8531S latches input value on
strapping pins which are used as configuration information to provide flexibility in application without mdio
access.
YT8531S also provides two software reset control registers. Two of them are used to reset all UTP internal logic
except some mdio configuration registers, by setting bit 15 of UTP mii register (address 0x0). And the third is
used to reset all SerDes internal logic except CDR and some mdio configuration registers, by setting bit15 of
SerDes mii register(address 0x0) to 1. These two bits are self-clear after reset process is done. For detailed
information about what register will be reset by software reset, please refer to register table.
Table 13. Reset Timing Characteristics
Symbol
Description
Min
Typ
Max
Units
The duration from all powers steady to reset
T1
10
ms
signal release to high
T2
The duration of reset signal remain low timing
10
ms
VDDx
GND
RESET
GND
Figure 11. Reset Timing Diagram
5.2. PHY Address
For YT8531S, Strapping PHYAD[2:0] is used to generate phy address.
YT8531S always responses to phy address 0. It can be disabled by configure bit[6] to 1'b0 of extended
register(address 0xa005). It also has another broadcast phy address which is configurable through mdio. Bit[4:0]
of extended register(address 0xa005) is broadcast phy address and its default value is 5’b11111. Bit[5] of
extended register(address 0xa005) is enable control for broadcast phy address and its default value is 1’b0.
5.3. RGMII Interface
Reduced gigabit media independent interface is a subset of GMII which is used for gigabit Ethernet. For
100M/10M application, RGMII is similar to MII. The only difference is that tx_er/rx_er is transmitted by
TX_CTL/RX_CTL on the falling edge of clock. TXD[3:0] and RXD[3:0] will be duplicated on both rising and
falling edge of clock.
For 100M application, TX_CLK and RX_CLK are 25MHz.
For 10M application, TX_CLK and RX_CLK are 2.5MHz.
16
Motorcomm YT8531SH / YT8531SC Datasheet
RX_CLK
RX_CLK
RX_CTL
RX_CTL
RXD[3:0]
RXD[3:0]
TX_CLK
TX_CLK
TX_CTL
TX_CTL
TXD[3:0]
TXD[3:0]
PHY
MAC
Figure 12. Connection Diagram of RGMII
5.4. LED
The LED interface can either be controlled by the PHY or controlled manually, independent of the state of the
PHY. Three status LEDs are available. Thy can be used to indicate operation speed, duplex mode, and link status.
The LEDs can be programmed to different status functions from their default value. They can also be controlled
directly from the register interface.
5.5. INT_N/PME_N Pin Usage
The INT_N/PME_N pin (pin 34) is designed to notify both interrupt and WOL events. The default mode of this
pin is INT_N (Ext_0xa00a, bit[6]=0). For general use, indication of a WOL event is also integrated into one of the
interrupt events which is triggered when any specified WOL event occurs. However, the ‘Pulse Low’ waveform
format is not supported during this mode; only the Active Low, level-triggered waveform is provided.
If PME_N mode is selected (Ext_0xa00a, bit[6]=1), pin 34 becomes a fully functional PME_N pin. Note that the
interrupt function is disabled in this mode.
5.6. Power Supplies
The YT8531S device requires only one external power supply: 3.3 V. Inside the chip there is a 3.3V rail, 1.1V
rail, 2.5V or 1.8V rail.
5.6.1. Internal Switch Regulator
YT8531S integrates a switch regulator which converts 3.3V to 1.1V at a high-efficiency for core power rail.
It is optional for an external regulator to provide this core voltage.
5.6.2. Internal LDO
YT8531S also integrates a LDO which converts 3.3V to 2.5V or 1.8V for RGMII I/O power rail and configured
by CFG_LDO[1:0].
Table 14. CFG_LDO[1:0] Configuration
Configuration
Description
2’b01
LDO is set to 2.5V
2’b10 or 2’b11
LDO is set to 1.8V
Use external 3.3V to supply to DVDD_RGMII pin.
2’b00
LDO is disabled
17
Motorcomm YT8531SH / YT8531SC Datasheet
6. Register Overview
Table 15. Register Access Types
Description
Read and write
Self-clear.
If default value is '0' ('1'), writing a '1' ('0') to this register field causes the function to be
activated immediately, and then the field will be automatically cleared to '0' ('1').
Read only.
Latch high.
Latch Low.
Read clear.
Software reset to 0.
Software reset to 1.
Default value depends on power on strapping.
Type
RW
SC
RO
LH
LL
RC
SWC
SWS
POS
6.1. Common Register
6.1.1. SMI_SDS_PHY (EXT_0xA000)
Bit
15:2
1
Symbol
Reserved
Smi_sds_phy
0
Reserved
Table 16. SMI_SDS_PHY (EXT_0xA000)
Access
Default Description
RO
0x0
Reserved
to control access whether UTP register or SDS
RW POS 0x0
register.
1 to access SDS;
0 to access UTP.
Default value depend on chip mode. When the
UTP port exsits, default 0; else default 1. Refer
AP note for details.
RO
0x0
Reserved
6.1.2. Chip_Config (EXT_0xA001)
Bit
15
Symbol
Sw_rst_n_mode
14:12
11
10
9
Reserved
Iddq_mode
Reserved
En_gate_rx_clk_rgmii
8
Rxc_dly_en
7
6
Reserved
En_ldo
5:4
Cfg_ldo
Table 17. Chip_Config (EXT_0xA001)
Access
Default Description
A whole chip software reset, it will also be
RW SC
0x1
asserted when chip mode changed, low active,
self clear
RO
0x0
Reserved
RW
0x0
Iddq test mode
RO
0x0
Reserved
RW
0x0
1 = to close RXC when PHY link down;
0 = do not close RXC when PHY link down.
rgmii clk 2ns delay control, depends on
RW POS 0x1
strapping
RO
0x0
Reserved
rgmii ldo enable, default is 0 and will be set to 1
RW
0x1
after power on strapping is done
Rgmii ldo voltage and RGMII/MDC/MDIO
RW POS 0x0
PAD's level shifter control. Depends on
18
Motorcomm YT8531SH / YT8531SC Datasheet
3
2:0
Reserved
Mode_sel
RO
RW POS
0x0
0x0
strapping.
2'b11: 1.8v
2'b10: 1.8v
2'b01: 2.5v
2'b00: 3.3v
Reserved
chip mode, depend on strapping.
3'b000: UTP_TO_RGMII;
3'b001: FIBER_TO_RGMII;
3'b010: UTP_FIBER_TO_RGMII;
3'b011: UTP_TO_SGMII;
3'b100: SGPHY_TO_RGMAC;
3'b101: SGMAC_TO_RGPHY;
3'b110: UTP_TO_FIBER_AUTO;
3’b111: UTP_TO_FIBER_FORCE.
6.1.3. SDS_Config (EXT_0xA002)
Bit
15:13
12
Symbol
Reserved
En_surppress_txer
11
10:8
7:0
Reserved
Reserved
Reserved
Table 18. SDS_Config (EXT_0xA002)
Access
Default Description
RO
0x0
Reserved
1: to surppress the RX_ER generated by the
RW
0x1
serdes when it works in SGMII PHY full duplex
mode and RX_DV is 0 and rx_lpi_active is 0;
0: to not surppress.
RW
0x1
Reserved
RO
0x0
Reserved
RW
0x80
Reserved
6.1.4. RGMII_Config1 (EXT_0xA003)
Bit
15
Symbol
Rgmac_cfg_mode
14
Tx_clk_sel
13:10
Rx_delay_sel
9
8
En_rgmii_fd_crs
En_rgmii_crs
Table 19. RGMII_Config1 (EXT_0xA003)
Access
Default Description
When chip mode is SGPHY_TO_RGMAC, it
RW
0x0
controls the source of the RGMII's speed, duplex
and link status. These information will be sent to
the SGMII PHY.
1: RGMII's speed, deplex, link status
information comes from EXT 0xA004;
0: these information comes from RGMII OOB.
Refer EXT 0xA005 for detail.
0: use original RGMII TX_CLK to drive the
RW
0x0
RGMII TX_CLK delay train;
1: use inverted RGMII TX_CLK to drive the
RGMII TX_CLK delay train.
Used for debug
RGMII RX_CLK delay train configuration,
RW
0x0
about 150ps per step
RW
0x0
See EXT 0xA003 bit[8].
0: to not encode GMII/MII CRS into RGMII
RW
0x0
OOB;
19
Motorcomm YT8531SH / YT8531SC Datasheet
7:4
Tx_delay_sel_fe
RW
0xf
3:0
Tx_delay_sel
RW
0x1
1: to encode GMII/MII CRS into RGMII OOB
when it's half duplex mode or EXT 0xA003
bit[9] is 1.
RGMII TX_CLK delay train configuration when
speed is 100Mbps or 10Mbps, it's 150ps per step
typically.
RGMII TX_CLK delay train configuration when
speed is 1000Mbps, it's150ps per step typically.
6.1.5. RGMII_Config2 (EXT_0xA004)
Bit
15:14
13
12
11:10
9
8
7:6
5
4
3:2
1
0
Table 20. RGMII_Config2 (EXT_0xA004)
Symbol
Access
Default Description
RGMII's speed information when it works as
Speed_rgphy
RO
0x0
RGMII PHY. It's also the source of RGMII
OOB.
RGMII's duplex information when it works as
Duplex_rgphy
RO
0x0
RGMII PHY. It's also the source of RGMII
OOB.
RGMII's linkup information when it works as
Link_up_rgphy
RO
0x0
RGMII PHY. It's also the source of RGMII
OOB.
RGMII's pause information when it works as
Pause_rgphy
RO
0x0
RGMII PHY.
RGMII's EEE capability information when it
Eee_cap_rgphy
RO
0x0
works as RGMII PHY.
RGMII's EEE clock stopable capability
Eee_clkstp_cap_rgphy
RO
0x0
information when it works as RGMII PHY.
RGMII's speed configuration when it works as
Speed_rgmac
RW
0x0
RGMII MAC and EXT A003 bit[15] is 1.
RGMII's duplex configuration when it works as
Duplex_rgmac
RW
0x0
RGMII MAC and EXT A003 bit[15] is 1.
RGMII's linkup configuration when it works as
Link_up_rgmac
RW
0x0
RGMII MAC and EXT A003 bit[15] is 1.
RGMII's pause configuration when it works as
Pause_rgmac
RW
0x0
RGMII MAC.
RGMII's EEE capability configuration when it
Eee_cap_rgmac
RW
0x0
works as RGMII MAC.
RGMII's EEE clock stopable capability
Eee_clkstp_cap_mac
RW
0x0
configuration when it works as RGMII MAC.
6.1.6. MDIO_Cfg_And_RGMII_OOB_Mon (EXT_0xA005)
Bit
15:14
13
12
Table 21. MDIO_Cfg_And_RGMII_OOB_Mon (EXT_0xA005)
Symbol
Access
Default Description
speed information RGMII MAC decods from the
Speed_rgmac_ob
RO
0x0
OOB
duplex information RGMII MAC decods from
Duplex_rgmac_ob
RO
0x0
the OOB
linkup information RGMII MAC decods from
Link_up_rgmac_ob
RO
0x0
the OOB
20
Motorcomm YT8531SH / YT8531SC Datasheet
11
10
9:8
7
6
Reserved
Bypass_mdio_watchdog
Reserved
En_mdc_la
En_phyaddr0
RO
RW
RO
RW
RW
0x0
0x0
0x0
0x1
0x1
5
4:0
En_bdcst_addr
Bdcst_addr
RW
RW
0x0
0x0
Reserved
bypass mdio watch dog
Reserved
enable mdc latch for read data
1: to always respond to MDIO command whose
PHYAD field is 0; 0: to only respond to MDIO
command whose PHYAD filed equals to PHY
address strapping.
enable broadcast address
broadcast address
6.1.7. Misc_Config (EXT_0xA006)
Bit
15:9
8
Symbol
Reserved
Fiber_high_pri_cmb
7
6
5
4
Jumbo_enable
Rem_lpbk_sds
Rem_lpbk_phy
Uldata_rloopback
3
2:1
Bp_gmii_fatal_rst
Comb_wait_timer_sel
0
Fib_speed_sel
Table 22. Misc_Config (EXT_0xA006)
Access
Default Description
RW
0x0
Reserved
1=fiber has higher priority in
RW
0x0
UTP_FIBER_TO_RGMII mode, else UTP has
higher priority
RW
0x0
enable jumbo frame
RW
0x0
set remote loopback for SDS
RW
0x0
set remote loopback for UTP
1=remain upload data when rem lpbk is set for
RW
0x0
phy or sds
RW
0x1
bypass gmii fifo overflow and underflow rst
select wait timer for first priority media after
RW
0x2
second priority media is link up;
2'b00: 1s;
2'b01: 5s;
2'b10: 15s;
2'b11: 25s
Select fiber speed when auto sensing is disable;
RW
0x1
1: 1000BX;
0: 100FX
6.1.8. MAC_Address_Cfg1 (EXT_0xA007)
Bit
15:0
Table 23. MAC_Address_Cfg1 (EXT_0xA007)
Symbol
Access
Default Description
mac_addr_loc_47_32
RW
0x0
highest 16 bits of MAC address used for WOL
6.1.9. MAC_Address_Cfg2 (EXT_0xA008)
Bit
15:0
Table 24. MAC_Address_Cfg2 (EXT_0xA008)
Symbol
Access
Default Description
mac_addr_loc_31_16
RW
0x0
middle 16 bits of MAC address used for WOL
6.1.10. MAC_Address_Cfg3 (EXT_0xA009)
Table 25. MAC_Address_Cfg3 (EXT_0xA009)
21
Motorcomm YT8531SH / YT8531SC Datasheet
Bit
15:0
Symbol
mac_addr_loc_15_0
Access
RW
Default
0x0
Description
lowest 16 bits of MAC address used for WOL
6.1.11. WOL_Cfg (EXT_0xA00A)
Bit
15:8
7
Symbol
Reserved
Sw_close_rgmii
6
Pmeb_intb_sel
5
Wol_src_manual
4
Wol_src_sel
3
2:0
Wol_en
Wol_lth_sel
Table 26. WOL_Cfg (EXT_0xA00A)
Access
Default Description
RO
0x0
Reserved
RW
0x0
1.disable rgmii interface
0.enable rgmii interface
RW
0x0
1: Pin 34 functions as PME_N.
0: Pin 34 functions as INT_N.
1: control manually the source of the WOL event
RW
0x0
coms from which media;
0: the source of the WOL event is controlled
automatically by chip mode: when UTP is
present, it comes UTP; otherwise, it coms from
SDS.
RW
0x0
It's valid when EXT_0xA00A bit[5] is 1.
1: WOL event comes from SDS;
0: WOL event comes from UTP.
RW
0x0
enable WOL.
RW
0x2
wol_lth_sel[0],
1: PME_N is level triggerd and active LOW;
When PME_N is LOW, EXT 0xA00A bit3
wol_en should be set to 0 to clear the PME_N.
0: PME_N is pulse triggered and active LOW,
the pusel width is controlled by wol_lth_sel[2:1].
Wol_lth_sel[2:1]:
00: 84ms;
01: 168ms;
10: 336ms;
11: 672ms.
6.1.12. LED_GENERAL_CFG (EXT_0xA00B)
Bit
15
Symbol
Col_blk_sel
14
Jabber_led_dis
Table 27. LED_GENERAL_CFG (EXT_0xA00B)
Access
Default Description
1 = when collision happens, and related LEDn
RW
0x1
cfg (n is 0/1/2) register's bit3 led_col_blk_en is
1, LED blink at Blink Mode2;
0 = when collision happens, and related LEDn
cfg (n is 0/1/2) register's bit3 led_col_blk_en is
0, LED blink at Blink Mode1.
LED could blinks at different frequency in Blink
Mode1 and Blink Mode2. Refer to EXT
A00F[3:0] for the Blink Mode2 and Blink
Mode1.
1 = when 10Mb/s Jabber happens, LED will not
RW
0x1
blink;
22
Motorcomm YT8531SH / YT8531SC Datasheet
13
Lpbk_led_dis
RW
0x1
12
Dis_led_an_try
RW
0x0
11:9
8
7:6
Reserved
Led_2_force_en
Led_2_force_mode
RO
RW
RW
0x0
0x0
0x0
5
4:3
Led_1_force_en
Led_1_force_mode
RW
RW
0x0
0x0
2
1:0
Led_0_force_en
Led_0_force_mode
RW
RW
0x0
0x0
1 = In internal loopback mode, LED will not
blink;
1: LED will be ON when auto-negotiation is at
LINK_GOOD_CHECK status, in which status,
the link is not up already.
Reserved
1 = enable LED2 force mode.
Valid when bit8 is set.
00: force LED OFF;
01: force LED ON;
10: force LED Blink at Blink Mode1;
11: force LED Blink at Blink Mode2.
LED could blinks at different frequency in Blink
Mode1 and Blink Mode2. Refer to EXT
A00F[3:0] for the Blink Mode2 and Blink
Mode1.
1 = enable LED1 force mode.
Valid when bit5 is set.
Refer EXT A00B[7:6] for the force mode
description.
1 = enable LED0 force mode.
Valid when bit2 is set.
Refer EXT A00B[7:6] for the force mode
description.
6.1.13. LED0_CFG (EXT_0xA00C)
Bit
15:14
Symbol
Led_src_sel_0
13
Led_act_blk_ind_0
12
Led_fdx_on_en_0
11
Led_hdx_on_en_0
10
Led_txact_blk_en_0
9
Led_rxact_blk_en_0
Table 28. LED0_CFG (EXT_0xA00C)
Access
Default Description
select the source of internal signals controlling
RW
0x0
LED0.
2'b00: UTP
2'b01: serdes
2'b10: UTP and serdes
2'b11: UTP or serdes
Default value of LED0 cfg depends on the
strapping of chip mode.
When traffic is present, make LED0 BLINK no
RW
0x0
matter the previous LED0 status is ON or OFF,
or make LED0 blink only when the previous
LED0 is ON.
1: If BLINK status is not activated, when PHY
RW
0x0
link up and duplex mode is full duplex, LED0
will be ON.
1: If BLINK status is not activated, when PHY
RW
0x0
link up and duplex mode is half duplex, LED0
will be ON.
1: If bit[13] is 1, or bit[13] is 0 and ON at certain
RW
0x1
speed or duplex more is/are activated, when
PHY link up and TX is active, make LED0 blink
at mode2.
1: If bit[13] is 1, or bit[13] is 0 and ON at certain
RW
0x1
speed or duplex more is/are activated, when
PHY link up and RX is active, make LED0 blink
23
Motorcomm YT8531SH / YT8531SC Datasheet
8
Led_txact_on_en_0
RW
0x0
7
Led_rxact_on_en_0
RW
0x0
6
Led_gt_on_en_0
RW
0x0
5
Led_ht_on_en_0
RW
0x0
4
Led_bt_on_en_0
RW
0x1
3
Led_col_blk_en_0
RW
0x0
2
Led_gt_blk_en_0
RW
0x0
1
Led_ht_blk_en_0
RW
0x0
0
Led_bt_blk_en_0
RW
0x0
at mode2.
1: if BLINK status is not activated, when PHY
link up and TX is active, make LED0 ON at least
10ms.
1: if BLINK status is not activated, when PHY
link up and RX is active, make LED0 ON at
least 10ms.
1: if BLINK status is not activated, when PHY
link up and speed mode is 1000Mbps, make
LED0 ON.
1: if BLINK status is not activated, when PHY
link up and speed mode is 100Mbps, make
LED0 ON;
1: if BLINK status is not activated, when PHY
link up and speed mode is 10Mbps, make LED0
ON;
1: if PHY link up and collision happen, make
LED0 BLINK;
1: if PHY link up and speed mode is 1000Mbps,
make LED0 BLINK;
1: if PHY link up and speed mode is 100Mbps,
make LED0 BLINK;
1: if PHY link up and speed mode is 10Mbps,
make LED0 BLINK;
6.1.14. LED1_CFG (EXT_0xA00D)
Bit
15:14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Symbol
Led_src_sel_1
Led_act_blk_ind_1
Led_fdx_on_en_1
Led_hdx_on_en_1
Led_txact_blk_en_1
Led_rxact_blk_en_1
Led_txact_on_en_1
Led_rxact_on_en_1
Led_gt_on_en_1
Led_ht_on_en_1
Led_bt_on_en_1
Led_col_blk_en_1
Led_gt_blk_en_1
Led_ht_blk_en_1
Led_bt_blk_en_1
Table 29. LED1_CFG (EXT_0xA00D)
Access
Default Description
RW
0x0
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
RW
0x1
Same logic as LED0 control.
RW
0x1
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
RW
0x1
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
6.1.15. LED2_CFG (EXT_0xA00E)
Bit
15:14
13
Symbol
Led_src_sel_2
Led_act_blk_ind_2
Table 30. LED2_CFG (EXT_0xA00E)
Access
Default Description
RW
0x0
Same logic as LED0 control.
RW
0x0
Same logic as LED0 control.
24
Motorcomm YT8531SH / YT8531SC Datasheet
12
11
10
9
8
7
6
5
4
3
2
1
0
Led_fdx_on_en_2
Led_hdx_on_en_2
Led_txact_blk_en_2
Led_rxact_blk_en_2
Led_txact_on_en_2
Led_rxact_on_en_2
Led_gt_on_en_2
Led_ht_on_en_2
Led_bt_on_en_2
Led_col_blk_en_2
Led_gt_blk_en_2
Led_ht_blk_en_2
Led_bt_blk_en_2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x0
0x0
0x1
0x1
0x0
0x0
0x1
0x0
0x0
0x0
0x0
0x0
0x0
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
Same logic as LED0 control.
6.1.16. LED_BLINK_CFG (EXT_0xA00F)
Bit
15:7
6:4
Symbol
Reserved
Led_duty
3:2
Freq_sel_2
1:0
Freq_sel_1
Table 31. LED_BLINK_CFG (EXT_0xA00F)
Access
Default Description
RO
0x0
Reserved
Select duty cycle of Blink:
RW
0x0
000: 50% ON and 50% OFF;
001: 67% ON and 33% OFF;
010: 75% ON and 25% OFF;
011: 83% ON and 17% OFF;
100: 50% ON and 50% OFF;
101: 33% ON and 67% OFF;
110: 25% ON and 75% OFF;
111: 17% ON and 83% OFF.
Select frequency of Blink Mode2:
RW
0x1
00: 2Hz;
01: 4Hz;
10: 8Hz;
11: 16Hz.
Select frequency of Blink Mode1:
RW
0x2
00: 2Hz;
01: 4Hz;
10: 8Hz;
11: 16Hz.
6.1.17. Pad Drive Strength Cfg (EXT_0xA010)
Bit
15:13
Symbol
Rgmii_sw_dr_rxc
12
Rgmii_sw_dr[2]
11
Int_od_en
10
Int_act_hi
Table 32. Pad Drive Strength Cfg (EXT_0xA010)
Access
Default Description
RW
0x3
Drive strenght of rx_clk pad.
3'b111: strongest;
3'b000: weakest.
Bit 2 of Rgmii_sw_dr[2:0], refer to ext A010
RW
0x0
[5:4]
RW
0x1
1'b1: Interupt pin acts as a open drain pad
1'b0: Interupt pin acts as a normal output pad
RW
0x0
1'b1: Interupt acts as high active
25
Motorcomm YT8531SH / YT8531SC Datasheet
9:8
Dr_sync_e
RW
0x3
7:6
Dr_mdio
RW
0x3
5:4
Rgmii_sw_dr[1:0]
RW POS
0x3
3:2
Dr_int_io
RW
0x3
1:0
Dr_led
RW
0x3
1'b0: interupt acts as low active
Drive strenght of SyncE pad. 2'b11: strongest;
2'b00: weakest
Drive strenght of mdio pad. 2'b11: strongest;
2'b00: weakest
Bit 1 and 0 of Rgmii_sw_dr, Drive strenght of
rxd/rx_ctl rgmii pad.
3'b111: strongest;
3'b000: weakest
Drive strenght of interrupt pad. 2'b11: strongest;
2'b00: weakest
Drive strenght of led pad. 2'b11: strongest;
2'b00: weakest
6.1.18. SyncE_CFG (EXT_0xA012)
Bit
15:8
7
6
5
4
3:1
0
Table 33. SyncE_CFG (EXT_0xA012)
Symbol
Access
Default Description
Reserved
RO
0x0
Reserved
1: In UTP_TO_FIBER mode, do not enable
Phy_do_fib
RW
0x1
UTP until fiber links up
0: always enable UTP
En_sync_e
RW
0x1
enable sync e clock output
always output sync e clock even when link is
En_sync_e_during_lnkdn
RW
0x0
down
Clk_fre_sel
RW
0x0
1'b1: output 125m clock; 1'b0: output 25m clock
select clock source of synce.
Clk_src_sel
RW
0x4
3'b000：internal 125MHz PLL output clock
3'b001：UTP recovered RX clock (when
{en_adc_1, en_adc_0}==2’b10, output adc1;
==2’b01 or 2’b11 output adc0 clock, else
disable output)
3'b010：SerDes 125MHz RX output clock
3'b011：clock ptp_in from digital (RGMII TX
delayed clock, or debug clock out)
3’b100: reference 25MHz clock (default)
3’b101: 25MHz SSC.
source of 3'b000, 3'b001 and 3'b010 can be
controled by clk_fre_sel.
1=output internal RGMII TXC to synce clock;
Ptp_clk_to_sds_sel
RW
0x0
used for template test; 1'b0=output one of
internal clock, including any channel's DA/AD
clock, to synce clock
6.2. UTP MII Register
6.2.1. Basic Control Register (0x00)
Bit
15
Symbol
Reset
Table 34. Basic Control Register (0x00)
Access
Default Description
PHY Software Reset. Writing 1 to this bit
RW SC
0x0
causes immediate PHY reset. Once the
26
Motorcomm YT8531SH / YT8531SC Datasheet
14
Loopback
RW SWC
0x0
13
Speed_Selection(LSB)
RW
0x0
12
Autoneg_En
RW
0x1
11
Power_down
RW SWC
0x0
10
Isolate
RW SWC
0x0
9
Re_Autoneg
RW SC
SWS
0x0
8
Duplex_Mode
RW
0x1
7
Collision_Test
RW SWC
0x0
6
5:0
Speed_ Selection(MSB)
Reserved
RW
RO
0x1
0x0
operation is done, this bit is cleared
automatically.
0: Normal operation
1: PHY reset
Internal loopback control
1’b0: disable loopback
1’b1: enable loopback
LSB of speed_selection[1:0]. Link speed can be
selected via either the Auto-Negotiation
process, or manual speed selection
speed_selection[1:0]. Speed_selection[1:0] is
valid when Auto-Negotiation is disabled by
clearing bit 0.12 to zero.
Bit6 bit13
1 1 = Reserved
1 0 = 1000Mb/s
0 1 = 100Mb/s
0 0 = 10Mb/s
1: to enable auto-negotiation;
0: auto-negotiation is disabled.
1 = Power down
0 = Normal operation
When the port is switched from power down to
normal operation, software reset and AutoNegotiation are performed even bit[15] RESET
and bit[9] RESTART_AUTO_NEGOTIATION
are not set by the user.
Isolate phy from RGMII/SGMII/FIBER.
1’b0: Normal mode
1’b1: Isolate mode
Auto-Negotiation automatically restarts after
hardware or software reset regardelss of bit[9]
RESTART.
1 = Restart Auto-Negotiation Process
0 = Normal operation
The duplex mode can be selected via either the
Auto-Negotiation process or manual duplex
selection. Manual duplex selection is allowed
when Auto-Negotiation is disabled by setting
bit[12] AUTO_NEGOTIATION to 0.
1 = Full Duplex
0 = Half Duplex
Setting this bit to 1 makes the COL signal
asserted whenever the TX_EN signal is
asserted.
1 = Enable COL signal test
0 = Disable COL signal test
See bit13.
Reserved. Write as 0, ignore on read
6.2.2. Basic Status Register (0x01)
Bit
Symbol
Table 35. Basic Status Register (0x01)
Access
Default Description
27
Motorcomm YT8531SH / YT8531SC Datasheet
15
14
13
12
11
10
9
8
100BASE-T4
100BASE-X_Fd
100BASE-X_Hd
10Mbps_Fd
10Mbps_Hd
100BASE-T2_Fd
100BASE-T2_Hd
Extended_Status
RO
RO
RO
RO
RO
RO
RO
RO
0x0
0x1
0x1
0x1
0x1
0x0
0x0
0x1
7
Unidirect_Ability
RO
0x0
6
Mf_Preamble_Suppression
RO
0x1
5
Autoneg_Complete
RO SWC
0x0
4
Remote_Fault
0x0
3
Autoneg_Ability
RO RC
SWC LH
RO
2
Link_Status
RO LL
SWC
0x0
1
Jabber_Detect
RO RC
SWC LH
0x0
0
Extended_Capability
RO
0x1
0x1
PHY doesn't support 100BASE-T4
PHY supports 100BASE-X_FD
PHY supports 100BASE-X_HD
PHY supports 10Mbps_Fd
PHY supports 10Mbps_Hd
PHY doesn't support 100BASE-T2_Fd
PHY doesn't support 100BASE-T2_Hd
Whether support EXTended status register in
MII 0xF
0: Not supported
1: Supported
1'b0: PHY able to transmit from MII only when
the PHY has determined that a valid link has
been established
1’b1: PHY able to transmit from MII regardless
of whether the PHY has determined that a valid
link has been established
1'b0: PHY will not accept management frames
with preamble suppressed
1’b1: PHY will accept management frames with
preamble suppressed
1'b0: Auto-negotiation process not completed
1’b1: Auto-negotiation process completed
1'b0: no remote fault condition detected
1’b1: remote fault condition detected
1'b0: PHY not able to perform Auto-negotiation
1’b1: PHY able to perform Auto-negotiation
Link status
1’b0: Link is down
1’b1: Link is up
10BASE-Te jabber detected. It would assert if
TX activity lasts longer than 42ms.
1’b0: no jabber condition detected
1’b1: Jabber condition detected.
To indicate whether support EXTended
registers, to access from address register 0x1E
and data register 0x1F
1’b0: Not supported
1’b1: Supported
6.2.3. PHY Identification Register1 (0x02)
Bit
15:0
Symbol
Phy_Id
Table 36. PHY Identification Register1 (0x02)
Access
Default Description
RO
0x4f51 Bits 3 to 18 of the Organizationally Unique
Identifier
6.2.4. PHY Identification Register2 (0x03)
Bit
15:10
Symbol
Phy_Id
9:4
Type_No
Table 37. PHY Identification Register2 (0x03)
Access
Default Description
Bits 19 to 24 of the Organizationally Unique
RO
0x3a
Identifier
RO
0x11
6 bits manufacturer's type number
28
Motorcomm YT8531SH / YT8531SC Datasheet
3:0
Revision_No
RO
0xa
4 bits manufacturer's revision number
6.2.5. Auto-Negotiation Advertisement (0x04)
Bit
15
14
13
12
11
10
Table 38. Auto-Negotiation Advertisement (0x04)
Access
Default Description
This bit is updated immediately after the writing
RW
0x0
operation; however the configuration does not
take effect until any of the following occurs:
This bit is updated immediately after the writing
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
If 1000BASE-T is advertised, the required next
pages are automatically transmitted. This bit
must be set to 0 if no additional next page is
needed.
1 = Advertise
0 = Not advertised
Ack
RO
0x0
Always 0.
1 = Set Remote Fault bit
Remote_Fault
RW
0x0
0 = Do not set Remote Fault bit
Extended nEXT page enable control bit
Extended_NEXT_Page
RW
0x1
1 = Local device supports transmission of
extended next pages
0 = Local device does not support transmission
of extended next pages.
This bit is updated immediately after the writing
Asymmetric_Pause
RW
0x0
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
1 = Asymmetric Pause
0 = No asymmetric Pause
This bit is updated immediately after the writing
Pause
RW
0x0
operation; however the configuration does not
take effect until any of the following occurs:
This bit is updated immediately after the writing
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
Symbol
NEXT_Page
29
Motorcomm YT8531SH / YT8531SC Datasheet
9
100BASE-T4
RO
0x0
8
100BASE-TX_Full_Duplex
RW
0x1
7
100BASETX_Half_Duplex
RW
0x1
6
10BASE-Te_Full_Duplex
RW
0x1
5
10BASE-Te_Half_Duplex
RW
0x1
30
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
1 = MAC PAUSE implemented
0 = MAC PAUSE not implemented
1 = Able to perform 100BASE-T4
0 = Not able to perform 100BASE-T4
Always 0
This bit is updated immediately after the writing
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
1 = Advertise
0 = Not advertised
This bit is updated immediately after the writing
operation; however the configuration does not
take effect until any of the following occurs:
This bit is updated immediately after the writing
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
1 = Advertise
0 = Not advertised
This bit is updated immediately after the writing
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
1 = Advertise
0 = Not advertised
This bit is updated immediately after the writing
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
Motorcomm YT8531SH / YT8531SC Datasheet
4:0
Selector_Field
RW
0x1
1 = Advertise
0 = Not advertised
Selector Field mode.
00001 = IEEE 802.3
6.2.6. Auto-Negotiation Link Partner Ability (0x05)
Bit
15
14
13
12
11
10
9
8
7
6
5
Table 39. Auto-Negotiation Link Partner Ability (0x05)
Symbol
Access
Default Description
Received Code Word Bit 15
1000BASE-X_Fd
RO SWC 0x0
1 = Link partner is capable of next page
0 = Link partner is not capable of next page
Acknowledge. Received Code Word Bit 14
ACK
RO SWC 0x0
1 = Link partner has received link code word
0 = Link partner has not received link code
word
Remote Fault. Received Code Word Bit 13
REMOTE_FAULT
RO SWC 0x0
1 = Link partner has detected remote fault
0 = Link partner has not detected remote fault
Technology Ability Field. Received Code Word
RESERVED
RO SWC 0x0
Bit 12
Technology Ability Field. Received Code Word
ASYMMETRIC_PAUSE
RO SWC 0x0
Bit 11
1 = Link partner requests asymmetric pause
0 = Link partner does not request asymmetric
pause
Technology Ability Field. Received Code Word
PAUSE
RO SWC 0x0
Bit 10
1 = Link partner supports pause operation
0 = Link partner does not support pause
operation
Technology Ability Field. Received Code Word
100BASE-T4
RO SWC 0x0
Bit 9
1 = Link partner supports 100BASE-T4
0 = Link partner does not support100BASE-T4
100BASETechnology Ability Field. Received Code Word
RO SWC 0x0
TX_FULL_DUPLEX
Bit 8
1 = Link partner supports 100BASE-TX fullduplex
0 = Link partner does not support 100BASE-TX
full-duplex
100BASETechnology Ability Field. Received Code Word
RO SWC 0x0
TX_HALF_DUPLEX
Bit 7
1 = Link partner supports 100BASE-TX halfduplex
0 = Link partner does not support 100BASE-TX
half-duplex
10BASETechnology Ability Field. Received Code Word
RO SWC 0x0
Te_FULL_DUPLEX
Bit 6
1 = Link partner supports 10BASE-Te fullduplex
0 = Link partner does not support 10BASE-Te
full-duplex
10BASETechnology Ability Field. Received Code Word
RO SWC 0x0
Te_HALF_DUPLEX
Bit 5
31
Motorcomm YT8531SH / YT8531SC Datasheet
4:0
SELECTOR_FIELD
RO SWC
0x0
1 = Link partner supports 10BASE-Te halfduplex
0 = Link partner does not support 10BASE-Te
half-duplex
Selector Field Received Code Word Bit 4:0
6.2.7. Auto-Negotiation Expansion Register (0x06)
Bit
15:5
4
3
2
1
0
Table 40. Auto-Negotiation Expansion Register (0x06)
Symbol
Access
Default Description
Reserved
RO
0x0
Reserved
RO RC
1 = Fault is detected
Parallel Detection fault
0x0
LH SWC
0 = No fault is detected
Link partner nEXT page
RO LH
1 = Link partner supports NEXT page
0x0
able
SWC
0 = Link partner does not support next page
1 = Local Device supports NEXT Page
Local NEXT Page able
RO
0x1
0 = Local Device does not support Next Page
RO RC
1 = A new page is received
Page received
0x0
LH
0 = No new page is received
Link Partner Auto
1 = Link partner supports auto-negotiation
RO
0x0
negotiation able
0 = Link partner does not support autonegotiation
6.2.8. Auto-Negotiation NEXT Page Register (0x07)
Bit
15
14
13
12
11
10:0
Table 41. Auto-Negotiation NEXT Page Register (0x07)
Symbol
Access
Default Description
Transmit Code Word Bit 15
NEXT Page
RW
0x0
1 = The page is not the last page
0 = The page is the last page
Reserved
RO
0x0
Reserved
Transmit Code Word Bit 13
Message page mode
RW
0x1
1 = Message Page
0 = Unformatted Page
Transmit Code Word Bit 12
Ack2
RW
0x0
1 = Comply with message
0 = Cannot comply with message
Transmit Code Word Bit 11
Toggle
RO
0x0
1 = This bit in the previously exchanged Code
Word is logic 0
0 = The Toggle bit in the previously exchanged
Code Word is logic 1
Transmit Code Word Bits [10:0].
Message/Unformatte
RW
0x1
These bits are encoded as Message Code Field
when bit[13] is set to 1, or as Unformatted Code
Field when bit[13] is set to 0.
6.2.9. Auto-Negotiation Link Partner Received NEXT Page Register (0x08)
Bit
15
Table 42. Auto-Negotiation Link Partner Received NEXT Page Register (0x08)
Symbol
Access
Default Description
Received Code Word Bit 15
NEXT Page
RO
0x0
1 = This page is not the last page
32
Motorcomm YT8531SH / YT8531SC Datasheet
14
Ack
RO
0x0
13
Message page mode
RO
0x0
12
Ack2
RO
0x0
11
Toggle
RO
0x0
10:0
Message/Unformatte
RO
0x0
0 = This page is the last page
Received Code Word Bit 14
1 = successfully received its Link Partner’s ack
0 = didn't receive its Link Partner’s ack
Received Code Word Bit 13
1 = Message Page
0 = Unformatted Page
Received Code Word Bit 12
1 = Comply with message
0 = Cannot comply with message
Received Code Word Bit 11
1 = This bit in the previously exchanged Code
Word is logic 0
0 = The Toggle bit in the previously exchanged
Code Word is logic 1
Received Code Word Bit 10:0
These bits are encoded as Message Code Field
when bit[13] is set to 1, or as Unformatted Code
Field when bit[13] is set to 0.
6.2.10. MASTER-SLAVE control register (0x09)
Bit
15:13
12
11
Table 43. MASTER-SLAVE control register (0x09)
Access
Default Description
The TX_TCLK signals from the RX_CLK pin
RW
0x0
is for jitter testing in test modes 2 and 3. When
exiting the test mode, hardware reset or
software reset through writing MII register 0x0
bit[15] must be performed to ensure normal
operation.
000 = Normal Mode
001 = Test Mode 1 - Transmit Waveform Test
010 = Test Mode 2 - Transmit Jitter Test
(MASTER mode)
011 = Test Mode 3 - Transmit Jitter Test
(SLAVE mode)
100 = Test Mode 4 - Transmit Distortion Test
110, 111 = Reserved, normal operation.
Master/Slave Manual
This bit is updated immediately after the writing
RW
0x0
configuration Enable
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
1 = Manual MASTER/SLAVE configuration
0 = Automatic MASTER/SLAVE configuration.
This bit is updated immediately after the writing
Master/Slave configuration RW
0x0
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
Symbol
Test mode
33
Motorcomm YT8531SH / YT8531SC Datasheet
10
Port Type
RW
0x0
9
1000BASE-T Full
RW
0x1
8
1000BASE-T Half-
RW
0x0
7:0
Reserved
RW
0x0
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
This bit is ignored if bit[12] is 0.
1 = Manual configuration as MASTER
0 = Manual configuration as SLAVE.
This bit is updated immediately after the writing
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
This bit is ignored if bit[12] is 1.
1 = Prefer multi-port device (MASTER)
0 = Prefer single port device (SLAVE)
This bit is updated immediately after the writing
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
1 = Advertise
0 = Not advertised
This bit is updated immediately after the writing
operation; however the configuration does not
take effect until any of the following occurs:
• Software reset is asserted by writing register
0x0 bit[15]
• Restart Auto-Negotiation is triggered by
writing register 0x0 bit[9]
• The port is switched from power down to
normal operation by writing register 0x0 bit[11]
• Link goes down
1 = Advertise
0 = Not advertised (default)
Write as 0, ignore on read.
6.2.11. MASTER-SLAVE Status Register (0x0A)
Bit
15
Table 44. MASTER-SLAVE Status Register (0x0A)
Symbol
Access
Default Description
RO RC
This register bit will clear on read, rising of MII
Master/Slave_cfg_error
0x0
SWC LH
0.12 and rising of AN complete.
1 = Master/Slave configuration fault detected
0 = No fault detected
34
Motorcomm YT8531SH / YT8531SC Datasheet
14
Master/Slave
RO
0x0
13
Local Receiver Status
RO
0x0
12
Remote Receiver
RO
0x0
11
Link Partner
RO
0x0
10
Link Partner
RO
0x0
9:8
7:0
Reserved
Idle Error Count
RO
RO RC
0x0
0x0
This bit is not valid unless register 0x1 bit5 is 1.
1 = Local PHY configuration resolved to Master
0 = Local PHY configuration resolved to Slave
1 = Local Receiver OK
0 = Local Receiver not OK
1 = Remote Receiver OK
0 = Remote Receiver not OK
This bit is not valid unless register 0x1 bit5 is 1.
1 = Link Partner supports 1000BASE-T half
duplex
0 = Link Partner does not support 1000BASE-T
half duplex
This bit is not valid unless register 0x1 bit5 is 1.
1 = Link Partner supports 1000BASE-T full
duplex
0 = Link Partner does not support 1000BASE-T
full duplex
Reserved
MSB of Idle Error Counter. The register
indicates the idle error count since the last read
operation performed to this register. The counter
pegs at 11111111 and does not roll over.
6.2.12. MMD Access Control Register (0x0D)
Bit
15:14
Symbol
Function
13:5
4:0
Reserved
DEVAD
Table 45. MMD Access Control Register (0x0D)
Access
Default Description
00 = Address
RW
0x0
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
RO
0x0
Reserved
MMD register device address.
RW
0x0
00001 = MMD1
00011 = MMD3
00111 = MMD7
6.2.13. MMD Access Data Register (0x0E)
Bit
15:0
Symbol
Address data
Table 46. MMD Access Data Register (0x0E)
Access
Default Description
If register 0xD bits [15:14] are 00, this register
RW
0x0
is used as MMD DEVAD address register.
Otherwise, this register is used as MMD
DEVAD data register as indicated by its address
register.
6.2.14. Extended status register (0x0F)
Bit
15
Table 47. Extended status register (0x0F)
Symbol
Access
Default Description
1 = PHY supports 1000BASE-X Full Duplex
1000BASE-X Full Duplex
RO
0x0
35
Motorcomm YT8531SH / YT8531SC Datasheet
14
1000BASE-X Half Duplex
RO
0x0
13
1000BASE-T Full Duplex
RO
0x1
12
1000BASE-T Half Duplex
RO
0x0
11:0
Reserved
RO
0x0
0 = PHY does not supports 1000BASE-X Full
Duplex
Always 0.
1 = PHY supports 1000BASE-X Half Duplex.
0 = PHY does not support 1000BASE-X Half
Duplex.
Always 0
1 = PHY supports 1000BASE-T Full Duplex
0 = PHY does not supports 1000BASE-T Full
Duplex
Always 1
1 = PHY supports 1000BASE-T Half Duplex
0 = PHY does not support 1000BASE-T Half
Duplex
Always 0.
Reserved
6.2.15. PHY Specific Function Control Register (0x10)
Bit
15:7
6:5
4
3
2
1
0
Table 48. PHY Specific Function Control Register (0x10)
Symbol
Access
Default Description
Reserved
RO
0x0
Reserved
Changes made to these bits disrupt normal
Cross_md
RW
0x3
operation, thus a software reset is mandatory
after the change. And the configuration does not
take effect until software reset.
00 = Manual MDI configuration
01 = Manual MDIX configuration
10 = Reserved
11 = Enable automatic crossover for all modes
Reserved
RO
0x0
Reserved
This bit is effective in 10BASE-Te half-duplex
Crs_on_tx
RW
0x0
mode and 100BASE-TX mode:
1 = Assert CRS on transmitting or receiving
0 = Never assert CRS on transmitting, only
assert it on receiving.
1 = SQE test enabled, 0 = SQE test disabled
En_sqe_test
RW
0x0
Note: SQE Test is automatically disabled in
full-duplex mode regardless the setting in this
bit.
If polarity reversal is disabled, the polarity is
En_pol_inv
RW
0x1
forced to be normal in 10BASE-Te.
1 = Polarity Reversal Enabled
0 = Polarity Reversal Disabled
1 = Disable 10BASE-Te jabber detection
Dis_jab
RW
0x0
function
0 = Enable 10BASE-Te jabber detection
function
6.2.16. PHY Specific Status Register (0x11)
Bit
Symbol
Table 49. PHY Specific Status Register (0x11)
Access
Default Description
36
Motorcomm YT8531SH / YT8531SC Datasheet
15:14
Speed_mode
RO
0x0
13
Duplex
RO
0x0
12
Page Received real-time
RO
0x0
11
Speed and Duplex Resolved
RO
0x0
10
Link status real-time
RO
0x0
9:7
6
Reserved
MDI Crossover Status
RO
RO
0x0
0x0
5
Wirespeed downgrade
RO
0x0
4
3
Reserved
Transmit Pause
RO
RO
0x0
0x0
2
Receive Pause
RO
0x0
1
Polarity Real Time
RO
0x0
0
Jabber Real Time
RO
0x0
37
These status bits are valid only when bit11 is 1.
Bit11 is set when Auto-Negotiation is
completed or Auto-Negotiation is disabled.
11 = Reserved
10 = 1000 Mbps
01 = 100 Mbps
00 = 10 Mbps
This status bit is valid only when bit11 is 1.
Bit11 is set when Auto-Negotiation is
completed or Auto-Negotiation is disabled.
1 = Full-duplex
0 = Half-duplex
1 = Page received
0 = Page not received
When Auto-Negotiation is disabled, this bit is
set to 1 for force speed mode.
1 = Resolved
0 = Not resolved
1 = Link up
0 = Link down
Reserved
This status bit is valid only when bit11 is 1.
Bit11 is set when Auto-Negotiation is
completed or Auto-Negotiation is disabled.
The bit value depends on register 0x10 “PHY
specific function control register” bits6~bit5
configurations. Register 0x10 configurations
take effect after software reset.
1 = MDIX
0 = MDI
1 = Downgrade
0 = No Downgrade
Reserved
This status bit is valid only when bit11 is 1.
Bit11 is set when Auto-Negotiation is
completed.
This bit indicates MAC pause resolution. This
bit is for information purposes only and is not
used by the device. When in force mode, this bit
is set to be 0.
1 = Transmit pause enabled
0 = Transmit pause disabled
This status bit is valid only when bit[11] is 1.
Bit[11] is set when Auto-Negotiation is
completed. This bit indicates MAC pause
resolution. This bit is for information purposes
only and is not used by the device. When in
force mode, this bit is set to be 0.
1 = Receive pause enabled
0 = Receive pause disabled
1 = Reverted polarity
0 = Normal polarity
1 = Jabber
0 = No jabber
Motorcomm YT8531SH / YT8531SC Datasheet
6.2.17. Interrupt Mask Register (0x12)
Bit
15
14
13
12
11
10
9:7
6
5
4
3
2
1
0
Table 50. Interrupt Mask Register (0x12)
Symbol
Access
Default Description
Auto-Negotiation Error INT RW
1 = Interrupt enable
0x0
mask
0 = Interrupt disable
Speed Changed INT mask
RW
0x0
same as bit 15
Duplex changed INT mask
RW
0x0
same as bit 15
Page Received INT mask
RW
0x0
same as bit 15
Link Failed INT mask
RW
0x0
same as bit 15
Link Succeed INT mask
RW
0x0
same as bit 15
reserved
RW
0x0
No used.
WOL INT mask
RW
0x0
same as bit 15
Wirespeed downgraded INT RW
0x0
same as bit 15
mask
Reserved
RW
0x0
No used.
Serdes Link Failed INT
RW
0x0
same as bit 15
mask
Serdes Link Success INT
RW
0x0
same as bit 15
mask
Polarity changed INT mask RW
0x0
same as bit 15
Jabber Happened INT mask RW
0x0
same as bit 15
6.2.18. Interrupt Status Register (0x13)
Bit
15
14
13
12
11
10
9:7
6
Table 51. Interrupt Status Register (0x13)
Symbol
Access
Default Description
Error can take place when any of the following
Auto-Negotiation Error INT RO RC
0x0
happens:
• MASTER/SLAVE does not resolve correctly
• Parallel detect fault
• No common HCD
• Link does not come up after negotiation is
complete
• Selector Field is not equal
• flp_receive_idle=true while Autoneg
Arbitration FSM is in NEXT PAGE WAIT state
1 = Auto-Negotiation Error takes place
0 = No Auto-Negotiation Error takes place
1 = Speed changed
Speed Changed INT
RO RC
0x0
0 = Speed not changed
1 = duplex changed
Duplex changed INT
RO RC
0x0
0 = duplex not changed
1 = Page received
Page Received INT
RO RC
0x0
0 = Page not received
1 = Phy link down takes place
Link Failed INT
RO RC
0x0
0 = No link down takes place
1 = Phy link up takes place
Link Succeed INT
RO RC
0x0
0 = No link up takes place
reserved
RO RC
0x0
No used.
1 = PHY received WOL magic frame.
WOL INT
RO RC
0x0
0 = PHY didn’t receive WOL magic frame
38
Motorcomm YT8531SH / YT8531SC Datasheet
5
Wirespeed downgraded INT
RO RC
0x0
4
3
Reserved
Serdes Link Failed INT
RO RC
RO RC
0x0
0x0
2
Serdes Link Success INT
RO RC
0x0
1
Polarity changed INT
RO RC
0x0
0
Jabber Happened INT
RO RC
0x0
1 = speed downgraded.
0 = Speed didn’t downgrade.
Reserved
1 = Sds link down takes place
0 = No Sds link down takes place
1 = Sds link up takes place
0 = No Sds link up takes place
1 = PHY revered MDI polarity
0 = PHY didn’t revert MDI polarity
1 = 10BASE-Te TX jabber happened
0 = 10BASE-Te TX jabber didn’t happen
Please refer to UTP MII Register 0x1 bit[1]
Jabber_Detect.
6.2.19. Speed Auto Downgrade Control Register (0x14)
Bit
15:12
11:6
5
4:2
1
0
Table 52. Speed Auto Downgrade Control Register (0x14)
Symbol
Access
Default Description
Reserved
RO
0x0
Reserved
Reserved
RW
0x20
Reserved
When this bit is set to 1, the PHY enables smartEn_speed_downgrade
RW POS 0x1
speed function. Writing this bit requires a
software reset to update. This bit will be set to
1'b0 in UTP_TO_FIBER mode; else set to 1'b1,
only take effect after software reset
Autoneg retry limit preIf these bits are set to 3, the PHY attempts five
RW
0x3
downgrade
times (set value 3 + additional 2) before
downgrading. The number of attempts can be
changed by these bits. Only take effect after
software reset
Reserved
RW
0x0
Reserved
Reserved
RO
0x0
Reserved
6.2.20. Rx Error Counter Register (0x15)
Bit
15:0
Symbol
Rx_err_counter
Table 53. Rx Error Counter Register (0x15)
Access
Default Description
This counter increase by 1 at the 1st rising of
RO SWC 0x0
RX_ER when RX_DV is 1. The counter will
hold at maximum 16'hFFFF and not roll over.
6.2.21. Extended Register's Address Offset Register (0x1E)
Bit
15:8
7:0
Table 54. Extended Register's Address Offset Register (0x1E)
Symbol
Access
Default Description
Reserved
RO
0x0
Reserved
Extended Register Address
It's the address offset of the extended register
RW
0x0
Offset
that will be Write or Read
39
Motorcomm YT8531SH / YT8531SC Datasheet
6.2.22. Extended Register's Data Register (0x1F)
Bit
15:0
Table 55. Extended Register's Data Register (0x1F)
Symbol
Access
Default Description
It's the data to be written to the extended register
Extended Register Data
RW
0x0
indicated by the address offset in register 0x1E,
or the data read out from that extended register.
6.3. UTP MMD Register
6.3.1. PCS Control 1 Register (MMD3, 0x0)
Bit
15
Symbol
Pcs_rst
14:11
10
9:0
Reserved
Clock_stoppable
Reserved
Table 56. PCS Control 1 Register (MMD3, 0x0)
Access
Default Description
Setting this bit will set all PCS registers to their
RW SC
0x0
default states. This action also initiate a
software reset as setting MII 0x0 bit15 and a
reset as setting MMD1 0x0 bit15 and MMD7
0x0 bit15.
RO
0x0
Reserved
RW SWC 0x0
Not used.
RO
0x0
Reserved
6.3.2. PCS Status 1 Register (MMD3, 0x1)
Bit
15:12
11
Symbol
Reserved
Tx_lpi_rxed
10
Rx_lpi_rxed
9
Tx_lpi_indic
8
Rx_lpi_indic
7:3
2
1:0
Reserved
Pcsrx_lnk_status
Reserved
Table 57. PCS Status 1 Register (MMD3, 0x1)
Access
Default Description
RO
0x0
Reserved
When read as 1, it indicates that the transmit
RO LH
0x0
PCS has received low power idle signaling one
or more times since the register was last read.
Lach High.
When read as 1, it indicates that the receive PCS
RO LH
0x0
has received low power idle signaling one or
more times since the register was last read. Lach
High.
When read as 1, it indicates that the transmit
RO
0x0
PCS is currently receiving low power idle
signals.
When read as 1, it indicates that the receive PCS
RO
0x0
is currently receiving low power idle signals.
RO
0x0
Reserved
RO LL
0x0
PCS status, latch low.
RO
0x0
Reserved
6.3.3. EEE Control and Capability Register (MMD3, 0x14)
Bit
15:3
2
Table 58. EEE Control and Capability Register (MMD3, 0x14)
Symbol
Access
Default Description
Reserved
RO
0x0
Reserved
1000BASE-T EEE
RO
0x1
Always 1. EEE is supported for 1000BASE-T
40
Motorcomm YT8531SH / YT8531SC Datasheet
1
0
100BASE-TX EEE
Reserved
RO
RO
0x1
0x0
Always 1. EEE is supported for 100BASE-TX
Reserved
6.3.4. EEE Wake Error Counter (MMD3, 0x16)
Bit
15:0
Symbol
Lpi_wake_err_cnt
Table 59. EEE Wake Error Counter (MMD3, 0x16)
Access
Default Description
RO RC
Count wake time faults where the PHY fails to
0x0
SWC
complete its normal wake sequence within the
time required for the specific PHY type.
6.3.5. Local Device EEE Ability (MMD7, 0x3C)
Bit
15:3
2
1
0
Symbol
Reserved
EEE_1000BT
EEE_100BT
Reserved
Table 60. Local Device EEE Ability (MMD7, 0x3C)
Access
Default Description
RO
0x0
Reserved
RW
0x0
PHY's 1000BASE-T EEE ability.
RW
0x0
PHY's 100BASE-TX EEE ability.
RO
0x0
Reserved
6.3.6. Link Partner EEE Ability (MMD7, 0x3 D)
Bit
15:3
2
1
0
Table 61. Link Partner EEE Ability (MMD7, 0x3D)
Symbol
Access
Default Description
Reserved
RO
0x0
Reserved
LP_ge_eee_ability
RO
0x0
Link partner's 1000BASE-T EEE ability.
LP_ge_eee_ability
RO
0x0
Link partner's 100BASE-TX EEE ability.
Reserved
RO
0x0
Reserved
6.4. UTP EXT Register
6.4.1. Pkgen Cfg1 (EXT_0x38)
Bit
15:13
12
Symbol
Reserved
En_pkgen_da_sa
11
Pkgen_brdcst
10
Pkgchk_txsrc_sel
Table 62. Pkgen Cfg1 (EXT_0x38)
Access
Default Description
RO
0x0
Reserved
1: set the DA/SA of the packet generated by
RW
0x0
pkg_gen to a programmed value; For DA, if
UTP EXT 0x38 bit[11] is 1, the DA is set to
broadcase address FF-FF-FF-FF-FF-FF; else,
the DA is set to fix value, the highest 5 Bytes
are 00-00-00-00-00, and the lowest 1 Byte is
programmed by UTP EXT 0x3A bit[15:8]. For
SA, the highest 5 Bytes are 00-00-00-00-00, and
the lowest 1 Byte is programmed by UTP EXT
0x3A bit[7:0].
0: the DA/SA is not programmed value
RW
0x0
Valid when UTP EXT 0x38 bit12 is 1.
1: set the DA to broadcase address FF-FF-FFFF-FF-FF
0: set the DA to a fixed programmed value.
1'b1: the package checker on TX side will check
RW
0x0
41
Motorcomm YT8531SH / YT8531SC Datasheet
9
Pkgen_en_az
RW
0x0
8:0
Pkgen_in_az_t
RW
0x1ff
the tx data generated by pkg_gen;
1'b0: the package checker on TX side will check
the tx data of UTP GMII/MII.
1: to enable send LPI pattern during the IPG of
the packages sent by pkg_gen.
The time how long LPI pattern is sent, unit is
us.
6.4.2. Pkgen Cfg2 (0x39)
Bit
15:8
Symbol
Pkgen_pre_az_t
7:0
Pkgen_aft_az_t
Table 63. Pkgen Cfg2 (EXT_0x39)
Access
Default Description
The time from the end of last package to the
RW
0x20
beginning of LPI pattern, unit is us.
The time from the end of LPI pattern to the
RW
0x19
beginning of next package, unit is us.
6.4.3. Pkgen Cfg3 (EXT_0x3A)
Bit
15:8
Symbol
Pkgen_da
7:0
Pkgen_sa
Table 64. Pkgen Cfg3 (EXT_0x3A)
Access
Default Description
Lowest 8 bits of DA, others is zero. Refer to
RW
0x0
UTP EXT 0x38 bit[12] for detail.
Lowest 8 bits of SA, others is zero. Refer to
RW
0x0
UTP EXT 0x38 bit[12] for detail.
6.4.4. Pkgen Cfg4 (0x3B)
Bit
15:8
7:0
Symbol
Reserved
Pkg_data_fix
Table 65. Pkgen Cfg4 (EXT_0x3B)
Access
Default Description
RO
0x0
Reserved
RW
0x0
Valid when EXT 0xA0 bit1:0 is 11.
The fixed GMII data pattern that will be sent.
6.4.5. Pkg Cfg0 (EXT_0xA0)
Bit
15
Symbol
Pkg_chk_en
14
Pkg_en_gate
13
Bp_pkg_gen
12
Pkg_gen_en
Table 66. Pkg Cfg0 (EXT_0xA0)
Access
Default Description
1: to enable UTP RX/TX package checker. RX
RW
0x0
checker checks the UTP GMII/MII RX data; TX
checker checks the UTP GMII/MII TX data.
1: to enable gate all the clocks to package selfRW
0x1
test module when bit15 pkg_chk_en is 0, bit13
bp_pkg_gen is 1 and bit12 pkg_gen_en is 0;
0: not gate the clocks.
1: normal mode, to send GMII/MII TX data
RW
0x1
from RGMII, SGMII or SerDes;
0: test mode, to send out the GMII/MII data
generated by UTP pkg_gen module.
1: to enable pkg_gen generating GMII/MII
RW SC
0x0
packages. But, the data will only be sent to
transceiver when Bit13 bp_pkg_gen is 1'b0. If
pkg_burst_size is 0, continuous packages will
be generated and will be stopped only when
42
Motorcomm YT8531SH / YT8531SC Datasheet
11:8
Pkg_prm_lth
RW
0x8
7:4
Pkg_ipg_lth
RW
0xd
3
2
Reserved
Pkg_corrupt_crc
RW
RW
0x0
0x0
1:0
Pkg_payload
RW
0x0
pkg_gen_en is set to 0;
Otherwise, after the expected packages are
generated, pkg_gen will stop, pkg_gen_en will
be self-cleared.
The preamble length of the generated packages,
in Byte unit. Pkg_gen function only support >=2
Byte preamble length. Values smaller than 2
will be ignored by the pkg_gen module.
The IPG of the generated packages, in Byte unit
for setting smaller than 12. For setting 13, ipg is
2ms; for setting 14, ipg is 20ms; for 15, ipg is
400ms; Pkg_gen function only support >=2
Byte preamble length. Values smaller than 2
will be ignored by the pkg_gen module.
Reserved
1: to make pkg_gen to send out CRC error
packages.
0: pkg_gen sends out CRC good packages.
Control the payload of the generated packages.
00: increased Byte payload;
01: random payload;
10: fix pattern 0x5AA55AA5...
11: fix pattern set by EXT 0x3B bit7:0.
6.4.6. Pkg Cfg1 (EXT_0xA1)
Bit
15:0
Symbol
Pkg_length
Table 67. Pkg Cfg1 (EXT_0xA1)
Access
Default Description
RW
0x40
To set the length of the generated packages.
6.4.7. Pkg Cfg2 (EXT_0xA2)
Bit
15:0
Symbol
Pkg_burst_size
Table 68. Pkg Cfg2 (EXT_0xA2)
Access
Default Description
To set the number of packages in a burst of
RW
0x0
package generation.
6.4.8. Pkg Rx Valid0 (EXT_0xA3)
Bit
15:0
Symbol
Pkg_ib_valid_high
Table 69. Pkg Rx Valid0 (EXT_0xA3)
Access
Default Description
Pkg_ib_valid[31:16], pkg_ib_valid is the
RO RC
0x0
number of RX packages from wire whose CRC
are good and length are >=64Byte and
=64Byte and 1518Byte.
6.4.11. Pkg Rx Os1 (EXT_0xA6)
Bit
15:0
Symbol
Pkg_ib_os_good_low
Table 72. Pkg Rx Os1 (EXT_0xA6)
Access
Default Description
Pkg_ib_os_good[15:0], pkg_ib_os_good is the
RO RC
0x0
number of RX packages from wire whose CRC
are good and length are >1518Byte.
6.4.12. Pkg Rx Us0 (EXT_0xA7)
Bit
15:0
Symbol
Pkg_ib_us_good_high
Table 73. Pkg Rx Us0 (EXT_0xA7)
Access
Default Description
Pkg_ib_us_good[31:16], pkg_ib_us_good is the
RO RC
0x0
number of RX packages from wire whose CRC
are good and length are 1518Byte.
6.4.14. Pkg Rx Err (EXT_0xA9)
Bit
15:0
Symbol
Pkg_ib_err
Table 75. Pkg Rx Err (EXT_0xA9)
Access
Default Description
pkg_ib_err is the number of RX packages from
RO RC
0x0
wire whose CRC are wrong and length are
>=64Byte, =1518Byte.
44
Motorcomm YT8531SH / YT8531SC Datasheet
6.4.16. Pkg Rx Fragment (EXT_0xAB)
Bit
15:0
Symbol
Pkg_ib_frag
Table 77. Pkg Rx Fragment (EXT_0xAB)
Access
Default Description
pkg_ib_frag is the number of RX packages from
RO RC
0x0
wire whose length are =64Byte and
=64Byte and
1518Byte.
6.4.21. Pkg Tx Os1 (EXT_0xB0)
Bit
15:0
Symbol
Pkg_ob_os_good_low
Table 82. Pkg Tx Os1 (EXT_0xB0)
Access
Default Description
Pkg_ob_os_good[15:0], pkg_ob_os_good is the
RO RC
0x0
number of TX packages from GMII whose CRC
are good and length are >1518Byte.
6.4.22. Pkg Tx Us0 (EXT_0xB1)
Table 83. Pkg Tx Us0 (EXT_0xB1)
45
Motorcomm YT8531SH / YT8531SC Datasheet
Bit
15:0
Symbol
Pkg_ob_us_good_high
Access
RO RC
Default
0x0
Description
Pkg_ob_us_good[31:0], pkg_ob_us_good is the
number of TX packages from GMII whose CRC
are good and length are
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