2SK2232
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N-Channel 60 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
• Isolated Package
60
VDS (V)
RDS(on) (Ω)
VGS = 10 V
• High Voltage Isolation = 2.5 kVRMS (t = 60 s;
f = 60 Hz)
0.027
Qg (Max.) (nC)
95
Qgs (nC)
27
• Sink to Lead Creepage Distance = 4.8 mm
46
• 175 °C Operating Temperature
Qgd (nC)
Configuration
RoHS
COMPLIANT
• Dynamic dV/dt Rating
Single
• Low Thermal Resistance
• Lead (Pb)-free Available
D
TO-220 FULLPAK
G
S
G D S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Currenta
Linear Derating Factor
Single Pulse Avalanche Energyb
Maximum Power Dissipation
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
VGS at 10 V
TC = 25 °C
TC = 100 °C
SYMBOL
LIMIT
VDS
VGS
60
± 20
45
ID
IDM
TC = 25 °C
for 10 s
6-32 or M3 screw
EAS
PD
dV/dt
TJ, Tstg
30
220
0.32
100
52
4.5
- 55 to + 175
300d
10
1.1
UNIT
V
A
W/°C
mJ
W
V/ns
°C
lbf · in
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 25 V, starting TJ = 25 °C, L = 129 µH, RG = 25 Ω, IAS = 30 A (see fig. 12).
c. ISD ≤ 52 A, dI/dt ≤ 250 A/µs, VDD ≤ VDS, TJ ≤ 175 °C.
d. 1.6 mm from case.
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THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
Maximum Junction-to-Ambient
RthJA
-
65
Maximum Junction-to-Case (Drain)
RthJC
-
3.1
PARAMETER
MAX.
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 µA
60
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.060
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
1.0
-
3.0
V
nA
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VGS = ± 20 V
-
-
± 100
VDS = 60 V, VGS = 0 V
-
-
25
VDS = 48 V, VGS = 0 V, TJ = 150 °C
-
-
250
-
0.027
-
Ω
15
-
-
S
IGSS
IDSS
RDS(on)
gfs
ID = 18 Ab
VGS = 10 V
VDS = 25 V, ID = 18
Ab
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Drain to Sink Capacitance
C
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
Internal Source Inductance
tr
td(off)
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
f = 1.0 MHz
VGS = 10 V
ID = 52 A, VDS = 48 V,
see fig. 6 and 13b
VDD = 30 V, ID = 52 A,
RG = 9.1 Ω, RD= 0.54 Ω,
see fig. 10b
tf
LD
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
-
1500
-
-
720
-
-
100
-
-
12
-
-
-
95
-
-
27
-
-
46
-
19
-
-
120
-
-
55
-
-
86
-
-
4.5
-
pF
nC
ns
nH
G
-
7.5
-
-
-
45
-
-
120
-
-
2.5
V
-
140
300
ns
-
1.2
2.8
µC
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 30 A, VGS = 0 Vb
TJ = 25 °C, IF = 52 A, dI/dt = 100 A/µsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC = 175 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
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Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
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RD
VDS
VGS
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T.
RG
+
-
I AS
V DD
VDS
10 V
tp
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
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Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
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Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
•
•
•
•
RG
dV/dt controlled by R G
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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