USB to Full UART IC with GPIO
Product Data Sheet
PL2303GC
PL2303GC USB to Full UART IC with GPIO
Single-chip USB to Asynchronous Serial Data Interface
USB Interface
UART Interface
Fully Compliant with USB 2.0 specification
(Full-Speed Mode).
Supports Serial UART Interface:
o RS232, RS422, RS485
USB-IF certified (USB logo compliant) with
TID 40001838.
o Flexible baud rate support up to 12Mbps
UHCI/OHCI (USB 1.1), EHCI (USB 2.0), xHCI
(USB 3.1) Host Controller Compatible.
o Odd, Even, Mark, Space, None parity mode
Provides royalty-free USB to Virtual Com Port
(VCP) drivers for Windows, Mac, Linux, and
Android.
o Hardware Flow Control (CTS/RTS and/or
DSR/DTR)
Highly integrated USB 1.1 FS Transceiver.
Integrated termination resistors and pull-up
resistor to reduce PCB external components.
o Configurable Remote Wakeup Pin
Supports 256-byte OTPROM (One-Time
Programmable ROM) for USB device
descriptors and GPIO custom configuration.
OTPROM can be programmed directly
through USB port.
o 5, 6, 7 or 8 data bits
o One, one and a half, or two stop bits
o Software Flow Control (XON/XOFF)
1024-byte bi-directional data FIFO buffers
(768-byte receive/256-byte transmit) for faster
data throughput. Configurable in OTPROM.
Configurable Transmit and Receive LED
pins(*1) .
Suspend Pin control for RS232 transceiver.
UART inverted signal configurable option.
Each IC has unique ID (for Serial Number).
Supports bus-power, self-power and
high-power USB device configuration.
Supports Windows USB Selective Suspend
(Remote Wakeup enabled).
Supports VBUS input detect function to attach
USB host after VBUS is detected.
Supports 3.3V VBUS voltage operation.
Battery Charger Detection
Supports Battery Charger (BC1.2) Detection to
enable fast charging of batteries(*1).
Miscellaneous
Integrated self-generated precise clock
generator. External crystal is optional.
Integrated Power-on-Reset (POR) circuit.
GPIO Interface
Versatile GPIO functions and routing logic
provides easy to use multi-I/O functions.
Low operating power and USB suspend current.
Configurable I/O pin output driving strength.
Wide I/O voltage range (1.8V/2.5V/3.3V/5V).
Total 16 General Purpose I/O (GPIO) pins can
be used after configured.
-40oC to 85oC Operating Temperature.
Optional Clock Output to external MCU(*1).
*1 Configurable pins shared with UART pins.
Integrated 5V to 3.3V LDO that can support
80mA for external components.
28-pin SSOP and 24-pin UQFN IC package
(RoHS compliant and Pb-free Green
Compound).
Pin-compatible with PL2303HXD chip (SSOP28).
Prolific Technology Inc.
© 2018-2020 Prolific Inc. All rights reserved.
7F, No.48, Sec. 3, Nan Kang Rd., Nan Kang, Taipei 115, Taiwan
Proprietary and Confidential
Tel：+886-2-2654-6363; Fax：886-2-22654-6161
Website：http://www.prolific.com.tw/
USB to Full UART IC with GPIO
Product Data Sheet
PL2303GC
REVISION HISTORY
Revision
Description
To change ordering information from version
G3 to G4.
Added driver support Windows Server 2019.
Added PL2303GR information
Added Chip Marking information
Del PL2303GL UDFN8 package information.
Added θjc information and modify Output Driving
1.0.3
1.0.2
1.0.1
1.0.0
Strength.
Formal release
Date
2020/4/27
2020/2/13
2019/5/3
2018/12/11
Prolific Technology Inc.
© 2018-2020 Prolific Inc. All rights reserved.
7F, No.48, Sec. 3, Nan Kang Rd., Nan Kang, Taipei 115, Taiwan
Proprietary and Confidential
Tel：+886-2-2654-6363; Fax：886-2-22654-6161
Website：http://www.prolific.com.tw/
USB to Full UART IC with GPIO
Product Data Sheet
1.
2.
PL2303GC
Product Applications
Single-chip upgrade solution for Legacy RS232 devices to USB interface
USB to RS232/RS422/RS485 interface converters/cables/dongles/adapters
MCU-based devices to USB host interface
Point-of-Sale (POS) Terminals/Printers/Pole Displays
USB Barcode/Smart Card Readers
PC I/O Docking Station/Port Replicators
Healthcare/Medical USB Interface Data Transfer Cable
Serial-over-IP Wireless Solution
Cellular/PDA USB Interface Data Transfer Cable
GPS/Navigation USB Interface
Industrial / Instrumentation / Automation Control USB Interface
USB Modem / Wireless / Zigbee USB Interface
Set-Top Box (STB) / Home Gateway USB Interface
Battery Charger Detection for high-current and quick charging of batteries.
Royalty-Free Driver Support
Windows 10, 8, 7, Vista, XP, (Microsoft Certified WHQL Drivers)
- Windows Update Driver installation available in Windows 7 and above (32/64-bit)
3.
Windows Server 2003, 2008, 2008 R2, 2012, 2016, 2019
Windows Embedded Industry, Point-of-Service (WEPOS), and POSReady
Windows Embedded Compact, Windows Embedded CE, Windows CE
Mac OS X
Linux OS
Android 3.2 and above
Ordering Information
Chip Product Name
Package Type
Ordering Part Number
MPQ
PL2303G4ZJG7P2
48pcs / tube
PL2303G4ZJG8P2
2000pcs / reel
PL2303G4FIG7P2
490pcs / tray
PL2303G4FIG8P2
4000pcs / reel
28-pin SSOP
PL2303GC
24-pin UQFN
Prolific Technology Inc.
© 2018-2020 Prolific Inc. All rights reserved.
7F, No.48, Sec. 3, Nan Kang Rd., Nan Kang, Taipei 115, Taiwan
Proprietary and Confidential
Tel：+886-2-2654-6363; Fax：886-2-22654-6161
Website：http://www.prolific.com.tw/
USB to Full UART IC with GPIO
Product Data Sheet
4.
PL2303GC
Block Diagram
USBDP
BC 1.2
Detection
USBDM
USB 1.1 Transceiver
PLL
3.3V LDO
&
POR
VIN
3V3OUT
XO
(optional)
Clock
Generator
DPLL
Serial Interface Engine
(SIE)
Power
Management
XI
(optional)
Control
Endpoint
Command
Sequencer
OTPROM
Bulk Out
Endpoint
Bulk In
Endpoint
Outbound
FIFO
Buffer
Inbound
FIFO
Buffer
Interrupt In
Endpoint
Event
Generator
Mux/Demux
External
EEPROM
(optional)
UART Controller
Descriptor
ROM
IO Functions
Control
Registers
IO
Routing
Logic
I2C EEPROM Controller
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
TXEN
RS232/422/485 Interface
(or configurable GPIO)
Figure 4-1 PL2303GC Block Diagram
Prolific Technology Inc.
© 2018-2020 Prolific Inc. All rights reserved.
7F, No.48, Sec. 3, Nan Kang Rd., Nan Kang, Taipei 115, Taiwan
Proprietary and Confidential
Tel：+886-2-2654-6363; Fax：886-2-22654-6161
Website：http://www.prolific.com.tw/
USB to Full UART IC with GPIO
Product Data Sheet
5.
PL2303GC
USB Logo Certification
The PL2303GC IC has been certified by the USB-IF organization with TID 40001838 to be fully compliant
with the USB 2.0 specification.
Prolific Technology Inc.
© 2018-2020 Prolific Inc. All rights reserved.
7F, No.48, Sec. 3, Nan Kang Rd., Nan Kang, Taipei 115, Taiwan
Proprietary and Confidential
Tel：+886-2-2654-6363; Fax：886-2-22654-6161
Website：http://www.prolific.com.tw/
Product Data Sheet
PL2303GC
Table of Contents
1.
Product Applications .............................................................................................3
2.
Royalty-Free Driver Support .................................................................................3
3.
Ordering Information .............................................................................................3
4.
Block Diagram........................................................................................................4
5.
USB Logo Certification..........................................................................................5
6.
Overview ............................................................................................................... 11
6.1
7.
8.
PL2303 G-Series USB to Serial Family Product Table ............................................. 12
Pin Diagram and Description .............................................................................. 13
7.1
SSOP28 Pin Diagram .............................................................................................. 13
7.2
UQFN24 Pin Diagram .............................................................................................. 14
7.3
Pin Out Description .................................................................................................. 15
7.4
GPIO Multi-Function Options ................................................................................... 17
Functional Description ........................................................................................ 19
8.1
BC 1.2 Detection ..................................................................................................... 19
8.2
USB 1.1 FS Transceiver .......................................................................................... 19
8.3
LDO Regulator......................................................................................................... 19
8.4
Clock Generator ...................................................................................................... 19
8.5
USB FS SIE ............................................................................................................. 19
8.6
Power Management................................................................................................. 20
8.7
Control Endpoint ...................................................................................................... 20
8.8
Bulk Out Endpoint.................................................................................................... 20
8.9
Bulk In Endpoint ...................................................................................................... 20
8.10 Interrupt In Endpoint ................................................................................................ 20
8.11 Command Sequencer .............................................................................................. 20
8.12 Outbound FIFO........................................................................................................ 20
8.13 Inbound FIFO .......................................................................................................... 21
8.14 Event Generator ...................................................................................................... 21
8.15 Internal OTPROM .................................................................................................... 21
8.16 Mux/Demux ............................................................................................................. 21
8.17 Descriptor ROM ....................................................................................................... 21
8.18 UART Control .......................................................................................................... 21
Release: Apr. 27, 20
- 6 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
8.19 Control Registers ..................................................................................................... 21
8.20 IO Functions ............................................................................................................ 22
8.21 I/O Routing Logic ..................................................................................................... 22
8.22 I2C EEPROM Controller .......................................................................................... 22
9.
Chip Function Configuration .............................................................................. 23
9.1
USB Data Configuration .......................................................................................... 23
9.2
UART Configuration................................................................................................. 25
9.3
GPIO (GPA) Configuration....................................................................................... 26
9.4
GPIO (GPB) Configuration....................................................................................... 28
9.5
Miscellaneous (MISC) Configuration ........................................................................ 30
10. Design Application Examples ............................................................................. 31
10.1 USB Bus Powered Design ....................................................................................... 31
10.2 Self Powered Design ............................................................................................... 31
10.3 Chip Reset Control .................................................................................................. 33
10.4 I/O Power Supply to PL2303GC .............................................................................. 34
10.5 USB to RS232 Cable Design ................................................................................... 35
10.6 USB to RS485/RS422 ............................................................................................. 36
10.7 Battery Charging Support ........................................................................................ 37
10.8 External I2C EEPROM Support ............................................................................... 39
11. DC & Temperature Characteristics ..................................................................... 40
11.1 Absolute Maximum Ratings ..................................................................................... 40
11.2 DC Characteristics ................................................................................................... 40
11.2.1 Operating Voltage and Suspend Current .................................................................. 40
11.2.2 I/O Pins ...................................................................................................................... 40
11.3 Temperature Characteristics.................................................................................... 41
11.4 Baud Rate Characteristics ....................................................................................... 41
12. Outline Diagram ................................................................................................... 42
12.1 Chip Marking information .......................................................................................... 42
12.2 SSOP28 Package.................................................................................................... 42
12.3 UQFN24 Package ................................................................................................... 44
13. Packing Information ............................................................................................ 45
13.1 Carrier Tape (SSOP-28) .......................................................................................... 45
13.2 Carrier Tape (UQFN24) ........................................................................................... 46
Release: Apr. 27, 20
- 7 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
13.3 Reel Dimension ....................................................................................................... 47
13.4 Tube Packing ........................................................................................................... 48
Release: Apr. 27, 20
- 8 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
List of Figures
Figure 4-1 PL2303GC Block Diagram ......................................................................................... 4
Figure 7-1 PL2303GC Pin Diagram (SSOP28) ......................................................................... 13
Figure 7-2 PL2303GC Pin Diagram (UQFN24) ......................................................................... 14
Figure 10-1 USB Bus Powered Design Example ...................................................................... 31
Figure 10-2a USB Self Powered Design Example 1.................................................................. 32
Figure 10-2b USB Self Powered Design Example 2.................................................................. 32
Figure 10-3a Chip Reset Control Application ............................................................................ 33
Figure 10-3b Chip Power Reset Timing Diagram ...................................................................... 33
Figure 10-4a IO Power Supply .................................................................................................. 34
Figure 10-4b VDD_IO Voltage Supply....................................................................................... 34
Figure 10-5 USB to RS232 Design Example ............................................................................. 35
Figure 10-6 USB to RS485/422 Design Example ...................................................................... 36
Figure 10-7a Battery Charging Design Example #1 .................................................................. 37
Figure 10-7b Battery Charging Design Example #2 .................................................................. 38
Figure 10-8 External I2C EEPROM Design Example ................................................................ 39
Figure 12-1 PL2303GC Outline Diagram (SSOP28) ................................................................. 43
Figure 12-2 PL2303GC Outline Diagram (UQFN24) 4 x 4 mm .................................................. 44
Figure 13-1a SSOP28 Carrier Tape .......................................................................................... 45
Figure 13-1b IC Reel Placements ............................................................................................. 45
Figure 13-2 UQFN24 Carrier Tape ............................................................................................ 46
Figure 13-3 Reel Dimension ..................................................................................................... 47
Figure 13-4 Tube Packing Dimension ....................................................................................... 48
Release: Apr. 27, 20
- 9 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
List of Tables
Table 7-1: USB Data Interface Pins .......................................................................................... 15
Table 7-2: UART (Serial Port) Interface Pins............................................................................. 15
Table 7-3: Configurable GPIO Pins – Group A (Shared with Serial Port Pins)........................... 15
Table 7-4: Configurable GPIO Pins – Group B .......................................................................... 16
Table 7-5: Power and Ground Pins ........................................................................................... 16
Table 7-6: Miscellaneous Pins .................................................................................................. 16
Table 7-7: Configurable GPIO Multi-Function Pins .................................................................... 17
Table 7-8: GPIO Multi-Function Option Descriptions ................................................................. 17
Table 9-1 USB Descriptor Configuration ................................................................................... 23
Table 9-2 UART Startup Configuration...................................................................................... 25
Table 9-3 GPIO (GPA Group) Configuration ............................................................................. 26
Table 9-4 GPIO (GPB Group) Configuration ............................................................................. 28
Table 9-5 Miscellaneous Configuration ..................................................................................... 30
Table 11-1 Absolute Maximum Ratings..................................................................................... 40
Table 11-2a Operating Voltage and Suspend Current ............................................................... 40
Table 11-2b I/O Pins ................................................................................................................. 40
Table 11-3 Temperature Characteristics ................................................................................... 41
Table 11-4 Baud Rate Characteristics....................................................................................... 41
Table 12-1 Package Dimension ................................................................................................ 42
Table 13-1 Reel Part Number Information ................................................................................. 47
Release: Apr. 27, 20
- 10 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
6.
Overview
The new PL2303GC chip is one of the latest G-Series IC product added to the popular PL2303 USB to Serial
(UART) Bridge Controller family, replacing the PL2303HXD mainstream chip. It provides an advanced
full-featured single-chip bridge solution for connecting a full-duplex UART asynchronous serial interface
device to any Universal Serial Bus (USB) capable host. The PL2303GC provides highly compatible USB
drivers to simulate the traditional COM port (via virtual COM Port) on most operating systems allowing
existing serial UART applications based on legacy COM port to easily migrate and be made USB ready.
The new PL2303GC is pin-to-pin compatible with the popular PL2303HXD chip (SSOP28). It also integrates
an internal precise clock generator (no external crystal required), USB 1.1 transceiver, Serial Interface Engine
(SIE), LDO voltage regulator, power-on- reset (POR), FIFO data buffers, and OTPROM.
The PL2303GC added several new features and enhancements:
Integrated termination resistors and pull-up resistor to reduce PCB external components.
New USB drivers for different OS platforms with faster performance and advanced features.
Precise baud rate generator (up to 12Mbps).
OTPROM can be programmed directly through USB (no high voltage generator required).
Larger TX/RX FIFO data buffers (1024-byte).
Up to 16 configurable GPIO pins.
Versatile GPIO functions and routing logic (TX/RX LED, VBUS_DET, USB_CFG, CLK_OUT, etc.).
Supports 3.3V VBUS voltage operation.
Wide I/O voltage range (1.8V/2.5V/3.3V/5V).
Configurable I/O pin output driving strength.
UART inverted signal configurable option.
Unique USB Serial Number for each IC.
Supports Battery Charger (BC1.2) Detection to enable fast charging of batteries.
The PL2303GC is designed to support a wide-range of serial application domain including mobile, embedded,
industrial, consumer, healthcare, navigation, and wearable solutions in mind. It provides a small footprint that
could easily fit in to any connectors and handheld devices. With very small power consumption in either
operating or suspend mode, the PL2303GC is perfect for bus powered operation with plenty of power left for
the attached devices. Flexible signal level requirement on the RS232-like serial port side also allows the
PL2303GC to connect directly to any 5V~1.8V range devices.
The PL2303GC is available in two small footprint Pb-free (RoHS compliant) green compound packages:
28-pin SSOP and 24-pin UQFN packages.
Release: Apr. 27, 20
- 11 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
6.1
PL2303 G-Series USB to Serial Family Product Table
Prolific’s new PL2303 G-series USB to Serial family product line offers a variety of new advanced features for
USB serial interface product design. The PL2303 G-series are redesigned to provide accurate and flexible
baud rate support as well as plenty of I/O functions that can be easily configured in OTPROM memory.
PL2303 G-Series USB to Serial (UART) Family Product Line
Product
PL2303GC
PL2303GS
PL2303GE
PL2303GT
PL2303GL
PL2303GR
USB to Full UART
(Integrated
Clock)
USB to Full UART
(Integrated Clock)
USB to Full UART
(High ESD
Protection)
USB to RS232
(Internal RS232
Transceiver)
USB to Basic
UART
(Low-Pin Count)
USB to RS485
(Internal RS485
Transceiver)
SSOP28
UQFN24
SSOP16
SSOP28
SSOP28
SOP8
SSOP28
UART Interface
RS232
RS422/RS485
RS232
RS422/RS485
RS232
RS422/RS485
RS232 Only
RS232
(TX-RX Only)
RS485 Only
Max. Data Rates
12Mbps
12Mbps
12Mbps
1Mbps
115200bps
10Mbps
Dedicated GPIO
Pins
6
0
6
4
0
4
9
9
9
0
0
0
Clocking
Internal1
Internal
Internal1
Internal
Internal
Internal
OTPROM2
USB Data +
Configurable
GPIO Function
USB Data +
Configurable
GPIO Function
USB Data +
Configurable
GPIO Function
USB Data +
Configurable
GPIO Function
USB Data
USB Data
External
EEPROM Option
YES3
YES3
YES3
YES3
NO
NO
Android OS
Support
YES
YES
YES
YES
YES
YES
768-byte (RX)
256-byte (TX)
768-byte (RX)
256-byte (TX)
768-byte (RX)
256-byte (TX)
768-byte (RX)
256-byte (TX)
768-byte (RX)
256-byte (TX)
768-byte (RX)
256-byte (TX)
YES
YES
YES
No
No
No
I/O Voltage
Range
I/O levels from
1.8V to 5V
I/O levels from
1.8V to 5V
I/O levels from
1.8V to 5V
3.3V
I/O levels from
1.8V to 5V
3.3V
Pin Compatible
PL2303HXD
(SSOP28 only)
New design
PL2303EA
PL2303RA
PL2303SA
New design
Description
Packages
Shared GPIO
(with UART pins)
Configurable
Data Buffer4
Battery Charger
Detection Option
1
– Also supports external crystal clock source to bypass internal clock.
2
– OTPROM allows setting the USB data descriptors. Also allows setting of multi-function GPIO options.
3
– External EEPROM (when enabled in OTPROM) will override OTPROM settings.
4
– TX/RX data buffers are configurable in OTPROM (PL2303GC, PL2303GS, and PL2303GE); or by driver customization.
Release: Apr. 27, 20
- 12 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
7.
7.1
Pin Diagram and Description
SSOP28 Pin Diagram
Figure 7-1 PL2303GC Pin Diagram (SSOP28)
Release: Apr. 27, 20
- 13 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
7.2
UQFN24 Pin Diagram
Figure 7-2 PL2303GC Pin Diagram (UQFN24)
Release: Apr. 27, 20
- 14 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
7.3
Pin Out Description
Table 7-1: USB Data Interface Pins
SSOP28
UQFN24
Pin No.
Pin No.
DP
15
10
I/O
USB Port Data Plus (D+) Signal.
DM
16
11
I/O
USB Port Data Minus (D-) Signal.
Pin Name
Type
Description
Table 7-2: UART (Serial Port) Interface Pins
SSOP28
UQFN24
Pin No.
Pin No.
TXD
1
21
Output
Serial Port: Transmitted Data Output
DTR_N
2
22
Output
Serial Port: Data Terminal Ready Control Output
RTS_N
3
23
Output
Serial Port: Request To Send Control Output
RXD
5
1
Input
RI_N
6
2
Input
DSR_N
9
4
Input
Serial Port: Data Set Ready Control Input
DCD_N
10
5
Input
Serial Port: Data Carrier Detect Control Input
CTS_N
11
6
Input
Serial Port: Clear To Send Control Input
Pin Name
Type
Description
Serial Port: Received Data Input
Serial Port: Ring Indicator (Remote Wakeup) Control
Input
Table 7-3: Configurable GPIO Pins – Group A (Shared with Serial Port Pins)
SSOP28
UQFN24
Pin No.
Pin No.
GPA0
1
21
I/O
GPA1
5
1
I/O
GPA2
3
23
I/O
GPA3
11
6
I/O
GPA4
2
22
I/O
GPA5
9
4
I/O
GPA6
10
5
I/O
GPA7
6
2
I/O
Pin Name
Release: Apr. 27, 20
Type
Description
Configurable GPIO Pin. (see Section 7.4)
Factory default is TXD serial port output pin.
Configurable GPIO Pin. (see Section 7.4)
Factory default is RXD serial port input pin.
Configurable GPIO Pin. (see Section 7.4)
Factory default is RTS_N serial port output pin.
Configurable GPIO Pin. (see Section 7.4)
Factory default is CTS_N serial port input pin.
Configurable GPIO Pin. (see Section 7.4)
Factory default is DTR_N serial port output pin.
Configurable GPIO Pin. (see Section 7.4)
Factory default is DSR_N serial port input pin.
Configurable GPIO Pin. (see Section 7.4)
Factory default is DCD_N serial port input pin.
Configurable GPIO Pin. (see Section 7.4)
Factory default is RI_N serial port input pin.
- 15 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
Table 7-4: Configurable GPIO Pins – Group B
SSOP28
UQFN24
Pin No.
Pin No.
GPB0
22
15
I/O
Configurable GPIO Pin. (see Section 7.4)
GPB1
23
16
I/O
Configurable GPIO Pin. (see Section 7.4)
GPB2
14
9
I/O
Configurable GPIO Pin. (see Section 7.4)
GPB3
13
8
I/O
Configurable GPIO Pin. (see Section 7.4)
GPB4
24
17
I/O
Configurable GPIO Pin. (see Section 7.4)
GPB5
25
18
I/O
Configurable GPIO Pin. (see Section 7.4)
GPB6
12
7
I/O
GPB7
8
3
I/O
Pin Name
Type
Description
Configurable GPIO Pin. (see Section 7.4)
Factory default is SUSP_N output pin.
Configurable GPIO Pin. (see Section 7.4)
Factory default is TXEN output pin
NOTE: All GPB pins are default Input mode (except GPB6).
Table 7-5: Power and Ground Pins
SSOP28
UQFN24
Pin No.
Pin No.
VDD_IO
4
24
Power
VO_33
17
12
Power
GND
18
VIN
20
Pin Name
Exposed
Pad
14
Type
Power
Power
Description
+1.8V to +5V I/O signal power input pin.
Note: VDD_IO voltage should not larger than VIN voltage.
+3.3V output power from integrated LDO regulator. For
self-powered design, supply +3.3V to this pin.
Ground
USB port VBUS input power supply.
For self-powered design, supply +3.3V to this pin.
Table 7-6: Miscellaneous Pins
Pin Name
SSOP28
UQFN24
Pin No.
Pin No.
12
7
SUSP_N
Type
Output
Description
Active low Shutdown control pin. Can be used to
shutdown external RS232 transceiver.
Active low Reset pin. Can be used by external device
RESET_N
19
13
Input
to reset the PL2303GC.
NOTE: This pin has internal pull-high. It can be pull up
to VIN or VDD_IO.
XI
27
19
Input
XO
28
20
Output
NC
7, 21, 26
-
NC
Release: Apr. 27, 20
Optional. 12MHz crystal oscillator input.
If not used, leave pin floating.
Optional. 12MHz crystal oscillator output.
If not used, leave pin floating.
No internal connection. Leave floating.
- 16 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
7.4
GPIO Multi-Function Options
The PL2303GC chip (SSOP28 package) provides a total of 16 configurable GPIO (General Purpose I/O) pins.
The pins are grouped into GPA and GPB set of pins. The table below shows the possible functions that can
be configured for each GPIO pin. These special functions can be easily configured in the OTPROM of the
PL2303GC or to an external I2C EEPROM using the Prolific OTPROM/EEPROM software tool. When these
pins are configured as standard GPIO pins, customers can refer to the Prolific GPIO SDK (software
development kit) to develop software to control the GPIO pins for customer application desired functions.
Table 7-7: Configurable GPIO Multi-Function Pins
SSOP28
UQFN24
Factory
Pin No.
Pin No.
Default
GPA0
1
21
TXD
GPA1
5
1
RXD
GPA2
3
23
RTS
TX_LED
CLK_OUT
SUSP_N
USB_CFG
TXEN
GPA3
11
6
CTS
RX_LED
TRX_LED
WAKEUP
VBUS_DET
BC_DET
GPA4
2
22
DTR
TX_LED
CLK_OUT
USB_CFG
EE_SDA
GPA5
9
4
DSR
RX_LED
TRX_LED
BC_SUSP_N
EE_SCL
GPA6
10
5
DCD
VBUS_DET
BC_DET
TXEN
GPA7
6
2
RI (WAKEUP)
GPB0
22
15
GPIO Input Pin
TX_LED
CLK_OUT
GPB1
23
16
GPIO Input Pin
RX_LED
TRX_LED
GPB2
14
9
GPIO Input Pin
VBUS_DET
EE_SDA
GPB3
13
8
GPIO Input Pin
USB_CFG
EE_SCL
GPB4
24
17
GPIO Input Pin
CLK_OUT
BC_SUSP_N
GPB5
25
18
GPIO Input Pin
BC_DET
GPB6
12
7
SUSP_N
USB_CFG
GPB7
8
3
TXEN Pin
GPIO Input
GPIO
Configurable Options (using OTPROM Tool)
WAKEUP
CLK_OUT
Table 7-8: GPIO Multi-Function Option Descriptions
SSOP28
UQFN24
GPIO Pins
GPIO Pins
GPA2 (Pin 3)
GPA2 (Pin 3)
GPA4 (Pin 2)
GPA4 (Pin 2)
GPB0 (Pin 22)
GPB0 (Pin 22)
GPA3 (Pin 11)
GPA3 (Pin 11)
GPA5 (Pin 9)
GPA5 (Pin 9)
GPB1 (Pin 23)
GPB1 (Pin 23)
GPIO
Function
TX_LED
RX_LED
Release: Apr. 27, 20
Type
Description
Output
Serial Port: TXD Access LED.
Output
Serial Port: RXD Access LED.
- 17 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
TRX_LED
VBUS_DET
USB_CFG
TXEN
SUSP_N
WAKEUP
BC_DET
BC_SUSP_N
CLK_OUT
EE_SDA
EE_SCL
GPA3 (Pin 11)
GPA3 (Pin 11)
GPA5 (Pin 9)
GPA5 (Pin 9)
GPB1 (Pin 23)
GPB1 (Pin 23)
GPA3 (Pin 11)
GPA3 (Pin 11)
GPA6 (Pin 10)
GPA6 (Pin 10)
GPB2 (Pin 14)
GPB2 (Pin 14)
GPA2 (Pin 3)
GPA2 (Pin 3)
GPA4 (Pin 2)
GPA4 (Pin 2)
GPB3 (Pin 13)
GPB3 (Pin 13)
GPB6 (Pin 12)
GPB6 (Pin 12)
GPA2 (Pin 3)
GPA2 (Pin 3)
GPA6 (Pin 10)
GPA6 (Pin 10)
GPB7 (Pin 8)
GPB7 (Pin 8)
Output
Input
When this pin is set to VBUS_DET mode,
the device will not attach to USB until
VBUS_DET input pin goes to high level.
There must be only one pin configured as
VBUS_DET pin.
Output
When device is attached to USB port and
configured by USB host, this USB_CFG pin
will output to high level. This pin can be
used to enable system function after USB is
configured.
Output
Transmit Data Enable Pin can be used to
enable RS485/RS422 transceiver when
data is being transmitted.
Output
Active low Shutdown control pin. This pin
has two options to choose. One is to
indicate chip suspend state by USB bus
state. The other option (factory default) is to
indicate chip un-configured state and chip
suspend state. These two options can be
configured in OTPROM or EEPROM.
Input
The remote wakeup function is to wake up
chip from suspended state when this pin
toggle in suspend state. There must be only
one pin configured as WAKEUP pin. The
factory default is RI (GPA7) pin.
Output
Battery Charge Detect pin. This active high
pin indicates BC 1.2 DCP/CDP is detected.
Output
This pin has same function as SUSP_N
except this pin will be forced inactive in chip
suspend state when BC 1.2 DCP/CDP is
detected.
GPA2 (Pin 3)
GPA2 (Pin 3)
GPB6 (Pin 12)
GPB6 (Pin 12)
GPA3 (Pin 11)
GPA3 (Pin 11)
GPA7 (Pin 6)
GPA7 (Pin 2)
GPB6 (Pin 12)
GPB6 (Pin 12)
GPA3 (Pin 11)
GPA3 (Pin 11)
GPA6 (Pin 10)
GPA6 (Pin 10)
GPB5 (Pin 25)
GPB5 (Pin 25)
GPA5 (Pin 9)
GPA5 (Pin 9)
GPB4 (Pin 24)
GPB4 (Pin 24)
GPA2 (Pin 3)
GPA2 (Pin 3)
GPA4 (Pin 2)
GPA4 (Pin 2)
GPB0 (Pin 22)
GPB0 (Pin 22)
GPB4 (Pin 24)
GPB4 (Pin 24)
GPB6 (Pin 12)
GPB6 (Pin 12)
GPA4 (Pin 2)
GPA4 (Pin 2)
Input/
GPB2 (Pin 14)
GPB2 (Pin 14)
Output
Output
This pin can generate clock output up to
12MHz. Clock rates can be configured in
OTPROM/EEPROM or customized driver.
Note: Only one GPIO pin can be configured
as CLK_OUT function.
GPA5 (Pin 9)
GPA5 (Pin 9)
Input/
GPB3 (Pin 13)
GPB3 (Pin 13)
Output
Release: Apr. 27, 20
Serial Port: TXD and RXD Access LED.
- 18 / 49 -
External I2C EEPROM interface serial data
signal.
External I2C EEPROM interface serial
clock signal.
Rev.1.0.3
Product Data Sheet
PL2303GC
8.
Functional Description
This section details the functional block diagram description of the PL2303GC.
8.1
BC 1.2 Detection
This function is used to detect VBUS power supply capability of USB host port and provides charging control
to battery charging IC. This function is enabled in OTPROM by setting GPIO pin to BC_DET option. This pin
will indicate if BC 1.2 DCP/CDP is detected when device is attached to the USB port. The external battery
charging IC uses the USB_CFG and SUSP_N signal pins to control its charging current support or the
BC_DET signal pin to enable fast charging current mode.
8.2
USB 1.1 FS Transceiver
The USB Transceiver provides the USB full-speed electrical signal requirements and USB physical
interface (DP/DM). This block also includes one precise internal oscillator for PLL. The PLL provides the
clock to other logic functions. This block also includes the internal USB series termination resistors on the
USB data lines and pull-up resistor for the DP signal.
8.3
LDO Regulator
This block is the 5V to 3.3V LDO regulator to power and drive the USB transceiver. It also includes 3.3V
brownout detection output signals that will be used by digital circuit to reset the chip. The LDO 5V to 3.3V
can supply 100mA for chip internal and external components.
8.4
Clock Generator
The clock generator module generates the 48MHz and 12MHz reference clock signals for internal chip
logic. The internal clocks will be stopped while in suspend state.
8.5
USB FS SIE
The USB Full-Speed Serial Interface Engine (SIE) block performs the processing of USB DP/DM signals.
It translates the internal parallel data to serial data and outputs to USB FS transceiver to generate
external USB DP/DM signals timing. It also translates external USB DP/DM signals pass through USB FS
transceiver to parallel data for internal circuit. This block supports USB packet decoding and encoding. It
also generates and check packet CRC, bit stuffing, SYNC and EOP frame signal. The DPLL module will
use the internal 48MHz clock to synchronize external DP/DM transitions to generate 12MHz clock for
USB interface related circuit.
Release: Apr. 27, 20
- 19 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
8.6
Power Management
This module will monitor the USB attachment and DP/DM signals state to create reset state, running state,
suspend state, wakeup state, etc.
8.7
Control Endpoint
The Control Endpoint module handles control endpoint packet transfer protocols such as SETUP packet,
DATA packet and return status packet.
8.8
Bulk Out Endpoint
The Bulk Out Endpoint module handles bulk-out endpoint packet transfer protocols such as DATA packet
and return status packet. It also transfers USB host bulk-out data to chip outbound FIFO.
8.9
Bulk In Endpoint
The Bulk In Endpoint module handles bulk-in endpoint packet transfer protocols such as DATA packet
and return status packet. It also transfers data inside the chip inbound FIFO to USB host through bulk-in
DATA packet.
8.10 Interrupt In Endpoint
The Interrupt In Endpoint module handles interrupt-in endpoint packet transfer protocols such as DATA
packet and return status packet. It transfers interrupt data generated inside the chip to USB host through
interrupt-in DATA packet.
8.11 Command Sequencer
This module handles the USB standard requests and vendor requests. It dispatches control signals to
relative peripheral modules and gather information from peripheral modules. When it received USB
standard request commands, it may check ROM data or data latched from OTP and return them to USB
host. When vendor requests are received, it dispatches to peripherals to set or get something.
8.12 Outbound FIFO
This buffer receives data from Bulk Out Endpoint and provides data to peripheral modules. It handles
read and write pointers and calculate full and empty conditions. There are also near empty threshold
check to notify peripheral module that FIFO is going to empty.
Release: Apr. 27, 20
- 20 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
8.13 Inbound FIFO
This buffer receives data from peripheral modules and provides data to Bulk In Endpoint. It handles read
and write pointers and calculate full and empty conditions. There are also near full threshold check to
notify peripheral module that FIFO is going to full.
8.14 Event Generator
This module provides interrupt data to Interrupt In Endpoint. This module senses interrupt event toggle
from UART peripheral and GPIO module.
8.15 Internal OTPROM
The OTPROM (One-Time Programming Read-Only Memory) is used to store chip function settings, GPIO
pin function setting and USB descriptor related data. A one-time programming user area of the memory is
available to allow customization of settings. The user area of the PL2303GC OTPROM can now be easily
programmed using the Prolific OTPROM software through USB port without any additional voltage
converter requirement. Refer to Section 9.0 for more information on the OTPROM configuration settings.
8.16 Mux/Demux
This module is designed to pass data between FIFO and UART peripheral module.
8.17 Descriptor ROM
This block contains the USB descriptor data for returning to USB host.
8.18 UART Control
The UART Control module handles the data transfer according to RS232 format and interface. Full set
flow control is implemented including RTS/CTS, DTR/DSR and software flow control. Flow control circuit
will check FIFO near full or near empty status to activate flow control signals. This module includes a
precise baud rate generator that can generate baud rates up to 12Mbps. The baud rate is set from USB
command.
8.19 Control Registers
The Control Registers module contains the chip control registers read and set, and initially loads from
OTPROM. USB host will use USB vendor command to read and write control registers to set chip
function.
Release: Apr. 27, 20
- 21 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
8.20 IO Functions
The IO Functions block implements generic GPIO function and many configurable I/O functions such as
TX access LED and RX access LED features, clock output features, and others (see Section 7.4).
8.21 I/O Routing Logic
The PL2303GC has many versatile I/O functions. Each GPIO pin is provided with multiple functions that
can be configured in the OTPROM. This module multiplexes I/O functions to different chip I/O pins. It also
handles I/O pin polarity, open-drain, pull-up/pull-down, and I/O pin drive capability functions.
8.22 I2C EEPROM Controller
The I2C EEPROM Controller provides an optional alternative solution to the OTPROM that allows an
external I2C EEPROM to be attached through GPIO pins 2 and 9 (GPA4/GPA5); or pins 14 and 13
(GPB2/GPB3) for the SDA and SCL interface. Using the PL2303G OTPROM/EEPROM Writer program,
customer can also write the chip function settings, GPIO pin function settings, and USB descriptor related
data to external I2C EEPROM. The advantage of using an external EEPROM is that it can be written
several times. The Prolific OTPROM/EEPROM software works by plugging the device through USB port
without any additional voltage converter requirement. Refer to Section 9.0 for more information on the
OTPROM/EEPROM configuration settings.
Release: Apr. 27, 20
- 22 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
9.
Chip Function Configuration
The default configuration descriptors are stored in the chip internal memory which will be loaded during
power-on reset or USB bus reset whenever OTPROM is empty. Several of the USB and configuration
descriptors could be modified and programmed one-time into the chip’s OTPROM using the PL2303GC
OTPROM/EEPROM Writer utility program. These descriptors include Vendor ID, Product ID, Serial Number,
Product String, UART settings, GPIO configurations, and other configuration descriptors. The PL2303GC
chip also provides an option to use an external I2C EEPROM to write the configurations several times.
9.1
USB Data Configuration
Table 9-1 USB Descriptor Configuration
Descriptors
Default Value
Description
This field allows writing the chip configuration settings
either into the OTPROM or to an external EEPROM.
OTPROM / External
EEPROM
Release: Apr. 27, 20
Use OTPROM – this option will write the new
settings into the chip’s OTPROM. The OTPROM
can only be written once. If the Space box
denotes a 1, it means it can be written.
Enable Ext. EEPROM (GPA5:SCL, GPA4:SDA) –
this option can be used if there is an external I2C
EEPROM attached to pins GPA5 and GPA4 of
PL2303GC. Settings will be written to the external
Use OTPROM
- 23 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
EEPROM and can be written several times.
Enable Ext. EEPROM (GPB3:SCL, GPB2:SDA) –
this option can be used if there is an external I2C
EEPROM attached to pins GPB3 and GPB2 of
PL2303GC. Settings will be written to the external
EEPROM and can be written several times.
NOTE: PL2303GC chip can only allow a one-time
switch from OTPROM to Ext EEPROM or vice-versa.
USB unique Vendor ID of Company or Manufacturer.
This ID is applied and registered from USB-IF.
Vendor ID (VID)
067B (hex)
Refer to this website for applying VID:
http://www.usb.org/developers/vendor/
Product ID (PID)
23A3 (hex)
USB Product ID assigned by Manufacturer.
Release No. (BCD)
0100 (hex)
This field reports the release number of the USB
device chip. This item is not allowed to be modified.
Device Power Mode
Bus Powered (100mA)
This field sets the USB device maximum power that
can be drawn by the device from the USB host. Enter
the value here if it is not 100mA or 500mA. Expressed
in 2 mA units (i.e., 50 = 100 mA).
Max Power
100mA
USB Selective
Suspend
Enable
Manufacturer String
Prolific Technology Inc.
Product String
Serial Number
This field sets the USB device if bus-powered or
self-powered device.
This field enables/disables the USB Selective Suspend
function. When enabled, Windows OS will suspend the
device when idle for few seconds (COM port not open).
USB-Serial Controller
Enable Unique Serial
Number ID
This field contains the product manufacturer string.
This field when entered will be the device string
displayed by Windows and other OS when device is
first detected and before driver is loaded or driver not
installed. After driver is loaded, Windows will show the
product string written inside the driver INF file.
Disable Serial Number – this option will disable
the Serial Number. Operating System will assign
a random serial number for the device.
Enable Unique Serial Number ID – this default
option enables the unique serial number
pre-programmed inside the chip.
Custom Serial Number – this option allows the
customer to set own product serial numbering:
o
Auto SN: allows to add prefix while the
numbers auto increment after each write.
o
Fixed SN: this will write the same number.
Device with serial number enabled allows the device
to be assigned with the same COM port number even
when plug to other USB ports of the same PC.
NOTE: The total string length for the manufacturer + product + serial number string is up to 90 characters.
Release: Apr. 27, 20
- 24 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
9.2
UART Configuration
Table 9-2 UART Startup Configuration
Functions
Default Value
Description
LED Flash
Fast
This option sets the flashing speed of the access LED
when configured using the TX_LED, RX_LED,
TRX_LED GPIO pins. Fast 11.4Hz and slow 2.8Hz.
UART Mode
Full-duplex UART
Full-Duplex UART – this default setting allows
simultaneous transmission of TX and RX lines.
Half-Duplex UART – this option only allows for
one-way transmission at a time. When there is no
data transmission, TXD will be tri-state.
Disable
This allows using the RXD pin as remote wakeup.
The received data from RXD may be wrong while chip
is waking up.
Disable
This option allows setting the software flow control
(Xon/Xoff) during chip initial startup. In general, this
option need not enabled because driver or software
can control this option.
Hardware Flow Control
Disable
This option allows setting the hardware flow control
(RTS/CTS, DTR/DSR, Both) during chip initial
startup. In general, this option need not enabled
because driver or software can control this option.
Buffer Size
Configuration
256(TX) - 768(RX)
Remote Wakeup (RXD)
Software Flow Control
Release: Apr. 27, 20
736(HW) - 384(LW)
This sets the internal buffer size configuration for TX
(downstream) and RX (upstream) as well as the high
and low watermark threshold levels.
- 25 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
9.3
GPIO (GPA) Configuration
Also refer to Section 7.4 for the complete GPIO Multi-Function options description.
Table 9-3 GPIO (GPA Group) Configuration
GPIO Function
Default Value
Default I/O
Description
This field also allows setting the pin as a standard GPIO.
GPA0
TXD
Output
TXD (default)
GPIO (General Purpose I/O)
This field also allows setting the pin as a standard GPIO.
GPA1
RXD
Input
RXD (default)
GPIO (General Purpose I/O)
This field allows setting the pin as a standard GPIO or
any of the following function:
GPA2
RTS
Output
RTS (default)
TX_LED
CLK_OUT (also refer to MISC folder)
SUSP_N (also refer to MISC folder)
USB_CFG
TXEN
GPIO (General Purpose I/O)
1
This field allows setting the pin as a standard GPIO or
any of the following function:
GPA3
Release: Apr. 27, 20
CTS
Input
- 26 / 49 -
CTS (default)
RX_LED
TRX_LED
WAKEUP
Rev.1.0.3
Product Data Sheet
PL2303GC
VBUS_DET (also refer to MISC folder)
BC_DET
GPIO (General Purpose I/O)
This field allows setting the pin as a standard GPIO or
any of the following function:
GPA4
DTR
Output
DTR (default)
TX_LED
CLK_OUT (also refer to MISC folder)
USB_CFG
EE_SDA
GPIO (General Purpose I/O)
1
This field allows setting the pin as a standard GPIO or
any of the following function:
GPA5
DSR
Input
DSR (default)
RX_LED
TRX_LED
BC_SUSP_N
EE_SCL
GPIO (General Purpose I/O)
This field allows setting the pin as a standard GPIO or
any of the following function:
GPA6
DCD
Input
DCD (default)
VBUS_DET (also refer to MISC folder)
BC_DET
TXEN
GPIO (General Purpose I/O)
This field also allows setting the pin as a standard GPIO.
GPA7
RI (Wakeup)
RI (default)
Input
GPIO (General Purpose I/O)
Enable
Open-Drain
Disabled
This field sets the selected I/O pin to open-drain output
mode.
This field enables the selected I/O pin weak pull-up.
Enable-Pull Up
Disabled
NOTE: The weak pull-up resistor is pull-up to VDD_IO.
When enabling pull-up for input pins, the input signal
voltage should not be higher than the VDD_IO voltage.
1
Inverse Polarity
Disabled
Output Driving
Strength
4mA
This field inverts the selected I/O pin input and output
signal polarity.
This field sets the output driving strength of the selected
pin. (4mA up to 8mA) @VDDIO3.3V
Note: Only one GPIO pin can be configured as CLK_OUT function.
Release: Apr. 27, 20
- 27 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
9.4
GPIO (GPB) Configuration
Also refer to Section 7.4 for the complete GPIO Multi-Function options description.
Table 9-4 GPIO (GPB Group) Configuration
GPIO Function
Default Value
Default I/O
Description
This field allows setting the pin as a standard GPIO or
any of the following function:
GPB0
GPIO
Input
GPIO (General Purpose I/O)
TX_LED
CLK_OUT (also refer to MISC folder)
1
This field allows setting the pin as a standard GPIO or
any of the following function:
GPB1
GPIO
Input
GPIO (General Purpose I/O)
RX_LED
TRX_LED
This field allows setting the pin as a standard GPIO or
any of the following function:
GPB2
GPIO
Input
GPIO (General Purpose I/O)
VBUS_DET (also refer to MISC folder)
EE_SDA
This field allows setting the pin as a standard GPIO or
any of the following function:
GPB3
Release: Apr. 27, 20
GPIO
Input
- 28 / 49 -
GPIO (General Purpose I/O)
USB_CFG
EE_SCL
Rev.1.0.3
Product Data Sheet
PL2303GC
This field allows setting the pin as a standard GPIO or
any of the following function:
GPB4
GPB5
GPIO
Input
GPIO
Input
GPIO (General Purpose I/O)
CLK_OUT (also refer to MISC folder)
BC_SUSP_N
1
This field allows setting the pin as a standard GPIO or
any of the following function:
GPIO (General Purpose I/O)
BC_DET
This field allows setting the pin as a standard GPIO or
any of the following function:
GPB6
GPB7
Enable
Open-Drain
SUSP_N
Output
GPIO
Input
Disabled
GPIO (General Purpose I/O)
USB_CFG
WAKEUP
CLK_OUT (also refer to MISC folder)
1
This field allows setting the pin as a standard GPIO or
any of the following function:
GPIO (General Purpose I/O)
TXEN
This field sets the selected I/O pin to open-drain output
mode.
This field enables the selected I/O pin weak pull-up.
Enable-Pull Up
Disabled
NOTE: The weak pull-up resistor is pull-up to VDD_IO.
When enabling pull-up for input pins, the input signal
voltage should not be higher than the VDD_IO voltage.
1
Inverse Polarity
Disabled
Output Driving
Strength
4mA
This field inverts the selected I/O pin input and output
signal polarity.
This field sets the output driving strength of the selected
pin. (4mA up to 8mA) @VDDIO3.3V
Note: Only one GPIO pin can be configured as CLK_OUT function.
Release: Apr. 27, 20
- 29 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
9.5
Miscellaneous (MISC) Configuration
This folder includes other miscellaneous chip configuration options including VBUS_DET, chip I/O suspend
state, SUSP_N, USB chip suspend, and clock output frequency divider options.
Table 9-5 Miscellaneous Configuration
Functions
Default Value
Description
Suspend Mode I/O State
Keep I/O Driving State
This option allows setting the I/O state when chip is in
suspend mode.
SUSP_N Pin
Active when both USB
not configured and
USB suspend
This option allows setting the SUSP_N pin behavior
when USB is not configured and in suspend state.
USB Chip Suspend
Enabled
This option can enable or disable the USB chip to
suspend.
This field sets the output clock divider value.
Output Clock Divider
0xFF
When value is 0, output clock pin will stay at low
state. When value is 0xff, output clock pin will stay at
high state. When other value, output clock rate is
24MHz / (1 + clock divider value).
The default value can be kept as is and let customer
driver or user tool through SDK to dynamic change
the clock divider rate.
Note: Only one GPIO pin can be configured as
CLK_OUT function.
Release: Apr. 27, 20
- 30 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
10. Design Application Examples
This section illustrates conceptual design application examples using the PL2303GC.
10.1 USB Bus Powered Design
The PL2303GC has a built-in 3.3V regulator. USB device power (pin VIN) can be supplied directly from USB
VBUS pin. The capacitor behind the USB connector on VBUS is a defined requirement of USB specification.
If the regulator output VO_33 needs to be maintained at 3.3V, VIN should be larger than 3.6V. It is also
recommended to add capacitor at VO_33 pin, please refer to schematic.
This built-in 3.3V regulator can supply 100mA in addition to providing chip operating power around 10mA. It is
also possible to supply power to external components under the range limit.
PL2303GC
USB connector
VIN
VBUS
Regulator
DD+
VO_33
C1
GND
C2
Figure 10-1 USB Bus Powered Design Example
10.2 Self Powered Design
The PL2303GC can also use external power supply. There are two possible ways to use external power
source. The first is to use system power source to connect to VIN, and the chip’s internal 3.3V regulator will
generate the 3.3V power output VO_33 for chip operations and external components. Below Figure 10-2a
shows this case. The second is to disable the internal regulator where the system should provide the same
3.3V voltage to VIN and VO_33. Under this condition, the chip will use this external 3.3V power as operating
power source. See Figure 10-2b.
For USB self-powered design, it is also recommended to enable the VBUS_DET GPIO input pin function
because the PL2303GC DP pin will be pulled up after power on even if USB is not attached yet. USB
specification states that a DP pull-up means to attach USB. If the VBUS_DET pin function is turned on and
connected to VBUS pin, the chip will only pull-up the DP pin to USB bus when VBUS_DET is active.
Release: Apr. 27, 20
- 31 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
To use self-powered design, USB power mode descriptor in the OTPROM or EEPROM of the PL2303GC
chip should also be programmed to self-powered mode to match this kind of configuration. USB hosts can
read the USB descriptor of the device to know if it is a self-powered device.
Supply 3.3V to 5V
PL2303GC
USB connector
VIN
VBUS
Regulator
DD+
VO_33
GND
VBUS_DET
Figure 10-2a USB Self Powered Design Example 1
Supply 3.3V
PL2303GC
USB connector
VIN
VBUS
Regulator
DD+
VO_33
GND
VBUS_DET
Figure 10-2b USB Self Powered Design Example 2
Release: Apr. 27, 20
- 32 / 49 -
Rev.1.0.3
Product Data Sheet
PL2303GC
10.3 Chip Reset Control
The PL2303GC has an internal power on reset circuit; therefore, external reset control circuit is optional.
External reset control (RESET_N pin) can help system designs to make sure of chip operation start time.
PL2303GC
VIN
Regulator
VO_33
VDD_IO
POR
RESET_N
Reset Gen
Figure 10-3a Chip Reset Control Application
The power ramp-up time shall keep below than 1ms as shown in diagram below.
VIN
2.4V
0V
800us
Figure 10-3b Chip Power Reset Timing Diagram
Release: Apr. 27, 20
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Rev.1.0.3
Product Data Sheet
PL2303GC
10.4 I/O Power Supply to PL2303GC
The PL2303GC supports a wide range of I/O voltage. The simple way to supply IO voltage is to directly
connect VDD_IO to VO_33 pin to provide 3.3V I/O voltage. Add capacitor to VDD_IO can help to reduce I/O
noise. Please refer to schematic for the detailed capacitor value.
PL2303GC
USB connector
VIN
VBUS
Regulator
DVO_33
D+
GND
C1
C2
VDD_IO
Figure 10-4a IO Power Supply
VDD_IO can also be supplied from other power source to provide different I/O voltage. All of the PL2303GC
I/O pins, including UART signals, use the same VDD_IO voltage. The I/O pins does not support mixed I/O
voltages. Unless open-drain option is enabled, the I/O connection between two chips shall use the same
VDD_IO voltage. PL2303GC I/O pin also supports 5V tolerance which allows 5V input signal level in different
VDD_IO voltage. {Note: VDD_IO voltage should not be larger than VIN voltage.}
PL2303GC
VIN
TXD
RX
RXD
TX
Regulator
VO_33
Supply IO
Voltage
VDD_IO
VDD_IO
Figure 10-4b VDD_IO Voltage Supply
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Rev.1.0.3
Product Data Sheet
PL2303GC
10.5 USB to RS232 Cable Design
The most common design application for the PL2303GC is the USB to RS232 converter cable or adapter
shown in the diagram below. This design pairs the PL2303GC with an RS232 transceiver chip (ex. SIPEX
SP213EHCA) to convert the PL2303GC TTL levels serial interface to RS232 level signals. The design below
includes the use of the SUSP_N pin (SHTDN#) to power down the transceiver chip to sleep mode when in
USB suspend mode. The default OTPROM supports this function directly and no need to program the OTP
for special GPIO setting. Below diagram also shows an access LED example on how to make use of GPB0
and GPB1 pins which are configured as TX and RX access LED.
RS232
PL2303GC
Transceiver
VDD_IO
TXD
T1IN
VO_33
RXD
R1OUT
USB connector
VBUS
VIN
D-
DM
D+
DP
RTS_N
T2IN
CTS_N
R2OUT
DTR_N
T3IN
DSR_N
R3OUT
DCD_N
R4OUT
RI_N
RTOUT
GND
C1
GND
SHTDN#
TX_LED/GPB0
VDD_IO
RX_LED/GPB1
VDD_IO
GPB2
GPB3
GPB4
GPB5
SUSP_N
GPB7
Figure 10-5 USB to RS232 Design Example
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Rev.1.0.3
Product Data Sheet
PL2303GC
10.6 USB to RS485/RS422
Another popular application for the PL2303GC is the USB to RS485/422 design. For RS485, the chip is
paired with an RS485 transceiver chip to convert the serial interface of the PL2303GC to RS485 levels.
RS485 transceivers are only enabled when data is being transmitted. Hence, it needs to use the TX_EN
(transmit enable) GPB7 GPIO pin to connect to the RS485 transceiver output enable pin and enable this pin
function using the OTPROM software. This application can also make use of the GPB0 and GPB1 pins
configured as TX and RX access LED.
RS485/RS422
Transceiver
VDD_IO
TXD
DI
VO_33
RXD
RO
RTS_N
RE\
CTS_N
DE
USB connector
VBUS
VIN
D-
DM
D+
DP
DTR_N
DSR_N
GND
DCD_N
C1
RI_N
GND
TX_LED/GPB0
VDD_IO
RX_LED/GPB1
VDD_IO
GPB2
GPB3
GPB4
GPB5
SUSP_N
TX_EN/GPB7
Figure 10-6 USB to RS485/422 Design Example
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Rev.1.0.3
Product Data Sheet
PL2303GC
10.7 Battery Charging Support
The PL2303GC supports USB battery charging specification (BC1.2) where in battery charging controller can
use signals from PL2303GC to control the charging current. An example of charging control concept is shown
in below diagram.
LTC4053
USB connector
VBUS
CHRG#
ACPR#
D-
VCC
D+
FAULT#
SHDN#
TIMER
PROG
GND
BAT
GND
NTC
BC_DET/GPB5
USB_CFG/GPB6
BC_SUSP_N/GPB4
VIN
PL2303GC
Figure 10-7a Battery Charging Design Example #1
This concept diagram uses the GPB5 GPIO pin configured as BC_DET (battery charge detect pin) signal and
this pin need to set to inverse polarity and open-drain mode. GPB6 GPIO pin is configured as USB_CFG and
is also set to inverse polarity and open-drain mode. GPB4 GPIO pin is configured as BC_SUSP_N function
and connected to shutdown signal of charging controller. All above signals can achieve charging conditions
as below table.
Charging Condition
Charging Current (max)
BC_SUSP_N
USB_CFG
BC_DET
Suspend
2.5mA
0
x
x
Un-configured
100mA
1
1
1
Operation
500mA
1
0
1
Fast Charging
1500mA
1
1
0
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Rev.1.0.3
Product Data Sheet
PL2303GC
Below is another example of charging controller support concept.
MAX8856
USB connector
VBUS
DD+
GND
BAT
SYS
BAT
SYS
IN
SETI
VL
GND
THM
EN1#
CHG#
EN2#
POK#
GATE
I=1A, R=16.8k
USB_CFG/GPB3
SUSP_N/GPB6
VIN
PL2303GC
Figure 10-7b Battery Charging Design Example #2
The above concept diagram uses GPB3 pin as USB_CFG and set to normal polarity and push-pull I/O mode
as default. GPB6 pin is configured as SUSP_N and set to inverse polarity and push-pull IO mode. The
SUSP_N option is also set active during USB bus suspend state only, and not when USB is not configured.
This concept diagram can achieve charging conditions as below table.
Charging Condition
Charging Current (max)
SUSP_N
USB_CFG
Suspend
2.5mA
1
1
Un-configured
100mA
0
0
Operation
500mA
0
1
Fast Charging
1000mA
1
0
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Rev.1.0.3
Product Data Sheet
PL2303GC
10.8 External I2C EEPROM Support
The PL2303GC can also support an external I2C EEPROM to override the OTPROM settings. To use an
external EEPROM, it needs to program the OTPROM to enable the external I2C EEPROM support. There
are two options, one is to use the GPB2 pin as I2C SDA and the GPB3 pin as I2C SCL; the other option is to
use GPA4(DTR_N) pin as I2C SDA and GPA5(DSR_N) pin as I2C SCL.
1k
1k
24C02
VDD
USB connector
VDD_IO
GPA4/GPB2
SDA-
VO_33
GPA5/GPB3
SCL
GND
VBUS
VIN
D-
DM
D+
DP
GND
C1
GND
Figure 10-8 External I2C EEPROM Design Example
There is signature field in external EEPROM space. When this field content is valid, the PL2303GC will load
the external EEPROM contents and override the settings defined in the OTPROM. Detailed information can
be checked with OTPROM and EEPROM software programming tool. The supported external I2C EEPROM
size is 256 bytes.
Release: Apr. 27, 20
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Rev.1.0.3
Product Data Sheet
PL2303GC
11. DC & Temperature Characteristics
11.1 Absolute Maximum Ratings
Table 11-1 Absolute Maximum Ratings
Items
Ratings
Power Supply Voltage – VIN
-0.3 to 6.0 V
Input Voltage of VDD_IO
-0.3 to VIN+0.3 V
Input Voltage of I/O pins with 5V Tolerance I/O
-0.3 to 6.0 V
Storage Temperature
-40 to 150 oC
Thermal Resistance (θjc)
19 oC/W (UQFN24)
Thermal Resistance (θjc)
31 oC/W (SSOP28)
Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. These are stress rating only, and functional
operation should be restricted to within the conditions. Exposure to absolute maximum rating conditions for extended periods may affect
the device’s reliability.
11.2 DC Characteristics
11.2.1 Operating Voltage and Suspend Current
Table 11-2a Operating Voltage and Suspend Current
Parameter
Power Supply Voltage Range
Power Supply for I/O Pins
Output Voltage of Regulator
Operating
Current(1) (Power Consumption)
Suspend Current
Symbol
Min
Typ
Max
Unit
VIN
2.8
5
5.5
V
VDD_IO
1.8
3.3
VIN+0.3
V
VO_33
2.97
3.3
3.63
V
IDD
-
9.5
15
mA
ISUS
-
250
450
A
Note: (1) – No device connected.
11.2.2 I/O Pins
Table 11-2b I/O Pins
Parameter
Symbol
Min
Typ
Max
Unit
Low
VIL
--
--
0.4
V
High
VIH
0.7* VDD_IO
--
--
V
Low
VOL
--
--
0.4
V
High
VOH
0.7*VDD_IO
--
--
V
Input Voltage (CMOS)
Output Voltage
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Rev.1.0.3
Product Data Sheet
PL2303GC
11.3 Temperature Characteristics
Table 11-3 Temperature Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Operating Temperature (ambient)
--
-40
--
85
o
Junction Operation Temperature
TJ
-40
25
125
o
C
C
11.4 Baud Rate Characteristics
Table 11-4 Baud Rate Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Baud rate @ VDD_IO = 5V
--
1
--
12M
bps
Baud rate @ VDD_IO = 3.3V
--
1
--
12M
bps
Baud rate @ VDD_IO = 1.8V
--
1
--
6M
bps
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Rev.1.0.3
Product Data Sheet
PL2303GC
12. Outline Diagram
12.1 Chip Marking information
Figure 12-1 Chip Part Number Information (SSOP)
Table 12-2 Chip Marking Information
Line
Marking
First Line
PL2303GC
Description
Chip Product Name
G
Green packing material
Second Line
YY
Last two digits of the manufacturing year
(GYYWWXX)
WW
Week number of the manufacturing year
XX
Chip Version
Third Line
XXXXXXXXX
Manufacturing LOT code
Example: “G19361A” – means Green packing + Year 2019 + Week no. 36 + 1A chip version.
12.2 SSOP28 Package
Table 12-1 Package Dimension
Symbol
Millimeter
Min
Nom
Inch
Max
Min
0.38
0.009
Nom
Max
b
0.22
0.015
E
7.40
7.80
8.20
0.291
0.307
0.323
E1
5.00
5.30
5.60
0.197
0.209
0.220
L
0.55
0.75
0.95
0.021
0.030
0.037
R1
0.09
D
9.9
0.402
0.413
0.004
10.2
A
10.5
0.390
2.0
0.079
e
0.65
0.0256
L1
1.25
0.050
A1
0.05
A2
1.65
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0.020
1.75
1.85
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0.065
0.069
0.073
Rev.1.0.3
Product Data Sheet
PL2303GC
Figure 12-1 PL2303GC Outline Diagram (SSOP28)
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Rev.1.0.3
Product Data Sheet
PL2303GC
12.3 UQFN24 Package
Figure 12-2 PL2303GC Outline Diagram (UQFN24) 4 x 4 mm
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Rev.1.0.3
Product Data Sheet
PL2303GC
13. Packing Information
13.1 Carrier Tape (SSOP-28)
Figure 13-1a SSOP28 Carrier Tape
Notes:
10 sprocket hole pitch cumulative tolerance 0.2
Camber not to exceed 1mm in 100mm.
Material: Black Polystyrene.
Ao and Bo measured on a plane 0.3mm above the bottom of the pocket.
Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier.
Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
IC quantity per one reel: 2,000 pieces (MOQ)
Figure 13-1b IC Reel Placements
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Rev.1.0.3
Product Data Sheet
PL2303GC
13.2 Carrier Tape (UQFN24)
Figure 13-2 UQFN24 Carrier Tape
Release: Apr. 27, 20
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Rev.1.0.3
Product Data Sheet
PL2303GC
13.3 Reel Dimension
Figure 13-3 Reel Dimension
Table 13-1 Reel Part Number Information
Package
Part Number
Normal Hub
W1 +0.3mm
Width
-0.2mm
W2 Max
UQFN24
RD33008SW-T + RD33004SW-T
12mm
12.8mm
18.2mm
SSOP28
RD33008SW-T + RD33008SW-T
16mm
16.8mm
22.2mm
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Rev.1.0.3
Product Data Sheet
PL2303GC
13.4 Tube Packing
Figure 13-4 Tube Packing Dimension
Release: Apr. 27, 20
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Rev.1.0.3
Product Data Sheet
PL2303GC
Disclaimer
All the information in this document is subject to change without prior notice. Prolific Technology Inc. does not
make any representations or any warranties (implied or otherwise) regarding the accuracy and completeness
of this document and shall in no event be liable for any loss of profit or any other commercial damage,
including but not limited to special, incidental, consequential, or other damages.
Trademarks
The Prolific logo is a registered trademark of Prolific Technology Inc. All brand names and product names
used in this document are trademarks or registered trademarks of their respective holders.
Copyrights
Copyright © 2018 – 2020 Prolific Technology Inc. All rights reserved.
No part of this document may be reproduced or transmitted in any form by any means without the express
written permission of Prolific Technology Inc.
Release: Apr. 27, 20
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Rev.1.0.3
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