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LPDDR4X SDRAM Datasheet
Preliminary Version 0.4
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Feb. 3, 2020
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ChangXin Memory Technologies, Inc.
ChangXin Memory Technologies, Inc. _ Confidential
DISCLAIMER
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The information presented in this document is for reference purposes only and may contain
inaccuracies, omissions and errors. The information contained herein is subject to change or
rendered obsolete without notice, including but not limited to product and roadmap changes,
component changes, new model and/or product releases, firmware upgrades, or the like. This
document supersedes and replaces all information supplied prior to the publication hereof. Any
information set forth in this document shall not be replied on if the product described therein is
obtained from any unauthorized distributor or other source not authorized by ChangXin Memory
Technologies, Inc. (hereinafter referred to as “CXMT”).
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CXMT assumes no obligation to update, correct or revise this information. CXMT reserves
the right to update, correct or revise this information without notice; in addition, CXMT has no
obligation to notify any party of such updates, corrections and revisions.
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This document and all information discussed herein remain the sole and exclusive property
of CXMT. No license of any patent, copyright, mask work, trademark or any other intellectual
property right is granted by one party to the other party under this document, by implication,
estoppel or otherwise.
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CXMT MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE
CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES,
ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION.
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CXMT SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR
FITNESS FOR ANY PARTICULAR PURPOSE. ALL SEMICONDUCTOR PRODUCTS HAVE
INHERENT FAILURES RATES AND LIMITED USEFUL LIVES. CUSTOMERS ARE SOLEY
RESPONSIBLE FOR DETERMINING WHETHER THE CXMT PRODUCT IS SUITABLE AND FIT
FOR THE CUSTOMER’S SYTTEM, APPLICATION OR PRODUCT. IN NO EVENT SHALL CXMT
BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL OR OTHER CONSEQUENTIAL DAMAGES
ARISING FROM THE USE OF ANY INFORMAITON CONTAINED HEREIN, EVEN IF CXMT HAS
EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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CONFIDENTIALITY OBLIGATION
This is to remind you of your continuing confidentiality obligation as set forth in the NonDisclosure Agreement or the like, executed between you and CXMT prior to this meeting and/or
visit CXMT and/or access any CXMT information by other means, directly or indirectly, even if it
appears to be pseudonymous or anonymous. CXMT reserves the right to pursue any adequate
legal action, including injunctive relief, in the case of any violations.
ChangXin Memory Technologies, Inc. _ Confidential
Revision History
0.1
Nov. 9, 2018
Initial release
0.2
Oct. 9, 2019
Update ordering information
0.3
Nov. 9, 2019
Update ordering information
0.4
Feb. 3, 2020
Update preliminary IDD
Remark
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Description
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Revision No.
ChangXin Memory Technologies, Inc. _ Confidential
Contents
1. Core Specifications�������������������������������������������������������������������������������������������������������������������������7
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1.1 Ordering Options����������������������������������������������������������������������������������������������������������������������8
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1.2 Part Number Decoding������������������������������������������������������������������������������������������������������������8
1.3 Address Table���������������������������������������������������������������������������������������������������������������������������8
2. Physical Specifications������������������������������������������������������������������������������������������������������������������9
2.1 200-Ball x32 Discrete Package Dimension������������������������������������������������������������������������� 10
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2.2 x32 Discrete Package Ballout�����������������������������������������������������������������������������������������������11
2.3 Block Diagram����������������������������������������������������������������������������������������������������������������������� 12
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2.4 Pad Definition ����������������������������������������������������������������������������������������������������������������������� 15
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3. Absolute Maximum DC Ratings������������������������������������������������������������������������������������������������� 17
4. AC and DC Operating Conditions��������������������������������������������������������������������������������������������� 19
4.1 Recommended DC Operating Conditions for Low Voltage������������������������������������������������ 20
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4.2 Input Leakage Current���������������������������������������������������������������������������������������������������������� 21
4.3 Input/Output Leakage Current���������������������������������������������������������������������������������������������� 21
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4.4 Operating Temperature Range��������������������������������������������������������������������������������������������� 21
4.5 Single Ended Output Slew Rate������������������������������������������������������������������������������������������� 22
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4.6 Differential Output Slew Rate����������������������������������������������������������������������������������������������� 24
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5. AC and DC Input/Output Measurement Levels����������������������������������������������������������������������� 25
5.1 1.1V High Speed LVCMOS (HS_LLVCMOS)���������������������������������������������������������������������� 26
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5.1.1 Standard Specifications������������������������������������������������������������������������������������������������ 26
5.1.2 DC Electrical Characteristics��������������������������������������������������������������������������������������� 26
5.1.3 AC Overshoot and Undershoot������������������������������������������������������������������������������������ 28
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5.2 Differential Input Voltage������������������������������������������������������������������������������������������������������� 28
5.2.1 Differential Input Voltage for Clock������������������������������������������������������������������������������ 28
5.2.2 Peak Voltage Calculation Method������������������������������������������������������������������������������� 30
5.3 Single-Ended Input Voltage for Clock���������������������������������������������������������������������������������� 30
ChangXin Memory Technologies, Inc. _ Confidential
5.4 AC/DC Input level for ODT Input������������������������������������������������������������������������������������������ 41
5.5 Overshoot and Undershoot for LVSTL��������������������������������������������������������������������������������� 42
5.6 Driver Output Timing Reference Load��������������������������������������������������������������������������������� 42
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5.7 LVSTL(Low Voltage Swing Terminated Logic) IO System������������������������������������������������� 44
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6. Input/Output Capacitance����������������������������������������������������������������������������������������������������������� 46
7. IDD Test Conditions and Specifications���������������������������������������������������������������������������������� 47
7.1 IDD Measurement Conditions���������������������������������������������������������������������������������������������� 48
7.2 IDD Specifications����������������������������������������������������������������������������������������������������������������� 54
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7.3 LPDDR4X IDD Parameters - Single Die����������������������������������������������������������������������������� 57
7.4 LPDDR4X IDD6 Parameters - Single Die��������������������������������������������������������������������������� 59
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8. Electrical Characteristics and AC Timing�������������������������������������������������������������������������������� 60
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8.1 Clock Specification���������������������������������������������������������������������������������������������������������������� 60
8.1.1 Definition for tCK(avg) and nCK���������������������������������������������������������������������������������� 60
8.1.2 Definition for tCK(abs)�������������������������������������������������������������������������������������������������� 60
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8.2 Clock Timing�������������������������������������������������������������������������������������������������������������������������� 62
8.3 Temperature Derating for AC Timing����������������������������������������������������������������������������������� 62
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8.4 CA Rx Voltage and Timing���������������������������������������������������������������������������������������������������� 63
8.5 DRAM Data Timing���������������������������������������������������������������������������������������������������������������� 67
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8.6 DQ Rx Voltage and Timing��������������������������������������������������������������������������������������������������� 69
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9. AC Timing Parameters ��������������������������������������������������������������������������������������������������������������� 74
9.1 Core AC Timing��������������������������������������������������������������������������������������������������������������������� 75
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9.2 Read AC Timing��������������������������������������������������������������������������������������������������������������������� 76
9.3 tDQSCK Timing �������������������������������������������������������������������������������������������������������������������� 77
9.4 Write AC Timing��������������������������������������������������������������������������������������������������������������������� 78
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9.5 Self Refresh Timing �������������������������������������������������������������������������������������������������������������� 78
9.6 Mode Register Read/Write AC Timing��������������������������������������������������������������������������������� 79
9.7 VRCG Enable/Disable Timing���������������������������������������������������������������������������������������������� 79
9.8 Command Bus Training AC Timing ������������������������������������������������������������������������������������� 80
ChangXin Memory Technologies, Inc. _ Confidential
9.9
Frequency Set Point Timing������������������������������������������������������������������������������������������������ 84
9.10 Write Leveling Timing ��������������������������������������������������������������������������������������������������������� 85
9.11 MPC [Write FIFO] AC Timing���������������������������������������������������������������������������������������������� 85
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9.12 DQS Interval Oscillator AC Timing������������������������������������������������������������������������������������� 86
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9.13 Read Preamble Training Timing ���������������������������������������������������������������������������������������� 86
9.14 ZQ Calibration Timing��������������������������������������������������������������������������������������������������������� 86
9.15 ODT CA AC Timing�������������������������������������������������������������������������������������������������������������� 86
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9.16 Power-Down AC Timing������������������������������������������������������������������������������������������������������ 87
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
1. Core Specifications
Through this section you will read contents as below:
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Ordering Options on Page 8
Part Number Decoding on Page 8
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Address Table on Page 8
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
1.1 Ordering Options
Table 1-1 LPDDR4X Device Ordering Information
Density
Organization
Data Rate
Package
CXDB3ABAM-MK
CXDB4ABAM-MK
CXDBBCCAM-MK
CXDB5CCAM-MK
1GB
2GB
3GB
4GB
2CH x32
2CH x32
2CH x32
2CH x32
3733 Mbps
3733 Mbps
3733 Mbps
3733 Mbps
200 Ball Discrete
200 Ball Discrete
200 Ball Discrete
200 Ball Discrete
CX
D
4
B
A
B
A
M
M
K
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Company
CX: Chang Xin Memory
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1.2 Part Number Decoding
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Product Family
D: DRAM
Product Type
B: LPDDR4X
Operating Temp.
M: Mobile Temp.(-25 °C~85 °C)
Product Version
M: 1st version
Voltage
A: VDD1/VDD2/VDDQ: 1.8V/1.1V/1.1V & 0.6V
Config IO/CH/CS
B: x32,2CH,1CS
C: x32,2CH,2CS
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Product Density
3: 8Gb
4: 16Gb
B: 24Gb
5: 32Gb
Package Type
A: 200ball FBGA 10x15 DDP
C: 200ball FBGA 10x15 QDP
Speed Type
K: 3733 Mbps
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1.3 Address Table
Table 1-2 Die Addressing Table
256Mb x16
512Mb x16
Bank Address
BA0~BA2
BA0~BA2
Row Address
A0~A14
A0~A15
Column Address
A0~A9
A0~A9
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Die Configuration
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
2. Physical Specifications
This chapter will introduce the 200-ball discrete package dimension, ballout assignment and pad
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definition.
• 200-Ball x32 Discrete Package Dimension on Page 10
• x32 Discrete Package Ballout on Page 11
• Block Diagram on Page 12
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• Pad Definition on Page 15
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
2.1 200-Ball x32 Discrete Package Dimension
Units: Millimeters
Package Overview
Seating Plane
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0.08 C
200* 0.31 ± 0.05 Post Reflow
( 0.28 SMD Ball Pads)
11
10
9
8
5
4
3
2
A1 INDEX Mark
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0.22 ± 0.05
A
B
C
D
E
F
G
H
J
K
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13.65
15 ± 0.1
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V
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0.65 TYP
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AB
0.8 TYP
A
8.8
B
10 ± 0.1
Bottom View
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A1 INDEX Mark
0.1 M C A B
0.9 ± 0.1
Top View
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Figure 2-1 200-Ball x32 Discrete FBGA Package Dimension
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
2.2 x32 Discrete Package Ballout
1
2
3
4
5
DNU
DNU
VSS
VDD2
ZQ0
ZQ1
DQ7_A
VDDQ
VDDQ DQ15_A VDDQ
A
6 7
8
9
VDD2
10
11
12
VSS
DNU
DNU
DQ8_A
DNU
B
DQ0_A VDDQ
VSS
DQ1_A DMI0_A DQ6_A
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DNU
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DQ14_A DMI1_A DQ9_A
VSS
VSS
VDDQ
VDDQ
DQ2_A DQS0_c_A DQ5_A
VSS
VSS
VDDQ
DQ4_A
VDD2
VDD2
DQ12_A VDDQ
VDD1
VSS
VSS
VDD1
VSS
ZQ2
VSS
CS0_A
VDD2
VDD2
CA2_A
CA3_A
CA4_A
VDD2
D
VSS DQS0_t_A
VDDQ
VSS
VSS DQS1_t_A
VSS
E
VSS
DQ3_A
VDD2
CA0_A
CS1_A
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H
J
VSS
DQ11_A VDD1
G
VSS ODTCA_A VSS
VDDQ
DQ13_ADQS1_c_A DQ10_A
F
VDD1
VSS
VSS
CA1_A
VSS
VDD2
VSS
VDD2
VDD2
VSS
VDD2
VSS
CA1_B
VSS
CKE0_B CKE1_B
VDD2
CA0_B
CS1_B
CS0_B
VDD2
VDD2
CA2_B
VSS
VDD1
VSS
VSS
VDD1
VDDQ
DQ4_B
VDD2
VDD2
DQ12_B VDDQ DQ11_B VDD1
DQ2_B DQS0_c_B DQ5_B
VSS
VSS
DQ13_BDQS1_c_B DQ10_B
VSS DQS0_t_B VSS
VDDQ
VDDQ
DQ1_B DMI0_B DQ6_B
VSS
VSS
CKE0_A CKE1_A
CK_t_A CK_c_A
N
VSS
P
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DQ3_B
VDD1
V
VSS
W
VSS
VDD2
VSS
CA5_B
VSS
CA3_B
CA4_B
VDD2
CS2_B
CKE2_A
CKE2_B
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VDD2
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VDDQ
VSS
VSS
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VSS ODTCA_B
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CA5_A
VDD2
CS2_A
VSS
VSS
VSS
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VSS
CK_t_B CK_c_B
VSS
VDD2
VSS RESET_n
DQS1_t_B VSS
VSS
VSS
VDDQ
Y
VSS
DQ14_B DMI1_B DQ9_B
VSS
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AA
DNU
DQ0_B
VDDQ
DQ7_B
VDDQ
VDDQ DQ15_B VDDQ
DQ8_B
DNU
DNU
VSS
VDD2
VSS
VSS
VDD2
DNU
DNU
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AB
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DNU
VSS
Figure 2-2 x32 Discrete Package Ballout
Note:
1 0.8mm pitch (X-axis), 0.65mm pitch (Y-axis), 22 rows using MO-311 0.80mm Pitch
2 Top View, A1 in top left corner. CS1_A/B, CE1_A/B, ZQ1 is floating for 2GB package.
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3 ODT(ca)_[x] balls are wired to ODT(ca)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if
present) are disabled in the package.
4 ZQ2, CKE2_A, CKE2_B, CS2_A, and CS2_B balls are reserved for 3-rank package. For 1-rank and 2-rank
package those balls are NC.
5 Die pad VSS and VSSQ signals are combined to VSS package balls.
6 Package requires dual channel die or functional equivalent of single channel die-stack.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
2.3 Block Diagram
VDD1 VDD2 Vss VDDQ
VDDQ
RZQ
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ZQ0
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CS0_B
CS0_A
CKE0_B
CKE0_A
Channel A
Die0
DMI[1:0]_A
DQ[15:0]_A
DQS[1:0]_t_A
DQS[1:0]_c_A
Channel B
Die1
4G bit
4G bit
ODT_CA
ODT_CA
DMI[1:0]_B
DQ[15:0]_B
DQS[1:0]_t_B
DQS[1:0]_c_B
ODT_CA_B
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ODT_CA_A
CK_c_B
CK_t_B
CA[5:0]_B
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CK_c_A
CK_t_A
CA[5:0]_A
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Figure 2-3 Dual-Die, Dual-Channel, Single-Rank Package Block Diagram (1GB x32 I/O)
VDD1 VDD2 Vss VDDQ
CKE0_A
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CK_c_A
CK_t_A
CA[5:0]_A
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DMI[1:0]_A
DQ[15:0]_A
DQS[1:0]_t_A
DQS[1:0]_c_A
CS0_B
CKE0_B
Channel A
Die0
Channel B
Die1
8G bit
8G bit
ODT_CA
ODT_CA
C
ODT_CA_A
ZQ0
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CS0_A
RZQ
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Reset_n
VDDQ
CK_c_B
CK_t_B
CA[5:0]_B
DMI[1:0]_B
DQ[15:0]_B
DQS[1:0]_t_B
DQS[1:0]_c_B
ODT_CA_B
Figure 2-4 Dual-Die, Dual-Channel, Single-Rank Package Block Diagram (2GB x32 I/O)
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
VDD1 VDD2 Vss VDDQ
VDDQ
RZQ
CS0_B
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CS0_A
l
ZQ0
Reset_n
CKE0_B
CKE0_A
Channel A
Die0
8G bit
DMI[1:0]_A
DQ[15:0]_A
DQS[1:0]_t_A
DQS[1:0]_c_A
Channel B
Die1
8G bit
ODT_CA
ODT_CA_A
CK_c_B
CK_t_B
CA[5:0]_B
ODT_CA
DMI[1:0]_B
DQ[15:0]_B
DQS[1:0]_t_B
DQS[1:0]_c_B
ODT_CA_B
on
CK_c_A
CK_t_A
CA[5:0]_A
VDDQ
RZQ
C
ZQ1
CS1_A
Channel B
Die3
4G bit
ge
d
Channel A
Die2
4G bit
ODT_CA
ODT_CA
VSS
ile
VSS
CS1_B
CKE1_B
an
d
CKE1_A
C
XM
T
Pr
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Figure 2-5 Quad-Die, Dual-Channel, Dual-Rank Package Block Diagram (3GB x32 I/O)
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
VDD1 VDD2 Vss VDDQ
VDDQ
RZQ
ZQ0
CS0_B
CS0_A
CKE0_B
CK_c_A
CK_t_A
CA[5:0]_A
Channel A
Die0
8G bit
DMI[1:0]_A
DQ[15:0]_A
DQS[1:0]_t_A
DQS[1:0]_c_A
CK_c_B
CK_t_B
CA[5:0]_B
Channel B
Die1
8G bit
ODT_CA
ODT_CA_A
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CKE0_A
l
Reset_n
DMI[1:0]_B
DQ[15:0]_B
DQS[1:0]_t_B
DQS[1:0]_c_B
ODT_CA_B
ODT_CA
VDDQ
RZQ
on
ZQ1
CS1_B
C
CS1_A
CKE1_A
Channel B
Die3
8G bit
an
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Channel A
Die2
8G bit
ge
d
ODT_CA
VSS
CKE1_B
ODT_CA
VSS
C
XM
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ile
Figure 2-6 Quad-Die, Dual-Channel, Dual-Rank Package Block Diagram (4GB x32 I/O)
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
2.4 Pad Definition
“_A” and “_B” indicate DRAM channels. “_A” pads are present in all devices while “_B” pads are
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present in dual channel SDRAM devices only.
LPDDR4X pad definitions are the same as LPDDR4, except ODT_CA pins as described in Table 1-3.
Table 2-3 Pad Definition
Description
Input
Clock: CK_t and CK_c are differential clock inputs. All address, command, and control input signals are sampled on the crossing of the
positive edge of CK_t and the negative edge of CK_c. AC timings for
CA parameters are referenced to CK. Each channel (A & B) has its
own clock pair.
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock circuits, input buffers, and output drivers. Power-saving
modes are entered and exited via CKE transitions. CKE is part of the
command code. Each channel (A & B) has its own CKE signal.
Input
Command/Address Inputs: CA signals provide the Command and
Address inputs according to the Command Truth Table. Each channel (A&B) has its own CA signals.
I/O
Data Input/Output: Bi-direction data bus.
I/O
Data Strobe: DQS_t and DQS_c are bi-directional differential output
clock signals used to strobe data during a READ or WRITE. The Data
Strobe is generated by the DRAM for a READ and is edge-aligned
with Data. The Data Strobe is generated by the Memory Controller
for a WRITE and must arrive prior to Data. Each byte of data has
a Data Strobe signal pair. Each channel (A & B) has its own DQS
strobes.
I/O
Data Mask Inversion: DMI is a bi-directional signal which is driven
HIGH when the data on the data bus is inverted, or driven LOW when
the data is in its normal state. Data Inversion can be disabled via
a mode register setting. Each byte of data has a DMI signal. Each
channel (A & B) has its own DMI signals. This signal is also used
along with the DQ signals to provide write data masking information
to the DRAM. The DMI pin function - Data Inversion or Data mask depends on Mode Register setting.
Pr
iv
DQ[15:0]_A, DQ[15:0]_B
Chip Select: CS is part of the command code. Each channel (A & B)
has its own CS signal.
ile
CS_A, CS_B
CA[5:0]_A, CA[5:0]_B
Input
ge
d
CKE_A, CKE_B
C
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T
DQS[1:0]_t_A,DQS[1:0]_c_A,
DQS[1:0]_t_B, DQS[1:0]_c_B
DMI[1:0]_A, DMI[1:0]_B
an
d
C
CK_t_A, CK_c_A,
CK_t_B, CK_c_B
Type
on
Symbol
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Symbol
Type
ZQ
Reference
VDDQ,VDD1,VDD2
Supply
VSS, VSSQ
GND
Ground Reference: Power supply ground reference
RESET_n
Input
RESET: When asserted LOW, the RESET_n signal resets all channels of the die. There is one RESET_n pad per die.
Input
CA ODT Control:
LPDDR4: The ODT_CA pin is used in conjunction with the Mode
Register to turn on/off the On-Die-Termination for CA pins.
LPDDR4X:The ODT_CA pin is ignored by LPDDR4X devices. ODT_
CS/CA/CK Function is fully controlled through MR11 and MR22. The
ODT_CA pin shall be connected to either VDD2 or Vss.
Calibration Reference: Used to calibrate the output drive strength
and the termination resistance. There is one ZQ pin per die. The ZQ
pin shall be connected to VDDQ through a 240Ω ± 1% resistor.
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Power Supplies: Isolated on the die for improved noise immunity.
C
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C
on
ODT_CA_A ,ODT_CA_B
Description
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
3. Absolute Maximum DC Ratings
This chapter specifies absolute maximum DC ratings. Stresses greater than those listed may
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cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to
C
XM
T
Pr
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ge
d
an
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C
on
absolute maximum rating conditions for extended periods may affect reliability.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 3-4 Absolute Maximum DC Ratings
VDD1 supply voltage relative to VSS
VDD2 supply voltage relative to VSS1
VDDQ supply voltage relative to VSSQ1
Voltage on any ball except VDD1 relative to VSS
Storage Temperature2
VDD1
VDD2
VDDQ
VIN, VOUT
TSTG
Min
Max
-0.4
1.5
-55
125
-0.4
2.1
Unit
V
°C
l
Symbol
1
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Parameter
Note:
1 See “Power-Ramp” for relationships between power supplies.
C
XM
T
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C
on
2 Storage temperature is the case surface temperature on the center/top side of the LPDDR4X device. For the
measurement conditions, please refer to JESD51-2.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
4. AC and DC Operating Conditions
This chapter points out four key conditions for low power device working reliably, safely and
l
legally, which are DC operating voltage, input/output leakage current, temperature, single-ended
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and differential output slew rate.
• Recommended DC Operating Conditions for Low Voltage on Page 20
• Input Leakage Current on Page 21
• Operating Temperature Range on Page 21
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• Single Ended Output Slew Rate on Page 22
C
on
• Input/Output Leakage Current on Page 21
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• Differential Output Slew Rate on Page 24
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
4.1 Recommended DC Operating Conditions for Low Voltage
Table 4-5 LPDDR4 Recommended DC Operating Conditions
Min
1.7
1.06
1.06
Note:
1 VDD1 uses significantly less current than VDD2.
Typ
1.8
1.1
1.1
Max
1.95
1.17
1.17
Unit
V
V
V
Note
1,2
1,2,3
2,3
l
Symbol
VDD1
VDD2
VDDQ
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DRAM
Core 1 Power
Core 1 Power/Input Buffer Power
I/O Buffer Power
2 The voltage range is for DC voltage only. DC is defined as the voltage supplied at the DRAM and is inclusive of
all noise up to 20 MHz at the DRAM package ball.
on
3 VdIVW and TdIVW limits described elsewhere in this document apply for voltage noise on supply voltages of
up to 45 mV (peak-to-peak) from DC to 20MHz.
Symbol
VDD1
VDD2
VDDQ
Min
1.7
1.06
0.57
an
d
DRAM
Core 1 Power
Core 1 Power/Input Buffer Power
I/O Buffer Power
C
Table 4-6 LPDDR4X Recommended DC Operating Conditions
Note:
Typ
1.8
1.1
0.6
Max
1.95
1.17
0.65
Unit
V
V
V
Note
1,2
1,2,3
2,3,4,5
ge
d
1 VDD1 uses significantly less current than VDD2.
2 The voltage range is for DC voltage only. DC is defined as the voltage supplied at the DRAM and is inclusive of
all noise up to 20 MHz at the DRAM package ball.
ile
3 The voltage noise tolerance from DC to 20 MHz exceeding a pk-pk tolerance of 45 mV at the DRAM ball is not
included in the TdIVW.
iv
4 VDDQ(max) may be extended to 0.67 V as an option in case the operating clock frequency is equal or less
than 800 Mhz.
C
XM
T
Pr
5 Pull up, pull down and ZQ calibration tolerance spec is valid only in normal VDDQ tolerance range (0.57 V - 0.65
V).
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
4.2 Input Leakage Current
Table 4-7 Input Leakage Current
Symbol
IL
Min
-4
Max
4
Unit
uA
l
Parameter/Condition
Input Leakage current1,2
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Note:
1 For CK_t, CK_c, CKE, CS, CA, ODT_CA and RESET_n. Any input 0V ≤ VIN ≤ VDD2 (All other pins not under
test = 0V).
2 CA ODT is disabled for CK_t, CK_c, CS, and CA.
on
4.3 Input/Output Leakage Current
Table 4-8 Input/Output Leakage Current
Symbol
IOZ
Max
5
Unit
uA
an
d
Note:
Min
-5
C
Parameter/Condition
Input/Output Leakage current1,2
1 For DQ, DQS_t, DQS_c and DMI. Any I/O 0V ≤ VOUT ≤ VDDQ.
2 I/Os status are disabled: High Impedance and ODT Off.
ge
d
4.4 Operating Temperature Range
TOPER
Min
-25
85
Max
85
105
Unit
°C
°C
Pr
Note:
Parameter/Condition
iv
Parameter/Condition
Standard
Elevated
ile
Table 4-9 Operating Temperature Range
XM
T
1 Operating Temperature is the case surface temperature on the center-top side of the LPDDR4 device. For the
measurement conditions, please refer to JESD51-2.
2 Some applications require operation of LPDDR4 in the maximum temperature conditions in the Elevated
Temperature Range between 85 °C and 105 °C case temperature. For LPDDR4 devices, derating may be
necessary to operate in this range. See MR4.
C
3 Either the device case temperature rating or the temperature sensor may be used to set an appropriate refresh
rate, determine the need for AC timing derating and/or monitor the operating temperature. When using the
temperature sensor, the actual device case temperature may be higher than the TOPER rating that applies for
the Standard or Elevated Temperature Ranges. For example, TCASE may be above 85 °C when the temperature
sensor indicates a temperature of less than 85 °C.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
4.5 Single Ended Output Slew Rate
delta TFse
on
VOLAC)
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Vcent
l
VOH(AC)
delta TRse
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Figure 4-7 Single Ended Output Slew Rate Definition
an
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Table 4-10 LPDDR4 Output Slew Rate (Single-ended)
Symbol
Value
Unit
Min
Max
3.5
9
V/ns
Single-ended Output Slew Rate (VOH = VDDQ/3)
SRQsea
Output slew-rate matching Ratio (Rise to Fall)
0.8
1.2
a
SR: Slew Rate, Q: Query Output (like in DQ, which stands for Data-in, Query-Output), se: Single-ended Signals
ge
d
Parameter
Note:
ile
1 Measured with output reference load.
Pr
iv
2 The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire
temperature and voltage range. For a given output, it represents the maximum difference between pull-up and
pull-down drivers due to process variation.
3 The output slew rate for falling and rising edges is defined and measured between VOL(AC) = 0.2*VOH(DC)
and VOH(AC) = 0.8*VOH(DC).
XM
T
4 Slew rates are measured under average SSO conditions, with 50% of DQ signals per data byte switching.
Table 4-11 LPDDR4X Output Slew Rate (Single-ended) for 0.6V VDDQ
Symbol
Value
Unit
Min
Max
3.0
9
V/ns
Single-ended Output Slew Rate (VOH = VDDQ*0.5)
SRQsea
Output slew-rate matching Ratio (Rise to Fall)
0.8
1.2
a
SR: Slew Rate, Q: Query Output (like in DQ, which stands for Data-in, Query-Output), se: Single-ended Signals
C
Parameter
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Note:
1 Measured with output reference load.
2 The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire
temperature and voltage range. For a given output, it represents the maximum difference between pull-up and
pull-down drivers due to process variation.
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3 The output slew rate for falling and rising edges is defined and measured between VOL(AC) = 0.2*VOH(DC)
and VOH(AC) = 0.8*VOH(DC).
C
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T
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C
on
4 Slew rates are measured under average SSO conditions, with 50% of DQ signals per data byte switching.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
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4.6 Differential Output Slew Rate
on
0
delta TRdiff
C
delta TFdiff
an
d
Figure 4-8 Differential Output Slew Rate Definition
Table 4-12 LPDDR4X Differential Output Slew Rate
Value
Min
Max
Differential Output Slew Rate (VOH = VDDQ/3
SRQdiffa
7
18
a
SR: Slew Rate, Q: Query Output (like in DQ, which stands for Data-in, Query-Output), diff: differential Signals
Symbol
ge
d
Parameter
V/ns
ile
Note:
Unit
1 Measured with output reference load.
Pr
iv
2 The output slew rate for falling and rising edges is defined and measured between VOL(AC) = -0.8*VOH(DC)
and VOH(AC) = 0.8*VOH(DC).
3 Slew rates are measured under average SSO conditions, with 50% of DQ signals per data byte switching
Table 4-13 LPDDR4X Differential Output Slew Rate for 0.6V VDDQ
XM
T
Value
Min
Max
Differential Output Slew Rate (VOH = VDDQ*0.5)
SRQdiffa
6
18
a
SR: Slew Rate, Q: Query Output (like in DQ, which stands for Data-in, Query-Output), diff: differential Signals
Parameter
Symbol
Unit
V/ns
C
Note:
1 Measured with output reference load.
2 The output slew rate for falling and rising edges is defined and measured between VOL(AC) = -0.8*VOH(DC)
and VOH(AC) = 0.8*VOH(DC).
3 Slew rates are measured under average SSO conditions, with 50% of DQ signals per data byte switching.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5. AC and DC Input/Output Measurement Levels
This chapter mainly defines DC electrical characteristics for input signals, AC overshoot and
l
undershoot specifications, differential input voltage specifications, and output driver to ensure the
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normal operation of LPDDR4X SDRAM.
• 1.1V High Speed LVCMOS (HS_LLVCMOS) on Page 26
• Differential Input Voltage on Page 28
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• Overshoot and Undershoot for LVSTL on Page 42
C
• AC/DC Input level for ODT Input on Page 41
on
• Single-Ended Input Voltage for Clock on Page 30
• Driver Output Timing Reference Load on Page 42
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• LVSTL(Low Voltage Swing Terminated Logic) IO System on Page 44
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5.1 1.1V High Speed LVCMOS (HS_LLVCMOS)
5.1.1 Standard Specifications
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All voltages are referenced to ground except where noted.
5.1.2 DC Electrical Characteristics
5.1.2.1 Input Level for CKE
on
This definition applies to CKE_A/ CKE_B.
Table 5-14 Input Level for CKE
Min
0.75*VDD2
-0.2
0.65*VDD2
-0.2
C
Symbol
VIH(AC)
VIL(AC)
VIH(DC)
VIL(DC)
an
d
Parameter
Input high level (AC)1
Input low level (AC)1
Input high level (DC)
Input low level (DC)
Note:
C
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Pr
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Refer AC Overshoot and Undershoot for VIH(AC) and VIL(AC)
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ChangXin Memory Technologies, Inc. _ Confidential
Max
VDD2+0.2
0.25*VDD2
VDD2+0.2
0.35*VDD2
Unit
V
V
V
V
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
VIH(AC) VIH VIH(DC)
VIL(DC)
Don't Care
l
VIL(AC) VIL
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Input Level
Figure 5-9 Input AC Timing Definition for CKE
Note:
1 AC level is guaranteed transition point.
on
2 DC level is hysteresis.
C
5.1.2.2 Input Level for Reset_n and ODT_CA
an
d
This definition applies to Reset_n and ODT_CA.
Table 5-15 Input Level for Reset_n and ODT_CA
Symbol
VIH
VIL
ge
d
Parameter
Input high level1
Input low level1
Note:
Min
0.80*VDD2
-0.2
Max
VDD2+0.2
0.20*VDD2
ile
Refer AC Overshoot and Undershoot for VIH and VIL
VIH
VIL
VIH
VIL
Don't Care
XM
T
Pr
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Input Level
C
Figure 5-10 Input AC Timing Definition for Reset_n and ODT_CA
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ChangXin Memory Technologies, Inc. _ Confidential
Unit
V
V
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5.1.3 AC Overshoot and Undershoot
Table 5-16 AC Over/Undershoot for Address and Control Pins
Specification
0.35 V
0.35 V
0.8 V-ns
0.8 V-ns
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Parameter
Maximum peak Amplitude allowed for overshoot area
Maximum peak Amplitude allowed for undershoot area
Maximum overshoot area above VDD/VDDQ
Maximum undershoot area below VSS/VSSQ
Overshoot Area
Maximum Amplitude
on
VDD
VSS
C
Volts(V)
an
d
Maximum Amplitude
Undershoot Area
Time(ns)
ge
d
Figure 5-11 AC Overshoot and Undershoot Definition for Address and Control Pins
ile
5.2 Differential Input Voltage
Pr
iv
5.2.1 Differential Input Voltage for Clock
The minimum input voltage need to satisfy both Vindiff_CK and Vindiff_CK/2 specification at input
XM
T
receiver and their measurement period is 1tCK. Vindiff_CK is the peak to peak voltage centered
C
on 0 volts differential and Vindiff_CK/2 is max and min peak voltage from 0V.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
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Vindiff_CK/2
Vindiff_CK/2
0.0
Half cycle
Time
on
Differential Input Voltage: CK_t, CK_c
Peak Voltage
Peak Voltage
an
d
Table 5-17 CK Differential Input Voltage
C
Figure 5-12 CK Differential Input Voltage
Data Rate
Symbol
CK differential input voltage
a.
1600/1867a
Vindiff_CK
2133/2400/3200
3733
Unit
Min
Max
Min
Max
Min
Max
420
-
380
-
360
-
ge
d
Parameter
The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the first column 1600/1867.
ile
Note:
iv
The peak voltage of Differential CK signals is calculated in a following equation.
Pr
• Vindiff_CK = (Max Peak Voltage) - (Min Peak Voltage)
• Max Peak Voltage = Max(f(t))
• Min Peak Voltage = Min(f(t))
C
XM
T
• f(t) = VCK_t - VCK_c
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mV
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5.2.2 Peak Voltage Calculation Method
The peak voltage of Differential Clock signals are calculated in a following equation.
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VIH.DIFF.Peak Voltage = Max(f(t))
VIL.DIFF.Peak Voltage = Min(f(t))
f(t) = VCK_t - VCK_c
Single Ended Input Voltage
C
on
CK_t
an
d
VrefCA
Max (f(t))
ge
d
Min (f(t))
ile
CK_c
Time
Pr
Note:
iv
Figure 5-13 Definition of Differential Clock Peak Voltage
VREFCA is LPDDR4X SDRAM internal setting value by VREF Training.
XM
T
5.3 Single-Ended Input Voltage for Clock
The minimum input voltage need to satisfy both Vinse_CK, Vinse_CK_High/Low specification at
C
input receiver.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
l
Vinse_CK_High
on
CK_c
Vinse_CK_Low
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Vinse_CK
Vinse_CK_High
Vinse_CK_Low
Vinse_CK
Single Ended Input Voltage: DQS_t and DQS_c
CK_t
C
Time
Figure 5-14 Clock Single-Ended Input Voltage
an
d
Note:
VREFCA is LPDDR4X SDRAM internal setting value by VREF Training.
ge
d
Table 5-18 Clock Single-Ended Input Voltage
Parameter
Symbol
Data Rate
1600/1867
Max
2133/2400/3200
Min
ile
Min
a
Max
3733
Min
Unit
Max
C
XM
T
Pr
iv
Clock Single-Ended input voltage
Vinse_CK
210
190
180
mV
Clock Single-Ended input voltage
Vinse_CK_High
105
95
90
mV
High from VREFDQ
Clock Single-Ended input voltage
Vinse_CK_Low
105
95
90
mV
Low from VREFDQ
a. The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the
first column 1600/1867.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5.3.2.1 Differential Input Slew Rate Definition for Clock
Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Figure
fid
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Differential Input Voltage: f(t)DQS_t-DQS_c
l
1-15 and the following Tables.
Peak Voltage
VIHDiff_CK
on
0.0
an
d
C
VILDiff_CK
Delta TFdiff
Peak Voltage
Delta TRdiff
Time
ge
d
Figure 5-15 Differential Input Slew Rate Definition for CK_t, CK_c
Note:
1 Differential signal rising edge from VILdiff_CK to VIHdiff_CK must be monotonic slope.
ile
2 Differential signal falling edge from VIHdiff_CK to VILdiff_CK must be monotonic slope.
iv
Table 5-19 Differential Input Slew Rate Definition for CK_t, CK_c
From
To
Defined by
VILdiff_CK
VIHdiff_CK
|VILdiff_CK - VIHdiff_CK|/DeltaTRdiff
VIHdiff_CK
VILdiff_CK
|VILdiff_CK - VIHdiff_CK|/DeltaTFdiff
XM
T
Pr
Description
Differential input slew rate
for rising edge(CK_t - CK_c)
Differential input slew rate
for falling edge(CK_t - CK_c)
Table 5-20 Differential Input Level for CK_t, CK_c
C
Parameter
Symbol
1600/1867
Data Rate
2133/2400/3200
a
3733
Unit
Min
Max
Min
Max
Min
Max
Differential Input High VIHdiff_CK
175
155
145
mV
Differential Input Low VILdiff_CK
-175
-155
-145
mV
a. The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the
first column 1600/1867.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 5-21 Differential Input Slew Rate for CK_t, CK_c
Data Rate
Parameter
Symbol
1600/1867a
Min
Max
2133/2400/3200
Min
Max
Unit
3733
Min
Max
5.3.2.2 Differential Input Cross Point Voltage
fid
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Differential Input Slew Rate for Clock SRIdiff_CK
2
14
2
14
2
14
V/ns
a. The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the
first column 1600/1867.
The cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in
Table 1-22. The differential input cross point voltage VIX is measured from the actual cross point
C
on
of true and complement signals to the mid level that is VREFCA.
an
d
CK_t
Vix_CK_FR
ge
d
VrefCA
Min(f(t))
Vix_CK_FR
ile
CK_c
Vix_CK_RF
VSS
Pr
Time
Figure 5-16 Vix Definition (Clock)
XM
T
Note:
Vix_CK_RF
Max(f(t))
iv
Single Ended Input Voltage
VDD
The base level of Vix_CK_FR/RF is VREFCA that is LPDDR4X SDRAM internal setting value by VREF Training.
C
Table 5-22 Cross Point Voltage for Differential Input Signals (Clock)
Parameter
Data Rate
Symbol
1600/1867a
Min
Max
2133/2400/3200
Min
Max
3733
Min
Unit
Max
Clock Differential input cross
Vix_CK_ratio
25
25
25
%
point voltage ratio1,2
a. The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the
first column 1600/1867.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Note:
1 Vix_CK_Ratio is defined by this equation: Vix_CK_Ratio = Vix_CK_FR/|Min(f(t))|
C
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T
Pr
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d
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C
on
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2 Vix_CK_Ratio is defined by this equation: Vix_CK_Ratio = Vix_CK_RF/Max(f(t))
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5.3.2.3 Differential Input Voltage for DQS
The minimum input voltage need to satisfy both Vindiff_DQS and Vindiff_DQS/2 specification
at input receiver and their measurement period is 1UI(tCK/2). Vindiff_DQS is the peak to peak
fid
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Time
C
XM
T
Pr
iv
ile
ge
d
Figure 5-17 DQS Differential Input Voltage
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ChangXin Memory Technologies, Inc. _ Confidential
Vindiff_DQS
C
0.0
Vindiff_DQS/2
on
Vindiff_DQS/2
Peak Voltage
an
d
Differential Input Voltage: DQS_t, DQS_c
l
voltage centered on 0 volts differential and Vindiff_DQS /2 is max and min peak voltage from 0V.
Peak Voltage
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 5-23 DQS Differential Input Voltage
Data Rate
Parameter
Symbol
1600/1867a
2133/2400/3200
3733
Unit
Min
Max
Min
Max
Min
Max
DQS differential input
Vindiff_DQS
360
360
340
mV
a. The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the
first column 1600/1867.
fid
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1
Note:
1 The peak voltage of Differential DQS signals is calculated in a following equation.
• Vindiff_DQS = (Max Peak Voltage) - (Min Peak Voltage)
• Max Peak Voltage = Max(f(t))
on
• Min Peak Voltage = Min(f(t))
• f(t) = VDQS_t - VDQS_c
C
5.3.2.4 Peak Voltage Calculation Method
• VIH.DIFF.Peak Voltage = Max(f(t))
ge
d
• VIL.DIFF.Peak Voltage = Min(f(t))
an
d
The peak voltage of Differential DQS signals are calculated in a following equation.
• f(t) = VDQS_t - VDQS_c
iv
VrefDQ
C
XM
T
Pr
Single Ended Input Voltage
ile
DQS_t
Min (f(t))
Max (f(t))
DQS_c
Time
Figure 5-18 Definition of Differential DQS Peak Voltage
Note:
VrefDQ is LPDDR4X SDRAM internal setting value by Vref Training.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5.3.2.5 Single-Ended Input Voltage for DQS
The minimum input voltage need to satisfy both Vinse_DQS, Vinse_DQS_High/Low specification
l
at input receiver.
Vinse_DQS_High
fid
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Vinse_DQS_Low
Vinse_DQS
on
C
an
d
CK_c
Vinse_DQS_High
VrefDQ
Vinse_DQS_Low
Vinse_DQS
Single Ended Input Voltage: DQS_t and DQS_c
CK_t
Time
Figure 5-19 DQS Single-Ended Input Voltage
ge
d
Note:
VrefDQ is LPDDR4X SDRAM internal setting value by Vref Training.
Symbol
iv
Parameter
ile
Table 5-24 DQS Single-Ended Input Voltage
Data Rate
1600/1867a
Min
Max
2133/2400/3200
Min
Max
3733
Min
Unit
Max
C
XM
T
Pr
DQS differential input
Vindiff_DQS
180
180
170
mV
DQS Single-Ended input
90
90
85
mV
Vinse_DQS_High
voltage High from VREFDQ
DQS Single-Ended input
90
90
85
mV
Vinse_DQS_Low
voltage Low from VREFDQ
a. The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the
first column 1600/1867.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5.3.2.6 Differential Input Slew Rate Definition for DQS
Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in
l
fid
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Peak Voltage
VIHDiff_DQS
on
0.0
Delta TFdiff
C
VILDiff_DQS
Peak Voltage
Delta TRdiff
an
d
Differential Input Voltage: f(t)DQS_t-DQS_c
Figure 1-20 and Table 1-25.
Time
Figure 5-20 Differential Input Slew Rate Definition for DQS_t, DQS_c
ge
d
Note:
1 Differential signal rising edge from VILdiff_DQS to VIHdiff_DQS must be monotonic slope.
ile
2 Differential signal falling edge from VIHdiff_DQS to VILdiff_DQS must be monotonic slope.
Table 5-25 Differential Input Slew Rate Definition for DQS_t, DQS_c
To
Defined by
Differential input slew rate for
rising edge(DQS_t - DQS_c)
VIHdiff_DQS
VIHdiff_DQS
|VILdiff_DQS - VIHdiff_DQS|/DeltaTRdiff
Differential input slew rate for
falling edge(DQS_t - DQS_c)
VIHdiff_DQS
VIHdiff_DQS
|VILdiff_DQS - VIHdiff_DQS|/DeltaTFdiff
iv
From
C
XM
T
Pr
Description
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 5-26 Differential Input Level for DQS_t, DQS_c
Parameter
1600/1867
Symbol
Data Rate
2133/2400/3200
a
3733
Unit
Table 5-27 Differential Input Slew Rate for DQS_t, DQS_c
Data Rate
1600/1867
Symbol
SRIdiff
Min
Max
Min
2
14
2
Max
14
C
XM
T
Pr
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d
an
d
C
Differential Input
Slew Rate
2133/2400/3200
3733
Min
on
Parameter
a
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l
Min
Max
Min
Max
Min
Max
Differential Input High
VIHdiff_DQS
140
140
120
mV
Differential Input Low
VILdiff_DQS
-140
-140
-120
mV
a. The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the
first column 1600/1867.
39
ChangXin Memory Technologies, Inc. _ Confidential
2
Unit
Max
14
V/ns
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5.3.2.7 Differential Input Cross Point Voltage
The cross point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements
l
in Table 1-28.
fid
en
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The differential input cross point voltage VIX is measured from the actual cross point of true and
complement signals to the mid level that is VREFDQ.
on
DQS_t
Vix_DQS_RF
Vix_DQS_FR
C
Max(f(t))
VrefDQ
an
d
Min(f(t))
DQS_c
VSSQ
Vix_DQS_RF Vix_DQS_FR
ge
d
Single Ended Input Voltage
VDDQ
Time
Figure 5-21 Vix Definition (DQS)
ile
Note:
C
XM
T
Pr
iv
The base level of Vix_DQS_FR/RF is VrefDQ that is LPDDR4X SDRAM internal setting value by Vref Training.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 5-28 Cross Point Voltage for Differential Input Signals (DQS)
Data Rate
Parameter
1600/1867
Symbol
Min
a
Max
2133/2400/3200
Min
3733
Max
Min
Unit
Max
fid
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l
DQS Differential input cross
Vix_DQS_ratio
20
20
20
%
point voltage ratio1,2
a. The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the
first column 1600/1867.
Note:
1 Vix_DQS_Ratio is defined by this equation: Vix_DQS_Ratio = Vix_DQS_FR/|Min(f(t))|.
5.4 AC/DC Input level for ODT Input
Symbol
Min
Max
Unit
0.75*VDD
-0.2
0.65*VDD
-0.2
VDD+0.2
0.25*VDD
VDD+0.2
0.35*VDD
V
V
V
V
an
d
Parameter
C
Table 5-29 Input Level for ODT
on
2 Vix_DQS_Ratio is defined by this equation: Vix_DQS_Ratio = Vix_DQS_RF/Max(f(t))
1
VIHODT(AC)
VILODT(AC)
VIHODT(DC)
VILODT(DC)
ODT Input High Level (AC)
ODT Input Low Level (AC)1
ODT Input High Level (DC)
ODT Input Low Level (DC)
ge
d
Note:
C
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T
Pr
iv
ile
See Overshoot and Undershoot Specifications
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5.5 Overshoot and Undershoot for LVSTL
Table 5-30 AC Overshoot/Undershoot Specification
Maximum peak amplitude allowed for overshoot area. See
Figure 1-22
Maximum peak amplitude allowed for undershoot area. See
Figure 1-22
Maximum area above VDD /VDDQ. See Figure 1-22
Maximum area below VSS. See Figure 1-22
Max
Max
Max
Max
0.3
V
0.3
V
0.1
V/ns
0.1
V/ns
on
Note:
Unit
1600/1866/3200
l
Data Rate
Min/Max
fid
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Parameter
C
1 VDD2 stands for VDD for CA[5:0], CK_t, CK_c, CS_n, CKE and ODT. VDD stands for VDDQ for DQ,
DMI,DQS_t and DQS_c.
an
d
2 VSS stands for VSS for CA[5:0], CK_t, CK_c, CS_n, CKE and ODT. VSS stands for VSSQ for DQ, DMI, DQS_t
and DQS_c.
3 Maximum peak amplitude values are referenced from actual VDD and VSS values.
ge
d
4 Maximum area values are referenced from maximum operating VDD and VSS values.
Overshoot Area
Maximum Amplitude
VDD
ile
Volts(V)
VSS
iv
Maximum Amplitude
Pr
Time(ns)
Undershoot Area
XM
T
Figure 5-22 Overshoot and Undershoot Definition
5.6 Driver Output Timing Reference Load
C
These ‘Timing Reference Loads’ are not intended as a precise representation of any particular
system environment or a depiction of the actual load presented by a production tester. System
designers should use IBIS or other simulation tools to correlate the timing reference load to a
system environment. Manufacturers correlate to their production test conditions, generally one or
more coaxial transmission lines terminated at the tester electronics.
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ChangXin Memory Technologies, Inc. _ Confidential
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Figure 5-23 Driver Output Reference Load for Timing and Slew Rate
Note:
on
All output timing parameter values are reported with respect to this reference load. This reference load is also used to
C
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T
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d
an
d
C
report slew rate.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
5.7 LVSTL(Low Voltage Swing Terminated Logic) IO System
LVSTL I/O cell is comprised of pull-up, pull-down driver and a terminator. The basic cell is shown
C
on
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in Figure 1-24.
an
d
Figure 5-24 LVSTL I/O Cell
To ensure that the target impedance is achieved the LVSTL I/O cell is designed to calibrated as
ge
d
below procedure.
First calibrate the pull-down device against a 240 Ω resister to VDDQ via the ZQ pin.
ile
• Set Strength Control to minimum setting.
iv
• Increase drive strength until comparator detects data bit is less than VDDQ/2.
C
XM
T
Pr
• NMOS pull-down device is calibrated to 240 Ω.
Figure 5-25 Pull-down Calibration
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Then calibrate the pull-up device against the calibrated pull-down device.
• Set VOH target and NMOS controller ODT replica via MRS (VOH can be automatically
controlled by ODT MRS).
fid
en
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• Increase drive strength until comparator detects data bit is greater than VOH target.
l
• Set Strength Control to minimum setting.
ge
d
an
d
C
on
• NMOS pull-up device is now calibrated to VOH target.
C
XM
T
Pr
iv
ile
Figure 5-26 Pull-up Calibration
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
6. Input/Output Capacitance
Table 6-31 Input/output Capacitance
Input capacitance delta, CK_t and CK_c
CDCK
Input capacitance, all other input-only pins
CI
Input capacitance delta, all other input-only pins
CDI
Input/output capacitance, DQ, DMI, DQS_t, DQS_c
CIO
CDDQS
Input/output capacitance delta, DQ, DMI
CDIO
Input/output capacitance, ZQ pin
CZQ
an
d
Input/output capacitance delta, DQS_t, DQS_c
Note:
Unit
Note
l
CCK
3733
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
1,2
pF
1,2,3
pF
1,2,4
pF
1,2,5
pF
1,2,6
pF
1,2,7
pF
1,2,8
pF
1,2
fid
en
tia
Input capacitance, CK_t and CK_c
Min/Max 3200 - 533
Min
0.5
Max
0.9
Min
0.0
Max
0.09
Min
0.5
Max
0.9
Min
-0.1
Max
0.1
Min
0.7
Max
1.3
Min
0.0
Max
0.1
Min
-0.1
Max
0.1
Min
0.0
Max
5.0
on
Symbol
C
Parameter
ge
d
1 This parameter applies to die device only (does not include package capacitance).
2 This parameter is not subject to production test. It is verified by design and characterization. The capacitance
is measured according to JEP147 (Procedure for measuring input capacitance using a vector network analyzer
(VNA) with VDD1, VDD2, VDDQ, VSS, VSSQ applied and all other pins floating.
ile
3 Absolute value of CCK_t . CCK_c.
iv
4 CI applies to CS_n, CKE, CA0~CA5.
Pr
5 CDI = CI . 0.5 * (CCK_t + CCK_c).
6 DMI loading matches DQ and DQS.
XM
T
7 Absolute value of CDQS_t and CDQS_c.
C
8 CDIO = CIO . 0.5 * (CDQS_t + CDQS_c) in byte-lane.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
7. IDD Test Conditions and Specifications
In this chapter, IDD measurement conditions including CA patterns and DQ patterns are defined.
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The key performance indicator IDD values are indtroduced in the second section of this chapter.
• IDD Measurement Conditions on Page 48
C
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C
on
• IDD Specifications on Page 54
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
7.1 IDD Measurement Conditions
The following definitions are used within the IDD measurement tables unless stated otherwise:
fid
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LOW: VIN ≤ VIL(DC) MAX
HIGH: VIN ≥ VIH(DC) MIN
STABLE: Inputs are stable at a HIGH or LOW level
Table 7-32 Definition of Switching for CA Input Signals
Switching for CA
R3
R4
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
HIGH
LOW
C
R2
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
R6
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
R7
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
R8
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
ile
Note:
R5
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
an
d
R1
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
ge
d
CK_t Edge
CKE
CS
CA0
CA1
CA2
CA3
CA4
CA5
on
SWITCHING: See Table 7-32 and Table 7-33.
1 CS must always be driven LOW.
iv
2 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus.
C
XM
T
Pr
3 The pattern is used continuously during IDD measurement for IDD values that require switching on the CA bus.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 7-33 CA Pattern for IDD4R
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
Read-1
CAS-2
DES
DES
DES
DES
Read-1
CAS-2
DES
DES
DES
DES
CA0
CA1
CA2
CA3
CA4
CA5
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
l
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N+10
N+11
N+12
N+13
N+14
N+15
Command
fid
en
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CS
on
CKE
C
Clock Cycle Number
an
d
Note:
1 BA[2:0] = 010, CA[9:4] = 000000 or 111111, Burst Order CA[3:2] = 00 or 11 (Same as LPDDR3 IDD4R).
2 Difference from LPDDR3 (JESD209-3): CA pins are kept low with DES CMD to reduce ODT current.
iv
XM
T
C
CS
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
ile
CKE
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
Pr
Clock Cycle Number
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N+10
N+11
N+12
N+13
N+14
N+15
ge
d
Table 7-34 CA Pattern for IDD4W
Command
Write-1
CAS-2
DES
DES
DES
DES
Write-1
CAS-2
DES
DES
DES
DES
CA0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CA1
L
H
H
L
L
L
L
L
L
H
H
L
L
L
L
L
CA2
H
L
L
L
L
L
L
L
H
L
L
H
L
L
L
L
CA3
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
CA4
L
L
H
L
L
L
L
L
L
H
H
H
L
L
L
L
CA5
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
Note:
1 BA[2:0] = 010, CA[9:4] = 000000 or 111111 (Same as LPDDR3 IDD4W).
2 Difference from LPDDR3 (JESD209-3): 1)-No burst ordering, and 2) CA pins are kept low with DES CMD to
reduce ODT current.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 7-35 Data Pattern for IDD4W (DBI off)
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
16
16
16
16
on
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d
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d
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iv
Pr
16
16
No. of 1’s
8
4
0
4
2
4
6
4
8
4
0
4
2
4
6
4
6
4
2
4
0
4
8
4
2
4
6
4
8
4
0
4
fid
en
tia
DQ[6]
16
XM
T
BL0
BL1
BL2
BL3
BL4
BL5
BL6
BL7
BL8
BL9
BL10
BL11
BL12
BL13
BL14
BL15
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
No. of
1’s
DQ[7]
l
DBI OFF Case
Note:
Simplified pattern compared predecessor. Same data pattern was applied to DQ[4], DQ[5], DQ[6], DQ[7] for reducing
C
complexity for IDD4W/R pattern programming.
50
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 7-36 Data Pattern for IDD4R (DBI off)
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
No. of
1’s
BL0
BL1
BL2
BL3
BL4
BL5
BL6
BL7
BL8
BL9
BL10
BL11
BL12
BL13
BL14
BL15
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
0
0
1
1
1
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
1
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
8
4
0
4
2
4
6
4
8
4
0
4
2
4
6
4
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
No. of
1’s
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
0
0
1
1
1
1
1
0
1
1
0
0
1
0
0
1
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
16
16
16
16
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ile
iv
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T
16
16
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on
fid
en
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l
DQ[6]
ge
d
DQ[7]
an
d
DBI OFF Case
8
4
0
4
6
4
2
4
0
4
8
4
2
4
6
4
Note:
C
Same data pattern was applied to DQ[4], DQ[5], DQ[6], DQ[7] for reducing complexity for IDD4W/R pattern programming
51
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 7-37 Data Pattern for IDD4W (DBI On)
DQ[5]
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
8
8
16
16
8
8
8
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iv
Pr
8
8
Note:
C
DBI enabled burst
52
ChangXin Memory Technologies, Inc. _ Confidential
No. of 1’s
1
4
0
4
2
4
3
4
1
4
0
4
2
4
3
4
1
4
0
4
3
4
2
4
2
4
1
4
2
4
3
4
fid
en
tia
DQ[6]
XM
T
BL0
BL1
BL2
BL3
BL4
BL5
BL6
BL7
BL8
BL9
BL10
BL11
BL12
BL13
BL14
BL15
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
No. of
1’s
DQ[7]
l
DBI ON Case
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 7-38 Data Pattern for IDD4R (DBI On)
DQ[4]
DQ[3]
DQ[2]
DQ[1]
DQ[0]
DBI
BL0
BL1
BL2
BL3
BL4
BL5
BL6
BL7
BL8
BL9
BL10
BL11
BL12
BL13
BL14
BL15
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
No. of
1’s
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
1
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
8
8
8
8
16
16
8
ile
iv
Pr
8
on
C
C
XM
T
8
53
ChangXin Memory Technologies, Inc. _ Confidential
No. of 1’s
1
4
0
4
2
4
3
4
1
4
0
4
2
4
3
4
l
DQ[5]
fid
en
tia
DQ[6]
ge
d
DQ[7]
an
d
DBI ON Case
1
4
0
4
3
4
2
4
2
4
1
4
2
4
3
4
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
7.2 IDD Specifications
IDD values are for the entire operating voltage range, and all of them are for the entire standard
C
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range, with the exception of IDD6ET which is for the entire elevated temperature range.
54
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 7-39 IDD Specification Parameters and Operating Conditions
Idle power-down standby current with clock stop:CK_t =LOW, CK_c
=HIGH;CKE is LOW;CS is LOW;All banks are idle;CA bus inputs are stable;Data bus inputs are stable,ODT disabled
VDD1
IDD02
VDD2
IDD0Q
VDDQ
IDD2P1
IDD2P2
IDD2PQ
IDD2PS1
IDD2PS2
IDD2PSQ
IDD2N1
IDD2N2
IDD2NQ
IDD2NS1
IDD2NS2
IDD2NSQ
IDD3P1
IDD3P2
IDD3PQ
IDD3PS1
IDD3PS2
IDD3PSQ
IDD3N1
IDD3N2
IDD3NQ
IDD3NS1
IDD3NS2
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
an
d
Active power-down standby current:tCK = tCKmin;CKE is LOW;CS is
LOW;One bank is active;CA bus inputs are switching;Data bus inputs are
stable, ODT disabled
Active power-down standby current with clock stop:CK_t=LOW, CK_
c=HIGH;CKE is LOW;CS is LOW;One bank is active;CA bus inputs are
stable;Data bus inputs are stable,ODT disabled
Pr
iv
ile
ge
d
Active non-power-down standby current:tCK = tCKmin;CKE is HIGH;CS
is LOW;One bank is active;CA bus inputs are switching;
Data bus inputs are stable,ODT disabled
Active non-power-down standby current with clock stopped:CK_t=LOW,
CK_c=HIGH;CKE is HIGH;CS is LOW;
One bank is active;CA bus inputs are stable;Data bus inputs are stable,ODT disabled
Operating burst READ current:tCK = tCKmin;CS is LOW between valid
commands;One bank is active;BL = 16 or 32; RL = RL(MIN);CA bus inputs
are switching;50% data change each burst transfer ODT disabled
IDD3NSQ
VDDQ
IDD4R1
IDD4R2
IDD4RQ
IDD4W1
IDD4W2
IDD4WQ
IDD51
IDD52
IDD5Q
IDD5AB1
IDD5AB2
IDD5ABQ
IDD5PB1
IDD5PB2
IDD5PBQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
VDD1
VDD2
VDDQ
XM
T
Operating burst WRITE current:tCK = tCKmin;CS is LOW between valid
commands;One bank is active;BL = 16 or 32; WL = WLmin;CA bus inputs
are switching;50% data change each burst transfer ODT disabled
All bank REFRESH Burst current:tCK = tCKmin;CKE is HIGH between valid
commands;tRC = tRFCabmin;Burst refresh;CA bus inputs are switching;Data bus inputs are stable;ODT disabled
C
All bank REFRESH Average current:tCK = tCKmin;CKE is HIGH between
valid commands;tRC = tREFI;CA bus inputs are switching;Data bus inputs
are stable;ODT disabled
Per bank REFRESH Average current:tCK = tCKmin; CKE is HIGH between
valid commands;tRC = tREFI/8;CA bus inputs are switching;Data bus
inputs are stable;ODT disabled
Note
3
l
IDD01
C
Idle non power-down standby current with clock stopped:CK_t=LOW;
CK_c=HIGH;CKE is HIGH;CS is LOW;All banks are idle;CA bus inputs are
stable;Data bus inputs are stable, ODT disabled
Power Supply
on
Idle non power-down standby current:tCK = tCKmin;CKE is HIGH;
CS is LOW;All banks are idle;CA bus inputs are switching;Data bus inputs
are stable,ODT disabled
Symbol
fid
en
tia
Parameter/Condition
Operating one bank active-precharge current:
tCK = tCKmin; tRC = tRCmin;CKE is HIGH; CS is LOW between valid
commands; CA bus inputs are switching; Data bus inputs are stable ,ODT
disabled
Idle power-down standby current: tCK = tCKmin;CKE is LOW;CS is
LOW;All banks are idle;CA bus inputs are switching;Data bus inputs are
stable,ODT disabled
55
ChangXin Memory Technologies, Inc. _ Confidential
3
3
3
3
3
4
4
4
5
4
4
4
4
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Note:
Power Supply
Note
VDD1
6,7,8,10
VDD2
6,7,8,10
VDDQ
4,6,7,8,10
VDD1
7,8,11
VDD2
7,8,11
VDDQ
4,7,8,11
l
Symbol
IDD61
IDD62
IDD6Q
IDD6ET1
IDD6ET2
IDD6ETQ
fid
en
tia
Parameter/Condition
Power Down Self Refresh current (-25 ° C to +85 ° C):CK_t=LOW, CK_
c=HIGH;CKE is LOW;CA bus inputs are stable;Data bus inputs are stable;Maximum 1x Self Refresh Rate;ODT disabled
Power Down Self Refresh current (+85 ° C to +105 ° C):
CK_t=LOW, CK_c=HIGH;CKE is LOW;CA bus inputs are stable;
Data bus inputs are stable;Maximum 1x Self Refresh Rate;ODT disabled
1 DBI Published IDD values are the maximum of the distribution of the arithmetic mean.
2 ODT disabled: MR11[2:0] = 000B.
3 IDD current specifications are tested after the device is properly initialized.
5 Guaranteed by design with output load = 5pF and RON = 40 Ω.
on
4 Measured currents are the summation of VDDQ and VDD2.
C
6 The 1x Self Refresh Rate is the rate at which the LPDDR4 device is refreshed internally during Self Refresh,
before going into the elevated Temperature range.
an
d
7 This is the general definition that applies to full array Self Refresh.
8 Supplier datasheets may contain additional Self Refresh IDD values for temperature subranges within the
Standard or elevated Temperature Ranges.
ge
d
9 For all IDD measurements, VIHCKE = 0.8 x VDD2, VILCKE = 0.2 x VDD2.
10 IDD6 85 °C is guaranteed, IDD6 45 °C is typical of the distribution of the arithmetic mean.
11 IDD6ET is a typical value, is sampled only, and is not tested.
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12 Dual Channel devices are specified in dual channel operation (both channels operating together).
56
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
7.3 LPDDR4X IDD Parameters - Single Die
VDD2 = 1.06 ~ 1.17V, VDDQ = 0.57 ~ 0.65V; VDD1 = 1.70 ~ 1.95V; TC = –25°C ~ +85°C
3733 Mbps
IDD01
VDD1
9
IDD02
VDD2
75
VDDQ
0.3
VDD1
1.6
IDD2P2
VDD2
5
IDD2PQ
VDDQ
0.1
IDD2PS1
VDD1
1.6
IDD2PS2
VDD2
5
IDD2PSQ
VDDQ
0.1
IDD2N1
VDD1
1.6
IDD2N2
VDD2
IDD2NQ
VDDQ
IDD2NS1
VDD1
IDD2NS2
VDD2
IDD2NSQ
VDDQ
IDD3P1
VDD1
2
VDD2
7.5
VDDQ
0.1
VDD1
2
VDD2
7.5
VDDQ
0.1
VDD1
2.8
IDD3N2
VDD2
40
IDD3NQ
VDDQ
0.1
IDD3NS1
VDD1
3
IDD3NS2
VDD2
30
IDD3NSQ
VDDQ
0.1
IDD4W1
VDD1
3.2
IDD4W2
VDD2
260
IDD4WQ
VDDQ
0.3
IDD4R1
VDD1
5.5
IDD4R2
VDD2
340
IDD4RQ
VDDQ
80
IDD3PQ
C
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T
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IDD3N1
iv
IDD3PS2
mA
mA
C
mA
an
d
0.1
1.6
20
mA
0.1
ile
IDD3PS1
IDD3PSQ
30
ge
d
IDD3P2
mA
on
IDD0Q
IDD2P1
Unit
57
ChangXin Memory Technologies, Inc. _ Confidential
Note
l
Supply
fid
en
tia
Symbol
mA
mA
mA
mA
mA
mA
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
3733 Mbps
IDD51
VDD1
18
IDD52
VDD2
150
IDD5Q
VDDQ
0.1
IDD5AB1
VDD1
3
IDD5AB2
VDD2
35
IDD5ABQ
VDDQ
0.1
IDD5PB1
VDD1
3
IDD5PB2
VDD2
35
IDD5PBQ
VDDQ
0.1
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58
ChangXin Memory Technologies, Inc. _ Confidential
Note
mA
mA
mA
on
Note:
Unit
l
Supply
fid
en
tia
Symbol
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
7.4 LPDDR4X IDD6 Parameters - Single Die
VDD2 = 1.06 ~ 1.17V, VDDQ = 0.57 ~ 0.65V; VDD1 = 1.70 ~ 1.95V; TC = –25°C ~ +85°C
Supply
VDD1
Full-Array Self Refresh Current
0.4
Unit
25°C
IDD62
VDD2
3.8
mA
IDD6Q
VDDQ
0.1
IDD61
VDD1
2.5
IDD62
VDD2
10
IDD6Q
VDDQ
0.1
85°C
Note
l
Symbol
IDD61
fid
en
tia
Temperature
mA
C
XM
T
Pr
iv
ile
ge
d
an
d
C
on
Note:
59
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
8. Electrical Characteristics and AC Timing
8.1 Clock Specification
min/max values may result in malfunction of the LPDDR4X device.
8.1.1 Definition for tCK(avg) and nCK
fid
en
tia
l
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the
on
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window,
N
tCKj
/N
N=200
an
d
tCK(avg)=
C
where each clock period is calculated from rising edge to rising edge.
j=1
Unit ‘tCK(avg)’ represents the actual clock average tCK(avg) of the input clock under operation.
ge
d
Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
timing specs are met.
ile
tCK(avg) may change by up to +/-1% within a 100 clock cycle window, provided that all jitter and
iv
8.1.2 Definition for tCK(abs)
Pr
tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next
XM
T
consecutive rising edge.
tCK(abs) is not subject to production test.
C
8.1.2.1 Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200
high pulses.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
N
tCH(avg)=
/ N x tCK(avg)
tCHj
N=200
j=1
low pulses.
N
tCL(avg)=
/ N x tCK(avg)
tCLj
N=200
on
j=1
fid
en
tia
l
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200
C
8.1.2.2 Definition for tCH(abs) and tCL(abs)
an
d
tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge
to the following falling edge.
ge
d
tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge
to the following rising edge.
ile
Both tCH(abs) and tCL(abs) are not subject to production test.
iv
8.1.2.3 Definition for tJIT(per)
XM
T
tCK(avg).
Pr
tJIT(per) is the single period jitter defined as the largest deviation of any signal tCK from
tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}.
C
tJIT(per),act is the actual clock jitter for a given system.
tJIT(per),allowed is the specified allowed clock period jitter.
tJIT(per) is not subject to production test.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
8.1.2.4 Definition for tJIT(cc)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock
l
cycles.
fid
en
tia
tJIT(cc) = Max of |{tCK(i +1) - tCK(i)}|.
tJIT(cc) defines the cycle to cycle jitter.
tJIT(cc) is not subject to production test.
on
8.2 Clock Timing
Symbol
Clock Timing
Average High pulse width
Average Low pulse width
Absolute clock period
Absolute High clock
pulse width
Absolute Low clock
pulse width
0.46
0.46
tCK(avg)MIN +tJIT(per)MIN
0.54
0.54
-
tCK(avg)
tCK(avg)
ns
tCH(abs)
0.43
0.57
tCK(avg)
tCL(abs)
0.43
0.57
tCK(avg)
ile
Parameter
Symbol
Pr
iv
Clock Timing
Average clock period
Clock period jitter
Maximum Clock Jitter between
consecutive cycles
Unit
Max
ge
d
tCH(avg)
tCL(avg)
tCK(abs)
1600/2400/3200
Min
an
d
Parameter
C
Table 8-40 Clock AC Timings
1600
Min
Max
2400
Min
Max
Min
3200
Max
Unit
tCK(avg)
tJIT(per)
1.25
-70
100
70
0.833
-50
100
50
0.625
-40
100
40
ps
ps
tJIT(cc)
-
140
-
100
-
80
ps
XM
T
8.3 Temperature Derating for AC Timing
Table 8-41 Temperature Derating AC Timing
Symbol
Min/Max
Temperature Derating1
DQS output access time from CK_t/CK_c (derated)
RAS-to-CAS delay (derated)
tDQSCK
tRCD
Min
Min
3600
tRCD + 1.875
C
Parameter
Data Rate
533/1066/1600/2133/
2667/3200/3733
62
ChangXin Memory Technologies, Inc. _ Confidential
Unit
ps
ns
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Symbol
Min/Max
tRC
Min
tRC + 3.75
ns
tRAS
tRP
tRRD
Min
Min
Min
tRAS + 1.875
tRP + 1.875
tRRD + 1.875
ns
ns
ns
l
ACTIVATE-to- ACTIVATE command period (derated)
Row active time (derated)
Row precharge time (derated)
Active bank A to active bank B (derated)
Unit
fid
en
tia
Parameter
Data Rate
533/1066/1600/2133/
2667/3200/3733
Note:
Timing derating applies for operation at 85 °C to 105 °C.
on
8.4 CA Rx Voltage and Timing
The command and address(CA) including CS input receiver compliance mask for voltage and
C
timing is shown in Figure 1-27. All CA, CS signals apply the same compliance mask and operate
an
d
in single data rate mode.
The CA input receiver mask for voltage and timing is shown in Figure 1-28. The receiver mask
(Rx Mask) defines the area that the input signal must not encroach in order for the DRAM input
ge
d
receiver to be expected to be able to successfully capture a valid input signal; it is not the valid
data-eye.
C
Rx Mask
Vcent_CA (pin mid)
Figure 8-27 CA Receiver(Rx) Mask
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ChangXin Memory Technologies, Inc. _ Confidential
VcIVW
XM
T
Pr
iv
ile
TcIVW_total
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
CAy
Vcent_CAx
CAz
Vcent_CAz
Vcent_CAy
fid
en
tia
Vref variation
(component)
l
CAx
Figure 8-28 Across Pin VREFCA Voltage Variation
on
Vcent_CA(pin mid) is defined as the midpoint between the largest Vcent_CA voltage level and
C
the smallest Vcent_CA voltage level across all CA and CS pins for a given DRAM component.
Each CA Vcent level is defined by the center, i.e., widest opening, of the cumulative data input
an
d
eye as depicted in Figure 1-28. This clarifies that any DRAM component level variation must
be accounted for within the DRAM CA Rx mask. The component level VREF will be set by the
system to account for Ron and ODT settings.
iv
ile
DQS_t
ge
d
CK_t, CK_c Data-in at DRAM Ball
Maximum CA Eye center aligned
C
CA
Rx Mask
DRAM Pin
VcIVW
XM
T
Pr
DQS_c
TcIVW
TcIVW for all CA signals is defined as centered on
the CK_t/CK_c crossing at DRAM pin
Figure 8-29 CA Timings at the DRAM Pins
All of the timing terms in Figure 1-29 are measured from the CK_t/CK_c to the center(midpoint) of
the TcIVW window taken at the VcIVW_total voltage levels centered around Vcent_CA(pin mid).
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
tf
tr
fid
en
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l
VcIVW
Vcent_CA (pin mid)
TcIPW
Figure 8-30 CA TcIPW and SRIN_cIVW definition (for each input pulse)
on
Note:
Vcent_CA
Rx Mask
Rx Mask
ge
d
Rx Mask
an
d
C
SRIN_cIVW=VcIVW_Total/(tr or tf), signal must be monotonic within tr and tf range.
VcIVW
VIHL_AC(min)/2
VIHL_AC(min)/2
ile
Figure 8-31 CA VIHL_AC Definition (for Each Input Pulse)
iv
Table 8-42 DRAM CMD/ADR, CS
* UI=tck(avg)min
Pr
DQDQ-3200
1333a/1600/1867
Unit
Note
Min
Max
Min
Max
VcIVW
Rx Mask voltage - p-p
175
155
mV
1,2,3
TcIVW
Rx timing window
0.3
0.3
UI
VIHL_AC CA AC input pulse amplitude pk-pk
210
190
mV
4,7
TcIPW
CA input pulse width
0.55
0.6
UI
5
SRIN_cIVW
Input Slew Rate over VcIVW
1
7
1
7
V/ns
6
a. The following Rx voltage and absolute timing requirements apply for DQ operating frequencies at or below 1333
for all speed bins. For example the TcIVW(ps) = 450ps at or below 1333 operating frequencies.
Parameter
C
XM
T
Symbol
65
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Note:
1 CA Rx mask voltage and timing parameters at the pin including voltage and temperature drift.
2 Rx mask voltage VcIVW total(max) must be centered around Vcent_CA(pin mid).
3 Vcent_CA must be within the adjustment range of the CA internal Vref.
5 CA only minimum input pulse width defined at the Vcent_CA(pin mid).
6 Input slew rate over VcIVW Mask centered at Vcent_CA(pin mid).
C
XM
T
Pr
iv
ile
ge
d
an
d
C
on
7 VIHL_AC does not have to be met when no transitions are occurring.
fid
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l
4 CA only input pulse signal amplitude into the receiver must meet or exceed VIHL AC at any point over the total
UI. No timing requirement above level. VIHL AC is the peak to peak voltage centered around Vcent_CA(pin
mid) such that VIHL_AC/2 min must be met both above and below Vcent_CA.
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
8.5 DRAM Data Timing
tQSH(DQS_t)
tQSL(DQS_t)
DQS_t
fid
en
tia
l
DQS_c
tQH
tDQSQ
C
on
Associated
DQ Pins
ge
d
DQS_t/DQS_c
an
d
Figure 8-32 Read Data Timing Definitions tQH and tDQSQ across all DQ Signals per DQS Group
tQW
iv
ile
DQx
DQy
C
XM
T
Pr
tQW
DQz
tQW
Figure 8-33 Read Data Timing tQW Valid Window Defined per DQ Signal
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 8-43 Read Output Timings
Unit UI = tCK(avg)min/2
Symbol
DQ-1600/1867
Min
Max
Parameter
DQ-2133/2400
Min
Max
DQ-3200
Min
Max
Unit
Note
C
XM
T
Pr
iv
ile
ge
d
an
d
C
on
fid
en
tia
l
Data Timing
DQS_t,DQS_c to DQ
tDQSQ Skew total, per group,
0.18
0.18
0.18
UI
per access (DBIDisabled)
DQ output hold time
min(tQSH,
min(tQSH,
min(tQSH,
tQH
total from DQS_t, DQS_c
UI
tQSL)
tQSL)
tQSL)
(DBI-Disabled)
DQ output window time
tQW_tototal, per pin (DBI-Dis0.75
0.73
0.7
UI
3
tal
abled)
DQ output window time
tQW_dj deterministic, per pin
TBD
TBD
TBD
UI
2,3
(DBIDisabled)
DQS_t,DQS_c to DQ
tDQSQ_
Skew total,per group,
0.18
0.18
0.18
UI
6
DBI
per access (DBI-Enabled)
Min
Min
Min
DQ output hold time
(tQSH_
(tQSH_
(tQSH_
TBD
UI
tQH_DBI total from DQS_t, DQS_c
DBI,tQSL_
DBI,tQSL_
DBI,tQSL_
(DBI-Enabled)
DBI)
DBI)
DBI)
DQ output window time
tQW_tototal, per pin (DBI-En0.75
0.73
0.7
UI
3
tal_DBI
abled)
Data Strobe Timing
DQS, DQS# differentCL(abs)
tCL(abs)
tCL(abs)
tQSL t i a l o u t p u t l o w t i m e
tCK(avg)
3,4
-0.05
-0.05
-0.05
(DBI-Disabled)
DQS, DQS# differentCH(abs)
tCH(abs)
tCL(abs)
tQSH tial output high time
tCK(avg)
3,5
-0.05
-0.05
-0.05
(DBI-Disabled)
DQS, DQS# differentCL(abs)
tCL(abs)
tCL(abs)
tQSL_DBI t i a l o u t p u t l o w t i m e
tCK(avg)
4,6
-0.045
-0.045
-0.045
(DBI-Enabled)
DQS, DQS# differentCH(abs)
tCH(abs)
tCH(abs)
tQSH_DBI tial output high time
tCK(avg)
5,6
-0.045
-0.045
-0.045
(DBI-Enabled)
a. The following Rx voltage and absolute timing requirements apply for DQ operating frequencies at or below
1333 for all speed bins. For example the TcIVW(ps) = 450ps at or below 1333 operating frequencies.
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Note:
1 The deterministic component of the total timing. Measurement method tbd.
2 This parameter will be characterized and guaranteed by design.
fid
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l
3 This parameter is function of input clock jitter. These values assume the min tCH(abs) and tCL(abs). When
the input clock jitter min tCH(abs) and tCL(abs) is 0.44 or greater of tck(avg) the min value of tQSL will be
tCL(abs)-0.04 and tQSH will be tCH(abs) -0.04.
4 tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c, as it measured the
next rising edge from an arbitrary falling edge.
5 tQSH describes the instantaneous differential output high pulse width on DQS_t - DQS_c, as it measured the
next rising edge from an arbitrary falling edge.
on
6 This parameter is function of input clock jitter. These values assume the min tCH(abs) and tCL(abs). When
the input clock jitter min tCH(abs) and tCL(abs) is 0.44 or greater of tck(avg) the min value of tQSL will be
tCL(abs)-0.04 and tQSH will be tCH(abs) -0.04.
an
d
C
8.6 DQ Rx Voltage and Timing
The DQ input receiver mask for voltage and timing is shown Figure 1-34 is applied per pin. The
“total” mask (VdIVW_total, TdiVW_total) defines the area the input signal must not encroach in
ge
d
order for the DQ input receiver to successfully capture an input signal with a BER of lower than
tbd. The mask is a receiver property and it is not the valid data-eye.
XM
T
C
Rx Mask
Vcent_DQ (pin mid)
Figure 8-34 DQ Receiver(Rx) Mask
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ChangXin Memory Technologies, Inc. _ Confidential
VdIVW Total
Pr
iv
ile
TdIVW_total
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
DQy
DQx
Vcent_DQx
DQz
Vcent_DQz
fid
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l
Vcent_DQy
Vref variation
(component)
Figure 8-35 Across Pin Vref DQ Voltage Variation
Vcent_DQ(pin_mid) is defined as the midpoint between the largest Vcent_DQ voltage level and
on
the smallest Vcent_DQ voltage level across all DQ pins for a given DRAM component. Each DQ
C
Vcent is defined by the center, i.e., widest opening, of the cumulative data input eye as depicted
in Figure 1-35. This clarifies that any DRAM component level variation must be accounted for
an
d
within the DRAM Rx mask. The component level Vref will be set by the system to account for Ron
ge
d
and ODT settings.
DQS,DQS Data-in at DRAM Latch
Internal composite Data-Eye Center aligned to DQS
DQS_c
DQS,DQS Data-in at DRAM Pin
Non Minumum Data-Eye/Maximum Rx Mask
ile
DQS_t
DQS_t
DQS_c
tDQS2DQx
VdiVW_TOTAL
Rx Mask
DRAM Pins
DQx
Pr
All DQ signals center aligned to the strobe at
the DRAM internal latch
XM
T
DQy
VdiVW_TOTAL
tDQS2DQy
Rx Mask
DRAM Pins
tDQS2DQz
C
DQz
Rx Mask
DRAM Pins
tDQ2DQ
Figure 8-36 DQ to DQS tDQS2DQ and tDQ2DQ Timings at the
DRAM Pins Referenced from the Internal Latch
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ChangXin Memory Technologies, Inc. _ Confidential
VdiVW_TOTAL
DQx,y,z
iv
tDQS(min) tDQH(min)
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Note:
1 The tDQS2DQ is measured at the center(midpoint) of the TdiVW window.
2 The DQz represents the max tDQS2DQ in this example
3 DQy represents the min tDQS2DQ in this example
tf
VdIVW Total
fid
en
tia
Rx Mask
l
tr
TdIPW
on
Vcent_CA (pin mid)
C
Figure 8-37 DQ TdIPW and SRIN_dIVW Definition (for Each Input Pulse)
an
d
Note:
SRIN_dIVW=VdIVW_Total/(tr or tf), signal must be monotonic within tr and tf range.
ge
d
Vcent_DQ
Rx Mask
Rx Mask
VdIVW_total
iv
ile
Rx Mask
VIHL_AC(min)/2
VIHL_AC(min)/2
C
XM
T
Pr
Figure 8-38 DQ VIHL_AC definition (for Each Input Pulse)
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Table 8-44 DRAM DQs in Receive Mode
* UI=tCK(avg)min/2
Parameter
DQ-3200
Min
-
Max
140
Unit
Note
l
Symbol
DQ1600/1867a/2133/2400
Min
Max
140
C
XM
T
Pr
iv
ile
ge
d
an
d
C
on
fid
en
tia
VdIVW_total Rx Mask voltage - p-p total
mV
1,2,3,4
Rx timing window total (At
TdIVW_total
0.22
0.25
UI
1,2,4
VdIVW voltage levels)
Rx timing window 1 bit toggle
TBD
TBD
UI
1,2,4,12
TdIVW_1bit
(At VdIVW voltage levels)
DQ AC input pulse amplitude
VIHL_AC
180
180
UI
5,13
pk-pk
Input pulse width
TdIPW DQ
0.45
0.45
UI
6
(At Vcent_DQ)
tDQS2DQ DQ to DQS offset
200
800
200
800
ps
7
tDQ2DQ DQ to DQ offset
30
30
ps
8
tDQS2DQ_temp DQ to DQS
tQSL
0.6
0.6
ps/° C
9
offset temperature variation
tDQS2DQ_ DQ to DQS offset voltage vari33
33
ps/50 mV
10
volt
ation
Input Slew Rate over VdIVW_
1
7
1
7
V/ns
11
SRIN_dIVW
total
tDQS2DQ_ DQ to DQS offset rank to rank
200
200
ps
14,15,16
rank2rank variation
a. The Rx voltage and absolute timing requirements apply for all DQ operating frequencies at or below 1600 for all
speed bins. For example TdIVW_total(ps) = 137.5ps at or below 1600 operating frequencies
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ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Note:
1 The Data Rx mask voltage and timing parameters are applied per pin and includes the DRAM DQ to DQS
voltage AC noise impact for frequencies >20 MHz and max voltage of 45mv pk-pk from DC-20MHz at a fixed
temperature on the package. The voltage supply noise must comply to the component Min-Max DC operating
conditions.
fid
en
tia
l
2 The design specification is a BER 20MHz and max voltage of 45mv pk-pk from DC-20MHz
at a fixed temperature on the package. For tester measurement VDDQ = VDD2 is assumed.
11 Input slew rate over VdIVW Mask centered at Vcent_DQ(pin_mid).
ile
12 Rx mask defined for a one pin toggling with other DQ signals in a steady state.
13 VIHL_AC does not have to be met when no transitions are occurring.
iv
14 The same voltage and temperature are applied to tDQS2DQ_rank2rank.
Pr
15 tDQS2DQ_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the
same design dies.
C
XM
T
16 tDQS2DQ_rabk2rank support was added to JESD209-4B, some older devices designed to support JESD2094 and JESD209-4A may not support this parameter. Refer to vendor datasheet.
73
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9. AC Timing Parameters
• Core AC Timing on Page 75
fid
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l
• Read AC Timing on Page 76
• tDQSCK Timing on Page 77
• Write AC Timing on Page 78
• VRCG Enable/Disable Timingon Page 79
• Frequency Set Point Timing on Page 85
• Write Leveling Timing on Page 85
an
d
• Command Bus Training AC Timing on Page 80
C
• Mode Register Read/Write AC Timingon Page 79
on
• Self Refresh AC Timing on Page 78
ge
d
• MPC [Write FIFO] AC Timing on Page 85
ile
• DQS Interval Oscillator AC Timing on Page 86
• Read Preamble Training Timing on Page 86
Pr
iv
• ZQ Calibration Timingon Page 86
• ODT CA AC Timingon Page 86
C
XM
T
• Power-Down AC Timing on Page 87
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9.1 Core AC Timing
Table 9-45 Core AC Timing Table
533/1066/1600/2133/2667/
4267
3200/3733
tRAS + tRPab
(with all bank precharge)
tRAS + tRPpb
(with per bank precharge)
Core Parameters
ACTIVATE-to-ACTIVATE command
period (same bank)
Data Rate
Unit
l
Symbol Min/Max
fid
en
tia
Parameter
MIN
tSR
MIN
max(15ns, 3nCK)
ns
tXSR
MIN
max(tRFCab + 7.5ns, 2nCK)
ns
tXP
MIN
max(7.5ns, 5nCK)
ns
tCCD
MIN
Internal READ to PRECHARGE
command delay
tRTP
MIN
RAS-to-CAS delay
tRCD
MIN
Row precharge time (single bank)
tRPpb
MIN
Row precharge time (all banks)
tRPab
MIN
tRAS
MAX
Row active time
C
ns
8
tCK(avg)
max(7.5ns, 8nCK)
ns
max(18ns, 4nCK)
ns
max(18ns, 4nCK)
ns
max(21ns, 4nCK)
ns
an
d
ge
d
Minimum Self Refresh Time (Entry
to Exit)
Self Refresh exit to next valid command delay
Exit Power-Down to next valid command delay
CAS-to-CAS delay
on
tRC
max(42ns, 3nCK)
ns
MIN
Min(9 * tREFI * Refresh Rate, 70.2) us
( Refresh Rate is specified by MR4, OP[2:0] )
us
tWR
MIN
max(18ns, 6nCK)
ns
tWTR
MIN
max(10ns, 8nCK)
ns
Active bank-A to active bank-B1
tRRD
MIN
max(10ns, 4nCK)
Max(7.5ns, 4nCK)2
ns
Precharge to Precharge Delay
tPPD
MIN
4
4
tCK
Four-bank ACTIVATE window
tFAW
MIN
40
302
ns
ile
tRAS
WRITE recovery time
C
XM
T
Pr
WRITE-to-READ delay
iv
Row active time
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LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9.2 Read AC Timing
Table 9-46 Read AC Timing Table
Unit
l
tCK(avg)
tCK(avg)
tCK(avg)
fid
en
tia
Data Rate
533/1066/1600/2133/2667/3200/3733/4267
1.8
0.4
1.4
(RL x tCK) + tDQSCK(Min) - 200ps
on
(RL x tCK) + tDQSCK(Max) + tDQSQ(Max) +
(BL/2 x tCK) - 100ps
(RL x tCK) + tDQSCK(Min) - (tRPRE(Max) x tCK) 200ps
(RL x tCK) + tDQSCK(Max) +(BL/2 x tCK) +
(RPST(Max) x tCK) - 100ps
0.18
C
XM
T
Pr
iv
ile
ge
d
an
d
C
Parameter
Symbol Min/Max
Core Parameters
READ preamble
tRPRE
MIN
0.5 tCK READ postamble
tRPST
MIN
1.5 tCK READ postamble
tRPST
MIN
DQ low-impedance time
tLZ(DQ)
MIN
from CK_t, CK_c
DQ high impedance time
tHZ(DQ)
MAX
from CK_t, CK_c
DQS_c low-impedance time
tLZ(DQS)
MIN
from CK_t, CK_c
DQS_c high impedance
tHZ(DQS)
MAX
time from CK_t, CK_c
DQS-DQ skew
tDQSQ
MAX
76
ChangXin Memory Technologies, Inc. _ Confidential
ps
ps
ps
ps
UI
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9.3 tDQSCK Timing
Table 9-47 tDQSCK Timing Table
Min
1.5
tDQSCK_temp
-
tDQSCK_volt
-
Max
3.5
Unit
ns
Note
1
l
Symbol
tDQSCK
fid
en
tia
Parameter
DQS Output Access Time from CK_t/CK_c
DQS Output Access Time from CK_t/CK_c
-Temperature Variation
DQS Output Access Time from CK_t/CK_c
-Voltage Variation
Note:
4
ps/°C
2
7
ps/mV
3
C
2 tDQSCK_temp max delay variation as a function of Temperature.
on
1 Includes DRAM process, voltage and temperature variation. It includes the AC noise impact for frequencies >
20 MHz and max voltage of 45 mV pk-pk from DC-20 MHz at a fixed temperature on the package. The voltage
supply noise must comply to the component Min-Max DC Operating conditions.
an
d
3 tDQSCK_volt max delay variation as a function of DC voltage variation for VDDQ and VDD2. tDQSCK_
volt should be used to calculate timing variation due to VDDQ and VDD2 noise < 20 MHz. Host controller
do not need to account for any variation due to VDDQ and VDD2 noise > 20 MHz. The voltage supply noise
must comply to the component Min-Max DC Operating conditions. The voltage variation is defined as the
Max[abs{tDQSCKmin@V1-tDQSCKmax@V2}, abs{tDQSCKmax@V1-tDQSCKmin@V2}]/abs{V1-V2}. For
tester measurement VDDQ = VDD2 is assumed.
ge
d
Table 9-48 CK to DQS Rank to Rank Timing Table
Parameter
Symbol
Min/Max
Note:
tDQSCK_rank2rank
Max
1.0
Unit
Note
ns
1,2
Pr
variation
1600/1866/2133/2667/3200/4267
iv
CK to DQS Rank to Rank
ile
Read Timing
Data Rate
1 The same voltage and temperature are applied to tDQS2CK_rank2rank.
C
XM
T
2 tDQSCK_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the same
design dies.
77
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9.4 Write AC Timing
Table 9-49 Write AC Timing Table
Min
0.2
Min
0.2
Min
Min
Min
1.8
0.4
1.4
Note:
Parameter
ge
d
Table 9-50 Self Refresh AC Timing Table
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Note
Min
Max(1.75ns, 3tCK)
ns
1
Min
Max(15ns, 3tCK)
ns
1
Min
Max(tRFCab +7.5ns,2tCK)
ns
2
ile
iv
tCK(avg)
Unit
Pr
Note:
tCK(avg)
tCK(avg)
Data Rate
533/1066/1600/2133/2667/3200/3733/4267
Symbol Min/Max
Self Refresh Timing
Delay from SRE command
tESCKE
to CKE Input low
Minimum Self Refresh Time
tSR
Exit Self Refresh to Valid
tXSR
commands
tCK(avg)
an
d
The length of Write Postamble depends on MR3 OP1 setting.
9.5 Self Refresh Timing
Unit
l
Min
Max
Min
Min
Data Rate
533/1066/1600/2133/2667/3200/3733/4267
0.75
1.25
0.4
0.4
fid
en
tia
Min/Max
on
Symbol
Write Timing
Write command to 1st
tDQSS
DQS latching
DQS input high-level
tDQSH
DQS input low-level width
tDQSL
DQS falling edge to CK
tDSS
setup time
DQS falling edge hold
tDSH
time from CK
Write preamble
tWPRE
0.5 tCK Write postamble
tWPST1
1.5 tCK Write postamble
tWPST1
C
Parameter
XM
T
Delay time has to satisfy both analog time(ns) and clock count(tCK). It means that tESCKE will not expire until CK has
C
toggled through at least 3 full cycles (3 *tCK) and 1.75ns has transpired.
78
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9.6 Mode Register Read/Write AC Timing
Symbol
Min/Max
Data Rate
Unit
tMRRI
Min
tRCD + 3nCK
tMRR
Min
8
nCK
tMRW
Min
MAX(10ns,10nCK)
-
tMRD
Min
max(14ns,10nCK)
-
C
533/1066/1600/2133/2667/3200/3733/4267Mbps
Min
Max
200
-
100
an
d
-
C
XM
T
Pr
iv
ile
ge
d
Speed
Parameter
Symbol
VREF high current
tVRCG_ENABLE
mode enable time
VREF high current
tVRCG_DISABLE
mode disable time
on
9.7 VRCG Enable/Disable Timing
Table 9-52 VRCG Enable/Disable Timing Table
-
fid
en
tia
Parameter
Mode Register Read/Write Timing
Additional time after tXP has expired until
MRR command may be issued
MODE REGISTER READ command period
MODE REGISTER WRITE command period
Mode register set command delay
l
Table 9-51 Mode Register Read/Write AC Timing Table
79
ChangXin Memory Technologies, Inc. _ Confidential
Unit
ns
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9.8 Command Bus Training AC Timing
Table 9-53 Command Bus Training AC Timing Table
Data Rate
533/1066/1600/2133/2667/3200/3733/4267
Min
Max(5ns, 5nCK)
-
Min
2
ns
2
ns
20
ns
RU(tADR/tCK )
tCK
10
ns
250
ns
Max
250
ns
Max
80
ns
Min
2tck + tXP (tXP = max(7.5ns, 5nCK))
-
Min
max(7.5ns, 5nCK))
-
Min
2
tCK
Min
10
ns
Min
Max(1.75ns, 3nCK)
-
Min
1.5
ns
Min
20
ns
Min
20
ns
Min
Min
Min
Max(5nCK, 200ns)
Max(5nCK, 200ns)
Max(5nCK, 250ns)
-
l
Min
Min
Min
ile
iv
Pr
on
Max
C
XM
T
Unit
fid
en
tia
Min
ge
d
Command Bus Training Timing
Valid Clock Requirement after
tCKELCK
CKE Input low
Data Setup for VREF Training
tDStrain
Mode
Data Hold for VREF Training
tDHtrain
Mode
Asynchronous Data Read
tADR
CA Bus Training Command to
CA Bus Training Command
tCACD2
Delay
Valid Strobe Requirement betDQSCKE1
fore CKE Low
First CA Bus Training ComtCAENT
mand Following CKE Low
VREF Step Time– multiple
tVREFCA_LONG
steps
VREF Step Time– one step
tVREFCA_SHORT
Valid Clock Requirement betCKPRECS
fore CS High
Valid Clock Requirement after
tCKPSTCS
CS High
Minimum delay from CS to
DQS toggle in command bus
tCS_VREF
training
Minimum delay from CKE High
tCKEHDQS
to Strobe High Impedance
Valid Clock Requirement betCKCKEH
fore CKE Input High
CA Bus Training CKE High to
tMRZ
DQ Tri-state
ODT turn-on Latency from
tCKELODTon
CKE
ODT turn-off Latency from
tCKELODToff
CKE
tXCBT_Short
Exit Command Bus Training
tXCBT_Middle
Mode to next valid command
delay3
tXCBT_Long
Min/Max
C
Symbol
an
d
Parameter
80
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Note:
1 DQS_t has to retain a low level during tDQSCKE period, as well as DQS_c has to retain a high level.
2 If tCACD is violated, the data for samples which violate tCACD will not be available, except for the last sample
(where tCACD after this sample is met). Valid data for the last sample will be available after tADR.
fid
en
tia
l
3 Exit Command Bus Training Mode to next valid command delay Time depends on value of VREF(CA) setting:
MR12 OP[5:0] and VREF(CA) Range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in Table 61.
Additionally exit Command Bus Training Mode to next valid command delay Time may affect VREF(DQ) setting.
Settling time of VREF(DQ) level is same as VREF(CA) level.
Data Rate
533/1066/1600/2133/2667/3200/3733/4267
Min
max(7.5ns, 3nCK)
tCK
Max
20
ns
RU(tADR/tCK )
tCK
Min
Min
Min
Min
ile
iv
Pr
250
Unit Note
1
ns
2tCK + tXP (tXP = max(7.5ns, 5nCK))
max(7.5ns, 5nCK))
ge
d
Command Bus Training Timing
Clock and Command Valid
tCKELCK
after CKE Low
Asynchronous Data Read
tADR
CA Bus Training Command
to CA Bus Training ComtCACD
mand Delay
First CA Bus Training ComtCAENT
mand Following CKE Low
Valid Clock Requirement
tCKPRECS
before CS High
Valid Clock Requirement
tCKPSTCS
after CS High
Clock and Command Valid
tCKCKEH
before CKE High
CA Bus Training CKE High
tMRZ
to DQ Tri-state
ODT turn-on Latency from
tCKELODTon
CKE
ODT turn-off Latency from
tCKELODToff
CKE
Exit Command Bus Training tXCBT_Short
Mode to next valid com- tXCBT_Middle
mand delay
tXCBT_Long
Min/Max
C
Symbol
an
d
Parameter
on
Table 9-54 Command Bus Training AC Timing Table for Mode 1
Min
2
tCK
Min
1.5
ns
Min
20
ns
Min
20
ns
Min
Min
Min
Max(5nCK, 200ns)
Max(5nCK, 200ns)
Max(5nCK, 250ns)
2
2
2
XM
T
Note:
1 If tCACD is violated, the data for samples which violate tCACD will not be available, except for the last sample
(where tCACD after this sample is met). Valid data for the last sample will be available after tADR.
C
2 Exit Command Bus Training Mode to next valid command delay Time depends on value of VREF(CA) setting:
MR12 OP[5:0] and VREF(CA) Range: MR12 OP[6] of FSP-OP 0 and 1. Additionally exit Command Bus
Training Mode to next valid command delay Time may affect VREF(DQ) setting. Settling time of VREF(DQ)
level is same as VREF(CA) level.
81
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Data Rate
533/1066/1600/2133/2667/3200/3733/4267
Min
Max(5ns,5nCK)
Min
2tCK + tXP (tXP = max(7.5ns, 5nCK))
Min
max(7.5ns, 5nCK))
-
Min
10
ns
Min
250
ns
Max
250
ns
2
Max
200
ns
3
100
ns
4
2
ns
2
ns
Min
Max
Min
Max
Max
16
80
5
100
20
ns
ns
ns
ns
ns
Min
0
ns
Min
Max
Min
Max
Min
Max
3
10
10
60
3
10
ns
ns
ns
ns
ns
ns
Min
Max(10ns, 5nCK)
-
Min
2
ns
Min
Max(110ns, 4nCK)
Min
10
Min
Max(1.75ns,3nCK)
Max
20
ns
Max
20
ns
Min
Min
ile
tDQ7SH
iv
DQ7sample hold time
C
XM
T
Pr
Asynchronous Data Read
tADSPW
Pulse Width
Hi-Z to asynchronous VreftHZ2VREF
CA valid data
Read to Write Delay at CBT
tCBTRTW
mode
CA Bus Training Command
to CA Bus Training ComtCACD
mand Delay
Minimum delay from CKE
High to Strobe High Imped- tCKEHDQS
ance
Clock and Command Valid
tCKCKEH
before CKE High
ODT turn-on Latency from
tCKELODTon
CKE
ODT turn-off Latency from
tCKELODToff
CKE for ODT_CA
Unit Note
l
ns
-
fid
en
tia
Max
ge
d
Command Bus Training Timing
Valid Clock Requirement
tCKELCK
after CKE Input low
Valid Clock Requirement
tCKPRECS
before CS High
Valid Clock Requirement
tCKPSTCS
after CS High
Valid Strobe Requirement
tDQSCKE
before CKE Low
First CA Bus Training ComtCAENT
mand Following CKE Low
VREF Step Time - Long
tVREFCA_Long
tVREFCA_MidVREF Step Time - Middle
dle
tVREFCA_
VREF Step Time - Short
Short
Data Setup for Vref Training
tDStrain
Mode
Data Hold for Vref Training
tDHtrain
Mode
Asynchronous Data Read
tADVW
Valid Window
DQS Input period at CBT
tDQSICYC
mode
Asynchronous Data Read
tADR
DQS_c high impedance
tHZCBT
time from CS High
Asynchronous Data Read
tAD2DQ7
to DQ7 toggle
Min/Max
on
Symbol
an
d
Parameter
C
Table 9-55 Command Bus Training AC Timing Table for Mode 2
82
ChangXin Memory Technologies, Inc. _ Confidential
ns
1
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
Min/Max
Data Rate
533/1066/1600/2133/2667/3200/3733/4267
Max
20
ns
Max
20
ns
Max
Max(10ns, 5nCK)
Min
Min
Min
Max(5nCK, 200ns)
Max(5nCK, 200ns)
Max(5nCK, 250ns)
ODT turn-off Latency from
tCKEHODToff
CKE for ODT_DQ and DQS
ODT_DQ turn-off Latency
from CS high during CB tODToffCBT
Training
ODT_DQ turn-on Latency
from the end of Valid Data tODTonCBT
out
Exit Command Bus Training tXCBT_Short
Mode to next valid com- tXCBT_Middle
mand delay
tXCBT_Long
Unit Note
l
Symbol
fid
en
tia
Parameter
Note:
5
5
5
on
1 DQS_t has to retain a low level during tDQSCKE period, as well as DQS_c has to retain a high level.
2 VREFCA_Long is the time including up to VREFmin to VREFmax or VREFmax to VREFmin change across
the VREFDQ Range in VREF voltage.
C
3 VREF_Middle is at least 2 stepsizes increment/decrement change within the same VREFDQ range in VREF
voltage.
an
d
4 VREF_Short is for a single stepsize increment/decrement change in VREF voltage.
C
XM
T
Pr
iv
ile
ge
d
5 Exit Command Bus Training Mode to next valid command delay Time depends on value of VREF(CA) setting:
MR12 OP[5:0] and VREF(CA) Range: MR12 OP[6] of FSP-OP 0 and 1.
83
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9.9
Frequency Set Point Timing
Table 9-56 Frequency Set Point Timing Table
Min
200
ns
200
ns
250
ns
Min
max(7.5ns, 4nCK)
-
Min
-
Min
Min
max(7.5ns, 4nCK)
C
Frequency Set Point parameters
Frequency Set Point
tFC_Short1
Switching Time
Minimum Self Refresh
tFC_Middle1
Time
Exit Self Refresh to Valid
tFC_Long1
commands
Valid Clock Requirement
tCKFSPE
after Entering FSP Change
Valid Clock Requirement
before 1st Valid Command
tCKFSPX
after FSP change
Unit
l
Data Rate
533/1066/1600/2133/2667/3200/3733/4267
Min/Max
fid
en
tia
Symbol
on
Parameter
an
d
Note:
Frequency Set Point Switching Time depends on value of VREF(CA) setting: MR12 OP[5:0] and VREF(CA) Range:
MR12 OP[6] of FSP-OP 0 and 1. Additionally change of Frequency Set Point may affect VREF(DQ) setting. Settling time
C
XM
T
Pr
iv
ile
ge
d
of VREF(DQ) level is same as VREF(CA) level.
84
ChangXin Memory Technologies, Inc. _ Confidential
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9.10 Write Leveling Timing
Table 9-57 Write Leveling Timing Table
tWLWPRE
First DQS_t/DQS_c edge after write leveling
mode is programmed
tWLMRD
Write leveling output delay
tWLO
Mode register set command delay
tMRD
Valid Clock Requirement before DQS Toggle
tCKPRDQS
Valid Clock Requirement after DQS Toggle
tCKPSTDQS
Unit
tCK
l
Value
20
20
40
0
20
max(14ns, 10nCK)
max(7.5ns, 4nCK)
max(7.5ns, 4nCK)
-
fid
en
tia
tWLDQSEN
Min/Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tCK
tCK
ns
ns
on
Write preamble for Write Leveling
Symbol
C
Parameter
DQS_t/DQS_c delay after write leveling mode
is programmed
-
Parameter
Symbol
Write Leveling Parameters
Parameters Write leveling hold time
Write leveling setup time
Write leveling input valid window
Min/Max
Min
Min
Min
ge
d
tWLH
tWLS
tWLIVW
an
d
Table 9-58 Write Leveling Setup and Hold Time
1600
Data Rate
2400
3200
150
150
240
100
100
160
75
75
120
4266
50
50
90
ile
9.11 MPC [Write FIFO] AC Timing
Symbol
Min/Max
Data Rate
533/1066/1600/2133/2667/3200/3733/4267
tMPCWR
Min
tRCD + 3nCK
Pr
Parameter
iv
Table 9-59 MPC [Write FIFO] AC Timing Table
C
XM
T
MPC Write FIFO Timing
Additional time after tXP has
expired until MPC [Write FIFO]
command may be issued
85
ChangXin Memory Technologies, Inc. _ Confidential
Unit
ps
ps
ps
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9.12 DQS Interval Oscillator AC Timing
Table 9-60 DQS Interval Oscillator AC Timing Table
Min/Max
Min
Note:
Start DQS OSC command is prohibited until tOSCO(Min) is satisfied.
9.13 Read Preamble Training Timing
Table 9-61 Read Preamble Training Timing Table
Symbol
tZQCAL
tZQLAT
tZQRESET
ge
d
Parameter
ZQ Calibration Time
ZQ Calibration Latch Time
ZQ Calibration Reset Time
an
d
9.14 ZQ Calibration Timing
Table 9-62 ZQCal Timing Table
ile
9.15 ODT CA AC Timing
Min
-
on
Symbol
tSDO
Max
Min(12nCK, 20ns)
Min /Max
Min
Min
Min
Value
1
max(30ns,8nCK)
max(50ns,3nCK)
Table 9-63 ODT CA AC Timing Table
iv
Speed
Parameter
ODT CA Value Update Time
600/1866/2133/2400/3200/4266
MIN
MAX
RU(TBDns/tCK(avg))
-
C
XM
T
Pr
Symbol
tODTUP
Unit
ns
C
Parameter
Delay from MRW command to DQS Driven
Value
Max(40ns,8nCK)
l
Symbol
tOSCO
fid
en
tia
Parameter
Delay time from OSC stop to Mode Register Readout
86
ChangXin Memory Technologies, Inc. _ Confidential
Unit
us
ns
ns
LPDDR4X SDRAM Datasheet Preliminary Ver. 0.4
9.16 Power-Down AC Timing
Table 9-64 Power-Down AC Timing
Data Rate
533/1066/1600/2133
/2667/3200/3733/4267
Unit
Min
Max(7.5ns,4nCK)
-
Min
Max(1.75ns,3nCK)
ns
1
Min
Max(5ns,5nCK)
ns
1
Min
1.75
ns
Max(5ns,5nCK)
ns
Max(1.75ns,3nCK)
ns
1
Max(7.5ns,5nCK)
ns
1
Min
1.75
ns
Min
Max(7.5ns,5nCK)
ns
Min
Max(14ns,10nCK)
ns
1
Min
Max(1.75ns,3nCK)
ns
1
Min
Min
ile
Note:
l
Note
fid
en
tia
on
Min
ge
d
Power Down Timing
CKE minimum pulse width (HIGH
tCKE
and LOW pulse width) tCKE
Delay from valid command to CKE
tCMDCKE
input LOW
Valid Clock Requirement after CKE
tCKELCK
Input low
Valid CS Requirement before CKE
tCSCKE
Input Low
Valid CS Requirement after CKE
tCKELCS
Input low
Valid Clock Requirement before
tCKCKEH
CKE Input High
Exit power- down to next valid
tXP
command delay
Valid CS Requirement before CKE
tCSCKEH
Input High
Valid CS Requirement after CKE
tCKEHCS
Input High
Valid Clock and CS Requirement
after CKE Input low after MRW tMRWCKEL
Command
Valid Clock and CS Requirement
after CKE Input low after ZQ CalitZQCKE
bration Start Command
Min/Max
C
Symbol
an
d
Parameter
C
XM
T
Pr
iv
Delay time has to satisfy both analog time(ns) and clock count(nCK).
87
ChangXin Memory Technologies, Inc. _ Confidential