XL9535, XL9555
Product datasheet
XL9535, XL9555
16-bit I2C-bus and SMBus I/O port Expander With Interrupt Output and Configuration Registers
Rev. 2.3 — 2018
1. DESCRIPTION
This device (XL9535/XL9555) is a 24-pin CMOS IC that provides 16-bit of General Purpose parallel
Input/Output (GPIO) expansion for most micro-controller families via the I 2C-bus/SMBus interface
[serial clock line (SCL), serial data line (SDA)]. These device is designed for 2.3-V to 5.5-V VCC
operation. The improvements include higher drive capability, 5 V I/O tolerance, lower supply
current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple
solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans,
etc.
These device consists of two 8-bit Configuration (Input or Output selection); Input Port, Output Port
and Polarity Inversion (active-HIGH or active-LOW operation) registers. At power on, the I/Os are
configured as inputs. The system master can enable the I/Os as either inputs or outputs by writing
to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or
Output register. The polarity of the Input Port register can be inverted with the Polarity Inversion
register. All registers can be read by the system master.
These device open-drain interrupt (INT) output is activated when any input state differs from its
corresponding Input Port register state and is used to indicate to the system master that an input
state has changed. The system master can reset these device in the event of a timeout or other
improper operation by utilizing the power-on reset feature. The power-on reset sets the registers to
their default values and initializes the I2C/SMBus state machine. Three hardware address pins (A0,
A1 and A2) vary the fixed I2C-bus address and allow up to eight devices to share the same
I2C-bus/SMBus.
2. FEATURES
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I2C-bus to 16-bit GPIO expander
Operating power supply voltage range of
2.3-V to 5.5-V
Low standby current consumption
5 V tolerant I/O ports
400 kHz fast-mode I2C-bus clock
frequency
Noise filter on SCL/SDA inputs
Internal power-on reset
No glitch on power-up
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Polarity Inversion register
Address by 3 hardware address pins for
use of up to 8 devices
Open-drain active LOW interrupt output
16 I/O pins which default to 16 inputs
Latch-up testing exceeds 100 mA per JESD
78
ESD protection exceeds JESD 22
2000 V HBM, 200 V MM and 1000 V CDM
Rev 2.3
XL9535, XL9555
Product datasheet
3. ORDERING INFORMATION
Table 1. Ordering Information
Part
Device
Package
Body size
Temperature
Number
Marking
Type
(mm)
(°C)
XL9535D
XL9535D
SOP24(300mil)
15.4 × 7.50
-40 to +85
XL9535SS
XL9535SS
SSOP24(209mil)
8.20 × 5.30
XL9535
XL9535
TSSOP24
XL9535QF24
XL9535QF24
XL9555D
Transport
Package
Media
Quantity
MSL3
T&R 13"
1000
-40 to +85
MSL3
T&R 13"
2500
7.80 × 4.40
-40 to +85
MSL3
T&R 13"
4000
QFN24-4×4
4.00 × 4.00
-40 to +85
MSL3
T&R 13"
5000
XL9555D
SOP24(300mil)
15.4 × 7.50
-40 to +85
MSL3
T&R 13"
1000
XL9555SS
XL9555SS
SSOP24(209mil)
8.20 × 5.30
-40 to +85
MSL3
T&R 13"
2500
XL9555
XL9555
TSSOP24
7.80 × 4.40
-40 to +85
MSL3
T&R 13"
4000
XL9555QF24
XL9555QF24
QFN24-4×4
4.00 × 4.00
-40 to +85
MSL3
T&R 13"
5000
MSL
4. PIN CONFIGURATIONS AND FUNCTIONS
SCL
21
A0
P16
15
P15
2
P02
3
18
P15
P03
4
8
17
P14
P04
5
14
P14
9
16
P13
P05
6
13
P13
P06
10
15
P12
P07
11
14
P11
GND
12
13
P10
Figure 1. Pin configuration for
SOP24/SSOP24/TSSOP24 (TOP VIEW)
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11
12
P11
P12
ePAD
EXPOSED
THERMAL PAD
P10
P05
P17
16
P01
P16
9
P04
17
P17
8
7
A0
19
P07
P03
18
20
XL9535
or
XL9555
GND
6
XL9535/XL9555
7
5
1
P06
P01
P02
P00
SDA
22
4
SCL
3
19
A2
P00
Pin 1 index
20
SDA
VCC
23
21
2
INT
A1
A1
VCC
22
24
A2
1
24
INT
23
Fred.W.XLD.XINLUDA
Figure 2. Pin configuration for
QFN24 (TOP VIEW)
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Rev 2.3
XL9535, XL9555
Product datasheet
Table 2. Pin Functions
PIN NUMBER
PIN
DESCRIPTION
NAME
SOP/SSOP/TSSOP
QFN
INT
1
22
Interrupt output (open-drain). Connect to V CC through a pull-up resistor.
A1
2
23
Address input 1. Connect directly to V CC or ground.
A2
3
24
Address input 2. Connect directly to V CC or ground.
P00
4
1
P01
5
2
P02
6
3
P03
7
4
Port 0 input/output. Push-pull design structure. At power on, P00-P07 are
P04
8
5
configured as an input. [1]
P05
9
6
P06
10
7
P07
11
8
GND
12
9 [2]
P10
13
10
P11
14
11
P12
15
12
P13
16
13
Port 1 input/output. Push-pull design structure. At power on, P10-P17 are
P14
17
14
configured as an input. [1]
P15
18
15
P16
19
16
P17
20
17
A0
21
18
Address input 0. Connect directly to V CC or ground.
SCL
22
19
Serial clock line. Connect to VCC through a pull-up resistor.
SDA
23
20
Serial data line. Connect to V CC through a pull-up resistor.
VCC
24
21
Supply voltage.
ePAD
-
Y
[2]
Supply ground.
Exposed thermal pad. Connect directly to ground.
[1]
XL9535 and XL9555 I/Os are totem pole. For XL9555 inside, note that there is a high value resistor tied to V CC at each pin.
[2]
QFN24 package die supply ground is connected to both the GND pin and the exposed thermal pad(ePAD). The GND pin must be
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the ePAD
needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the
board thermal vias need to be incorporated in the PCB in the thermal pad region.
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Rev 2.3
XL9535, XL9555
Product datasheet
5. FUNCTIONAL BLOCK DIAGRAM
Fred.W.XLD.XINLUDA
XL9535 or XL9555
VCC
1
INT
LP
Filter
21
2
3
A0
A1
A2
8 Bits
Write Pulse
22
SCL
Input
Filter
23
SDA
I/O
Port
(0)
11-4
P07-P00
Read Pulse
I2C-BUS/SMBus
Control Logic
24
VCC
8 Bits
Power-On
Reset
Write Pulse
12
GND
REMARK:
Interrupt
Logic
I/O
Port
(1)
20-13
P17-P10
Read Pulse
(1)
All I/Os are set to inputs at reset.
(2)
Pin numbers shown are for the TSSOP24 package.
Figure 3. Block Diagram
6. SPECIFICATIONS
6.1. Absolute Maximum Ratings [3]
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VCC
Supply voltage range
-0.5
+6
V
VIN
Input pin voltage range [4]
-0.5
+6
V
VO
Output pin voltage range [4]
-0.5
+6
V
IIK
Input clamp current
VIN
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