2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Features
NAND Flash Memory
Serial Peripheral Interface (SPI)
Features
• Security
– Blocks 7:0 are valid when shipped from factory
with ECC enabled
– Software write protection with lock register
– Hardware write protection to freeze BP bits
– Lock tight to freeze BP bits during one power cycle
• Permanent block lock protection
– OTP Space: 10 pages one-time programmable
NAND Flash memory area
• Operating voltage range
– VCC = 2.7–3.6V
• Operating temperature
– Industrial: –40°C to +85°C
• Quality and reliability
– Endurance:100,000PROGRAM/ERASEcycles
– Data retention: JESD47H-compliant; see qualification report
– Additional: Uncycled data retention: 10 years
24/7 @85°C
• Package
– 16-pin SOP, 300 mils
– 8-pinWSON,6mmx8mm x0.8mm
– 24-ball T-PBGA, 05/6mm x 8mm
• Single-level cell (SLC) technology
• 2Gb density
• Organization
– Page size x1: 2176 bytes (2048 + 128 bytes)
– Block size: 64 pages (128K + 8K bytes)
– Planesize:2Gb (2planes,1024blocks per plane)
• Standard and extended SPI-compatible serial bus
interface
– Instruction, address on 1 pin; data out on 1, 2, or
4 pins
– Instructionon1pin;address,dataouton2or4
pins
– Instruction,addresson1pin;datainon1or4
pins
• User-selectable internal ECC supported
– 8 bits/sector
• Array performance
– 133 MHz clock frequency (MAX)
– Page read: 25µs (MAX) with on-die ECC disabled;
70µs (MAX) with on-die ECC enabled
– Page program: 200µs (TYP) with on-die ECC disabled; 220µs (TYP) with on-die ECC enabled
– Block erase: 2ms (TYP)
• Advanced features
– Read page cache mode
– Read unique ID
– Read parameter page
• Device initialization
– Automatic device initialization after power-up
1
.
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Features
Part Numbering Information
Figure 1: Part Number Chart
2
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Features
Contents
GeneralDescription......................................................................................................................................................................7
Architecture.........................................................................................................................................................................................................8
PinAssignments............................................................................................................................................................................ 9
Pin Descriptions.......................................................................................................................................................................... 10
Memory Mapping........................................................................................................................................................................ 11
Array Organization......................................................................................................................................................................................... 11
BusOperation.............................................................................................................................................................................. 12
SPI Modes................................................................................................................................................................................. 12
SPI Protocols............................................................................................................................................................................ 12
SPI NAND Command Definitions............................................................................................................................................ 13
RESET Operation............................................................................................................................................................................................ 14
WRITEOperations...................................................................................................................................................................... 15
WRITE ENABLE (06h)...............................................................................................................................................................................15
WRITE DISABLE (04h)............................................................................................................................................................................. 15
READ Operations............................................................................................................................................................................................ 16
PAGEREAD(13h)....................................................................................................................................................................16
READ FROM CACHE x1 (03h or 0Bh)................................................................................................................................................. 18
READ FROM CACHE x2 (3Bh)...............................................................................................................................................................19
READ FROM CACHE x4 (6Bh)...............................................................................................................................................................20
READ FROM CACHE Dual I/O (BBh)................................................................................................................................................. 21
READ FROM CACHE Quad I/O (EBh)................................................................................................................................................ 22
READ PAGE CACHE RANDOM (30h)..................................................................................................................................................23
READ PAGE CACHE LAST (3Fh)...........................................................................................................................................................25
READ ID (9Fh)......................................................................................................................................................................... 25
ParameterPage............................................................................................................................................................................ 26
Parameter Page Data Structure Table...................................................................................................................................................... 26
Unique ID Page.............................................................................................................................................................................27
Program Operations....................................................................................................................................................................................... 29
PAGE PROGRAM........................................................................................................................................................................................ 29
PROGRAMLOADx1(02h).....................................................................................................................................................29
PROGRAM EXECUTE (10h)................................................................................................................................................................... 30
RANDOM DATAPROGRAM x1 (84h).................................................................................................................................. 32
PROGRAM LOAD x4 (32h) and PROGRAM LOAD RANDOM DATA x4 (34h)....................................................................... 33
INTERNAL DATAMOVE........................................................................................................................................................ 33
Block Erase Operations.................................................................................................................................................................................34
Features Operations.......................................................................................................................................................................................36
GET FEATURES (0Fh) and SET FEATURES (1Fh)..........................................................................................................................36
Feature Settings..........................................................................................................................................................................................37
Security – Volatile Block Protection.......................................................................................................................................................... 38
Security – Block Protection Bits................................................................................................................................................................. 38
Security – Hardware Write Protection......................................................................................................................................................39
Security – Device Lock Tight (LOT)...........................................................................................................................................39
Permanent Block Lock Protection.............................................................................................................................................................39
PROTECTION Command (2Ch) Details.............................................................................................................................................40
PermanentBlockLockProtectionDisableMode............................................................................................................. 40
Security– One Time Programmable (OTP)............................................................................................................................. 41
EnableOTPAccess................................................................................................................................................................. 41
OTP Configuration States....................................................................................................................................................................... 41
OTPProtection andProgramPrevention........................................................................................................................... 42
Exit OTP.................................................................................................................................................................................... 42
3
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Features
Status Register........................................................................................................................................................................... 43
ECC Protection............................................................................................................................................................................44
Error Management.................................................................................................................................................................... 46
SPI NOR Read Configuration.................................................................................................................................................. 47
Power-Up and Power-Down......................................................................................................................................................50
Electrical Specifications...........................................................................................................................................................52
Package Dimensions................................................................................................................................................................. 57
Package Dimensions............................................................................................................................................................ 58
Package Dimensions............................................................................................................................................................ 59
Revision History..........................................................................................................................................................................60
Rev. C –2021/ 06/15........................................................................................................................................................... 60
4
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Features
List of Figures
Figure1: Part Number Chart......................................................................................................................................................2
Figure2: FunctionalBlock Diagram.........................................................................................................................................8
Figure 3: 8-Pin, U-PDFN (Top View)......................................................................................................................................... 9
Figure 4: 16-Pin, SOP2 (Top View).............................................................................................................................................9
Figure5: 24-BallT-PBGA,5 x 5 (Balls Down)...........................................................................................................................9
Figure 6: Memory Map.............................................................................................................................................................. 11
Figure7: ArrayOrganization....................................................................................................................................................11
Figure 8: SPI Modes Timing......................................................................................................................................................12
Figure9: RESET (FFh)Timing..................................................................................................................................................14
Figure10: WRITEENABLE (06h)Timing............................................................................................................................... 15
Figure11: WRITEDISABLE(04h)Timing.............................................................................................................................. 15
Figure12: PAGEREAD (13h)Timing...................................................................................................................................... 17
Figure13: READ FROMCACHE (03hor0Bh)Timing......................................................................................................... 18
Figure14: READFROMCACHE x2......................................................................................................................................... 19
Figure15: READFROMCACHE x4......................................................................................................................................... 20
Figure16: READFROMCACHEDualI/O............................................................................................................................. 21
Figure17: READFROMCACHEQuadI/O............................................................................................................................ 22
Figure 18: READ PAGE CACHE RANDOM Sequence....................................................................................................................... 24
Figure 19: READ ID (9Fh) Timing............................................................................................................................................ 25
Figure20: PROGRAM LOAD (02h)Timing............................................................................................................................ 30
Figure 21: PROGRAM EXECUTE (10h) Timing................................................................................................................................... 31
Figure22: PROGRAM LOAD RANDOM DATA(84h)Timing.............................................................................................. 32
Figure23: PROGRAMLOAD x4 (32h)Timing....................................................................................................................... 33
Figure 24: BLOCK ERASE (D8h) Timing................................................................................................................................................35
Figure 25: GET FEATURES (0Fh) Timing.............................................................................................................................................. 36
Figure 26: SET FEATURES (1Fh) Timing...............................................................................................................................................36
Figure27: PROTECTCommandCycle................................................................................................................................... 40
Figure 28: Read from Cache (03h)...........................................................................................................................................48
Figure29: FastRead from Cache (0Bh).................................................................................................................................. 49
Figure 30: SPI Power-Up............................................................................................................................................................50
Figure 31: SPI Power-UpTiming..............................................................................................................................................50
Figure32: Alternative SPI Power-UpTiming.........................................................................................................................51
Figure33: ACMeasurementI/OWaveform.......................................................................................................................... 52
Figure 34: WP# Timing...............................................................................................................................................................55
Figure35: Serial InputTiming................................................................................................................................................. 56
Figure36: SerialOutputTiming.............................................................................................................................................. 56
Figure37: 16-pinSOP (300 milsbodywidth) ........................................................................................................................57
Figure38: 8-pin WSON 6mm x 8mm .....................................................................................................................................58
Figure39: 24-PinT-PBGA(5 x5 Ball GridArray)6mm x8mm...........................................................................................59
5
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Features
List of Tables
Table 1: SPI Pin Descriptions .........................................................................................................................................
Table 2: SPI NAND Command Set ..................................................................................................................................
Table 3: READ ID Table .................................................................................................................................................
Table 4: Parameter Table ...............................................................................................................................................
Table 5: Feature Address Settings and Data Bits ...........................................................................................................
Table 6: Block Lock Register Block Protect Bits .............................................................................................................
Table 7: Configuration Registers for Security .................................................................................................................
Table 8: Status Register Bit Descriptions .......................................................................................................................
Table 9: ECC Status Register Bit Descriptions ...............................................................................................................
Table 10:ECC Protection .................................................................................................................................................
Table 11:Error Management Details ...............................................................................................................................
Table 12:Absolute Maximum Ratings ..............................................................................................................................
Table 13:Operating Conditions .......................................................................................................................................
Table 14:AC Measurement Conditions ............................................................................................................................
Table 15:Capacitance ................................................................................................................................................................
Table 16:DC Characteristics ...........................................................................................................................................
Table 17:AC Characteristics ...........................................................................................................................................
Table 18:PROGRAM/READ/ERASE Characteristics .......................................................................................................
6
10
13
25
26
37
38
42
43
44
45
46
52
52
52
53
53
53
54
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
General Description
General Description
Serial peripheral interface (SPI) NAND is an SLC NAND Flash memory device that
provides a cost-effective nonvolatile memory storage solution where pin count
must be kept to a minimum. It is also an alternative solution to SPI NOR, offering
superior write performance and cost per bit over SPI NOR. The hardware
interface creates a low pin count device with a standard pin out that remains the
same from one density to another and supports future upgrades to higher
densities without board redesign.
The serial electrical interface follows the industry-standard serial peripheral interface.
New command protocols and registers are defined for SPI operation. The command set
resembles common SPI-NOR command sets, modified to handle NAND specific
functions and additional new features.
New features include user-selectable internal ECC and first page auto-load on
power- up.SPI NAND Flash devices have six signal lines plus VCC and ground
(GND).The signal lines are SCK (serial clock), SI, SO (for command/response and data
input/output), and control signals CS, HOLD#, WP#. This hardware interface creates
a low pin-count device with a standard pinout that remains the same from one density
to another, supporting future upgrades to higher densities without board
redesign.
Each block of the serial NAND Flash device is divided into 64 programmable
pages, each page consisting of 2176 bytes. Each page is further divided into a
2048-byte data storage region and a 128-byte spare area. The 128-byte area is
typically used for memory and error management functions.
With internal ECC enabled as the default after poweron, ECC code is generated
internally when a page is written to the memory core. The ECC code is stored
in the spare area of each page.When a page is read to the cache register,the
ECC code is calculated again and compared with the stored value. Errors are
corrected if necessary. The device either outputs corrected data or returns an ECC
error status. The internal ECC can be configured off after device initialization.
Contact Zetta representative if ECC is required to be default off after power on.
The first eight blocks are valid when shipped from factory. Security functions are
also provided including software block protection: Lock tight and hardware
protection modes avoid array data corruption.
7
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Architecture
Architecture
The devices use an industry-standard NAND Flash memory coreorganized by
page/block. The standard parallel NAND Flash electrical interface and I/O logic are
replaced by an SPI interface. The new command protocol set is a modification
of the SPI NOR command set available in the industry. The modifications are
specifically to handle functions related to NAND Flash architecture. The interface
supports page and random read/write and internal data move functions. The device
also includes an internal ECC feature.
Data is transferred to or from the NAND Flash memory array,page-by-page, to a
cache register and a data register. The cache register is closest to I/O control circuits
and acts as a data buffer for the I/O data;the data register is closest to the
memory array and acts as a data buffer for the NAND Flash memory array
operation.
The NAND Flash memory array is programmed and read in page-based operations; it is
erased in block-based operations. The cache register functions as the buffer memory to
enable random data READ/WRITE operations. These devices also use a new SPI status
register that reports the status of device operation.
Figure 2: Functional Block Diagram
8
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Pin Assignments
Pin Assignments
Figure 3: 8-Pin, WSON (Top View)
CS#
1
8
VCC
SO/IO1
2
7
HOLD#/IO3
WP#/IO2
3
6
SCK
VSS
4
5
SI/IO0
Figure 4: 16-Pin, SOP2 (Top View)
HOLD#/IO3
1
16
SCK
VCC
2
15
SI/IO0
DNU
3
14
DNU
DNU
4
13
DNU
DNU
5
12
DNU
DNU
6
11
DNU
CS#
7
10
SO/IO1
VSS
8
9
WP#/IO2
Figure 5: 24-Ball T-PBGA, 5 x 5 (Balls Down)
1
2
3
4
5
DNU
DNU
DNU
DNU
DNU
SCK
VSS
VCC
DNU
DNU
CS#
DNU
WP#/IO2
DNU
DNU
S0/IO1
S1/IO0
HOLD#/IO3
DNU
DNU
DNU
DNU
DNU
DNU
A
B
C
D
E
9
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Pin Descriptions
Pin Descriptions
Table 1: SPI Pin Descriptions
Symbol
Type
Description
CS#
Input
Chip select: Places the device in active power mode when driven LOW. Deselects the device and places SO at High-Z when HIGH. After power-up, the device requires a falling
edge on CS# before any command can be written.
The device goes into standby mode when no PROGRAM, ERASE, or WRITE STATUS REGISTER operation is in progress.
In the case of write-type instructions, CS# must be driven HIGH after a whole sequence is
completed. Single command and address sequences and array-based operations are registered on CS#.
SCK
Input
Serial clock: Provides serial interface timing. Latches commands, addresses, and data on
SI on the rising edge of SCK. Triggers output on SO after the falling edge of SCK. While
CS# is HIGH, keep SCK at VCC or GND (determined by mode 0 or mode 3). Do not toggle
SCK until CS# is driven LOW.
WP#
Input
Write protect: When LOW, prevents overwriting block lock bits (BP[3:0] and TB) if the
block register write disable (BRWD) bit is set.
WP# must not be driven by the host during a x4 READ operation. If the device is deselected, this pin defaults as an input pin.
HOLD#
Input
Hold: Hold functionality is disabled by default except the special part numbers. Contact
Zetta Sales representatives for details. When enabled, the external pull-up resistor is
necessary to avoid accidental operation being placed on hold.
HOLD# pauses any serial communication with the device without deselecting it. To start
the HOLD condition, the device must be selected, with CS# driven LOW. During HOLD status (HOLD# driven LOW), SO is High-Z and all inputs at SI and SCK are ignored. Hold
mode starts at the falling edge of HOLD#, provided SCK is also LOW. If SCK is HIGH when
HOLD# goes LOW, hold mode is kicked off at the next falling edge of SCK. Similarly, hold
mode is exited at the rising edge of HOLD#, provided SCK is also LOW. If SCK is HIGH,
hold mode ends after the next falling edge of SCK. HOLD# must not be driven by the host
during the x4 READ operation.
SI/IO0, SO/IO1,
IO2, IO3
I/O
Serial I/O: The bidirectional I/O signals transfer address, data, and command information.
The device latches commands, addresses, and data on the rising edge of SCK, and data is
shifted out on the falling edge of the SCK. If the device is deselected, IO[0,2] defaults as
an input pin and IO[1,3] defaults as an output pin.
VCC
Supply
VCC: Supply voltage
VSS
Supply
VSS: Ground
DNU
–
Do not use: Must be left floating.
NC
–
No Connect: Not internal connection; can be driven or floated.
SI must not be driven by the host during x2 or x4 READ operations.
10
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Memory Mapping
Memory Mapping
Figure 6: Memory Map
Blocks
RA[16:6]
0
1
2
Pages
RA[5:0]
0
1
••• •••
Bytes
CA[11:0]
0
1
2
Notes:
• • • • • • • • • • • •• • •• • •• • • 2047
63
• • • • • • • • • • • • • • • • • • • • • • • •• • •• • •• • •• • •• • •• • •
2175
1. The 12-bit column address is capable of addressing from 0 to 4095 bytes; however, only
bytes 0 through 2175 are valid. Bytes 2176 through 4095 of each page are “out of
bounds,” do not exist in the device, and cannot be addressed.
2. Block RA6 controls the plane selection.
Array Organization
Figure 7: Array Organization
11
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Bus Operation
Bus Operation
SPI Modes
The device can be driven by a micro controller with its SPI running in
either of two modes depending on clock polarity (CPOL) and clock phase
(CPHA) settings:
• CPOL = 0, CPHA = 0 (Mode 0)
• CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched in on the rising edge of SCK, and output data is available
fromthe falling edge of SCK for both modes.
Thedifference between the two modes,shown here,is the clock polarity when
the bus master is in standby mode and not transferring data.
• SCK remains at 0 for CPOL = 0, CPHA = 0 (Mode 0)
• SCK remains at 1 for CPOL = 1, CPHA = 1 (Mode 3)
Figure 8: SPI Modes Timing
CPOL CPHA
0
0
SCK
1
1
SCK
SI
MSB
LSB
MSB
SO
LSB
CS#
Notes:
1. While CS# is HIGH, keep SCK at VCC or GND (determined by mode 0 or mode 3). Do not
begin toggling SCK until after CS# is driven LOW.
2. All timing diagrams shown in this data sheet are mode 0.
SPI Protocols
Standard SPI: Command, address, and data are transmitted on a single data line. Input
on SI is latched in on the rising edge of SCK. Output on SO is available on
the falling edge of SCK.
Extended SPI: An extension of the standard SPI protocol. Command and address
are transmitted on a single data line through SI. Data are transmitted on two or four
data lines, IO[3:0], depending on the command.
12
2Gb 3.3V x1, x2, x4: SPI NAND Flash Memory
SPI NAND Command Definitions
SPI NAND Command Definitions
Table 2: SPI NAND Command Set
Command
Op Code
Address Dummy
Bytes
Bytes
Data
Bytes
Comments
RESET
FFh
0
0
0
Reset the device
GET FEATURES
0Fh
1
0
1
Get features
SET FEATURES
1Fh
1
0
1
Set features
READ ID
9Fh
0
1
2
Read device ID
PAGE READ
13h
3
0
0
Array read
READ PAGE CACHE RANDOM
30h
3
0
0
Cache read
READ PAGE CACHE LAST
3Fh
0
0
0
Ending of cache read
READ FROM CACHE x1
03h, 0Bh
2
1
1 to 2176 Output cache data at column address
READ FROM CACHE x2
3Bh
2
1
1 to 2176 Output cache data on IO[1:0]
READ FROM CACHE x4
6Bh
2
1
1 to 2176 Output cache data on IO[3:0]
READ FROM CACHE Dual
IO
BBh
2
1
1 to 2176 Input address/Output cache data on IO[1:0]
READ FROM CACHE Quad
IO
EBh
2
2
1 to 2176 Input address/Output cache data on IO[3:0]
WRITE ENABLE
06h
0
0
0
Sets the WEL bit in the status register to 1; required to enable operations that change the content of the memory array
WRITE DISABLE
04h
0
0
0
Clears the WEL bit in the status register to 0; required to disable operations that change the
content of the memory array
BLOCK ERASE
D8h
3
0
0
Block erase
PROGRAM EXECUTE
10h
3
0
0
Array program
PROGRAM LOAD x1
02h
2
0
1 to 2176 Load program data into cache register on SI
PROGRAM LOAD x4
32h
2
0
1 to 2176 Load program data into cache register on SO[3:0]
PROGRAM LOAD RANDOM
DATA x1
84h
2
0
1 to 2176 Overwrite cache register with input data on SI
PROGRAM LOAD RANDOM
DATA x4
34h
2
0
1 to 2176 Overwrite cache register with input data on
SO[3:0]
PERMANENT BLOCK LOCK
PROTECTION
2Ch
3
0
0
13
Permanently protect a specific group of blocks
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
RESET Operation
RESET Operation
The RESET command (FFh) is used to put the memory device into a known
condition and to abort the command sequence in progress. READ, PROGRAM, and
ERASE commands can be aborted while the device is in the busy state.Once the
RESETcommand is issued to the device, it will take tPOR to reset. During this
period, the GET FEATURE command could be issued to monitor the status
(OIP) except for 4Gb stacked device. For 4Gb stacked device, no command
should be issued until tPOR.The contents of the memory location being
programmed or the block being erased are no longer valid.The first page data
of the first block is auto-loaded to the cache register.
All other status register bits will be cleared. The ECC status register bits will be updated
after a reset. The configuration register bits CFG[2:0] will be cleared after a reset. All the
other configuration register bits will not be reset.The block lock register bits
will not be cleared after reset until the device is power cycled or is written to
by SET FEATURE command.
Figure 9: RESET (FFh) Timing
0
1
2
3
SCK
Command (FFh)
CS#
SI
SO
High-Z
14
4
5
6
7
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
WRITE Operations
WRITE Operations
WRITE ENABLE (06h)
The WRITE ENABLE (06h) command sets the WEL bit in the status register to 1. Write
enable is required in the following operations that change the contents of the
memory array:
• PAGE PROGRAM
• OTP AREA PROGRAM
• BLOCK ERASE
Figure 10: WRITE ENABLE (06h) Timing
0
1
2
3
4
5
6
7
SCK
CS#
Command (06h)
SI
WRITE DISABLE (04h)
The WRITE DISABLE (04h) command clears the WEL bit in the status register to 0,
disabling the following operations:
• PAGE PROGRAM
• OTP AREA PROGRAM
• BLOCK ERASE
Figure 11: WRITE DISABLE (04h) Timing
0
1
2
3
4
5
SCK
CS#
Command (04h)
SI
15
6
7
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
READ Operations
READ Operations
PAGE READ (13h)
The PAGE READ (13h) command transfers data from the NAND Flash array to the cache
register. It requires a 24-bit address consisting of 7 dummy bits and a 17-bit
block/page address (8 dummy bits followed by an 16-bit block/page address for
1Gb). After the block/page addressis registered, the device starts the transfer
from the main array to the cache register. During this data transfer busy time of tRD,
the GET FEATURES command can be issued to monitor the operation.
Following successful completion of PAGE READ,the READ FROM CACHE
command must be issued to read data out of cache.The command sequence is
as follows to transfer data from array to output:
•
•
•
•
•
•
•
13h (PAGE READ command to cache)
0Fh (GET FEATURES command to read the status)
03h or 0Bh (READ FROM CACHE)
3Bh (READ FROM CACHE x2)
6Bh (READ FROM CACHE x4)
BBh (READ FROM CACHE Dual I/O)
EBh (READ FROM CACHE Quad I/O)
16
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
READ Operations
Figure 12: PAGE READ (13h) Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCK
CS#
Command (13h)
Address bits
SI
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
High-Z
SO
1
23
24
25
26
27
28
29
30
0
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
CS#
tCS
Address bits
SI
8
7
6
5
4
3
2
1
GET FEATURES (0Fh)
Status register address (C0h)
7
0
6
5
4
3
2
MSB
High-Z
SO
1
13
14
2
15
16
17
18
19
20
21
22
23
SCK
CS#
SI 2
1
0
Status register data out
Status register data out
7
SO
MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
2
Don’t Care
17
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
READ Operations
READ FROM CACHE x1 (03h or 0Bh)
The READ FROM CACHE x1 command enables sequentially reading one or more data
bytes from the cache buffer. The command is initiated by driving CS# LOW, shifting in
command opcode 03h/0Bh, followed by a 16 bit column address and 8-bit
dummy clocks. Both the commands run at fast mode.
Data is returned from the addressed cache buffer,MSB first,on SO at the falling
edge of SCK.The address is automatically incremented to the next higher
address after each byte of data is shifted out,enabling a continuous stream of
data.This command is completed by driving CS# HIGH.
Figure 13: READ FROM CACHE (03h or 0Bh) Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCK
CS#
Command (03h or 0Bh)
3 dummy bits
0
SI
0
12-bit column address
0
12
11
10
9
8
7
6
5
1 dummy byte
4
3
2
1
0
MSB
Plane select
High-Z
SO
1
SCK
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
17431...
17439
CS#
1 dummy byte
SI
High-Z
0
Data out 1
SO
High-Z
7
6
5
4
3
Data out 2176
2
1
0
MSB
7
6
5
4
3
2
1
0
MSB
1
Don’t Care
Note:
1. Plane select is a dummy bit for 1Gb devices.
18
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
READ Operations
READ FROM CACHE x2 (3Bh)
The READ FROM CACHE x2 (3Bh) command is similar to READ FROM CACHE x1 (03h
or0Bh) except that data is output on the following two pins, enabling data
transfer at twice the rate: IO0(SI) and IO1(SO).
Figure 14: READ FROM CACHE x2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCK
CS#
Command (3Bh)
3 dummy bits
0
SI
0
12-bit column address
0
12
Plane select
10
11
9
8
7
6
5
4
1 dummy byte
3
2
1
0
MSB
High-Z
SO
1
SCK
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
8727...
8735
CS#
1 dummy byte
SI
High-Z
SO
High-Z
SI switches from input to output
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Data out 1
1
Note:
Data out 2
1. Plane select is a dummy bit for 1Gb devices.
19
Data out 2175
Data out 2176
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
READ Operations
READ FROM CACHE x4 (6Bh)
The READ FROM CACHE x4 (6Bh) command is similar to READ FROM CACHE x1 command, but with the capability to output data across four data lines.
Figure 15: READ FROM CACHE x4
0
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CS#
Command
3 dummy bits
SI/
IO0
0
0
12-bit column address
0
12
11
High-Z
WP#/
IO2
High-Z
HOLD#/
IO3
High-Z
9
8
7
6
5
4
3
2
1
0
MSB
Plane select
SO/
IO1
10
1 dummy byte
1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
SCK
CS#
1 dummy byte
SI/
IO0
High-Z
SO/
IO1
High-Z
WP#/
IO2
High-Z
HOLD#/
IO3
High-Z
SI switches from input to output
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
Byte 1
1
Note:
Byte 2
Byte 3
Byte 4
1. Plane select is a dummy bit for 1Gb devices.
20
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
READ Operations
READ FROM CACHE Dual I/O (BBh)
The READ FROM CACHE Dual IO (BBh) command enables improved random access
while maintaining two IO pins, IO0 and IO1. It is similar to the READ FROM CACHE x2
(3Bh) command but with capability to input either the column address or the
dummy clocks two bits per clock, thereby reducing command overhead. Refer to the
Electrical Specifications for the supported frequency.
Figure 16: READ FROM CACHE Dual I/O
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SCK
Command (BBh)
CS#
Plane select
SI
IO0
4 dummy cycles
12
SO
IO1
3
23
SCK
CS#
24
data out 1
25
26
27
28
data out 2
29
30
dummy
bits
31
32
data out 3
data out 1
10
8
6
4
2
0
6
4
11
9
7
5
3
1
7
5
12-bit column address
33
34
35
36
data out 4
37
38 . . . . . . 8716
data out x
8717
8718
8719
8720
data out 2175
8721
8723
8722
8724
data out 2176
SI
IO0
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
SO
IO1
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Don’t Care
Note:
1. Plane select is a dummy bit for 1Gb devices.
21
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
READ Operations
READ FROM CACHE Quad I/O (EBh)
The READ FROM CACHE Quad I/O (EBh) command is similar to the READ
FROM CACHE Dual I/O (BBh) command except that address and data bits are
input and output through four pins: IO0, IO1, IO2, and IO3. The quad IO dramatically
reduces command overhead, enabling faster random access to the cache buffer.
Refer to the Electrical Specifications for the supported frequency.
Figure 17: READ FROM CACHE Quad I/O
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SCK
Command
CS#
Plane select
S1
IO0
12
4 dummy cycles
data
out 1
data
out 2
data
out 3
data
out 4
8
4
0
4
0
4
0
4
0
4
S0
IO1
9
5
1
5
1
5
1
5
1
5
WP#
IO2
10
6
2
6
2
6
2
6
2
6
HOLD#
IO3
11
7
3
7
3
7
3
7
3
7
3 dummy
bits
12-bit
column address
23
24
25
26
27 . . . . 4363
4364
4365
4366
4367
SCK
data
out 4
data
out 5
data
out 5
Data
out x
CS#
data
out
2175
data
out
2176
SI
IO0
0
4
0
4
0
4
0
4
0
4
0
4
SO
IO1
1
5
1
5
1
5
1
5
1
5
1
5
WP#
IO2
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#
IO3
3
7
3
7
3
7
3
7
3
7
3
7
Note:
1. Plane select is a dummy bit for 1Gb devices.
22
Don’t Care
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
READ Operations
READ PAGE CACHE RANDOM (30h)
The READ PAGE CACHE RANDOM(30h) command reads the specified block
and page into the data register while the previous page is output from the
cache register. This command is accepted by the die when it is ready (OIP =0,
CRBSY =0). This command is used to improve the read through put as follows:
1. 13h – PAGE READ to cache
2. 0Fh – GET FEATURE command to the read status until OIP status bit is changed
from 1 to 0
3. 30h – READ PAGE CACHE RANDOM command to transfer data from data
register to cache register and kick off the next page transfer from array to
data register
4. 0Fh – GET FEATURE command to read the status until OIP status bit is
changed from 1 to 0
5. 03h, 0Bh, 3Bh, 6Bh, BBh, or EBh – READ FROM CACHE TO OUTPUT
command
6. 0Fh – GET FEATURE command to read the status until CRBSY = 0
7. Repeat step 3 to step 6 to read out all expected pages until last page
8. 3Fh – READ PAGE CACHE LAST command to end the read page cache sequence
and copy a last page from the data register to the cache register
9. 0Fh – GET FEATURE command to read the status until OIP status bit is
changed from 1 to 0
10. 03h, 0Bh, 3Bh, 6Bh, BBh, or EBh – READ FROM CACHE TO OUTPUT command to
read out last page from cache register to output
The READ PAGE CACHE RANDOM command requires a 24 bit address consisting
of 8 dummy bits followed by a 16-bit block/page address for 1Gb device or 7
dummy bits followed by a 17-bit block/page address for 2Gb or higher devices. After
the block/page addresses are registered,the device starts to transfer data from
data register to cache register for tRCBSY. After tRCBSY, OIP bit (through GET
FEATURE command to check this status bit) goes to 0 from1, indicating that
the cache register is available and that the specified page in the READ PAGE
CACHE RANDOM command is copying from the the Flash array to the data
register. At this point, data can be output from the cache register beginning at the
column address specified by READ FROM CACHE commands.
The status register CRBSY bit value remains at 1, indicating that the specified page in
READ PAGE CACHE RANDOM command is copying from the Flash array to
the data register; CRBSY returns to 0 to indicating the copying from array is
completed. During tRCBSY, the error check and correction is also performed.
Note:With an on-die ECC-enabled die,ECC is executed after data is
transferred from the data register to the cache register; therefore, tRCBSY
includes this ECC time, which must be factored in when checking the OIP status.
23
Figure 18: READ PAGE CACHE RANDOM Sequence
0
1
2
3
4
5
6
7
8
9
10
23
22
21
11
12
13
14
15
28
29
3
2
30
31
SCK
CS#
tRD
Page x
SI
13h
20
19
18
17
16
1
0
SO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
28
29
30
31
0
1
2
3
4
5
6
7
8
9
10
11
12
22
23
1
0
24
25
30
31
32
SCK
CS#
t
RCBSY
Page y
SI
23
30h
22
21
20
19
18
Dummy byte
17
16
3
2
1
0
11
03h
MSB
SO
Page x data 1
6
7
5
4
3
2
MSB
1
0
7
1
1
2
3
4
5
6
7
8
9
10
11
12
26
27
28
29
30
31
0
1
6
7
8
29
30
31
24
CS#
Page Z
SI
MSB
SO
23
30h
Page x data 2
7
6
5
4
3
2
MSB
1
0
7
t
22
21
20
19
4
3
2
1
RCBSY
0
03h
Page x data n
6
5
4
3
2
1
0
7
6
1
0
2
1
0
1
2
3
4
5
6
7
0
1
6
7
8
29
30
31
SCK
CS#
Read page cache last
3Fh
SI
MSB
SO
MSB
Page Y data 2
7
6
5
4
3
2
1
0
7
tRCBSY
03h
MSB
6
5
4
3
2
1
0
7
Page Z data n
Page Z data 1 Page Z data 2
6
0
7
0
7
6
0
7
6
0
2
Don’t Care
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
READ Operations
0
SCK
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
READ Operations
READ PAGE CACHE LAST (3Fh)
The READ PAGECACHELAST(3Fh) command ends the READ PAGE CACHE
RANDOM
Sequence and copies a page from the data register to the cache register. This
command is accepted by the die when it is ready (OIP = 0, CRBSY = 0). After this
command is issued, the status register bit OIP goes HIGH and the device is
busy (CRBSY =0, OIP = 1) for tRCBSY. Address is not applied in this command
sequence. When data is completely copied to cache register,OIP goes LOW and
READ FROM CACHE commands could be issued to output data.
READ ID (9Fh)
READ ID reads the 2-byte identifier code programmed into the device, which includes
ID and device configuration data as shown in the table below.
Table 3: READ ID Table
Byte
Description
7
6
5
4
3
2
1
0
Value
Byte 0
Manufacturer ID
0
0
1
0
1
1
0
0
2Ch
Byte 1
2Gb 3.3V Device ID
0
0
1
0
0
1
0
0
24h
Figure 19: READ ID (9Fh) Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCK
CS#
Command (9Fh)
Dummy byte
0
SI
0
0
0
0
0
0
0
Manufacturer ID
High-Z
SO
Device ID
7
6
MSB
23
24
25
26
27
28
29
30
1
31
SCK
CS#
SI
Device ID
SO
7
6
5
4
3
2
1
0
MSB
Don’t Care
1
25
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Parameter Page
Parameter Page
The following command flow must be issued by the memory controller to
access the parameter page contained within Zetta SPI devices:
1. 1Fh – SET FEATURES command with a feature address of B0h and data value
for CFG[2:0] = 010b ( to access OTP/Parameter/UniqueID pages).
2. 13h – PAGE READ command with a block/page address of 0x01h, and then check
the status of the read completion using the GET FEATUR ES (0Fh) command with
a feature address of C0h.
3. 03h – READ FROM CACHE command with an address of 0x00h to read the
data outof the NAND device(see the following Parameter Page Data
Structure table for a description of the contents of the parameter page.)
4. 1Fh – SET FEATURES command with a feature address of B0h and data
value of 00h to exit the parameter page reading.
Parameter Page Data Structure Table
Table 4: Parameter Table
Byte
Description
Value (hex)
0-3
Parameter page signature
4Fh, 4Eh, 46h, 49h
4-5
Revision number
00h
6-7
Feature support
00h
8-9
Optional commands support
06h, 00h
10-31
Reserved
00h
32-43
Device manufacturer
4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h, 20h, 20h
44-63
Device model
4Dh, 54h, 32h, 39h, 46h, 32h, 47h, 30h, 31h, 41h, 42h, 41h, 47h,
44h, 53h, 46h, 20h, 20h, 20h, 20h
44-63
Device model
4Dh, 54h, 32h, 39h, 46h, 32h, 47h, 30h, 31h, 41h, 42h, 41h, 47h,
44h, 31h, 32h, 20h, 20h, 20h, 20h
44-63
Device model
4Dh, 54h, 32h, 39h, 46h, 32h, 47h, 30h, 31h, 41h, 42h, 41h, 47h,
44h, 57h, 42h, 20h, 20h, 20h, 20h
64
Manufacturer ID
2Ch
65-66
Date code
00h
67-79
Reserved
00h
80-83
Number of data bytes per page
00h, 08h, 00h, 00h
84-85
Number of spare bytes per page
80h, 00h
86-89
Number of data bytes per partial page
00h, 02h, 00h, 00h
90-91
Number of spare bytes per partial page
20h, 00h
92-95
Number of pages per block
40h, 00h, 00h, 00h
96-99
Number of blocks per unit
00h, 08h, 00h, 00h
100
Number of logical units
01h
101
Number of address cycles
00h
102
Number of bits per cell
01h
103-104
Bad blocks maximum per unit
28h, 00h
26
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Unique ID Page
Table 4: Parameter Table (Continued)
Byte
Description
Value (hex)
105-106
Block endurance
01h, 05h
107
Guaranteed valid blocks at beginning of
target
08h
108-109
Block endurance for guaranteed valid
blocks
00h
110
Number of programs per page
04h
111
Partial programming attributes
00h
112
Number of ECC bits
00h
113
Number of interleaved address bits
00h
114
Interleaved operation attributes
00h
115-127
Reserved
00h
128
I/O pin capacitance
08h
129-130
Timing mode support
00h
131-132
Program cache timing
00h
133-134
tPROG
58h, 02h
135-136
tERS
137-138
tR
139-140
tCCS
141-163
Reserved
00h
164-165
Vendor-specific revision number
00h
166-179
Vendor specific
01h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 02h, 02h, B0h, 0Ah,
B0h
180-247
Reserved
00h
248
ECC maximum correct ability
08h
249
Die select feature
00h
250-253
Reserved
00h
254-255
Integrity CRC
Set at Test
256-512
2nd copy of the parameter table
513-768
3rd copy of the parameter table
769-2048
Additional redundant parameter pages
maximum page program time
maximum block erase time
maximum page read time
minimum
10h, 27h
46h, 00h
00h
Unique ID Page
The following command flow must be issued by the memory controller to
access the unique ID page contained within the device:
1. Issue a SET FEATURES (1Fh) command on a feature address of B0h and data
value of 40h (Access to OTP, Parameter, Unique ID pages, ECC disable).
2. Issue a PAGE READ (13h) command on a block/page address of 0x00h, and then
poll the status register OIP bit until device ready using the GET FEATURES (0Fh)
command issued on a feature address of C0h.
27
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Unique ID Page
3. Issue a READ FROM CACHE (03h) command on an address of 0x00h to read the
unique ID data out of the NAND device.
4. To exit reading the unique ID page, issue a SET FEATURES (1Fh) command with
a feature address of B0h and data value of 10h or 00h (main array READ, ECC
enable/disable).
The device stores 16 copies of the unique ID data. Each copy is 32 bytes: the first
16 bytes are unique data, and the second 16 bytes are the complement of the first 16
bytes. The host should XOR the first 16 bytes with the second 16 bytes. If the result is 16
bytes of FFh, that copy of the unique ID data is correct. If a non-FFh result is
returned, the host can repeat the XOR operation on a subsequent copy of the
unique ID data.
28
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Program Operations
Program Operations
PAGE PROGRAM
A PAGE PROGRAM operation sequence enables the host to input 1 byte to 2176 bytes of
data within a page to a cacheregister,and moves the data from the cache
register to the specified block and page address in the array.Only four partialpage programs are allowed on a single page.If more than 2176 bytes areloaded,
then those additional bytes are ignored by the cache register.
The page program sequence is as follows:
•
•
•
•
06h (WRITE ENABLE command)
02h (PROGRAM LOAD command)
10h (PROGRAM EXECUTE command)
0Fh (GET FEATURES command to read the status)
PROGRAM LOAD x1 (02h)
Prior to performing the PROGRAM LOAD operation, a WRITE ENABLE (06h) command
mustbe issued.As withany command that changes thememory contents,the
WRITE ENABLE command must be executed in order to set the WELbit.WRITE
ENABLE is followed by a PROGRAM LOAD (02h) command. The PROGRAM LOAD
command consists of an 8-bit op code, followed by 3 dummy bits, followed by a
plane select (if available) and a 12-bit column address, and then the data bytes to be
programmed. The data bytes are loaded into a cache register that is 2176 bytes long.
Only four partial-page programs are allowed on a single page.If more than 2176
bytes are loaded,those additional bytes are ignored by the cache register. The
command sequence ends when CS# goes from LOW to HIGH.
29
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Program Operations
Figure 20: PROGRAM LOAD (02h) Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
SCK
CS#
3 dummy bits
Command (02h)
SI
0
0
0
12-bit column address
12
10
11
9
8
7
6
5
4
Data byte 1
3
2
1
0
7
6
MSB
Plane select
1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38 39
17424…
17431
SCK
CS#
Data byte 1
SI
7
6
5
4
3
Data byte 2
2
1
0
7
6
5
4
3
Data byte 2176
2
1
0
7
6
5
4
3
2
1
0
Don’t Care
1
Note:
1. Plane select is a dummy bit in 1Gb device.
PROGRAM EXECUTE (10h)
The PROGRAM EXECUTE command consists of an 8-bit op code, followed by a 24bit address. After the page/block address is registered, the device starts the transfer
from the cache register to the main array and is busy for tPROG time. During
this busy time, the status register can be polled to monitor the status of the
operation (refer to the status register section). When the operation completes
successfully, the next series of data can be loaded with the PROGRAM LOAD
command.
30
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Program Operations
Figure 21: PROGRAM EXECUTE (10h) Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCK
CS#
Command (10h)
Address bits
SI
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
High-Z
SO
1
SCK
23
24
25
26
27
28
29
0
30 31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CS#
Get Feature (0Fh)
Address bits
SI
7
6
5
4
3
2
1
Status register address (C0h)
0
7
6
5
4
3
2
1
MSB
SO
High-Z
2
1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
0
SCK
CS#
Status register address
SI
2
1
0
Status register data out
Status register data out
SO
High-Z
7
2
6
5
4
3
2
1
0
7
MSB
6
5
4
3
2
MSB
Don’t Care
31
0
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Program Operations
RANDOM DATA PROGRAM x1 (84h)
TheRANDOM DATA PROGRAM operation programs or replaces data in a page
with existing data. The random data program sequence is as follows:
•
•
•
•
06h (WRITE ENABLE command)
84h (PROGRAM LOAD RANDOM DATA command)
10h (PROGRAM EXECUTE command)
0Fh (GET FEATURES command to read the status)
The PROGRAM LOAD RANDOM DATA x1 (84h) operation is similar to PROGRAM LOAD
x1 (02h). The difference is that PROGRAM LOAD X1command will reset the cache buffer
to an all FFh value, while PROGRAM LOAD RANDOM DATA X1 command will
only update the data bytes that are specified by the command input sequence,
and the rest of data in the cache buffer will remain unchanged. If the random
data is not sequential, then another PROGRAM LOAD RANDOM DATA x1 (84h)
command must be issued with a new column address. After the data is loaded, a
PROGRAM EXECUTE (10h) command can be issued to start the programming
operation.
Figure 22: PROGRAM LOAD RANDOM DATA (84h) Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCK
CS#
Command (84h)
3 dummy bits
0
SI
0
0
12-bit column address
12
11
10
9
8
7
6
5
4
Data byte 1
3
2
1
0
7
6
MSB
Plane select
23
24
25
26
27
28
29
30
31
32
33
34
35
1
36
37
38 39
17424…
17431
SCK
CS#
Data byte 1
SI
7
6
5
4
3
Data byte 2
2
1
0
7
6
5
4
3
Data byte 2176
2
1
0
1
7
6
5
4
3
2
1
0
Don’t Care
Note:
1. Plane select is a dummy bit in 1Gb device.
32
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Program Operations
PROGRAM LOAD x4 (32h) and PROGRAM LOAD RANDOM DATA x4 (34h)
The PROGRAM LOAD x4 (32h) and RANDOM DATAx4 (34h) is similar to
PROGRAM LOADx1(02h) command and RANDOM DATA x1(84h),but with
the capability to input the data across four data lines.
Figure 23: PROGRAM LOAD x4 (32h) Timing
0
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
43
44
45
46
47
SCK
CS#
Dummy bits and plane select 1
Command (32h)
column address bits A[11:0]
15
4
0
4
0
4
0
0
4
0
4
0
0
4
0
4
0
IO1
5
1
5
1
5
1
1
5
1
5
1
1
5
1
5
1
IO2
6
2
6
2
6
2
2
6
2
6
2
2
6
2
6
2
IO3
7
3
7
3
7
3
3
7
3
7
3
3
7
3
7
3
IO0
14
13
3
2
1
0
Byte 1
Byte 2
Byte 11
Byte 12
Byte 2175 Byte 2176
Don’t Care
Note:
1. Number of dummy bits are different for the different densities, and plane select is not
available in 1Gb. Plane select is a dummy bit in 1Gb device.
INTERNAL DATA MOVE
The INTERNAL DATA MOVE command programs or replaces data in a page
with existing data. The internal data move command sequence is as follows:
•
•
•
•
•
13h (PAGE READ command to cache)
06h (WRITE ENABLE command)
84h (PROGRAM LOAD RANDOM DATA command)
10h (PROGRAM EXECUTE command)
0Fh (GET FEATURES command to read the status)
Note: If the random data is not sequential, another PROGRAM LOAD RANDOM DATA
(84h) command must be issued with the new column address.
33
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Block Erase Operations
Block Erase Operations
The BLOCK ERASE (D8h) command is used to erase at the block level. The
blocks are organized as 64 pages per block, 2176 bytes per page (2048 + 128
bytes). Each block is 136KB. The BLOCK ERASE command (D8h) operates on
one block at a time. The command sequence for the BLOCK ERASE operation
is as follows:
• 06h (WRITE ENABLE command)
• D8h (BLOCK ERASE command)
• 0Fh (GET FEATURES command to read the status register)
Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06h)
command must be issued. As with any command that changes the memory
contents, the WRITE ENABLE command must be executed in order to set
the WEL bit. If the WRITE ENABLE command is not issued, then the rest of
the erase sequence is ignored. A WRITE ENABLE command must be
followed by a BLOCK ERASE (D8h) command. This command requires a 24bit address consisting of dummy bits followed by a valid block address. After the
address is registered, the control logic automatically controls timing and ERASE
and VERIFY operations. The device is busy for tERS time during the BLOCK
ERASE operation. The GET FEATURES (0Fh) command can be used to
monitor the status of the operation. (See the following figure.)
34
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Block Erase Operations
Figure 24: BLOCK ERASE (D8h) Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCK
CS#
Command (D8h)
Address bits
SI
23
SO
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
High-Z
1
23
24
25
26
27
28
29
30
0
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
CS#
Address bits
SI
7
6
5
4
3
GET FEATURES (0Fh)
2
1
Status register address (C0h)
0
6
7
5
4
3
2
1
0
MSB
SO
High-Z
2
1
12
13
14
15
16
17
18
19
20
21
22
23
SCK
CS#
SI
2
1
0
Status register data out
Status register data out
SO
High-Z
7
6
5
4
3
2
1
0
7
MSB
6
5
4
3
2
1
0
MSB
2
Don’t Care
35
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Features Operations
Features Operations
GET FEATURES (0Fh) and SET FEATURES (1Fh)
The GET FEATURES (0Fh) and SET FEATURES (1Fh) commands either monitor the
device status or alter the device configuration from the default at power-on.
These commands use a 1-byte feature address to determine which feature is
to be read or modified. Features such as OTP protect, block locking, SPI NOR like
protocol configuration, and ECC correction can be managed by setting specific bits in
feature addresses. Typically, the status register at feature address C0h is read to check
the device status, except WEL, which is a writable bit with the WRITE ENABLE
(06h) command.
When a feature is set, it remains active until the device is power cycled or the
feature is written to.Unless specified otherwise,when the device is set,it remains
set even if a RESET (FFh) command is issued. CFG[2:0] will be cleared to 000
after a reset and the device is back to normal operation.
Figure 25: GET FEATURES (0Fh) Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
1
15
16
17
18
19
20
21
22
23
2
1
0
SCK
CS#
1 byte address
Command (0Fh)
7
SI
5
6
4
3
0
MSB
SO
Data byte
High-Z
7
6
5
4
3
MSB
Don’t Care
Figure 26: SET FEATURES (1Fh) Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
SCK
CS#
1 byte address
Command (1Fh)
SI
7
6
5
4
3
MSB
Data byte
2
1
0
7
6
5
4
3
2
1
0
MSB
Don’t Care
36
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Features Operations
Feature Settings
Table 5: Feature Address Settings and Data Bits
Register
Feature Data Bits
Feature
Address
7
6
5
4
3
2
1
0
Notes
Block lock
Address = A0h;
Access = R/W
BRWD
BP3
BP2
BP1
BP0
TB
WP#/HOLD#
Disable
–
1, 2
Configuration
Address = B0h;
Access = R/W
CFG2
CFG1
LOT_EN
ECC_EN
–
–
CFG0
–
1
Status
Address = C0h;
Access = R
CRBSY
ECCS2
ECCS1
ECCS0
P_Fail
E_Fail
WEL
OIP
1
Die select
Address = D0h;
Access = R/W
–
DS0
–
–
–
–
–
–
1
Notes:
1. See the corresponding register bit description in Security Features, ECC Protection, Status Register, and Read Protocol – Similar to SPI NOR sections.
2. When the WP#/HOLD# disable bit is at the default value of 0, and with BRWD set to 1
and WP# LOW, block lock registers [7:2] cannot be changed.
37
2Gb 3.3V x1, x2, x4: SPI NAND Flash Memory
Security – Volatile Block Protection
Security – Volatile Block Protection
The block lock feature protects the entire device or ranges of device blocks
from the PROGRAM and ERASE operations. The SET FEATURE command must be
issued to alter the state of block protection. After power-up,the device is in the
locked state by default; block lock register bits BP[3:0] and TB are 1 . Reset will
notmodify the block protection state. When a PROGRAM/ERASE command is issued
to a locked block, a status register P_Fail bit or E_Fail bit will be set to indicate the
operation failure.
The following command sequence unlocks all blocks after power-up:The
SET FEATURES register write (1Fh) operation is issued, followed by the feature
address (A0h). Then, 00h is issued on data bits to unlock all blocks.
Security – Block Protection Bits
Table 6: Block Lock Register Block Protect Bits
BP3
BP2
BP1
BP0
0
0
0
0
0
None—all unlocked
0
0
0
0
1
Upper 1/1024 locked
2046:2047
0
0
0
1
0
Upper 1/512 locked
2044:2047
0
0
0
1
1
Upper 1/256 locked
2040:2047
0
0
1
0
0
Upper 1/128 locked
2032:2047
0
0
1
0
1
Upper 1/64 locked
2016:2047
0
0
1
1
0
Upper 1/32 locked
1984:2047
0
0
1
1
1
Upper 1/16 locked
1920:2047
0
1
0
0
0
Upper 1/8 locked
1792:2047
0
1
0
0
1
Upper 1/4 locked
1536:2047
0
1
0
1
0
Upper 1/2 locked
1024:2047
1
0
0
0
0
All unlocked
None
All locked
0:2047
1
0
0
0
1
Lower 1/1024 locked
0:1
1
0
0
1
0
Lower 1/512 locked
0:3
1
0
0
1
1
Lower 1/256 locked
0:7
1
0
1
0
0
Lower 1/128 locked
0:15
1
0
1
0
1
Lower 1/64 locked
0:31
1
0
1
1
0
Lower 1/32 locked
0:63
1
0
1
1
1
Lower 1/16 locked
0:127
1
1
0
0
0
Upper 1/8 locked
0:255
1
1
0
0
1
Lower 1/4 locked
0:511
1
1
0
1
0
Lower 1/2 locked
0:1023
1
1
1
1
1
All locked (default)
0:2047
All others
38
Protected Portion
Protected
Blocks
TB
None
2Gb 3.3V x1, x2, x4: SPI NAND Flash Memory
Security – Hardware Write Protection
Security – Hardware Write Protection
Hardware write protection prevents the block protection state from hardware modifications.
The following command sequence enables hardware write protection: The SET FEATURE command is issued on feature address A0h. Then, the WP#/Hold# disable bit
state is set to 0 as the default after power up.
The BRWD bit is operated in conjunction with WP#/Hold# disable bit. When BRWD is
set to 1 and WP# is LOW,none of the other block lock register bits [7:2] can be
set.The block lock state can not be changed, regardless of what is unlocked
or locked. Also, when the WP#/Hold# disable bit is set to 1, the hardware protected
mode is disabled. The default value of BRWD and WP#/ Hold# disable bits = 0
after power up.
Security – Device Lock Tight (LOT)
The lock tight mode prevents the block protection state from software
modifications. After it is enabled,this mode can not be disabled by a software
command.Also,BP,TB, and BRWD bits are protected from further software changes.
Only another power cycle can disable the lock tight mode.
The following command sequence enables the lock tight mode: The SET
FEATURES register write (1Fh) operation is issued, followed by the feature address
(B0h). Then, data bits are set to enable LOT (LOT_EN bit = 1).
When the hardware write protection mode is disabled during quad or x4
mode,lock tight can be used to prevent a block protection state change.
Permanent Block Lock Protection
48 blocks per die (0 to 47) can be permanently locked using PROTECT command.
The PROTECT command provides nonvolatile, irreversible protection of up to twelve
groups (48 blocks). Implementation of the protection is group-based, which means that
a mini- mum of one group (4 blocks) is protected when the PROTECT command is
issued. Because block protection is nonvolatile, a power-on or power-off
sequence does not affect the block status after the PROTECT command is issued.
The device is shipped from the factory with no blocks protected so that users can
program or erase the blocks before is suing the PROTECT command. Block
protection is also irreversible in that when protection is enabled by issuing the
PROTECT command,the protected blocks can no longer be programmed or
erased. If permanent lock is disabled, PROTECT command would be ignored. As
with any command that changes the memory contents, the WRITE ENABLE
must be executed. If this command is not issued, then the protection command
is ignored.WRITE ENABLE must be followed by a PROTECTION command (2Ch).
The following PROTECT sequence is used:
•
•
•
•
06h (WRITE ENABLE)
2Ch (permanent block lock protection)
24-bit address (see the PROTECTION Command Details)
After tPROG time, use GET FEATURE command (0Fh) with feature address C0h to verify P_Fail bit
39
2Gb 3.3V x1, x2, x4: SPI NAND Flash Memory
Permanent Block Lock Protection
Figure 27: PROTECT Command Cycle
0
1
2
3
4
5
6
7
8
9
10
11 12 13
14
15 28
29
30 31
SCK
CS#
tPROG
Page Y
SI
2Ch
23
22
21
20 19
18
17 16
3
2
1
0
SO
PROTECTION Command (2Ch) Details
To enable protection,the PROTECTION command consists of an 8-bit commandcode,
followed by a 24-bit address (8 dummy bits and an 16-bit page/block address for 1Gb or 7
dummy bits and an 17-bit page/ block address for 2Gb die). Row address bits 11, 10, 9, 8
(namedasY) input the targeted block group information.Where Ydefines the group
of blocks to be protected. There are 12 Groups Y where Y = 0000b-1011b:
•
•
•
•
Y = 0000 protects Group0 = blks 0, 1, 2, 3.
Y = 0001 protects Group1 = blks 4, 5, 6, 7.
......
Y = 1011 protects Group11 = blks 44, 45, 46, 47.
After tPROG, the targeted block groups are protected. Upon PROTECT operation failure, the
status register reports a value of 0Ch(P_FAIL=1and WEL=1).UponPROTECT
operation success, the status register reports a value of 00h.
Note: There is no status register to check the PROTECT status of a block or a
group.A permanent blocks table should be maintained and updated after a group is
protected.
Permanent Block Lock Protection Disable Mode
This mode disables the ability to accept the PROTECTION command. Running this
command sequence ensures no more groups can ever be permanently locked.
The following disable PROTECT sequence is used
• SET FEATURE command (1Fh) with B0h mode and data value C2h
• 06h (WRITE ENABLE)
• 10h (Execute with block/page address as '0')
• After tPROG time, use GET FEATURE command (0Fh) with feature address C0h to verify
P_Fail bit
40
2Gb 3.3V x1, x2, x4: SPI NAND Flash Memory
Security – One Time Programmable (OTP)
Security – One Time Programmable (OTP)
This device offers a protected, one-time programmable NAND Flash memory area.
Ten full pages (10 x 2176 bytes per page) per die are available, and the entire
range is guaranteed. Customers can choose how to use the OTP area, such as
programming serial numbers or other data for permanent storage. The OTP area
can't be erased. When ECC is enabled, data written in the OTP area is ECC
protected. Besides some additional configuration bits are described in this section.
Enable OTP Access
OTP access needs to be enabled in order to read and write to the OTP region.When
the dieisin OTP operation mode,all subsequent page program or pageread
commands are applied to the OTP area. SET FEATURES command (1Fh) with feature
address B0h and data 50h (OTP operation mode with ECC enabled ) or 40h (OTP
operation mode with ECC disabled ) are used to enable the OTP access.
After OTP accessis enabled,the following sequence is used to program one or
morepages
WRITE ENABLE command (06h)
• PROGRAM EXECUTE command (10h) with the row address of page (OTP
page address range 02h-0Bh)
• Verify until OIP bit not busy using GET FEATURE command (0Fh) with feature address C0h
• Using GET FEATURE command (0Fh) with feature address C0h, verify if P_FAIL bit is
0 for the successful operation.
After OTP access is enabled, the following sequence is used to read one or more
pages
• PAGE READ command (13h) with the page address (02h-0Bh)
• Verify until OIP bit is not busy using GET FEATURE command (0Fh) with
feature address C0h
• Page data using READ FROM CACHE command (03h).
OTP Configuration States
To check the status of OTP data protect,SPI NOR read enable,or permanent
block Lock protection, the following sequence is used
• SET FEATURES command (1Fh) with feature address B0h and data (C0h for OTP data
protect bit, 82h for NOR read protocol enable bit, C2h for permanent block lock
disable bit)
• PAGE READ command (13h) with address 0
• Verify until OIP bit not busy using GET FEATURE command (0Fh) with feature address C0h
• READ FROM CACHE command (03h) with address 0
• Expect the read from cache data all 1 for the mode disabled or all "0" for
enabled.
Note: Configuration status of CFG[2:0] can be read using GET FEATURE command
(0Fh) with feature address B0h.
41
2Gb 3.3V x1, x2, x4: SPI NAND Flash Memory
Security – One Time Programmable (OTP)
OTP Protection and Program Prevention
This mode is used to prevent further programming of the pages in
the OTP area. To protect and prevent programming the OTP area, the
following sequence is used
SET FEATURES command (1Fh) with feature address B0h and data C0h
(CFG[2:0] = 110b)
WRITE ENABLE command (06h)
PROGRAM EXECUTE command (10h) with the row address 00h
Verify until OIP bit not busy and P_FAIL bit 0 using GET FEATURE
command (0Fh) with status register address C0h.
Exit OTP
To exit from OTP operation mode and return the device to normal array
operation mode, the SET FEATURES command (1Fh) is issued. This is
followed by setting the feature address = B0h and data CFG[2:0] = 000b.
Last, the RESET (FFh) command is issued.
Table 7: Configuration Registers for Security
CFG2
CFG1
CFG0
0
0
0
State
Normal operation
0
1
0
Access OTP area/Parameter/Unique ID
1
1
0
Access to OTP data protection bit to lock OTP area
1
0
1
Access to SPI NOR read protocol enable mode
1
1
1
Access to permanent block lock protection disable mode
42
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Status Register
Status Register
The device has an 8-bit status register that software can read during the device
operation. All bits are read-only register except WEL, which could be changed by
WRITE DISABLE (04h) and WRITE ENABLE (06h) commands. None of bits can be
changed by SET FEATURE command (1Fh).The status register can be read by
issuing the GET FEATURES (0Fh) command, followed by the feature address
(C0h). The status register will output the status of the operation.
Table 8: Status Register Bit Descriptions
Bit
7
Bit Name
Description
Cache read busy
(CRBSY)
This bit is set (CRBSY = 1) when READ PAGE CACHE RANDOM command is executing; this
bit remains a 1 until the page specified at READ PAGE CACHE RANDOM command is
transferred from array to data register. When the bit is 0, the device is in the ready state
and background read page cache operation is completed.
RESET command is acceptable during CRBSY = 1 and could halt background read page
cache operation and download first page at block 0 into cache register at default.
6
ECC status register
(ECCS2)
5
ECC status register
(ECCS1)
4
ECC status register
(ECCS0)
3
Program fail (P_Fail)
See ECC Protection for the ECC status definition.
ECC status is set to 000b either following a RESET or at the beginning of the READ. It is
then updated after the device completes a valid READ operation.
ECC status is invalid if ECC is disabled (via a SET FEATURES command to get access the
configuration register).
After a power-up RESET, ECC status is set to reflect the contents of block 0, page 0.
Indicates that a program failure has occurred (P_Fail = 1). This bit will also be set if the
user attempts to program an invalid address or a locked or protected region, including
the OTP area.
This bit is cleared during the PROGRAM EXECUTE command sequence or a RESET command (P_Fail = 0).
2
Erase fail (E_Fail)
Indicates that an erase failure has occurred (E_Fail = 1). This bit will also be set if the user
attempts to erase a locked region or if the ERASE operation fails.
This bit is cleared (E_Fail = 0) at the start of the BLOCK ERASE command sequence or a
RESET command.
1
Write enable latch
(WEL)
Indicates the current status of the write enable latch (WEL) and must be set (WEL = 1) prior to issuing a PROGRAM EXECUTE or BLOCK ERASE command. It is set by issuing the
WRITE ENABLE command.
WEL can also be cleared (WEL = 0) by issuing the WRITE DISABLE command or a successful
PROGRAM/ERASE operation.
0
Operation in progress (OIP)
This bit is set (OIP = 1 ) when a PROGRAM EXECUTE, PAGE READ, READ PAGE CACHE
LAST, BLOCK ERASE, READ PAGE CACHE RANDOM (within tRCBSY to wait for cache register readiness) or RESET command or a power-up initialization is executing; the device is
busy. When the bit is 0, the interface is in the ready state.
43
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
ECC Protection
ECC Protection
The device offers an 8-bit data corruption protection by offering internal ECC to
obtain the data integrity.The internal ECC can be enabled or disabled by setting the
ECC_EN bit in the configuration register.ECC is enabled after device power-up by
default.The READ and PROGRAM commands operate with internal ECC by default.
Reset will not change the existing configuration. To enable/disable ECC after power on,
perform the following command sequence:
• Issue the SET FEATURES command (1Fh)
• Issue configuration register address (B0h)
• Then:To enable ECC,set bit4(ECCenable) to1;To disable ECC,clear bit4( ECC
enable) to 0
During a PROGRAM operation, the device calculates an expected ECC code on the ECCprotected bytes in the cache register, before the page is written to the NAND Flash array. The
ECC code is stored in the spare area of the page.
During a READ operation, the page data is read from the array to the cache
register, where the ECC code is calculated and compared with the expected ECC code value
read from the array.If a1–8-biterror is detected,the error is corrected in the cache
register. Only corrected data is output on the I/O bus.The ECC status register bit
indicates whether or not the error correction is successful.The table below
describes the ECC protection scheme used throughout a page.
Note: The unique ID and parameter page are not ECC protected areas. Multiple copies are
provided for parameter page to obtain the data integrity.XOR method is provided
for unique ID to verify the data.
With internal ECC, users must accommodate the following (details provided in table be- low):
• Spare area definitions
• WRITEs are supported for main and spare areas (user meta data I and II). WRITEs to the
ECC area are prohibited
When using partial-page programming, the following conditions must both be met:
• In the main user area and user meta data area I, single partial-page programming operations must be used
• Within a page, a maximum of four partial-page programming operations can be performed
Table 9: ECC Status Register Bit Descriptions
Bit 2
Bit 1
Bit 0
0
0
0
No errors
0
0
1
1-3 bit errors detected and corrected
0
1
0
Bit errors greater than 8 bits detected and not corrected
0
1
1
4-6 bit errors detected and corrected. Indicates data refreshment might be taken
1
0
1
7-8 bit errors detected and corrected. Indicates data refreshment must be taken to guarantee
data retention
Others
Description
Reserved
44
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
ECC Protection
Table 10: ECC Protection
Max Byte
Address
Min Byte
Address
ECC
Protected
Area
1FFh
000h
Yes
Main 0
User Main data 0
3FFh
200h
Yes
Main 1
User Main data 1
5FFh
400h
Yes
Main 2
User Main data 2
7FFh
600h
Yes
Main 3
User Main data 3
803h
800h
No
Spare 0
Reserved (bad block data)
807h
804h
No
Spare 1
User meta data II
80Bh
808h
No
Spare 2
User meta data II
80Fh
80Ch
No
Spare 3
User meta data II
813h
810h
No
Spare 0
User meta data II
817h
814h
No
Spare 1
81Bh
818h
No
Spare 2
81Fh
81Ch
No
Spare 3
827h
820h
Yes
Spare 0
82Fh
828h
Yes
Spare 1
837h
830h
Yes
Spare 2
83Fh
838h
Yes
Spare 3
84Fh
840h
Yes
Spare 0
ECC for Main/Spare 0
85Fh
850h
Yes
Spare 1
ECC for Main/Spare 1
86Fh
860h
Yes
Spare 2
ECC for Main/Spare 2
87Fh
870h
Yes
Spare 3
ECC for Main/Spare 3
45
Description
User meta data I
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Error Management
Error Management
This NAND Flash device is specified to have the minimum number of valid
blocks (NVB) of the total available blocks per die shown in the table below.This
means the devices may have blocks that are invalid when shipped from the
factory.An invalid block is one that contains at least one page that has more bad
bits than can be corrected by the minimum required ECC. Additional bad
blocks may develop with use. However,the total number of available blocks will
not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices may contain bad blocks, they can be
used reliably in systems that provide bad-block management and errorcorrection algorithms.
This ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block
does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased.The factory identifies
invalid blocks before shipping by attempting to program the bad-block mark into
every location in the first page of each invalid block. It may not be possible to
program every location in an invalid block with the bad-block mark.However,the
first spare area location in each bad block is guaranteed to contain the bad-block
mark.This method is compliant with ONFI factory defect mapping requirements.
See the following table for the bad-block mark.
System software should initially check the first spare area location for non-FFh
data on the first page of each block prior to performing any program
or erase operations on the NAND Flash device. A bad-block table can then
be created, enabling system software to map around these areas. Factory
testing is performed under worst case conditions. Because invalid blocks
may be marginal, it may not be possible to recover the bad-block marking
if the block is erased.
Table 11: Error Management Details
Description
Requirement
Minimum number of valid blocks per die (NVB)
2008
Total available blocks per die
2048
First spare area location in the first page of each block
Byte 2048
Value programmed for bad block at the first byte of spare area
00h
Minimum required ECC
8-bit ECC per sector (544) bytes of data
Minimum ECC with internal ECC enabled
8-bit ECC per 512 bytes (user data) + 8 bytes
(Spare) + 16 bytes (ECC data)
46
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
SPI NOR Read Configuration
SPI NOR Read Configuration
Some chip set vendors may have already designed in SPI NOR IP to support
system boot; address allocation on clock cycle in SPI NAND read from cache
protocol will cause incompatibility. To be drop-in compatible to SPI NOR read
protocol, this device offers an alternative solution to implement 03h/0Bh
commands,as are done with SPINOR. Refer to the Electrical Specifications for
detail timing requirement. This solution would be enabled using the following
command sequence:
• SET FEATURE command (1Fh) with feature address B0h and CFG
bits[2:0] = 101b (access SPI NOR read protocol enable mode)
• WRITE ENABLE command (06h)
• PROGRAM EXECUTE command (10h) with block/page address all 0
• GET FEATURE command (0Fh) with status register address C0h to check until
device is ready (OIP bit clear) and verify that P_FAIL bit is not set
• SET FEATURE command (1Fh) with feature address B0h and CFG bits[2:0] =
000b (re- turn to normal operation mode)
• GET FEATURE command (0Fh) at address B0h and CFG bits[2:0] = 101b to
verify all 0; all 1 indicates SPI NOR mode not enabled.
• It is a nonvolatile configuration setting and power cycle will not
recover it back to SPI NAND default mode. The rest of the SPI NAND
commands still work in this configuration.
47
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
SPI NOR Read Configuration
Figure 28: Read from Cache (03h)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SCK
11 dummy bits
12-bit column
address
Plane select
(bit 12)
Command (03h)
CS#
12
SI
11
10
9
SO
1
23
SCK
CS#
SI
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
2
1
39
16,919
16,927
12-bit column address
7
8
7
6
5
4
3
2
1
0
data out 1
SO
7
6
5
4
3
data out 2176
0
7
6
5
4
3
2
1
0
7
6
1
Don’t Care
Note:
1. SPI NOR compatible. Plane select bit not available in 1Gb device and can be used as a
dummy bit.
48
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
SPI NOR Read Configuration
Figure 29: Fast Read from Cache (0Bh)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SCK
11 dummy bits
12-bit column
address
Plane select
(bit 12)
Command (0Bh)
CS#
12
SI
11
10
9
SO
1
23
SCK
CS#
SI
24
25
26
27
28
29
30
31
12-bit column address
7
8
7
6
5
4
3
32
33
34
35
36
37
38
39
40
41
42
1 dummy byte
2
1
43
44
45
46
47
48
0
7
data out 1
0
SO
7
1
6
5
4
3
2
1
6
Don’t Care
Note:
1. SPI NOR compatible. Plane select bit not available in 1Gb device and can be used as a
dummy bit.
49
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Power-Up and Power-Down
Power-Up and Power-Down
At power-up and power-down, the device must not be selected;that is,CS# must
follow the voltage applied on V CC until V CC reaches the correct values: V CC, min at powerup and VSS at power-down. Zetta NAND Flash devices are designed to prevent
data corruption during power transitions.VCC is internally monitored and when
VCC reaches the write inhibit voltage V WI, a minimum of 250μs must elapse before
issuing a RESET (FFh) command. After issuing the RESET command, 1.25ms must
elapse before issuing any other command. GET FEATURE command could be
issued to poll the status register (OIP) before the first access. Normal
precautions must be taken for supply line decoupling to stabilize the VCC
supply.Each device in a system should have the VCC line decoupled by a
suitable capacitor (typically 100nF) close to the package pins.
Note:For power cycle testing,the system must not initiate the powerup sequence until VCC drops down to 0V.
Figure 30: SPI Power-Up
VCC
VCC,max
Chip selection not allowed
VCC,min
Chip
reset
VWI
tPOR
Polling allowed
Device fully accessible
Status register OIP bit 0
Time
Figure 31: SPI Power-Up Timing
Zetta has developed an alternative SPI NAND sequence that does not require
issuing an explicit RESET(FFh) command upon power-up.This is default device
initialization setting. When device V CC has reached the write inhibit voltage, the device
automatically kicks off the initialization. At default setting, first page data would be
automatically loaded into cache register. During the initialization, GET FEATURE
command could be issued to poll the status register (OIP) before the first access; Or, the
first access can occur 1.25ms after VCC reaches VCC,min.
50
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Power-Up and Power-Down
Figure 32: Alternative SPI Power-Up Timing
Mode 3
SCK
Mode 0
VCC,min = 2.7V
VCC
WP#
Power-up: 1st page
autoload = 1.25ms1
CS#
SI
SO
Read from cache (03h, 3Bh, or 6Bh)
High-Z
Don’t Care
Note:
1. Poll status register OIP bit is allowed during device initialization.
51
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Electrical Specifications
Electrical Specifications
Stresses greater than those listed can cause permanent damage to the device. These are
stress ratings only,and functional operation of the device at these or any other
conditions above values in this specification is not guaranteed. Exposure to absolute
maximum rating conditions for extended periods can affect reliability.
Table 12: Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Supply voltage (SPI)
VCC
–0.6
4.6
V
I/O voltage
VCC
–0.6
4.6
V
Operating temperature (ambient)
TA
–40
85
°C
Storage temperature
TS
–65
150
°C
Note:
1. During infrequent, nonperiodic transitions and for periods less than 20ns, voltage potential between VSS and VCC may undershoot to –2.0V or overshoot to VCC_MAX + 2.0V.
Table 13: Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
VCC
2.7
3.3
3.6
V
TA
–40
25
85
°C
Supply voltage
Ambient operating temperature (industrial)
Table 14: AC Measurement Conditions
Parameter
Symbol
Min
Max
30/10
Unit
Load Capacitance
CL
Input rise and fall time
–
–
5
pF
ns
Input rise and fall time (>100 MHz)
–
–
1.5
ns
voltage1
–
0.2 VCC
0.8 VCC
V
Input timing reference voltages
–
0.3 VCC
0.7 VCC
V
Output timing reference voltages
–
Input pulse
Note:
VCC/2
1. These are Min/Max specifications for dual/quad operations.
Figure 33: AC Measurement I/O Waveform
I/O timing
reference levels
Input levels
0.8 VCC
0.7
0.5
0.3
0.2 VCC
52
VCC
VCC
VCC
V
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Electrical Specifications
Table 15: Capacitance
Symbol
Test
Conditions
Min
Max
Unit
Input/output capacitance (IO0, IO1, IO2, IO3)
CIN
VOUT = 0V
–
9
pF
Input capacitance (other pins)
CIN
VIN = 0V
–
9
pF
Description
Notes:
1. These parameters are verified in device characterization and are not 100% tested.
2. The value includes the silicon and package together.
Table 16: DC Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VIH
–
0.7 × VCC
–
VCC + 0.4
V
Input low voltage
VIL
–
–0.5
–
0.3 × VCC
V
Output high voltage
VOH
IOH = –100µA
VCC - 0.2
–
–
V
Output low voltage
VOL
IOL = 1.6mA
–
–
0.4
V
ILI
–
–
–
±10
µA
Output leakage current
ILO
–
–
–
±10
µA
Page read current
ICC3
–
–
25
35
mA
Program current
ICC4
–
–
20
25
mA
Erase current
ICC5
–
–
20
25
mA
Standby current
ICC1
CE# = VCC; VIN = VSS or VCC
–
15
50
µA
Input high voltage
Input leakage current
Notes:
1. Typical values are given for TA = 25 °C.
2. These parameters are verified in device characterization and are not 100% tested.
Table 17: AC Characteristics
Parameter
Symbol
Min
Max
Unit
fC
–
133
MHz
Clock LOW time
tWL
3.375
–
ns
Clock HIGH time
tWH
3.375
–
ns
Clock LOW time (SPI NOR read 03h mode at 20 MHz)
tWL
22.5
–
ns
Clock HIGH time (SPI NOR read 03h mode at 20 MHz)
tWH
22.5
–
ns
Clock rise time
tCRT
1.3
–
V/ns
Clock fall time
tCFT
1.3
Clock frequency1, 2
V/ns
tCS
30
–
ns
tCSS/ tCSH
3.375
–
ns
Chip select# non-active setup/hold time relative to SCK
tCSH
2.5
–
ns
Output disable time
tDIS
Command deselect time
Chip select# active setup/hold time relative to SCK
–
6
ns
Data input setup time
tSUDAT
2.5
–
ns
Data input hold time
tHDDAT
1.75
–
ns
tV
–
6
ns
Clock LOW to output valid (30pF)
53
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Electrical Specifications
Table 17: AC Characteristics (Continued)
Parameter
Symbol
Min
Max
Unit
Clock LOW to output valid (10pF)
tV
–
5
ns
Clock LOW to output valid (similar to SPI NOR 20 MHz read 30pF)
tV
–
30
ns
Clock LOW to output valid (similar to SPI NOR 20 MHz read 10pF)
tV
–
28
ns
Output hold time (30pF)
tHO
2
–
ns
Output hold time (10pF)
tHO
1.5
–
ns
Output hold time (SPI NOR similar to 20 MHz read 30pF)
tHO
0
–
ns
Output hold time (SPI NOR similar to 20 MHz read 10pF)
tHO
0
–
ns
WP# hold time
tWPH
100
–
ns
WP# setup time
tWPS
20
–
ns
Notes:
1. Read from Cache Dual I/O (BBh) and Quad I/O (EBh) can run up to 108 MHz.
2. When read protocol similar to SPI NOR is enabled, Read from Cache 03h command can
run up to 20 MHz, while read from Cache 0Bh command can run up to 133 MHz.
Table 18: PROGRAM/READ/ERASE Characteristics
Parameter
BLOCK ERASE operation time (128KB)
PROGRAM PAGE operation time (ECC disabled)
Symbol
Typ
Max
Unit
tERS
2
10
ms
tPROG
200
600
µs
220
600
–
25
46
70
–
5
PROGRAM PAGE operation time (ECC enabled)
tRD
Page read time (ECC disabled)
Page read time (ECC enabled)
Data transfer time from data register to cache register (internal ECC disabled)
tRCBSY
Data transfer time from data register to cache register (internal ECC enabled)
Power-on reset time (device initialization) from VCC MIN
Write inhibit voltage
Reset time for READ, PROGRAM, and ERASE operations (internal ECC disabled)
Notes:
µs
40
50
µs
tPOR
–
1.25
ms
VWI
–
2.5
V
tRST1
–
30/35/525
µs
–
75/80/570
µs
–
4
–
Reset time for READ, PROGRAM, and ERASE operations (internal ECC enabled)
Number of partial-page programming operations supported
µs
NOP2
1. For first RESET condition after power-up, tRST will be 1.25ms maximum. For stacked die,
no command should be issued during this time.
2. In the main user area and in user meta data area I, single partial-page programming operations must be used. Within a page, the user can perform a maximum of four partialpage programming operations.
54
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Electrical Specifications
Figure 34: WP# Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SCK
CS#
Command (1Fh)
Address (A0h)
7
SI
6
5
MSB
tWPS
4
3
Data byte
2
1
0
7
6
5
4
MSB
WP#
1
17
18
19
20
21
22
23
SCK
CS#
Data byte
SI
6
5
4
3
2
1
0
tWPH
WP#
1
Don’t Care
55
3
2
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Electrical Specifications
t
Figure 35: Serial Input Timing
Figure 36: Serial Output Timing
tWL
tWH
SCK
CS#
t HO
SO
tV
t HO
High-Z
tDIS
LSB OUT
Don’t Care
56
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Package Dimensions
Package Dimensions
Figure 37: 16-pin SOP (300 mils body width)
0.5 ±0.25 X 45°
10.3 ±0.2
2.5 ±0.15
16X 0.2 ±0.1
0.1 A
0.275 ±0.045
16X 0.42 ±0.09
See Detail A
1.27 TYP
16
9
Plating material composition: PPF
(0.003µm–0.015µm Au, 0.02µm–0.15µm Pd,
0.5µm–2.0µm Ni).
Plastic package material: epoxy novolac.
10.3 ±0.2
7.5 ±0.1
Pin 1 ID
1
Package width and length do not
include mold protrusion. Allowable
protrusion is 0.25 per side.
8
0.25 gage plane
Seating plane
0.2 ±0.1
(for reference
only)
Note:
1. All dimensions are in millimeters.
57
0.83 ±0.44
Detail A
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Package Dimensions
Package Dimensions
Figure 38: 8-pin WSON 6mm x 8mm x0.8mm
58
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Package Dimensions
Package Dimensions
Figure 39: 24-Pin T-PBGA (5 x 5 Ball Grid Array) 6mm x 8mm
Seating plane
A
24X Ø0.4
Dimensions apply
to solder balls postreflow on Ø0.35 SMD
ball pads.
0.1 A
Ball A1 ID
5
4
3
2
Ball A1 ID
1
A
B
4 CTR
C
8 ±0.1
D
1 TYP
E
1.1 ±0.1
1 TYP
4 CTR
0.25 MIN
6 ±0.1
Note:
1. All dimensions are in millimeters.
59
2Gb 3.3V x1, x2, x4: SPI NAND FlashMemory
Revision History
Revision History
Rev.
Date
Description
1.0
2021-06-15
Initial Release
1.1
2021-10-08
Modify Package Information
60
工商网监
湘ICP备2023018690号
