SiT5156AICFA-28VT-12.000000F

SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Description Features The SiT5156 is a ±0.5 ppm to ±2.5 ppm MEMS SuperTCXO that is engineered for best dynamic performance. It is ideal for high reliability telecom, wireless and networking, industrial, precision GNSS and audio/video applications. ◼ Leveraging SiTime’s unique DualMEMS® temperature sensing and TurboCompensation® technologies, the SiT5156 delivers the best dynamic performance for timing stability in the presence of environmental stressors such as air flow, temperature perturbation, vibration, shock, and electromagnetic interference. This device also integrates multiple on-chip regulators to filter power supply noise, eliminating the need for a dedicated external LDO. The SiT5156 offers three device configurations that can be ordered using Ordering Codes for: 1) TCXO with non-pullable output frequency, 2) VCTCXO allowing voltage control of output frequency, 3) DCTCXO enabling digital control of output frequency using an I2C interface, pullable to 5 ppt (parts per trillion) resolution. ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ ◼ Applications ◼ ◼ The SiT5156 can be factory programmed for any combination of frequency, stability, voltage, and pull range. Programmability enables designers to optimize clock configurations while eliminating long lead times and customization costs associated with quartz devices where each frequency is custom built. Refer to Manufacturing Guideline for proper reflow profile and PCB cleaning recommendations to ensure best performance. Block Diagram Any frequency from 1 MHz to 60 MHz in 1 Hz steps Factory programmable options for short lead times Best dynamic stability under airflow, thermal shock ▪ ±0.5 ppm stability across temperature ▪ ±15 ppb/°C typical frequency slope (ΔF/ΔT) -40°C to +105°C operating temperature No activity dips or micro jumps Resistant to shock, vibration and board bending On-chip regulators eliminate the need for external LDOs Digital frequency pulling (DCTCXO) via I 2C ▪ Digital control of output frequency and pull range ▪ Up to ±3200 ppm pull range ▪ Frequency pull resolution down to 5 ppt 2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage LVCMOS or clipped sinewave output RoHS and REACH compliant Pb-free, Halogen-free, Antimony-free ◼ ◼ ◼ ◼ Precision GNSS systems Microwave backhaul Network routers and switches Professional audio and video equipment Storage and servers Test and measurement Related products for automotive applications. For aerospace and defense applications SiTime recommends using only Endura™ SiT5146. 5.0 mm x 3.2 mm Package Pinout SDA / NC OE / VC / NC 1 9 VDD SCL / NC 2 8 NC NC 3 7 NC GND 4 6 CLK 10 5 A0 / NC Figure 2. Pin Assignments (Top view) (Refer to Table 13 for Pin Descriptions) Figure 1. SiT5156 Block Diagram Rev 1.07 1 January 2023 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Ordering Information The part number guide illustrated below is for reference only, in which boxes identify order codes having more than one option. To customize and build an exact part number, use the SiTime Part Number Generator. To validate the part number, use the SiTime Part Number Decoder. Part Family TCXO VCTCXO DCTCXO Silicon Revision Letter Package Size Pin 1 Function – TCXO mode only "F": 5.0 mm x 3.2 mm "E": Output Enable "N": No Connect SiT5156AC - FK - 33 E 0 - 19.123456 T SiT5156AC - FK - 33 V T - 19.123456 T SiT5156AC - FKG33 J R - 19.123456 T "I": Industrial, -40 to 85°C "C": Extended Commercial, -20 to 70°C "E": Extended Industrial, -40 to 105°C Packaging "T": 12 mm Tape & Reel, 3 ku reel "Y": 12 mm Tape & Reel, 1 ku reel “X”: 12 mm Tape & Reel, 250 u reel (blank): bulk[2] Output Waveform Frequency "-": LVCMOS[1] "C": Clipped Sinewave 1.000000 MHz to 60.000000 MHz Temperature Range Pull Range – DCTCXO mode only Frequency Stability "T": ±6.25 ppm "R": ±10 ppm "Q": ±12.5 ppm "M": ±25 ppm "B": ±50 ppm "C": ±80 ppm "E": ±100 ppm "F": ±125 ppm "K": for ±0.5 ppm "A": for ±1.0 ppm "D": for ±2.5 ppm I2C Address Mode – DCTCXO mode only “0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”, “9”, “A”, “B”, “C”, “D”, “E”, “F”: Order code representing hex value of I2C address. When the I2C address is factory programmed using this code, pin A0 is no connect (NC). "G": "H": "X": "L": "Y": "S": "Z": "U": ±150 ppm ±200 ppm ±400 ppm ±600 ppm ±800 ppm ±1200 ppm ±1600 ppm ±3200 ppm Pin 1 Function – DCTCXO mode only "I": Output Enable "J": No Connect, software OE control “G”: I2C pin addressable mode. Address is set by the logic on A0 pin. Supply Voltage "25": 2.5 V ± 10% "28": 2.8 V ± 10% "30": 3.0 V ± 10% "33": 3.3 V ± 10% Notes: 1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in Table 1 (Electrical Characteristics). Contact SiTime for other rise/fall time options for best EMI or driving multiple loads. For differential outputs, contact SiTime. 2. Bulk is available for sampling only. Rev 1.07 Page 2 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO TABLE OF CONTENTS Description ................................................................................................................................................................................... 1 Features....................................................................................................................................................................................... 1 Applications ................................................................................................................................................................................. 1 Block Diagram ............................................................................................................................................................................. 1 5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1 Ordering Information .................................................................................................................................................................... 2 Electrical Characteristics.............................................................................................................................................................. 4 Device Configurations and Pin-outs ............................................................................................................................................. 9 Pin-out Top Views................................................................................................................................................................. 9 Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10 Waveforms................................................................................................................................................................................. 12 Timing Diagrams ........................................................................................................................................................................ 13 Typical Performance Plots ......................................................................................................................................................... 14 Architecture Overview ................................................................................................................................................................ 16 Frequency Stability ............................................................................................................................................................. 16 Output Frequency and Format ............................................................................................................................................ 16 Output Frequency Tuning ................................................................................................................................................... 16 Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 17 Device Configurations ................................................................................................................................................................ 17 TCXO Configuration ........................................................................................................................................................... 17 VCTCXO Configuration ...................................................................................................................................................... 18 DCTCXO Configuration ...................................................................................................................................................... 19 VCTCXO-Specific Design Considerations ................................................................................................................................. 20 Linearity .............................................................................................................................................................................. 20 Control Voltage Bandwidth ................................................................................................................................................. 20 FV Characteristic Slope KV ................................................................................................................................................. 20 Pull Range, Absolute Pull Range ........................................................................................................................................ 21 DCTCXO-Specific Design Considerations ................................................................................................................................. 22 Pull Range and Average Pull Range .................................................................................................................................. 22 Output Frequency ............................................................................................................................................................... 23 I2C Control Registers .......................................................................................................................................................... 25 Register Descriptions.......................................................................................................................................................... 25 Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 25 Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 26 Register Address: 0x02. DIGITAL PULL RANGE CONTROL [15] ....................................................................................... 27 Serial Interface Configuration Description .......................................................................................................................... 28 Serial Signal Format ........................................................................................................................................................... 28 Parallel Signal Format ........................................................................................................................................................ 29 Parallel Data Format ........................................................................................................................................................... 29 I2C Timing Specification ...................................................................................................................................................... 31 I2C Device Address Modes ................................................................................................................................................. 32 Schematic Example ............................................................................................................................................................ 33 Dimensions and Patterns ........................................................................................................................................................... 34 Layout Guidelines ...................................................................................................................................................................... 35 Manufacturing Guidelines .......................................................................................................................................................... 35 Additional Information ................................................................................................................................................................ 36 Revision History ......................................................................................................................................................................... 37 Rev 1.07 Page 3 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Electrical Characteristics All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are at 25°C and 3.3 V Vdd. Table 1. Output Characteristics Parameters Symbol Min. Typ. Max. Unit Condition Frequency Coverage Nominal Output Frequency Range F_nom 1 – 60 MHz Temperature Range Operating Temperature Range T_use -20 – +70 °C Extended Commercial, ambient temperature -40 – +85 °C Industrial, ambient temperature -40 – +105 °C Extended Industrial, ambient temperature Frequency Stability Frequency Stability over Temperature F_stab – – ±0.5 ppm – – ±1.0 ppm Referenced to (max frequency + min frequency)/2 over the rated temperature range. Vc=Vdd/2 for VCTCXO – – ±2.5 ppm Initial Tolerance F_init – – ±1 ppm Initial frequency at 25°C at 48 hours after 2 reflows Supply Voltage Sensitivity F_Vdd – ±7.10 ±16.25 ppb ±0.5 ppm F_stab, Vdd ±5% – ±11.83 ±32.50 ppb ±1.0ppm F_stab, Vdd ±5% – ±28.40 ±65.0 ppb ±2.5 ppm F_stab, Vdd ±5% – ±0.81 ±2.75 ppb ±0.5 ppm F_stab. LVCMOS output, 15 pF ±10%. Clipped sinewave output, 10 kΩ || 10 pF ±10% – ±1.35 ±5.50 ppb ±1.0 ppm F_stab. LVCMOS output, 15 pF ±10%. Clipped sinewave output, 10 kΩ || 10 pF ±10% – ±3.24 ±11.00 ppb ±2.5 ppm F_stab. LVCMOS output, 15 pF ±10%. Clipped sinewave output, 10 kΩ || 10 pF ±10% – ±15 ±25 ppb/°C ±0.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C – ±25 ±50 ppb/°C ±1.0 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C – ±60 ±100 ppb/°C ±2.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C – ±0.13 ±0.21 ppb/s ±0.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C – ±0.21 ±0.42 ppb/s ±1.0 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C – ±0.50 ±0.83 ppb/s ±2.5 ppm F_stab, 0.5°C/min ramp rate, -40 to 105°C Output Load Sensitivity Frequency vs. Temperature Slope Dynamic Frequency Change during Temperature Ramp F_load ΔF/ΔT F_dynamic One-Year Aging F_1y – ±1 – ppm At 25°C, after 2-days of continued operation. Aging is measured with respect to day 3 20-Year Aging F_20y – ±2 – ppm At 25°C, after 2-days of continued operation. Aging is measured with respect to day 3 DC 45 – 55 % Rise/Fall Time Tr, Tf 0.8 1.2 1.9 ns Output Voltage High VOH 90% – – Vdd IOH = +3 mA Output Voltage Low VOL – – 10% Vdd IOL = -3 mA Z_out_c – 17 – Ohms Impedance looking into output buffer, Vdd = 3.3 V – 17 – Ohms Impedance looking into output buffer, Vdd = 3.0 V – 18 – Ohms Impedance looking into output buffer, Vdd = 2.8 V – 19 – Ohms Impedance looking into output buffer, Vdd = 2.5 V LVCMOS Output Characteristics Duty Cycle Output Impedance 10% - 90% Vdd Clipped Sinewave Output Characteristics Output Voltage Swing V_out 0.8 – 1.2 V Clipped sinewave output, 10 kΩ || 10 pF ±10% Rise/Fall Time Tr, Tf – 3.5 4.6 ns 20% - 80% Vdd, F = 19.2 MHz ms Time to first pulse, measured from the time Vdd reaches 90% of its final value. Vdd ramp time = 100 µs from 0V to Vdd Start-up Characteristics Start-up Time Output Enable Time Time to Rated Frequency Stability Rev 1.07 T_start – 2.5 3.5 T_oe – – 680 ns F_nom = 10 MHz. See Timing Diagrams section below. T_stability – 5 45 ms Time to first accurate pulse within rated stability, measured from the time Vdd reaches 90% of its final value. Vdd ramp time = 100 µs Page 4 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Table 2. DC Characteristics Parameters Symbol Min. Typ. Max. Unit Condition Supply Voltage Supply Voltage Vdd 2.25 2.5 2.75 V 2.52 2.8 3.08 V 2.7 3.0 3.3 V 2.97 3.3 3.63 V Contact SiTime for 2.25 V to 3.63 V continuous supply voltage support Current Consumption Current Consumption OE Disable Current Idd I_od – 44 53 mA F_nom = 19.2 MHz, No Load, TCXO and DCTCXO modes – 48 57 mA F_nom = 19.2 MHz, No Load, VCTCXO mode – 43 51 mA OE = GND, output weakly pulled down. TCXO, DCTCXO – 47 55 mA OE = GND, output weakly pulled down. VCTCXO mode Typ. Max. Unit Table 3. Input Characteristics Parameters Symbol Min. Condition Input Characteristics – OE Pin Input Impedance Z_in 75 – – kΩ Input High Voltage VIH 70% – – Vdd Input Low Voltage VIL – – 30% Vdd Internal pull up to Vdd Frequency Tuning Range – Voltage Control or I2C mode Pull Range Absolute Pull Range[3] PR APR ±6.25 – – ppm VCTCXO mode; contact SiTime for ±12.5 and ±25 ppm ±6.25 ±10 ±12.5 ±25 ±50 ±80 ±100 ±125 ±150 ±200 ±400 ±600 ±800 ±1200 ±1600 ±3200 – – ppm DCTCXO mode ±2.75 – – ppm ±0.5 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm ±2.25 – – ppm ±1.0 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm ±0.75 – – ppm ±2.5 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm Upper Control Voltage VC_U 90% – – Vdd VCTCXO mode Lower Control Voltage VC_L – – 10% Vdd VCTCXO mode Control Voltage Input Impedance VC_z 8 – – MΩ VCTCXO mode Control Voltage Input Bandwidth VC_bw – 10 – kHz VCTCXO mode; contact SiTime for other bandwidth options 1.0 % Frequency Control Polarity F_pol Pull Range Linearity PR_lin Positive – 0.5 VCTCXO mode VCTCXO mode I2C Interface Characteristics, 200 Ohm, 550 pF (Max I2C Bus Load) Bus Speed F_I2C ≤ 400 kHz -40 to 105°C ≤ 1000 kHz -40 to 85°C Input Voltage Low VIL_I2C – – 30% Vdd DCTCXO mode Input Voltage High VIH_I2C 70% – – Vdd DCTCXO mode Output Voltage Low VOL_I2C – – 0.4 V DCTCXO mode IL 0.5 – 24 µA 0.1 VDD< VOUT < 0.9 VDD. Includes typical leakage current from 200 kΩ pull resister to VDD. DCTCXO mode CIN – – 5 pF DCTCXO mode Input Leakage current Input Capacitance Note: 3. APR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to Table 17 for APR with respect to other pull range options. Rev 1.07 Page 5 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Table 4. Jitter & Phase Noise – LVCMOS, -40°C to 85°C Parameters Symbol Min. Typ. Max. Unit Condition Jitter RMS Phase Jitter (random) T_phj – 0.31 0.48 ps F_nom = 10 MHz, Integration bandwidth = 12 kHz to 5 MHz – 0.31 0.48 ps F_nom = 50 MHz, Integration bandwidth = 12 kHz to 20 MHz RMS Period Jitter T_jitt_per – 0.8 1.1 ps F_nom = 10 MHz, population 10 k Peak Cycle-to-Cycle Jitter T_jitt_cc – 6 9 ps F_nom = 10 MHz, population 1 k, measured as absolute value 1 Hz offset – -80 -74 dBc/Hz 10 Hz offset – -108 -102 dBc/Hz 100 Hz offset – -127 -123 dBc/Hz 1 kHz offset – -148 -145 dBc/Hz 10 kHz offset – -154 -151 dBc/Hz 100 kHz offset – -154 -150 dBc/Hz 1 MHz offset – -167 -163 dBc/Hz 5 MHz offset – -168 -164 dBc/Hz – -112 -105 dBc Phase Noise T_spur Spurious F_nom = 10 MHz TCXO and DCTCXO modes, and VCTCXO mode with ±6.25 ppm pull range F_nom = 10 MHz, 1 kHz to 5 MHz offsets Table 5. Jitter & Phase Noise – Clipped Sinewave, -40°C to 85°C Parameters Symbol Min. Typ. Max. Unit Condition Jitter RMS Phase Jitter (random) T_phj – 0.31 0.45 ps F_nom = 19.2 MHz, Integration bandwidth = 12 kHz to 5 MHz – 0.31 0.48 ps F_nom = 60 MHz, Integration bandwidth = 12 kHz to 20 MHz Phase Noise 1 Hz offset – -74 -68 dBc/Hz 10 Hz offset – -102 -97 dBc/Hz 100 Hz offset – -121 -117 dBc/Hz 1 kHz offset – -142 -140 dBc/Hz 10 kHz offset – -148 -146 dBc/Hz 100 kHz offset – -149 -145 dBc/Hz 1 MHz offset – -162 -159 dBc/Hz 5 MHz offset – -164 -160 dBc/Hz – -109 -104 dBc Spurious Rev 1.07 T_spur Page 6 of 38 F_nom = 19.2 MHz TCXO and DCTCXO modes, and VCTCXO mode with ±6.25 ppm pull range F_nom = 19.2 MHz, 1 kHz to 5 MHz offsets www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Table 6. Jitter & Phase Noise – LVCMOS, -40°C to 105°C Parameters Symbol Min. Typ. Max. Unit Condition Jitter RMS Phase Jitter (random) T_phj – 0.31 0.48 ps F_nom = 10 MHz, Integration bandwidth = 12 kHz to 5 MHz – 0.31 0.50 ps F_nom = 50 MHz, Integration bandwidth = 12 kHz to 20 MHz RMS Period Jitter T_jitt_per – 0.8 1.1 ps F_nom = 10 MHz, population 10 k Peak Cycle-to-Cycle Jitter T_jitt_cc – 6 9 ps F_nom = 10 MHz, population 1 k, measured as absolute value 1 Hz offset – -80 -74 dBc/Hz 10 Hz offset – -108 -102 dBc/Hz 100 Hz offset – -127 -123 dBc/Hz 1 kHz offset – -148 -145 dBc/Hz 10 kHz offset – -154 -151 dBc/Hz 100 kHz offset – -154 -150 dBc/Hz 1 MHz offset – -167 -162 dBc/Hz 5 MHz offset – -168 -164 dBc/Hz – -112 -101 dBc F_nom = 10 MHz, 1 kHz to 5 MHz offsets, Vdd = 2.5 V – -112 -106 dBc F_nom = 10 MHz, 1 kHz to 5 MHz offsets, Vdd = 2.8 V, 3.0 V, 3.3 V Phase Noise Spurious T_spur F_nom = 10 MHz TCXO and DCTCXO modes, and VCTCXO mode with ±6.25 ppm pull range. Table 7. Jitter & Phase Noise – Clipped Sinewave, -40°C to 105°C Parameters Symbol Min. Typ. Max. Unit Condition Jitter RMS Phase Jitter (random) T_phj – 0.31 0.46 ps F_nom = 19.2 MHz, Integration bandwidth = 12 kHz to 5 MHz – 0.31 0.50 ps F_nom = 60 MHz, Integration bandwidth = 12 kHz to 20 MHz Phase Noise 1 Hz offset – -74 -68 dBc/Hz 10 Hz offset – -102 -97 dBc/Hz 100 Hz offset – -121 -117 dBc/Hz 1 kHz offset – -142 -140 dBc/Hz 10 kHz offset – -148 -146 dBc/Hz 100 kHz offset – -149 -145 dBc/Hz 1 MHz offset – -162 -158 dBc/Hz 5 MHz offset – -164 -159 dBc/Hz – -109 -103 dBc Spurious Rev 1.07 T_spur Page 7 of 38 F_nom = 19.2 MHz TCXO and DCTCXO modes, and VCTCXO mode with ±6.25 ppm pull range F_nom = 19.2 MHz, 1 kHz to 5 MHz offsets www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Table 8. Absolute Maximum Limits Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Parameter Test Conditions Storage Temperature Continuous Power Supply Voltage Range (Vdd) Human Body Model (HBM) ESD Protection JESD22-A114 Soldering Temperature (follow standard Pb-free soldering guidelines) Value Unit -65 to 125 °C -0.5 to 4 V 2000 V 260 °C 130 °C Input Voltage, Maximum Any input pin Vdd + 0.3 V Input Voltage, Minimum Any input pin -0.3 V Junction Temperature[4] Note: 4. Exceeding this temperature for an extended period of time may damage the device. Table 9. Thermal Considerations[5] Package JA[6] (°C/W) JC, Bottom (°C/W) Ceramic 5.0 mm x 3.2 mm 54 15 Note: 5. Measured in still air. Refer to JESD51 for θJA and θJC definitions. 6. Devices soldered on a JESD51 2s2p compliant board. Table 10. Maximum Operating Junction Temperature[7] Max Operating Temperature (ambient) Maximum Operating Junction Temperature 70°C 80°C 85°C 95°C 105°C 115°C Note: 7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature. Table 11. Environmental Compliance Value Unit Mechanical Shock Resistance Parameter MIL-STD-883F, Method 2002 30000 g Mechanical Vibration Resistance MIL-STD-883F, Method 2007 70 g Temperature Cycle JESD22, Method A104 – – Solderability MIL-STD-883F, Method 2003 – – Moisture Sensitivity Level MSL1 @260°C – – Rev 1.07 Test Conditions Page 8 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Device Configurations and Pin-outs Table 12. Device Configurations I2C Programmable Parameters Configuration Pin 1 Pin 5 TCXO OE/NC NC – – VCTCXO VC NC DCTCXO OE/NC A0/NC Frequency Pull Range, Frequency Pull Value, Output Enable control. Pin-out Top Views OE/NC 1 NC 9 VDD VC 1 2 8 NC NC NC 3 7 NC GND 4 6 CLK 10 5 SDA NC NC OE / NC 1 NC SCL 7 NC 6 CLK 9 VDD 2 8 NC 3 GND 4 10 5 9 VDD 2 8 NC NC 3 7 NC GND 4 6 CLK 10 5 NC NC A0 / NC Figure 3. TCXO Figure 4. VCTCXO Figure 5. DCTCXO Table 13. Pin Description Pin 1 Symbol OE/NC [10]/VC I/O Internal Pull-up/Pull Down Resistor OE – Input 100 kΩ Pull-Up NC – No Connect – H or L or Open: No effect on output frequency or other device functions VC – Input – Control Voltage in VCTCXO Mode SCL – Input 200 kΩ Pull-Up Function H[8]: specified frequency output L: output is high impedance. Only output driver is disabled. I2C serial clock input. 2 SCL / NC [10] 3 NC[10] No Connect – H or L or Open: No effect on output frequency or other device functions 4 GND Power – Connect to ground No Connect 5 A0 / NC[10] H or L or Open: No effect on output frequency or other device functions Device I2C address when the address selection mode is via the A0 pin. This pin is NC when the I2C device address is specified in the ordering code. A0 Logic Level I2C Address 0 1100010 1 1101010 A0 – Input 100 kΩ Pull-Up NC – No Connect – H or L or Open: No effect on output frequency or other device functions. Output – LVCMOS, or clipped sinewave oscillator output 7 NC [10] No Connect – H or L or Open: No effect on output frequency or other device functions 8 NC[10] No Connect – H or L or Open: No effect on output frequency or other device functions 9 VDD Power – Connect to power supply[9] SDA / NC [10] SDA – Input/Output 200 kΩ Pull Up 10 NC – No Connect – 6 CLK I2C Serial Data. H or L or Open: No effect on output frequency or other device functions. Notes: 8. In OE mode for noisy environments, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option. 9. A 0.1 μF capacitor in parallel with a 10 μF capacitor are required between VDD and GND. The 0.1 μF capacitor is recommended to place close to the device, and place the 10 μF capacitor less than 2 inches away. 10. All NC pins can be left floating and do not need to be soldered down. Rev 1.07 Page 9 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs VDD 9 + 7 10 10µF 5 1 2 3 4 15pF (including probe and fixture capacitance) 7 6 10 10µF - 8 0.1µF Power Supply Test Point CLK 9 + 6 0.1µF Power Supply - 8 VDD Test Point CLK 5 1 2 3 10pF 10kΩ (including probe and fixture resistance and capacitance) 4 Vdd Vdd OE Function OE Function Figure 6. LVCMOS Test Circuit (OE Function) VDD CLK 9 + 8 7 VDD Test Point 10 5 10µF 1 2 3 15pF 7 6 10pF 10 10µF - (including probe and fixture capacitance) 4 8 0.1µF Power Supply Test Point CLK 9 + 6 0.1µF Power Supply - Figure 7. Clipped Sinewave Test Circuit (OE Function) for AC and DC Measurements 10kΩ 5 1 2 3 (including probe and fixture resistance and capacitance) 4 Control Voltage Control Voltage VC Function VC Function Figure 8. LVCMOS Test Circuit (VC Function) VDD CLK 9 + 7 Test Point 6 VDD 10 10µF 1 5 2 3 4 15pF (including probe and fixture capacitance) 1 5 2 3 4 10pF 10kΩ (including probe and fixture resistance and capacitance) NC Function NC Function Rev 1.07 6 Any state or floating Any state or floating Figure 10. LVCMOS Test Circuit (NC Function) 7 10 10µF - 8 0.1µF Power Supply Test Point CLK 9 + 0.1µF Power Supply - 8 Figure 9. Clipped Sinewave Test Circuit (VC Function) for AC and DC Measurements Figure 11. Clipped Sinewave Test Circuit (NC Function) for AC and DC Measurements Page 10 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs (continued) VDD 9 + 8 7 6 A0/NC 0.1µF Power Supply - Test Point CLK 10 10µF SDA 5 1 [11] 2 Any state or floating NC Function 3 15pF (including probe and fixture capacitance) 4 SCL Figure 12. LVCMOS Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements VDD 9 + 8 7 A0/NC 6 0.1µF Power Supply 10 10µF - Test Point CLK 1 SDA[11] 10pF 5 2 Any state or floating NC Function 3 10kΩ (including probe and fixture resistance and capacitance) 4 SCL Figure 13. Clipped Sinewave Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements VDD CLK Test Point 9 + - 8 7 6 A0/NC 0.1µF Power Supply 10pF 10 10µF 1 5 2 3 4 10kΩ (including probe and fixture resistance and capacitance) Any state or floating NC Function Figure 14. Clipped Sinewave Test Circuit for Phase Noise Measurements, Applies to All Configurations (NC Function shown for example only) Note: 11. SDA is open-drain and may require pull-up resistor if not present in I2C test setup. Rev 1.07 Page 11 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Waveforms tr tf 90 % Vdd 50 % Vdd 10 % Vdd High Pulse (TH) Low Pulse (TL) Period Figure 15. LVCMOS Waveform Diagram[12] tr tf 80 % Vout 50 % Vout Vout 20 % Vout High Pulse (TH) Low Pulse (TL) Period Figure 16. Clipped Sinewave Waveform Diagram[12] Note: 12. Duty Cycle is computed as Duty Cycle = TH/Period. Rev 1.07 Page 12 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Timing Diagrams 90% Vdd Vdd Vdd 50% Vdd T_start Vdd Pin Voltage OE Voltage CLK Output CLK Output HZ HZ T_start: Time to start from power-off T_oe: Time to re-enable the clock output Figure 18. OE Enable Timing (OE Mode Only) Figure 17. Startup Timing Rev 1.07 T_oe Page 13 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Typical Performance Plots 2.5 V 2.8 V 3.0 V 3.3 V 2.5 V 1.25 55 2.8 V 3.0 V 3.3 V 1.20 1.15 Rise time (ns) Duty cycle (%) 53 51 49 1.10 1.05 1.00 47 0.95 0.90 45 10 20 30 40 50 10 60 20 Frequency (MHz) Figure 19. Duty Cycle (LVCMOS) 2.5 V 2.8 V 3.0 V 3.3 V 2.5 V 46 45 44 43 42 41 40 10 2.8 V 3.0 V 3.3 V 20 30 40 50 50 49 48 47 46 45 44 60 10 20 2.5 V 500 2.8 V 30 40 50 60 Frequency (MHz) Figure 21. IDD TCXO (LVCMOS) Figure 22. IDD VCTCXO (LVCMOS) 3.0 V 2.5 V 3.3 V 3.3 V 1.90 Period Jitter (ps RMS) Phase Jitter (fs RMS) 60 51 Frequency (MHz) 400 300 200 100 0 1.70 1.50 1.30 1.10 0.90 0.70 0.50 10 20 30 40 50 60 10 20 Figure 23. RMS Phase Jitter, DCTCXO, TCXO (LVCMOS) 2.5 V 2.8 V 30 40 50 60 Frequency (MHz) Frequency (MHz) 3.0 V Figure 24. RMS Period Jitter (LVCMOS) 2.5 V 3.3 V 2.8 V 3.0 V 3.3 V 500 48 47 Phase Jitter (fs RMS) Current consumption (mA) 50 52 47 46 45 44 43 42 41 400 300 200 100 40 10 20 30 40 50 60 Frequency (MHz) 0 10 20 30 40 50 60 Frequency (MHz) Figure 25. IDD DCTCXO (LVCMOS) Rev 1.07 40 Figure 20. Rise Time (LVCMOS) Current consumption (mA) Current consumption (mA) 48 30 Frequency (MHz) Figure 26. RMS Phase Jitter, VCTCXO (LVCMOS) Page 14 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO 2.5 V 6.25 5 3.75 2.5 1.25 0 -1.25 -2.5 -3.75 -5 2.8 V 3.40 3.20 3.00 2.80 2.60 -5 -3.75 -2.5 -1.25 0 1.25 2.5 3.75 5 6.25 10 15 20 25 DCTCXO pull (ppm) 2.5 V 2.8 V 3.0 V 2.5 V 3.3 V 40 45 50 55 60 2.8 V 3.0 V 3.3 V 50 Current consumption (mA) Current consumption (mA) 35 Figure 28. Rise Time (Clipped Sinewave) 45.5 45.0 44.5 44.0 43.5 49 48 47 46 45 44 43 43.0 10 15 20 25 30 35 40 45 50 55 10 60 15 20 25 Frequency (MHz) 2.5 V 2.8 V 30 35 40 45 50 55 60 Frequency (MHz) Figure 29. IDD TCXO (Clipped Sinewave) 3.0 V Figure 30. IDD VCTCXO (Clipped Sinewave) 3.3 V 2.5 V Current consumption (mA) 500 Phase Jitter (fs RMS) 30 Frequency (MHz) Figure 27. DCTCXO frequency pull characteristic 400 300 200 100 2.8 V 3.0 V 3.3 V 46.5 46.0 45.5 45.0 44.5 44.0 43.5 43.0 0 10 20 30 40 50 10 60 15 20 25 Frequency (MHz) 2.5 V 2.8 V 30 35 40 45 50 55 60 Frequency (MHz) Figure 31. RMS Phase Jitter, DCTCXO, TCXO (Clip Sine) 3.0 V Figure 32. IDD DCTCXO (Clipped Sinewave) 2.5 V 3.3 V 500 55 400 53 Duty cycle (%) Phase Jitter (fs RMS) 3.3 V 3.60 -6.25 -6.25 300 200 2.8 V 3.0 V 3.3 V 51 49 47 100 45 0 10 20 30 40 50 60 Frequency (MHz) 10 15 20 25 30 35 40 45 50 55 60 Frequency (MHz) Figure 33. RMS Phase Jitter, VCTCXO (Clipped Sine) Rev 1.07 3.0 V 3.80 Rise Time (ns) Frequency deviation (ppm) Typical Performance Plots (continued) Page 15 of 38 Figure 34. Duty Cycle (Clipped Sinewave) www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Architecture Overview Functional Overview Based on SiTime’s innovative Elite Platform®, the SiT5156 delivers exceptional dynamic performance, i.e. resilience to environmental stressors such as shock, vibration, and fast temperature transients. Underpinning the Elite platform are SiTime’s unique DualMEMS® temperature sensing architecture and TurboCompensation™ technologies. The SiT5156 is designed for maximum flexibility with an array of factory programmable options, enabling system designers to configure this precision device for optimal performance in a given application. DualMEMS is a noiseless temperature compensation scheme. It consists of two MEMS resonators fabricated on the same die substrate. The TempFlat® MEMS resonator is designed with a flat frequency characteristic over temperature whereas the temperature sensing resonator is by design sensitive to temperature changes. The ratio of frequencies between these two resonators provides an accurate reading of the resonator temperature with 20 µK resolution. By placing the two MEMS resonators on the same die, this temperature sensing scheme eliminates any thermal lag and gradients between resonator and temperature sensor, thereby overcoming an inherent weakness of legacy quartz TCXOs. The DualMEMS temperature sensor drives a state-of-theart CMOS temperature compensation circuit. The TurboCompensation design, with >100 Hz compensation bandwidth, achieves a dynamic frequency stability that is far superior to any quartz TCXO. The digital temperature compensation enables additional optimization of frequency stability and frequency slope over temperature within any chosen temperature range for a given system design. The Elite platform also incorporates a high resolution, low noise frequency synthesizer along with the industry standard I2C bus. This unique combination enables system designers to digitally control the output frequency in steps as low as 5 ppt and over a wide range up to ±3200 ppm. For more information regarding the Elite platform and its benefits please visit: ◼ SiTime's breakthroughs section ◼ TechPaper: DualMEMS Temperature Sensing Technology ◼ TechPaper: DualMEMS Resonator TDC Rev 1.07 Frequency Stability The SiT5156 comes in three factory-trimmed stability grades. Table 14. Stability Grades vs. Ordering Codes Frequency Stability Over Temperature Ordering Code ±0.5 ppm K ±1.0 ppm A ±2.5 ppm D Output Frequency and Format The SiT5156 can be factory programmed for an output frequency without sacrificing lead time or incurring an upfront customization cost typically associated with customfrequency quartz TCXOs. The device supports both LVCMOS and clipped sinewave output. Ordering codes for the output format are shown below: Table 15. Output Formats vs. Ordering Codes Output Format Ordering Code LVCMOS “-“ Clipped Sinewave “C” Output Frequency Tuning In addition to the non-pullable TCXO, the SiT5156 can also support output frequency tuning through either an analog control voltage (VCTCXO), or I2C interface (DCTCXO). The I2C interface enables 16 factory programmed pull-range options from ±6.25 ppm to ±3200 ppm. The pull range can also be reprogrammed via I2C to any supported pull-range value. Refer to Device Configuration section for details. Page 16 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Pin 1 Configuration (OE, VC, or NC) Device Configurations Pin 1 of the SiT5156 can be factory programmed to support three modes: Output Enable (OE), Voltage Control (VC), or No Connect (NC). The SiT5156 supports 3 device configurations – TCXO, VCTCXO, and DCTCXO. The TCXO and VCTCXO options are directly compatible with the quartz TCXO and VCTCXO. The DCTCXO configuration provides performance enhancement by eliminating VCTCXO’s sensitivity to control voltage noise with an I 2C digital interface for frequency tuning. Table 16. Pin Configuration Options Pin 1 Configuration Operating Mode Output OE TCXO/DCTCXO Active or High-Z NC TCXO/DCTCXO Active VC VCTCXO Active When pin 1 is configured as OE pin, the device output is guaranteed to operate in one of the following two states: ◼ Clock output with the frequency specified in the part number when Pin 1 is pulled to logic high ◼ Hi-Z mode with weak pull down when pin 1 is pulled to logic low. When pin 1 is configured as NC, the device is guaranteed to output the frequency specified in the part number at all times, regardless of the logic level on pin 1. In the VCTCXO configuration, the user can fine-tune the output frequency from the nominal frequency specified in the part number by varying the pin 1 voltage. The guaranteed allowable variation of the output frequency is specified as pull range. A VCTCXO part number must contain a valid pull-range ordering code. Figure 35. Block Diagram – TCXO TCXO Configuration The TCXO generates a fixed frequency output, as shown in Figure 35. The frequency is specified by the user in the frequency field of the device ordering code and then factory programmed. Other factory programmable options include supply voltage, output types (LVCMOS or clipped sinewave), and pin 1 functionality (OE or NC). Refer to the Ordering Information section at the end of the datasheet for a list of all ordering options. Rev 1.07 Page 17 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO VCTCXO Configuration A VCTCXO, shown in Figure 36, is a frequency control device whose output frequency is an approximately linear function of control voltage applied to the voltage control pin. VCTCXOs have a number of use cases including the VCO portion of a jitter attenuation/jitter cleaner PLL Loop. The SiT5156 achieves a 10x better pull range linearity of 250 nsec FM+ (1 MHz) >0 nsec FM (400 KHz) >0 nsec SM (100 KHz) >0 nsec FM+ > 450 nsec FM (400 KHz) > 900 nsec SM (100 KHz) > 3450 nsec tHOLD tVD:AWK tVD:DAT Rev 1.07 NA (s-awk + s-data)/(m-awk/s-data) Page 31 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Table 24. Pin Selectable I2C Address Control[17] I2C Device Address Modes A0 Pin 5 There are two I2C address modes: I2C Address 0 1100010 1 1101010 Notes: 17. Table 24 is only valid for the DCTCXO device option which supports I2C control and A0 Device Address Control Pin. Table 23. Factory Programmed I2C Address Control[16] I2C Address Ordering Code Device I2C Address 0 1100000 1 1100001 2 1100010 3 1100011 4 1100100 5 1100101 6 1100110 7 1100111 8 1101000 9 1101001 A 1101010 B 1101011 C 1101100 D 1101101 E 1101110 F 1101111 Notes: 16. Table 23 is only valid for the DCTCXO device option which supports I2C Control. Rev 1.07 Page 32 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Schematic Example Figure 49. DCTCXO schematic example Rev 1.07 Page 33 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Dimensions and Patterns Package Size – Dimensions (Unit: mm) Recommended Land Pattern (Unit: mm) Rev 1.07 Page 34 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Layout Guidelines ◼ ◼ ◼ Manufacturing Guidelines The SiT5156 uses internal regulators to minimize the impact of power supply noise. For further reduction of noise, it is essential to use two bypass capacitors (0.1 μF and 10 μF). Place the 0.1 μF capacitor as close to the VDD pin as possible, typically within 1 mm to 2 mm. Place the 10 μF capacitor within 2 inches of the device VDD and VSS pins. It is also recommended to connect all NC pins to the ground plane and place multiple vias under the GND pin for maximum heat dissipation. The SiT5156 Super-TCXOs are precision timing devices. Proper PCB solder and cleaning processes must be followed to ensure best performance and long-term reliability. ◼ No Ultrasonic or Megasonic Cleaning: Do not subject the SiT5156 to an ultrasonic or megasonic cleaning environment. Otherwise, permanent damage or long-term reliability issues to the device may result. ◼ No external cover. Unlike legacy quartz TCXOs, the SiT5156 is engineered to operate reliably, without performance degradation in the presence of ambient disturbers such as airflow and sudden temperature changes. Therefore, the use of an external cover typically required by quartz TCXOs is not needed. ◼ Reflow profile: For mounting these devices to the PCB, IPC/JEDEC J-STD-020 compliant reflow profile must be used. Device performance is not guaranteed if soldered manually or with a non-compliant reflow profile. ◼ PCB cleaning: After the surface mount (SMT)/reflow process, solder flux residues may be present on the PCB and around the pads of the device. Excess residual solder flux may lead to problems such as pad corrosion, elevated leakage currents, increased frequency aging, or other performance degradation. For optimal device performance and long-term reliability, thorough cleaning to remove all the residual flux and drying of the PCB is required as shortly after the reflow process as possible. Water soluble flux is recommended. In addition, it is highly recommended to avoid the use of any “no clean” flux. However, if the reflow process necessitates the use of “no clean” flux, then utmost care should be taken to remove all residual flux between SiTime device and the PCB. Note that ultrasonic PCB cleaning should not be used with SiTime oscillators. ◼ For additional manufacturing guidelines and marking/ tape-reel instructions, refer to SiTime Manufacturing Notes. For additional layout recommendations, refer to the Best Design Layout Practices. Rev 1.07 Page 35 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Additional Information Table 25. Additional Information Document Description Download Link ECCN #: EAR99 Five character designation used on the commerce Control List (CCL) to identify dual use items for export control purposes. — HTS Classification Code: 8542.39.0000 A Harmonized Tariff Schedule (HTS) code developed by — the World Customs Organization to classify/define internationally traded goods. Evaluation Boards SiT6722EB Evaluation Board User Manual https://www.sitime.com/support/user-guides Demo Board SiT6702DB Demo Board User Manual https://www.sitime.com/support/user-guides Time Machine II MEMS oscillator programmer http://www.sitime.com/support/time-machine-oscillator-programmer Time Master Web-based Configurator Web tool to establish proper programming https://www.sitime.com/time-master-web-based-configurator Manufacturing Notes Tape & Reel dimension, reflow profile and other manufacturing related info https://www.sitime.com/support/resource-library/manufacturing-notessitime-products Qualification Reports RoHS report, reliability reports, composition reports http://www.sitime.com/support/quality-and-reliability Performance Reports Additional performance data such as phase noise, current consumption and jitter for selected frequencies http://www.sitime.com/support/performance-measurement-report Termination Techniques Termination design recommendations http://www.sitime.com/support/application-notes Layout Techniques Layout recommendations http://www.sitime.com/support/application-notes Rev 1.07 Page 36 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO Revision History Table 26. Revision History Version Release Date Change Summary 0.1 0.15 10 May 2016 4 August 2016 0.16 0.2 0.4 12 September 2016 21 September 2016 19 December 2016 0.5 21 July 2017 0.51 20 August 2017 0.52 24 November 2017 0.55 5 February 2018 0.60 1.0 1 March 2018 26 June 2018 1.01 1.02 1.03 3 July 2018 4 July 2018 3 August 2018 1.04 4 December 2018 1.05 28 March 2020 1.06 1.07 23 May 2020 1 January 2023 First release, advanced information Replaced QFN package with SOIC-8 package Added 10 µF bypass cap requirement Updated test circuits to reflect both new bypass cap requirement and SOIC-8 package Update Table 1 (Electrical Characteristics) Updated test circuit diagrams Revised Table 1 (Electrical Characteristics) Added DCTCXO mode Added I2C information Added I2C Added 5.0 mm x 3.2 mm package information Updated Table 1 (Electrical Characteristics) Changed to preliminary Updated 5.0 mm x 3.2 mm package dimensions Updated test circuits Updated Table 1 (Electrical Characteristics) Updated part ordering info Misc. corrections Updated the Thermal Characteristics table Added more on Manufacturing Guideline section Added View labels to Package Drawings Updated the frequency vs. output type changes to 60 MHz Updated links and notes Added 105°C support, updated Ordering Information Updated Electrical Characteristics tables. Added Performance Plots. Improved readability. Fixed bad hyperlinks. Updated I2C specifications in Table 3 (Input Characteristics). Updated Mechanical Shock Resistance, Table 11 (Environmental Compliance) Added test circuit for clipped sinewave phase noise. Revised phase noise specifications. Updated package outline drawing. Updated conditions for one day and one year aging specs. Various formatting updates. Formatting updates Fixed APR typo for 125 ppm pull range and 0.5 ppm stability, Table 18 Fixed test condition typo (10 MHz to 50 MHz) for phase jitter in Table 4 Corrected typos in package drawing dimensions Added nominal value for LVCMOS output impedance Increased Mechanical Shock Resistance to 30000g Added “X” ordering code for 250u Tape and Reel Improved I2C bus frequency specification Updated Manufacturing Guidelines to recommend water soluble flux Corrected typos for write/read I2C polarity Clarified PCB cleaning instructions Added link to SiT6702DB Added ECCN and HTS codes Formatting updates Added note for Theta JA Updated DCTCXO Delay and Settling Time table Added max and min input voltage to the Absolute Maximum Limits table Updated output impedance typical spec Clarified Initial Tolerance specification condition Relabeled “First Pulse Accuracy” parameter to “Time to Rated Frequency Stability” for clarity Revised Parallel Data Format section description and figures Updated company disclaimer, links, references and icons Rev 1.07 Page 37 of 38 www.sitime.com SiT5156 1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform Super-TCXO SiTime Corporation, 5451 Patrick Henry Drive, Santa Clara, CA 95054, USA | Phone: +1-408-328-4400 | Fax: +1-408-328-4439 © SiTime Corporation 2016-2023. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liabi lity for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress. 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CRITICAL USE EXCLUSION POLICY BUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS: USED IN LIFE SUPPORT DEVICES, TO OPERATE NUCLEAR FACILITIES, FOR MILITARY OR AEROSPACE USE, OR IN OTHER MISSION CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROP ERTY MAY BE AT STAKE. For aerospace and defense applications, SiTime recommends using only Endura™ ruggedized products. SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibited. Rev 1.07 Page 38 of 38 www.sitime.com