18NM60N

STL18NM60N N-channel 600 V, 0.260 Ω 6 A PowerFLAT™ 8x8 HV , MDmesh™ II Power MOSFET Features Order code STL18NM60N VDSS @ TJmax 650 V RDS(on) max < 0.310 Ω ID 12 A (1) 1. The value is rated according to Rthj-case ■ ■ ■ 100% avalanche tested Low input capacitance and gate charge Low gate input resistance Applications ■ Switching applications Figure 1. Internal schematic diagram Description This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. Table 1. Device summary Marking 18NM60N Package PowerFLAT™ 8x8 HV Packaging Tape and reel Order code STL18NM60N November 2011 Doc ID 018856 Rev 2 1/14 www.st.com 14 Contents STL18NM60N Contents 1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 4 5 Test circuits .............................................. 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 Doc ID 018856 Rev 2 STL18NM60N Electrical ratings 1 Electrical ratings Table 2. Symbol VDS VGS ID (1) Absolute maximum ratings Parameter Drain-source voltage Gate-source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (continuous) at Tamb = 25 °C Drain current (continuous) at Tamb = 100 °C Drain current (pulsed) Total dissipation at Tamb = 25 °C Total dissipation at TC = 25 °C Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) Peak diode recovery voltage slope Storage temperature Max. operating junction temperature Value 600 ± 25 12 7.5 2.1 1.2 8.4 3 110 3.5 105 15 - 55 to 150 150 Unit V V A A A A A W W A mJ V/ns °C °C ID (1) ID(2) ID(2) IDM (2),(3) PTOT (2) PTOT(1) IAR EAS dv/dt (4) Tstg Tj 1. The value is rated according to Rthj-case 2. When mounted on FR-4 board of inch², 2oz Cu 3. Pulse width limited by safe operating area 4. ISD ≤ 12 A, di/dt ≤ 400 A/µs, VDSpeak ≤V(BR)DSS, VDD = 80% V(BR)DSS Table 3. Symbol Rthj-case Rthj-amb(1) Thermal data Parameter Thermal resistance junction-case max Thermal resistance junction-amb max Value 1.14 45 Unit °C/W °C/W 1. When mounted on 1inch² FR-4 board, 2 oz Cu Doc ID 018856 Rev 2 3/14 Electrical characteristics STL18NM60N 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) On /off states Parameter Drain-source breakdown voltage Test conditions ID = 1 mA, VGS = 0 Min. 600 1 100 100 2 3 0.260 4 0.310 Typ. Max. Unit V µA µA nA V Ω VDS = 600 V Zero gate voltage drain current (VGS = 0) VDS = 600 V, TC= 125 °C Gate-body leakage current (VDS = 0) VGS = ± 25 V Gate threshold voltage VDS = VGS, ID = 250 µA Static drain-source on resistance VGS = 10 V, ID = 6 A Table 5. Symbol Ciss Coss Crss Coss eq.(1) RG Qg Qgs Qgd Dynamic Parameter Input capacitance Output capacitance Reverse transfer capacitance Output equivalent capacitance Intrinsic gate resistance Total gate charge Gate-source charge Gate-drain charge Test conditions Min. Typ. 1000 60 3 225 3.5 35 6 20 Max. Unit pF pF pF pF Ω nC nC nC VDS = 50 V, f = 1 MHz, VGS = 0 - - VDS = 0 to 480 V, VGS = 0 f = 1 MHz open drain VDD = 480 V, ID = 13 A, VGS = 10 V (see Figure 14) - - - - 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS. Table 6. Symbol td(on) tr td(off) tf Switching times Parameter Turn-on delay time Rise time Turn-on delay time Fall time Test conditions VDD = 300 V, ID = 13 A, RG = 4.7 Ω, VGS = 10 V (see Figure 17) Min. Typ. 20 22 50 40 Max Unit ns ns ns ns - - 4/14 Doc ID 018856 Rev 2 STL18NM60N Electrical characteristics Table 7. Symbol ISD ISDM (1) VSD (2) trr Qrr IRRM trr Qrr IRRM Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 12 A, VGS = 0 ISD = 13 A, di/dt = 100 A/µs VDD = 60 V (see Figure 19) VDD = 60 V di/dt = 100 A/µs, ISD = 13 A Tj=150 °C (see Figure 19) Test conditions Min. 300 4.0 25 360 4.5 25 Typ. Max. Unit 12 48 1.6 A A V ns µC A ns µC A - 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 018856 Rev 2 5/14 Electrical characteristics STL18NM60N 2.1 Figure 2. Electrical characteristics (curves) Safe operating area Figure 3. K δ=0.5 Thermal impedance Zth PowerFLAT 8x8 HV 0.2 0.1 10 -1 0.05 0.02 0.01 Single pulse 10 -5 10 -2 10 -4 10 -3 10 -2 tp (s) Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. (norm) Normalized BVDSS vs temperature AM09028v1 Figure 7. RDS(on) (Ω) 0.270 Static drain-source on resistance AM09788v1 VDS 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 -50 -25 ID=1mA VGS=10V 0.265 0.260 0.255 0.250 0.245 0 25 50 75 100 TJ(°C) 0 2 4 6 8 10 12 ID(A) 6/14 Doc ID 018856 Rev 2 STL18NM60N Figure 8. VGS (V) 12 10 VDS 8 300 6 4 2 0 0 10 20 30 40 200 10 100 0 Qg(nC) 1 0.1 100 400 Electrical characteristics Capacitance variations AM05532v1 Gate charge vs gate-source voltage Figure 9. AM05531v1 VDD=480V ID=13A 500 C (pF) 1000 Ciss Coss Crss 1 10 100 VDS(V) Figure 10. Normalized gate threshold voltage vs temperature Figure 11. Normalized on resistance vs temperature Figure 12. Source-drain diode forward characteristics Doc ID 018856 Rev 2 7/14 Test circuits STL18NM60N 3 Test circuits Figure 14. Gate charge test circuit VDD 12V 2200 Figure 13. Switching times test circuit for resistive load 47kΩ 100nF 1kΩ RL VGS VD RG PW D.U.T. μF 3.3 μF VDD Vi=20V=VGMAX 2200 μF IG=CONST 2.7kΩ 47kΩ PW 1kΩ 100Ω D.U.T. VG AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit A D G S B 25 Ω D.U.T. A FAST DIODE B A L=100μH B D G 3.3 μF 1000 μF L VD 2200 μF 3.3 μF VDD VDD ID RG S Vi D.U.T. Pw AM01470v1 AM01471v1 Figure 17. Unclamped inductive waveform V(BR)DSS VD Figure 18. Switching time waveform ton tdon tr toff tdoff tf 90% IDM 90% 10% ID VDD VDD 0 10% VDS 90% VGS AM01472v1 0 10% AM01473v1 8/14 Doc ID 018856 Rev 2 STL18NM60N Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Doc ID 018856 Rev 2 9/14 Package mechanical data STL18NM60N Table 8. PowerFLAT™ 8x8 HV mechanical data mm Dim. Min. A A1 b D E D2 E2 e L aaa bbb ccc 0.40 7.05 4.15 0.80 0.00 0.95 Typ. 0.90 0.02 1.00 8.00 8.00 7.20 4.30 2.00 0.50 0.10 0.10 0.10 0.60 7.30 4.40 Max. 1.00 0.05 1.05 10/14 Doc ID 018856 Rev 2 STL18NM60N Package mechanical data Figure 19. PowerFLAT™ 8x8 HV drawing mechanical data BOTTOM VIEW b bbb CAB PIN#1 ID L 0.40 D2 ccc C A 0.20±0.008 SIDE VIEW E2 A1 C SEATING PLANE 0.08 C D A B INDEX AREA aaa C TOP VIEW aaa C 8222871_Rev_B Doc ID 018856 Rev 2 E 11/14 Package mechanical data STL18NM60N Figure 20. PowerFLAT™ 8x8 HV recommended footprint 7.30 7.70 2.00 1.05 Footprint 12/14 Doc ID 018856 Rev 2 0.60 4.40 STL18NM60N Revision history 5 Revision history Table 9. Date 19-May-2011 03-Nov-2011 Document revision history Revision 1 2 First release. Section 4: Package mechanical data has been updated. Minor text changes. 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