AT24C16D
I²C-Compatible (Two-Wire)
Serial EEPROM 16‑Kbit (2,048 x 8)
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low-Voltage Operation:
– VCC = 1.7V to 3.6V
Internally Organized as 2,048 x 8 (16K)
Industrial Temperature Range: -40°C to +85°C
I2C-Compatible (Two-Wire) Serial Interface:
– 100 kHz Standard Mode, 1.7V to 3.6V
– 400 kHz Fast Mode, 1.7V to 3.6V
– 1 MHz Fast Mode Plus (FM+), 2.5V to 3.6V
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
Write-Protect Pin for Full Array Hardware Data Protection
Ultra Low Active Current (1 mA maximum) and Standby Current (0.8 μA maximum)
16-Byte Page Write Mode:
– Partial page writes allowed
Random and Sequential Read Modes
Self-Timed Write Cycle within 5 ms Maximum
ESD Protection > 4,000V
High Reliability:
– Endurance: 1,000,000 write cycles
– Data retention: 100 years
Green Package Options (Lead-free/Halide-free/RoHS compliant)
Die Sale Options: Wafer Form
Packages
•
8-Lead PDIP, 8-Lead SOIC, 5-Lead SOT23, 8-Lead TSSOP, 8-Pad UDFN and 8-Ball VFBGA
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 1
AT24C16D
Table of Contents
Features......................................................................................................................................................... 1
Packages........................................................................................................................................................1
1.
Package Types (not to scale)..................................................................................................................4
2.
Pin Descriptions...................................................................................................................................... 5
2.1.
2.2.
2.3.
2.4.
2.5.
3.
Description.............................................................................................................................................. 7
3.1.
3.2.
4.
Byte Write...................................................................................................................................17
Page Write..................................................................................................................................17
Acknowledge Polling.................................................................................................................. 18
Write Cycle Timing..................................................................................................................... 18
Write Protection..........................................................................................................................19
Read Operations................................................................................................................................... 20
8.1.
8.2.
8.3.
9.
Device Addressing..................................................................................................................... 16
Write Operations................................................................................................................................... 17
7.1.
7.2.
7.3.
7.4.
7.5.
8.
Clock and Data Transition Requirements...................................................................................13
Start and Stop Conditions.......................................................................................................... 13
Acknowledge and No-Acknowledge...........................................................................................14
Standby Mode............................................................................................................................ 14
Software Reset...........................................................................................................................14
Memory Organization............................................................................................................................16
6.1.
7.
Absolute Maximum Ratings..........................................................................................................9
DC and AC Operating Range.......................................................................................................9
DC Characteristics....................................................................................................................... 9
AC Characteristics......................................................................................................................10
Electrical Specifications..............................................................................................................11
Device Operation and Communication................................................................................................. 13
5.1.
5.2.
5.3.
5.4.
5.5.
6.
System Configuration Using Two-Wire Serial EEPROMs ........................................................... 7
Block Diagram.............................................................................................................................. 8
Electrical Characteristics.........................................................................................................................9
4.1.
4.2.
4.3.
4.4.
4.5.
5.
Ground......................................................................................................................................... 5
Serial Data (SDA).........................................................................................................................5
Serial Clock (SCL)........................................................................................................................5
Write-Protect (WP)....................................................................................................................... 5
Device Power Supply (VCC)......................................................................................................... 6
Current Address Read................................................................................................................20
Random Read............................................................................................................................ 20
Sequential Read.........................................................................................................................21
Device Default Condition from Microchip.............................................................................................. 22
10. Packaging Information.......................................................................................................................... 23
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 2
AT24C16D
10.1. Package Marking Information.....................................................................................................23
11. Revision History.................................................................................................................................... 36
The Microchip Website.................................................................................................................................37
Product Change Notification Service............................................................................................................37
Customer Support........................................................................................................................................ 37
Product Identification System.......................................................................................................................38
Microchip Devices Code Protection Feature................................................................................................ 38
Legal Notice................................................................................................................................................. 39
Trademarks.................................................................................................................................................. 39
Quality Management System....................................................................................................................... 40
Worldwide Sales and Service.......................................................................................................................41
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 3
AT24C16D
Package Types (not to scale)
1.
Package Types (not to scale)
8-lead PDIP/SOIC/TSSOP
(Top View)
5-lead SOT23
(Top View)
NC
1
8
Vcc
NC
2
7
WP
SCL
1
NC
3
6
SCL
GND
2
GND
4
5
SDA
SDA
3
5
WP
4
Vcc
8-ball VFBGA
(Top View)
8-pad UDFN
(Top View)
NC
1
8
Vcc
NC
2
7
WP
NC
1
8
Vcc
NC
2
7
WP
NC
3
6
SCL
NC
3
6
SCL
GND
4
5
SDA
GND
4
5
SDA
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 4
AT24C16D
Pin Descriptions
2.
Pin Descriptions
The descriptions of the pins are listed in Table 2-1.
Table 2-1. Pin Function Table
Name
NC
NC
NC
GND
SDA
SCL
WP(2)
VCC
8-Lead
PDIP
1
2
3
4
5
6
7
8
8-Lead
SOIC
1
2
3
4
5
6
7
8
8-Lead
TSSOP
1
2
3
4
5
6
7
8
5-Lead
SOT23
－
－
－
2
3
1
5
4
8-Pad
UDFN(1)
1
2
3
4
5
6
7
8
8-Ball
VFBGA
1
2
3
4
5
6
7
8
Function
No Connect
No Connect
No Connect
Ground
Serial Data
Serial Clock
Write-Protect
Device Power Supply
Notes:
1. The exposed pad on this package can be connected to GND or left floating.
2. If the WP pin is not driven, it is internally pulled down to GND. In order to operate in a wide variety of
application environments, the pull-down mechanism is intentionally designed to be somewhat strong. Once
this pin is biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull‑down mechanism disengages.
Microchip recommends connecting this pin to a known state whenever possible.
2.1
Ground
The ground reference for the power supply. GND should be connected to the system ground.
2.2
Serial Data (SDA)
The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. The
SDA pin must be pulled high using an external pull-up resistor (not to exceed 10 kΩ in value) and may be wire-ORed
with any number of other open-drain or open-collector pins from other devices on the same bus.
2.3
Serial Clock (SCL)
The SCL pin is used to provide a clock to the device and to control the flow of data to and from the device. Command
and input data present on the SDA pin is always latched in on the rising edge of SCL, while output data on the SDA
pin is clocked out on the falling edge of SCL. The SCL pin must either be forced high when the serial bus is idle or
pulled high using an external pull-up resistor.
2.4
Write-Protect (WP)
The write-protect input, when connected to GND, allows normal write operations. When the WP pin is connected
directly to VCC, all write operations to the protected memory are inhibited.
If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that
may appear in customer applications, Microchip recommends always connecting the WP pin to a known state. When
using a pull‑up resistor, Microchip recommends using 10 kΩ or less.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 5
AT24C16D
Pin Descriptions
Table 2-2. Write-Protect
2.5
WP Pin Status
Part of the Array Protected
At VCC
Full Array
At GND
Normal Write Operations
Device Power Supply (VCC)
The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at invalid VCC
voltages may produce spurious results and should not be attempted.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 6
AT24C16D
Description
3.
Description
The AT24C16D provides 16,384 bits of Serial Electrically Erasable and Programmable Read-Only Memory
(EEPROM) organized as 2,048 words of 8 bits each. This device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operations are essential. The device is available in spacesaving 8-lead SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP, 5-lead SOT23 and 8-ball VFBGA packages. All
packages operate from 1.7V to 3.6V.
3.1
System Configuration Using Two-Wire Serial EEPROMs
VCC
RPUP(max) =
tR(max)
0.8473 x CL
V - VOL(max)
RPUP(min) = CC
IOL
VCC
SCL
SDA
WP
I2C Bus Host:
Microcontroller
NC
VCC
NC
WP
Client
AT24CXXX
NC
SDA
GND
GND
© 2017-2021 Microchip Technology Inc.
Datasheet
SCL
DS20005858B-page 7
AT24C16D
Description
Block Diagram
Memory
System Control
Module
Power-on
Reset
Generator
VCC
High-Voltage
Generation Circuit
Row Decoder
3.2
EEPROM Array
1 page
Write
Protection
Control
Address Register
and Counter
Column Decoder
SCL
Data Register
DOUT
GND
© 2017-2021 Microchip Technology Inc.
WP
Data & ACK
Input/Output Control
DIN
Start
Stop
Detector
SDA
Datasheet
DS20005858B-page 8
AT24C16D
Electrical Characteristics
4.
Electrical Characteristics
4.1
Absolute Maximum Ratings
Temperature under bias
-55°C to +125°C
Storage temperature
-65°C to +150°C
VCC
-0.5V to +4.10V
Voltage on any pin with respect to ground
-0.6V to +4.10V
DC output current
5.0 mA
ESD protection
> 4 kV
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
4.2
DC and AC Operating Range
Table 4-1. DC and AC Operating Range
AT24C16D
4.3
Operating Temperature (Case)
Industrial Temperature Range
-40°C to +85°C
VCC Power Supply
Low-Voltage Grade
1.7V to 3.6V
DC Characteristics
Table 4-2. DC Characteristics
Parameter
Supply
Voltage
Symbol
Minimum
Typical(1)
Maximum
Units
VCC
1.7
—
3.6
V
—
0.08
0.3
mA
—
0.15
0.5
—
0.20
1.0
mA
VCC = 3.6V, Write at 1 MHz
—
0.08
0.4
μA
VCC = 1.8V(2), VIN = VCC or
GND
—
0.10
0.8
μA
VCC = 3.6V, VIN = VCC or GND
Supply
Current
ICC1
Supply
Current
ICC2
Test Conditions
VCC = 1.8V(2), Read at
400 kHz
VCC = 3.6V, Read at 1 MHz
Standby
Current
ISB
Input
Leakage
Current
ILI
—
0.10
3.0
μA
VIN = VCC or GND
Output
Leakage
Current
ILO
—
0.05
3.0
μA
VOUT = VCC or GND
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 9
AT24C16D
Electrical Characteristics
...........continued
Parameter
Symbol
Minimum
Typical(1)
Maximum
Units
Input Low
Level
VIL
-0.6
—
VCC x 0.3
V
Note 2
Input High
Level
VIH
VCC x 0.7
—
VCC + 0.5
V
Note 2
VOL1
—
—
0.2
V
VCC = 1.8V, IOL = 0.15 mA
VOL2
—
—
0.4
V
VCC = 3.0V, IOL = 2.1 mA
Output Low
Level
Output Low
Level
Test Conditions
Note:
1.
2.
4.4
Typical values characterized at TA = +25°C unless otherwise noted.
This parameter is characterized but is not 100% tested in production.
AC Characteristics
Table 4-3. AC Characteristics(1)
Parameter
Clock
Frequency, SCL
Clock Pulse
Width Low
Clock Pulse
Width High
Input Filter Spike
Suppression
(SCL, SDA)(2)
Clock Low to
Data Out Valid
Bus Free Time
between Stop
and Start(2)
Start Hold Time
Start Set-Up
Time
Data In Hold
Time
Data In Set-up
Time
Inputs Rise
Time(2)
Inputs Fall
Time(2)
Stop Set-Up
Time
Write-Protect
Setup Time
Fast Mode
VCC = 1.7V to 3.6V
Min.
Max.
fSCL
Standard Mode
VCC = 1.7V to 3.6V
Min.
Max.
—
100
—
400
—
1,000
kHz
tLOW
4,700
—
1,300
—
500
—
ns
tHIGH
4,000
—
600
—
400
—
ns
tI
—
100
—
100
—
100
ns
tAA
—
4,500
—
900
—
450
ns
tBUF
4,700
—
1,300
—
500
—
ns
tHD.STA
4,000
—
600
—
250
—
ns
tSU.STA
4,700
—
600
—
250
—
ns
tHD.DAT
0
—
0
—
0
—
ns
tSU.DAT
200
—
100
—
100
—
ns
tR
—
1,000
—
300
—
100
ns
tF
—
300
—
300
—
100
ns
tSU.STO
4,700
—
600
—
250
—
ns
tSU.WP
4,000
—
600
—
100
—
ns
Symbol
© 2017-2021 Microchip Technology Inc.
Datasheet
Fast Mode Plus
VCC = 2.5V to 3.6V
Min.
Max.
Units
DS20005858B-page 10
AT24C16D
Electrical Characteristics
...........continued
Parameter
Write-Protect
Hold Time
Data Out Hold
Time
Write Cycle
Time
Symbol
Standard Mode
VCC = 1.7V to 3.6V
Min.
Max.
Fast Mode
VCC = 1.7V to 3.6V
Min.
Max.
Fast Mode Plus
VCC = 2.5V to 3.6V
Min.
Max.
Units
tHD.WP
4,000
—
600
—
400
—
ns
tDH
100
—
50
—
50
—
ns
tWR
—
5
—
5
—
5
ms
Notes:
1. AC measurement conditions:
– CL: 100 pF
– RPUP (SDA bus line pull-up resistor to VCC): 1.3 kΩ (1000 kHz), 4 kΩ (400 kHz), 10 kΩ (100 kHz)
– Input and pulse voltages: 0.3 x VCC to 0.7 x VCC
– Input rise and fall times: ≤50 ns
– Input and output timing reference voltages: 0.5 x VCC
2. These parameters are determined through product characterization and are not 100% tested in production.
Figure 4-1. Bus Timing
tF
tHIGH
tR
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA In
tDH
tAA
tBUF
SDA Out
4.5
4.5.1
Electrical Specifications
Power-Up Requirements and Reset Behavior
During a power-up sequence, the VCC supplied to the AT24C16D should monotonically rise from GND to the
minimum VCC level (as specified in Table 4-1), with a slew rate no faster than 0.1 V/µs.
4.5.2
Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, the
AT24C16D includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commands
until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and into Standby
mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a
stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal to the
minimum VCC level, the bus host must wait at least tPUP before sending the first command to the device. See Table
4-4 for the values associated with these power-up parameters.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 11
AT24C16D
Electrical Characteristics
Table 4-4. Power-up Conditions(1)
Symbol
Parameter
Min.
Max.
Units
100
－
µs
tPUP
Time required after VCC is stable before the device can accept commands
VPOR
Power-on Reset Threshold Voltage
－
1.5
V
tPOFF
Minimum time at VCC = 0V between power cycles
1
－
ms
Note:
1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT24C16D drops below the maximum VPOR level
specified, it is recommended that a full power cycle sequence be performed. First, drive the VCC pin to GND, waiting
at least the minimum tPOFF time, and then perform a new power-up sequence in compliance with the requirements
defined in this section.
4.5.3
Pin Capacitance
Table 4-5. Pin Capacitance(1)
Symbol
Test Condition
Max.
Units
Conditions
CI/O
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN
Input Capacitance (SCL)
6
pF
VIN = 0V
Note:
1. This parameter is characterized but is not 100% tested in production.
4.5.4
EEPROM Cell Performance Characteristics
Table 4-6. EEPROM Cell Performance Characteristics
Operation
Test Condition
Write Endurance(1)
TA = 25°C, VCC (min.) < VCC < VCC (max.)
Byte or Page Write mode
Data Retention(1)
TA = 55°C
Min.
Max.
Units
1,000,000
—
Write Cycles
100
—
Years
Note:
1. Performance is determined through characterization and the qualification process.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 12
AT24C16D
Device Operation and Communication
5.
Device Operation and Communication
The AT24C16D operates as a client device and utilizes a simple I2C-compatible two-wire digital serial interface to
communicate with a host controller, commonly referred to as the bus host. The host initiates and controls all read and
write operations to the client devices on the serial bus, and both the host and the client devices can transmit and
receive data on the bus.
The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin is
used to receive the clock signal from the host, while the bidirectional SDA pin is used to receive command and data
information from the host as well as to send data back to the host. Data is always latched into the AT24C16D on
the rising edge of SCL and always output from the device on the falling edge of SCL. Both the SCL and SDA pins
incorporate integrated spike suppression filters and Schmitt Triggers to minimize the effects of input spikes and bus
noise.
All command and data information is transferred with the Most Significant bit (MSb) first. During bus communication,
one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have been transferred, the
receiving device must respond with either an Acknowledge (ACK) or a No-Acknowledge (NACK) response bit during
a ninth clock cycle (ACK/NACK clock cycle) generated by the host. Therefore, nine clock cycles are required for
every one byte of data transferred. There are no unused clock cycles during any read or write operation, so there
must not be any interruptions or breaks in the data stream during each data byte transfer and ACK or NACK clock
cycle.
During data transfers, data on the SDA pin must only change while SCL is low and the data must remain stable while
SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur.
Start and Stop conditions are used to initiate and end all serial bus communication between the host and the client
devices. The number of data bytes transferred between a Start and a Stop condition is not limited and is determined
by the host. In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic high state at the
same time.
5.1
Clock and Data Transition Requirements
The SDA pin is an open-drain terminal and therefore must be pulled high with an external pull‑up resistor. SCL is
an input pin that can either be driven high or pulled high using an external pull‑up resistor. Data on the SDA pin
may change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or Stop
condition as defined below. The relationship of the AC timing parameters with respect to SCL and SDA for the
AT24C16D are shown in the timing waveform in Figure 4-1. The AC timing characteristics and specifications are
outlined in AC Characteristics.
5.2
5.2.1
Start and Stop Conditions
Start Condition
A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a stable logic
‘1’ state and will bring the device out of Standby mode. The host uses a Start condition to initiate any data transfer
sequence; therefore, every command must begin with a Start condition. The device will continuously monitor the SDA
and SCL pins for a Start condition but will not respond unless one is detected. Refer to Figure 5-1 for more details.
5.2.2
Stop Condition
A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the logic
‘1’ state.
The host can use the Stop condition to end a data transfer sequence with the AT24C16D, which will subsequently
return to Standby mode. The host can also utilize a repeated Start condition instead of a Stop condition to end the
current data transfer if the host will perform another operation. Refer to Figure 5-1 for more details.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 13
AT24C16D
Device Operation and Communication
5.3
Acknowledge and No-Acknowledge
After every byte of data is received, the receiving device must confirm to the transmitting device that it has
successfully received the data byte by responding with what is known as an Acknowledge (ACK). An ACK is
accomplished by the transmitting device first releasing the SDA line at the falling edge of the eighth clock cycle
followed by the receiving device responding with a logic ‘0’ during the entire high period of the ninth clock cycle.
When the AT24C16D is transmitting data to the host, the host can indicate that it is done receiving data and wants
to end the operation by sending a logic ‘1’ response to the AT24C16D instead of an ACK response during the ninth
clock cycle. This is known as a No-Acknowledge (NACK) and is accomplished by the host sending a logic ‘1’ during
the ninth clock cycle, at which point the AT24C16D will release the SDA line so the host can then generate a Stop
condition.
The transmitting device, which can be the bus host or the Serial EEPROM, must release the SDA line at the
falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic ‘0’ to ACK the
previous 8-bit word. The receiving device must release the SDA line at the end of the ninth clock cycle to allow the
transmitter to continue sending new data. A timing diagram has been provided in Figure 5-1 to better illustrate these
requirements.
Figure 5-1. Start Condition, Data Transitions, Stop Condition and Acknowledge
SDA
Must Be
Stable
SDA
Must Be
Stable
1
2
SCL
Acknowledge Window
8
9
SDA
Start
Condition
5.4
Acknowledge
Valid
SDA
Change
Allowed
SDA
Change
Allowed
The transmitting device (Host or Client)
must release the SDA line at this point to allow
the receiving device (Host or Client) to drive the
SDA line low to ACK the previous 8-bit word.
Stop
Condition
The receiver (Host or Client)
must release the SDA line at
this point to allow the transmitter
to continue sending new data.
Standby Mode
The AT24C16D features a low-power Standby mode that is enabled when any one of the following occurs:
•
•
•
•
•
5.5
A valid power-up sequence is performed (see Power-Up Requirements and Reset Behavior).
A Stop condition is received by the device unless it initiates an internal write cycle (see Write Operations).
At the completion of an internal write cycle (see Write Operations).
An unsuccessful match of the device type identifier or hardware address in the device address byte occurs (see
Device Addressing).
The bus host does not ACK the receipt of data read out from the device; instead it sends a NACK response (see
Section Read Operations).
Software Reset
After an interruption in protocol, power loss or system Reset, any two‑wire device can be protocol reset by clocking
SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until SDA is released by the
EEPROM will vary. The software Reset sequence should not take more than nine dummy clock cycles. Once the
software Reset sequence is complete, new protocol can be sent to the device by sending a Start condition followed
by the protocol. Refer to Figure 5-2 for an illustration.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 14
AT24C16D
Device Operation and Communication
Figure 5-2. Software Reset
Dummy Clock Cycles
SCL
1
2
3
8
SDA Released
by EEPROM
9
Device is
Software Reset
SDA
In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to
reset the device (see Power-Up Requirements and Reset Behavior).
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 15
AT24C16D
Memory Organization
6.
Memory Organization
The AT24C16D is internally organized as 128 pages of 16 bytes each.
6.1
Device Addressing
Accessing the device requires an 8-bit device address byte following a Start condition to enable the device for a read
or write operation.
The Most Significant four bits of the device address byte is referred to as the device type identifier. The device type
identifier '1010' (Ah) is required in bits 7 through 4 of the device address byte (see Table 6-1).
Following the 4-bit device type identifier in the bit 3, bit 2 and bit 1 position of the device address byte are bits A10,
A9 and A8, which are the three Most Significant bits of the memory array word address.
The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is
high and a write operation is initiated if this bit is low.
Upon the successful comparison of the device address byte, the AT24C16D will return an ACK. If a valid comparison
is not made, the device will NACK.
Table 6-1. Device Address Byte
Most Significant Bits
of the Word Address
Device Type Identifier
Package
All Package Types
R/W Select
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
A10
A9
A8
R/W
For all operations except the current address read, a word address byte must be transmitted to the device
immediately following the device address byte. The word address byte consists of the remaining eight bits of the
11-bit memory array word address, and is used to specify which byte location in the EEPROM to start reading or
writing. Refer to Table 6-2 to review these bit positions.
Table 6-2. Word Address Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A7
A6
A5
A4
A3
A2
A1
A0
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 16
AT24C16D
Write Operations
7.
Write Operations
All write operations for the AT24C16D begin with the host sending a Start condition, followed by a device address
byte with the R/W bit set to logic ‘0’, and then by the word address byte. The data value(s) to be written to the device
immediately follow the word address byte.
7.1
Byte Write
The AT24C16D supports the writing of a single 8-bit byte. Selecting a data word in the AT24C16D requires an 11-bit
word address.
Upon receipt of the proper device address and the word address bytes, the EEPROM will send an Acknowledge. The
device will then be ready to receive the 8-bit data word. Following receipt of the 8‑bit data word, the EEPROM will
respond with an ACK. The addressing device, such as a bus host, must then terminate the write operation with a
Stop condition. At that time, the EEPROM will enter an internally self-timed write cycle, which will be completed within
tWR, while the data word is being programmed into the nonvolatile EEPROM. All inputs are disabled during this write
cycle and the EEPROM will not respond until the write is complete.
Figure 7-1. Byte Write
1
SCL
2
3
4
5
6
7
8
9
1
2
Device Address Byte
SDA
1
MSb
0
1
0
A10
A9
4
5
6
7
8
9
1
2
3
A8
0
0
A7
A6
A5
A4
A3
A2
4
5
6
7
8
9
D2
D1
D0
0
Data Word
Word Address Byte
Start
by
Host
7.2
3
A1
MSb
ACK
from
Client
A0
0
ACK
from
Client
D7
MSb
D6
D5
D4
D3
ACK
from
Client
Stop
by
Host
Page Write
A page write operation allows up to 16 bytes to be written in the same write cycle, provided all bytes are in the same
row of the memory array (where address bits A10 through A4 are the same). Partial page writes of less than 16 bytes
are also allowed.
A page write is initiated the same way as a byte write, but the bus host does not send a Stop condition after the first
data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the bus host can
transmit up to fifteen additional data words. The EEPROM will respond with an ACK after each data word is received.
Once all data to be written has been sent to the device, the bus host must issue a Stop condition (see Figure 7-2) at
which time the internally self-timed write cycle will begin.
The lower four bits of the word address are internally incremented following the receipt of each data word. The higher
order address bits are not incremented and retain the memory page row location. Page write operations are limited
to writing bytes within a single physical page, regardless of the number of bytes actually being written. When the
incremented word address reaches the page boundary, the address counter will rollover to the beginning of the same
page. Nevertheless, creating a rollover event should be avoided as previously loaded data in the page could become
unintentionally altered.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 17
AT24C16D
Write Operations
Figure 7-2. Page Write
1
SCL
2
3
4
5
6
7
8
9
1
2
3
Device Address Byte
SDA
1
MSb
0
1
0
A10
A9
4
5
6
7
8
9
A1
A0
0
Word Address Byte
A8
Start
by
Host
0
A7
0
A6
A5
A4
A3
A2
MSb
ACK
from
Client
1
2
ACK
from
Client
3
4
5
6
7
8
9
Data Word (n)
D7
D6
D5
D4
D3
1
2
3
4
5
7
8
9
Data Word (n+x), max of 16 without rollover
D2
D1
D0
0
MSb
D7
D6
D5
D4
D3
D2
D1
D0
0
MSb
ACK
from
Client
7.3
6
ACK
from
Client
Stop
by
Host
Acknowledge Polling
An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would prefer not to
wait the fixed maximum write cycle time (tWR). This method allows the application to know immediately when the
Serial EEPROM write cycle has completed, so a subsequent operation can be started.
Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated. This involves
repeatedly sending a Start condition followed by a valid device address byte with the R/W bit set at logic ‘0’. The
device will not respond with an ACK while the write cycle is ongoing. Once the internal write cycle has completed, the
EEPROM will respond with an ACK, allowing a new read or write operation to be immediately initiated. A flowchart
has been included below in Figure 7-3 to better illustrate this technique.
Figure 7-3. Acknowledge Polling Flowchart
Send any
Write
protocol.
Send
Stop
condition
to initiate the
Write cycle.
Send Start
condition followed
by a valid
Device Address
byte with R/W = 0.
Did
the device
ACK?
YES
Proceed to
next Read or
Write operation.
NO
7.4
Write Cycle Timing
The length of the self-timed write cycle (tWR) is defined as the amount of time from the Stop condition that begins the
internal write cycle to the Start condition of the first device address byte sent to the AT24C16D that it subsequently
responds to with an ACK. Figure 7-4 has been included to show this measurement. During the internally self-timed
write cycle, any attempts to read from or write to the memory array will not be processed.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 18
AT24C16D
Write Operations
Figure 7-4. Write Cycle Timing
SCL
8
9
9
ACK
ACK
Data Word n
SDA
D0
tWR
Stop
Condition
7.5
Start
Condition
First Acknowledge from the device
to a valid device address sequence after
write cycle is initiated. The minimum tWR
can only be determined through
the use of an ACK Polling routine.
Stop
Condition
Write Protection
The AT24C16D utilizes a hardware data protection scheme that allows the user to write‑protect the entire memory
contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pin is at GND or left
floating.
Table 7-1. AT24C16D Write-Protect Behavior
WP Pin Voltage
Part of the Array Protected
VCC
Full Array
GND
None － Write Protection Not Enabled
The status of the WP pin is sampled at the Stop condition for every byte write or page write operation prior to the
start of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition has been sent will not
alter or interrupt the execution of the write cycle. The WP pin state must be valid with respect to the associated setup
(tSU.WP) and hold (tHD.WP) timing as shown in Figure 7-5 below. The WP setup time is the amount of time that the
WP state must be stable before the Stop condition is issued. The WP hold time is the amount of time after the Stop
condition that the WP pin must remain stable.
If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the
device address, word address and data bytes. However, no write cycle will occur when the Stop condition is issued.
The device will immediately be ready to accept a new read or write command.
Figure 7-5. Write-Protect Setup and Hold Timing
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 19
AT24C16D
Read Operations
8.
Read Operations
Read operations are initiated the same way as write operations with the exception that the Read/Write Select bit in
the device address byte must be a logic ‘1’. There are three read operations:
•
•
•
8.1
Current Address Read
Random Address Read
Sequential Read
Current Address Read
The internal data word address counter maintains the last address accessed during the last read or write operation,
incremented by one. This address stays valid between operations as long as the VCC is maintained to the part. The
address rollover during a read is from the last byte of the last page to the first byte of the first page of the memory.
A current address read operation will output data according to the location of the internal data word address counter.
This is initiated with a Start condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The
device will ACK this sequence and the current address data word is serially clocked out on the SDA line. All types
of read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock
cycle. After the NACK response, the host may send a Stop condition to complete the protocol or it can send a Start
condition to begin the next sequence.
Figure 8-1. Current Address Read
1
SCL
2
3
4
5
6
7
8
9
1
2
Device Address Byte
SDA
1
MSb
0
Start
by
Host
8.2
1
0
A10
A9
3
4
5
6
7
8
9
D2
D1
D0
1
Data Word (n)
A8
1
0
D7
D6
MSb
ACK
from
Client
D5
D4
D3
NACK
from
Host
Stop
by
Host
Random Read
A random read begins in the same way as a byte write operation does to load in a new data word address. This is
known as a “dummy write” sequence; however, the data byte and the Stop condition of the byte write must be omitted
to prevent the part from entering an internal write cycle. Once the device address and word address are clocked in
and acknowledged by the EEPROM, the bus host must generate another Start condition. The bus host now initiates
a current address read by sending a Start condition, followed by a valid device address byte with the R/W bit set to
logic ‘1’. In this second device address byte, the bit position usually reserved for the Most Significant bit of the word
address (bit 1) is a "don’t care" bit since the address that will be read from is determined only by what was sent in
the dummy write portion of the sequence. The EEPROM will ACK the device address and serially clock out the data
word on the SDA line. All types of read operations will be terminated if the bus host does not respond with an ACK (it
NACKs) during the ninth clock cycle. After the NACK response, the host may send a Stop condition to complete the
protocol, or it can send a Start condition to begin the next sequence.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 20
AT24C16D
Read Operations
Figure 8-2. Random Read
1
SCL
2
3
4
5
6
7
8
9
1
2
3
Device Address Byte
SDA
1
0
MSb
1
A10
0
A9
4
5
6
7
8
9
A1
A0
0
Word Address Byte
A8
0
A7
0
Start
by
Host
A6
A5
A4
A3
A2
MSB
ACK
from
Client
ACK
from
Client
Dummy Write
1
2
3
4
5
6
7
8
9
1
2
3
0
1
0
X
X
X
1
D7
0
MSb
6
7
8
9
D6
D5
D4
D3
D2
D1
D0
1
MSb
Start
by
Host
8.3
5
Data Word (n)
Device Address Byte
1
4
ACK
from
Client
NACK
from
Host
Stop
by
Host
Sequential Read
Sequential reads are initiated by either a current address read or a random read. After the bus host receives a data
word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment the
word address and serially clock out sequential data words. When the maximum memory address is reached, the data
word address will rollover and the sequential read will continue from the beginning of the memory array. All types of
read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock
cycle. After the NACK response, the host may send a Stop condition to complete the protocol or it can send a Start
condition to begin the next sequence.
Figure 8-3. Sequential Read
1
SCL
2
3
4
5
6
7
8
9
1
2
3
Device Address Byte
SDA
1
0
MSb
1
A10
0
A9
A8
1
D7
0
6
7
8
9
D6
D5
D4
D3
D2
D1
D0
0
MSb
ACK
from
Client
2
3
4
5
6
7
8
9
1
2
Data Word (n+1)
D7
5
Data Word (n)
Start
by
Host
1
4
D6
D5
D4
D3
D2
ACK
from
Host
3
4
5
6
7
8
9
1
2
Data Word (n+2)
D1
D0
0
MSb
D7
D6
D5
D4
D3
D2
4
5
6
7
8
9
D1
D0
1
Data Word (n+x)
D1
D0
0
MSb
D7
D6
D5
D4
D3
D2
MSb
ACK
from
Host
© 2017-2021 Microchip Technology Inc.
3
ACK
from
Host
Datasheet
NACK
from
Host
Stop
by
Host
DS20005858B-page 21
AT24C16D
Device Default Condition from Microchip
9.
Device Default Condition from Microchip
The AT24C16D is delivered with the EEPROM array set to logic ‘1’, resulting in FFh data in all locations.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 22
AT24C16D
Packaging Information
10.
Packaging Information
10.1
Package Marking Information
AT24C16D: Package Marking Information
8-lead SOIC
8-lead TSSOP
8-pad UDFN
2.0 x 3.0 mm Body
8-lead PDIP
###
H%
NNN
ATHYWW
###%CO
ATMLHYWW
###% CO
YYWWNNN
YYWWNNN
5-lead SOT23
8-ball VFBGA
1.5 x 2.0 mm Body
##%UYY
WWNNN
ATMLUYWW
###% CO
YYWWNNN
Note 1:
###U
WNNN
designates pin 1
Note 2: Package drawings are not to scale
Note 3: For SOT23 package with date codes before 7B, the bottom line (YMXX) is marked on the bottom side and there is no Country of Assembly (@) mark on the top line.
Catalog Number Truncation
AT24C16D
Truncation Code ###: 16D / ##: AD
Date Codes
YY = Year
16: 2016
17: 2017
18: 2018
19: 2019
Voltages
20: 2020
21: 2021
22: 2022
23: 2023
Y = Year
6: 2016
7: 2017
8: 2018
9: 2019
0: 2020
1: 2021
2: 2022
3: 2023
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Origin
Device Grade
CO = Country of Origin
H or U: Industrial Grade
% = Minimum Voltage
M: 1.7V min
Atmel Truncation
AT: Atmel
ATM: Atmel
ATML: Atmel
Trace Code
NNN = Alphanumeric Trace Code (2 Characters for Small Packages)
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 23
AT24C16D
Packaging Information
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
C
A2
A
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 24
AT24C16D
Packaging Information
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(NOTE 5)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
Number of Pins
N
e
Pitch
Top to Seating Plane
A
Molded Package Thickness
A2
Base to Seating Plane
A1
Shoulder to Shoulder Width
E
Molded Package Width
E1
Overall Length
D
Tip to Seating Plane
L
c
Lead Thickness
b1
Upper Lead Width
b
Lower Lead Width
eB
Overall Row Spacing
§
MIN
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
INCHES
NOM
8
.100 BSC
.130
.310
.250
.365
.130
.010
.060
.018
-
MAX
.210
.195
.325
.280
.400
.150
.015
.070
.022
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
5. Lead design above seating plane may vary, based on assembly vendor.
Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 25
AT24C16D
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
2X
0.10 C A–B
2X
0.10 C A–B
NOTE 1
2
1
e
B
NOTE 5
NX b
0.25
C A–B D
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2
© 2020 Microchip Technology Inc.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 26
AT24C16D
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2
© 2020 Microchip Technology Inc.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 27
AT24C16D
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev F
© 2020 Microchip Technology Inc.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 28
AT24C16D
Packaging Information
8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
(DATUM B)
E1 E
1
0.20 C B A
2
8X b
0.10
e
C B A
TOP VIEW
A
0.05 C
C
SEATING
PLANE
A1
A2
A
8X
0.10 C
A
SIDE VIEW
H
c
L
(L1)
VIEW A-A
Microchip Technology Drawing C04-086 Rev C Sheet 1 of 2
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 29
AT24C16D
Packaging Information
8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Foot Length
L
Footprint
L1
c
Lead Thickness
Foot Angle
b
Lead Width
MIN
0.80
0.05
4.30
2.90
0.45
0.09
0°
0.19
MILLIMETERS
NOM
8
0.65 BSC
1.00
6.40 BSC
4.40
3.00
0.60
1.00 REF
4°
-
MAX
1.20
1.05
4.50
3.10
0.75
0.25
8°
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.20mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-086 Rev C Sheet 2 of 2
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 30
AT24C16D
Packaging Information
8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G1
8
SILK SCREEN
C
Y1
1
2
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Contact Pad to Center Pad (X6)
G1
MIN
MILLIMETERS
NOM
0.65 BSC
5.80
MAX
0.45
1.50
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2086 Rev B
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 31
AT24C16D
Packaging Information
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 32
AT24C16D
Packaging Information
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 33
AT24C16D
Packaging Information
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 34
AT24C16D
Packaging Information
d 0.10
(4X)
d 0.08 C
f 0.10 C
E
A
C
D
2. b
j n 0.15 m C A B
j n 0.08m C
PIN 1 BALL PAD CORNER
A1
B
A2
TOP VIEW
PIN 1 BALL PAD CORNER
3
2
1
A
SIDE VIEW
4
d
(d1)
8
7
6
5
COMMON DIMENSIONS
(Unit of Measure - mm)
e
(e1)
BOTTOM VIEW
8 SOLDER BALLS
Notes:
1. This drawing is for general information only.
SYMBOL
MIN
NOM
MAX
A
0.73
0.79
0.85
A1
0.09
0.14
0.19
A2
0.40
0.45
0.50
b
0.20
0.25
0.30
D
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
NOTE
2
1.50 BSC
E
2.0 BSC
e
0.50 BSC
e1
0.25 REF
d
1.00 BSC
d1
0.25 REF
7/1/14
TITLE
GPC
DRAWING NO.
8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch,
Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
GXU
8U3-1
REV.
G
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://
www.microchip.com/packaging.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 35
AT24C16D
Revision History
11.
Revision History
Revision B (March 2021)
Replaced terminology “Master” and “Slave” with “Host” and “Client”, respectively. Updated formatting to current
template. Updated the PDIP, SOIC, TSSOP, UDFN and SOT23 package drawings to Microchip format. Removed
WLCSP product offering.
Revision A (October 2017)
Updated to the Microchip template. Microchip DS20005858 replaces Atmel document 8906. Updated the "Software
Reset" section. Added ESD rating. Removed lead finish designation. Updated trace code format in package
markings.
Atmel Documentation 8906 Revision F (January 2017)
Updated Power-on Requirements and Reset Behavior section.
Atmel Documentation 8906 Revision E (December 2016)
Part marking SOT23: Moved backside mark (YMXX) to front side line 2. Added @ = Country of Assembly.
Atmel Document 8906 Revision D (November 2015)
Added, "Since the WLCSP has no WP pin, the write protection feature is not offered on the WLCSP." Updated the
8MA2 - UDFN and 4U-5 - WLCSP package drawings.
Atmel Document 8906 Revision C (May 2015)
Updated 8S1 - JEDEC SOIC and 4U-5 - WLCSP package drawings.
Atmel Document 8906 Revision B (January 2015)
Added 100 kHz timing set for reference, UDFN extended quantity option, and the figure for "System Configuration
Using 2-Wire Serial EEPROMs." Updated the 8X, 8MA2, and 4U-5 package outline drawings and the ordering
information section. Remove preliminary status.
Atmel Document 8906 Revision A (April 2014)
Initial release of this document.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 36
AT24C16D
The Microchip Website
Microchip provides online support via our website at www.microchip.com/. This website is used to make files and
information easily available to customers. Some of the content available includes:
•
•
•
Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online
discussion groups, Microchip design partner program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of
seminars and events, listings of Microchip sales offices, distributors and factory representatives
Product Change Notification Service
Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will
receive email notification whenever there are changes, updates, revisions or errata related to a specified product
family or development tool of interest.
To register, go to www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Embedded Solutions Engineer (ESE)
Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: www.microchip.com/support
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 37
AT24C16D
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
AT 24C1 6 D-S S HM-T
Shipping Carrier Option
T = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Extended Quantity Option
B = Bulk (Tubes)
Product Family
Operating Voltage
24C = Standard I2C-compatible
Serial EEPROM
M = 1.7V to 3.6V
Device Grade or
Wafer/Die Thickness
Device Density
16 = 16 Kilobit
H or U = Industrial Temperature Range
(-40°C to +85°C)
11
= 11mil Wafer Thickness
Device Revision
Package Option
SS = JEDEC SOIC
X
= TSSOP
MA = 2.0mm x 3.0mm UDFN
P
= PDIP
ST = SOT23
C
= VFBGA
WWU = Wafer Unsawn
Examples
Package
Package
Drawing
Code
Package
Option
Shipping Carrier Option
AT24C16D‑PUM
PDIP
P
P
Bulk (Tubes)
AT24C16D‑SSHM‑T
SOIC
SN
SS
Tape and Reel
AT24C16D‑STUM‑T
SOT23
NMB
ST
Tape and Reel
AT24C16D‑XHM‑B
TSSOP
ST
X
Bulk (Tubes)
AT24C16D‑MAHM‑T
UDFN
Q4B
MA
Tape and Reel
AT24C16D‑MAHM‑E
UDFN
Q4B
MA
Extended Qty. Tape and Reel
VFBGA
8U3‑1
C
Tape and Reel
Device
AT24C16D‑CUM‑T
Device Grade
Industrial
Temperature
(-40°C to 85°C)
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
•
•
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure when used in the intended manner and under normal
conditions.
There are dishonest and possibly illegal methods being used in attempts to breach the code protection features
of the Microchip devices. We believe that these methods require using the Microchip products in a manner
outside the operating specifications contained in Microchip’s Data Sheets. Attempts to breach these code
protection features, most likely, cannot be accomplished without violating Microchip’s intellectual property rights.
Microchip is willing to work with any customer who is concerned about the integrity of its code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code
protection does not mean that we are guaranteeing the product is “unbreakable.” Code protection is constantly
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 38
AT24C16D
evolving. We at Microchip are committed to continuously improving the code protection features of our products.
Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act.
If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue
for relief under that Act.
Legal Notice
Information contained in this publication is provided for the sole purpose of designing with and using Microchip
products. Information regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications.
THIS INFORMATION IS PROVIDED BY MICROCHIP “AS IS”. MICROCHIP MAKES NO REPRESENTATIONS
OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED
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IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR
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MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE
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The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,
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Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching,
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dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge,
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VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
© 2017-2021 Microchip Technology Inc.
Datasheet
DS20005858B-page 39
AT24C16D
All other trademarks mentioned herein are property of their respective companies.
©
2017-2021, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-7911
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart,
DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb,
TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered
trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Quality Management System
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
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DS20005858B-page 40
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