MCP3565R
Two-Channel, 153.6 ksps, Low Noise
24-Bit Delta-Sigma ADC with Internal Voltage Reference
Features
General Description
• One Differential or Two Single-Ended Input
Channels
• 24-Bit Resolution
• Programmable Data Rate: Up to 153.6 ksps
• Programmable Gain: 0.33x to 64x
• 106.7 dB SINAD, -116 dBc THD, 120 dBc SFDR
(Gain = 1x, 4800 SPS)
• Low-Temperature Drift:
- Offset error drift: 4/Gain nV/°C (AZ_MUX = 1)
- Gain error drift: 0.5 ppm/°C (Gain = 1x)
• Low Noise: 90 nVRMS (Gain = 16x,12.5 SPS)
• RMS Effective Resolution: Up to 23.3 Bits
• Wide Input Voltage Range: 0V to AVDD
• Selectable Internal 2.4V Voltage Reference with
15 ppm/°C Drift
• Differential Voltage Reference Inputs
• Internal Oscillator or External Clock Selection
• Ultra-Low Full Shutdown Current Consumption
(< 2.4 µA)
• Internal Temperature Sensor
• Burnout Current Sources for Sensor Open/Short
Detection
• 24-Bit Digital Offset and Gain Error Calibration
Registers
• Internal Conversions Sequencer (SCAN mode)
for Automatic Multiplexing
• Advanced Security Features:
- 16-bit CRC for secure SPI communications
- 16-bit CRC and IRQ for securing
configuration
- Register map lock with 8-bit secure key
- Monitor controls for system diagnostics
• 20 MHz SPI-Compatible Interface with Mode 0,0
and 1,1
• AVDD: 2.7V-3.6V
• DVDD: 1.8V-3.6V
• Extended Temperature Range: -40°C to +125°C
• Package: 2 mm x 2 mm x 0.55 mm 12-Lead UQFN
The MCP3565R is a one differential channel or two
single-ended channels, 24-bit Delta-Sigma Analogto-Digital Converter (ADC) with a programmable data
rate of up to 153.6 ksps. It offers integrated features,
such as internal voltage reference, internal oscillator,
temperature sensor and burnout sensor detection, in
order to reduce system component count and total
solution cost.
2020-2021 Microchip Technology Inc.
The MCP3565R ADC is fully configurable with Oversampling Ratio (OSR) from 32 to 98304 and gain from
1/3x to 64x. The device includes an internal sequencer
(SCAN mode) with multiple monitor channels and a
24-bit timer to be able to automatically create conversion loop sequences without needing MCU communications. Advanced security features, such as CRC and
register map lock, can ensure configuration locking and
integrity, as well as communication data integrity for
secure environments.
The device comes with a 20 MHz SPI-compatible serial
interface. Communication is largely simplified with 8-bit
commands, including various Continuous Read/Write
modes and 24/32-bit multiple data formats that can be
accessed by the Direct Memory Access (DMA) of an
8-bit, 16-bit or 32-bit MCU.
The MCP3565R device is available in an ultra-small,
2 mm x 2 mm x 0.55 mm 12-Lead UQFN package and
is specified over an extended temperature range from
-40°C to +125°C.
Applications
• Precision Sensor Transducers and Transmitters:
Pressure, Strain, Flow and Force Measurement
• Factory Automation and Process Controls
• Portable Instrumentation
• Temperature Measurements
DS20006401C-page 1
MCP3565R
Package Type
12-Lead UQFN* (2 mm x 2 mm x 0.55 mm)
12
11
DGND
DVDD
AVDD
A. MCP3565R: Single Channel Device
10
9 SDO
AGND 1
EP
13
REFIN- 2
8 SDI
7 SCK
5
6
CS
CH1
4
CH0
REFIN+ 3
*Includes Exposed Thermal Pad (EP); see Table 3-1.
Functional Block Diagram
REFIN+/OUT
AVDD
Voltage +
2.4V
Reference -
REFIN-
DVDD
AMCLK
VREF_SEL
DMCLK/DRCLK
Clock
Generation
(RC
Oscillator)
VREF- VREF+
DMCLK
VIN+
VIN-
AGND AVDD
DS20006401C-page 2
+
x
SINC3 Filter
with Digital
Gain
POR
AVDD
Monitoring
AGND
ANALOG
SINC1
Filter
Offset/Gain
Calibration
OSR[3:0]
PRE[1:0]
SDO
Digital SPI
Interface
and Control
SDI
SCK
CS
'6A/D Converter
Burnout
Current
Sources
TEMP
Diodes
nd
'62 Order
Modulator
with Analog
Gain
Analog
Differential
Multiplexer
CH0
CH1
+
POR
DVDD
Monitoring
DIGITAL
DGND
2020-2021 Microchip Technology Inc.
MCP3565R
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
DVDD, AVDD ......................................................................................................................................................-0.3 to 4.0V
Digital Inputs and Outputs w.r.t. DGND ............................................................................................ -0.3V to DVDD + 0.3V
Analog Inputs w.r.t. AGND ............................................................................................................. ....-0.3V to AVDD + 0.3V
Current at Input Pins ............................................................................................................................................... ±5 mA
Current at Output and Supply Pins ...................................................................................................................... ±20 mA
Storage Temperature ..............................................................................................................................-65°C to +150°C
Ambient Temperature with Power Applied ..............................................................................................-65°C to +125°C
Soldering Temperature of Leads (10 seconds) ..................................................................................................... +300°C
Maximum Junction Temperature (TJ) ........................................................................................... .........................+150°C
ESD on All Pins (HBM) 6.0 kV
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions, above
those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2020-2021 Microchip Technology Inc.
DS20006401C-page 3
MCP3565R
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V,
MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions,
TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz.
Parameters
Sym.
Min.
Typ.
Max.
Units
Analog Operating Voltage
AVDD
2.7
—
3.6
V
Digital Operating Voltage
DVDD
1.8
—
AVDD + 0.1
V
Analog Operating Current
AIDD
—
0.56
0.81
mA
—
0.69
0.96
mA
—
0.93
1.3
mA
Conditions
Supply Requirements
Analog Operating Current
AIDD
DVDD ≤ 3.6V
BOOST[1:0] = 00, 0.5x
BOOST[1:0] = 01, 0.66x
BOOST[1:0] = 10, 1x
—
1.65
2.2
mA
—
—
0.96
mA
BOOST[1:0] = 11, 2x
—
—
1.2
mA
BOOST[1:0] = 01, 0.66x,
VREF = 2.4V internal
—
—
1.6
mA
BOOST[1:0] = 10, 1x,
VREF = 2.4V internal
—
—
2.5
mA
BOOST[1:0] = 11, 2x,
VREF = 2.4V internal
BOOST[1:0] = 00, 0.5x,
VREF = 2.4V internal
Digital Operating Current
DIDD
—
0.25
0.37
mA
(Note 8)
Analog Partial Shutdown
Current
AIDDS_PS
—
—
22
µA
CONFIG0 = 0x00
Digital Partial Shutdown
Current
DIDDS_PS
—
—
17
µA
CONFIG0 = 0x00
Analog Full Shutdown
Current
AIDDS_FS
—
—
0.4
µA
CONFIG0 = 0x00 with Full
Shutdown Fast-CMD
Digital Full Shutdown
Current
DIDDS_FS
—
—
2
µA
CONFIG0 = 0x00 with Full
Shutdown Fast-CMD
Power-on Reset (POR)
Threshold Voltage
VPOR_A
—
1.75
—
V
For analog circuits
VPOR_D
—
1.2
—
V
For digital circuits
POR Hysteresis
VPOR_HYS
—
150
—
mV
POR Reset Time
tPOR
—
1
—
µs
Note 1:
2:
3:
4:
5:
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
REFIN- must be connected to ground for single-ended measurements.
Full-Scale Range (FSR) = 2 x VREF/GAIN.
This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured
between the two input pins of the channel selected with the input multiplexer.
6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Sections 2.0 “Typical
Performance Curves”.
7: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
8: DIDD is measured while no transfer is present on the SPI bus.
9: An external buffer is recommended for external use.
10:Start-up time is the reaction time to the SPI command.
11:Settling time depends on bypass caps on the REFIN+/OUT pin.
DS20006401C-page 4
2020-2021 Microchip Technology Inc.
MCP3565R
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V,
MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions,
TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Input Voltage at Input Pin
CHN
AGND – 0.1
—
AVDD + 0.1
V
Differential Input Range
VIN
-VREF/GAIN
—
+VREF/GAIN
V
Differential Input
Impedance (Note 5)
ZIN
—
510
—
k
GAIN = 0.33x, proportional to
1/AMCLK
—
260
—
k
GAIN = 1x, proportional to
1/AMCLK
—
150
—
k
GAIN = 2x, proportional to
1/AMCLK
—
80
—
k
GAIN = 4x, proportional to
1/AMCLK
—
40
—
k
GAIN = 8x, proportional to
1/AMCLK
—
20
—
k
GAIN ≥ 16x, proportional to
1/AMCLK
ILI_A
—
±10
—
nA
IVREF
-2%
2.4
+2%
V
Internal VREF
Temperature Coefficient
TCREFE
—
15
40
ppm/°C
TA = -40°C to +125°C,
Extended Temperature Range
(Note 2)
Internal VREF
Temperature Coefficient
TCREFI
—
9
40
ppm/°C
TA = -40°C to +85°C,
Industrial Temperature Range
(Note 2)
Voltage Reference Buffer
Short-Circuit Current
IREF_SC
—
—
8
mA
tVREF_SET
—
12
—
ms
REFIN+/OUT shorted to AGND,
VREF_SEL = 1 (Note 9)
VREF_Noise
—
14.3
—
µV
Analog Inputs
Analog Input Leakage
Current During ADC
Shutdown
Analog inputs are measured
with respect to AGND
Internal Voltage Reference
Internal VREF Absolute
Voltage
Internal Reference
Settling Time
Internal VREF Output
Noise
VREF_SEL = 1,
TA = +25°C only
Settling to 10 ppm from final
value, bypass capacitor 1 µF
(Notes 2, 11)
VREF_SEL = 1, AZ_VREF = 1
(chopper on), TA = +25°C only
(Note 2)
Note 1:
2:
3:
4:
5:
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
REFIN- must be connected to ground for single-ended measurements.
Full-Scale Range (FSR) = 2 x VREF/GAIN.
This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured
between the two input pins of the channel selected with the input multiplexer.
6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Sections 2.0 “Typical
Performance Curves”.
7: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
8: DIDD is measured while no transfer is present on the SPI bus.
9: An external buffer is recommended for external use.
10:Start-up time is the reaction time to the SPI command.
11:Settling time depends on bypass caps on the REFIN+/OUT pin.
2020-2021 Microchip Technology Inc.
DS20006401C-page 5
MCP3565R
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V,
MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions,
TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
External Voltage Reference Input
Reference Voltage Range
(VREF+ – VREF-)
VREF
0.6
—
AVDD
V
External Noninverting
Input Voltage Reference
VREF+
VREF- + 0.6
—
AVDD
V
External Inverting Input
Voltage Reference
VREF-
AGND
—
VREF+ – 0.6
V
Resolution
24
—
—
Bits
OSR ≥ 256 (Note 1)
VOS
-900/GAIN
—
900/GAIN
µV
-(0.05 + 0.8/
GAIN)
—
0.05 + 0.8/
GAIN
AZ_MUX = 0 (Note 6)
—
70/GAIN
300/GAIN
VREF_SEL = 0
DC Performance
No Missing Code
Resolution
Offset Error
Offset Error Temperature
Coefficient
Gain Error
Gain Error Temperature
Coefficient
Integral Nonlinearity
(Note 7)
VOS_DRIFT
AZ_MUX = 1 (Notes 2, 6)
nV/°C
—
4/GAIN
16/GAIN
GE
-3
—
+3
%
GE_DRIFT
—
0.5
2
ppm/°C
1
4
INL
AZ_MUX = 0 (Notes 2, 6)
AZ_MUX = 1 (Notes 2, 6)
(Note 6)
GAIN: 1x, 2x, 4x (Note 2)
GAIN: 8x (Note 2)
GAIN: 0.33x, 16x (Note 2)
2
8
-10
—
+10
-7
—
+7
GAIN = 1x (Note 2)
-7
—
+7
GAIN = 2x (Note 2)
-10
—
+10
GAIN = 4x (Note 2)
-20
—
+20
GAIN = 8x (Note 2)
-32
—
+32
ppm FSR GAIN = 0.33x (Note 2)
GAIN = 16x (Note 2)
AVDD Power Supply
Rejection Ratio
DC PSRR
—
-76 – 20 x
LOG (GAIN)
—
dB
AVDD varies from 2.7V to 3.6V,
VIN = 0V
DVDD Power Supply
Rejection Ratio
DC PSRR
—
-110
—
dB
DVDD varies from 1.8V to 3.6V,
VIN = 0V
DC Common-Mode
Rejection Ratio
DC CMRR
—
-126
—
dB
VINCOM varies from 0V to AVDD,
VIN = 0V
Note 1:
2:
3:
4:
5:
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
REFIN- must be connected to ground for single-ended measurements.
Full-Scale Range (FSR) = 2 x VREF/GAIN.
This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured
between the two input pins of the channel selected with the input multiplexer.
6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Sections 2.0 “Typical
Performance Curves”.
7: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
8: DIDD is measured while no transfer is present on the SPI bus.
9: An external buffer is recommended for external use.
10:Start-up time is the reaction time to the SPI command.
11:Settling time depends on bypass caps on the REFIN+/OUT pin.
DS20006401C-page 6
2020-2021 Microchip Technology Inc.
MCP3565R
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V,
MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions,
TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
SINAD
105.8
106.7
—
dB
AVDD = DVDD = VREF = 3.3V
and TA = +25°C (Note 2)
98.1
99.4
—
dB
AVDD = DVDD = 3.3V,
VREF = 2.4V internal, bypass
capacitor 0.1 µF and
TA = +25°C (Note 2)
106.7
107.2
—
dBc
AVDD = DVDD = VREF = 3.3V
and TA = +25°C (Note 2)
98.5
99.8
—
dBc
AVDD = DVDD = 3.3V,
VREF = 2.4V internal, bypass
capacitor 0.1 µF and
TA = +25°C (Note 2)
—
-116
-111
dB
AVDD = DVDD = VREF = 3.3V
and TA = +25°C, includes the
first 10 harmonics (Note 2)
—
-110
-105
dB
AVDD = DVDD = 3.3V,
VREF = 2.4V internal, bypass
capacitor 0.1 µF and
TA = +25°C, includes the first 10
harmonics (Note 2)
110
120
—
dBc
AVDD = DVDD = VREF = 3.3V
and TA = +25°C (Note 2)
108
113
—
dBc
AVDD = DVDD = 3.3V,
VREF = 2.4V internal, bypass
capacitor 0.1 µF and
TA = +25°C (Note 2)
CTALK
—
-130
—
dB
VIN = 0V, Perturbation = 0 dB at
50 Hz, applies to all
perturbation channels and all
input channels
AC Power Supply
Rejection Ratio
AC PSRR
—
-75 – 20 x
LOG (GAIN)
—
dB
VIN = 0V, DVDD = 3.3V,
AVDD = 3.3V + 0.3 VP, 50 Hz
AC Common-Mode
Rejection Ratio
AC CMRR
—
-122
—
dB
VINCOM = 0 dB at 50 Hz,
VIN = 0V
AC Performance
Signal-to-Noise and
Distortion Ratio
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic
Range
Input Channel Crosstalk
SNR
THD
SFDR
Note 1:
2:
3:
4:
5:
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
REFIN- must be connected to ground for single-ended measurements.
Full-Scale Range (FSR) = 2 x VREF/GAIN.
This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured
between the two input pins of the channel selected with the input multiplexer.
6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Sections 2.0 “Typical
Performance Curves”.
7: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
8: DIDD is measured while no transfer is present on the SPI bus.
9: An external buffer is recommended for external use.
10:Start-up time is the reaction time to the SPI command.
11:Settling time depends on bypass caps on the REFIN+/OUT pin.
2020-2021 Microchip Technology Inc.
DS20006401C-page 7
MCP3565R
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V,
MCLK = 4.9152 MHz, VREF = AVDD, ADC_MODE[1:0] = 11. All other register map bits to their default conditions,
TA = -40°C to +125°C, VIN = -0.5 dBFS at 50 Hz.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
ADC Timing Parameters
Sampling Frequency
DMCLK
See Table 5-6
MHz
See Figure 4-1
Output Data Rate
DRCLK
See Table 5-6
ksps
See Figure 4-1
Data Conversion Time
ADC Start-up Delay
SCAN Mode Time Delays
TCONV
TADC_SETUP
See Table 5-6
See Figure 4-1
256
—
DMCLK
periods
ADC_MODE[1:0] bits change
from ‘0x’ to ‘1x’
—
0
—
DMCLK
periods
ADC_MODE[1:0] bits change
from ‘10’ to ‘11’
TDLY_SCAN
0
—
512
DMCLK
periods
Time delay between sampling
channels
TTIMER_SCAN
0
—
16777215
DMCLK
periods
Time interval between SCAN
cycles
tDODR
—
—
50
ns
tDOMDAT
—
—
100
ns
Data Transfer Time to DR
(Data Ready Event)
Modulator Output Valid
from AMCLK High
200
External Master Clock Input (CLK_SEL[1] = 0) (MCLK = SCK)
Master Clock Input
Frequency Range
ms
—
fMCLK_EXT
2.7V ≤ DVDD ≤ 3.6V
1.8V ≤ DVDD ≤ 2.7V
1
—
20
MHz
DVDD ≥ 2.7V
1
—
10
MHz
DVDD < 2.7V
fMCLK_DUTY
45
—
55
%
fMCLK_INT
3.3
—
6.6
MHz
Internal Oscillator Start-up
Time
tOSC_STARTUP
—
10
—
µs
CLK_SEL[1] changes from ‘0’
to ‘1’, time to stabilize the clock
frequency to ±1 kHz of the final
value (Note 10)
Internal Oscillator Current
Consumption
IDDOSC
—
30
—
µA
Should be added to DIDD when
CLK_SEL[1:0] = 1x
TAcc
—
±5
—
°C
See Section 5.1.2 “Internal
Temperature Sensor”
Master Clock Input Duty
Cycle
Internal Clock Oscillator
Internal Master Clock
Frequency
Internal Temperature Sensor
Temperature
Measurement Accuracy
CLK_SEL[1] = 1
Note 1:
2:
3:
4:
5:
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
REFIN- must be connected to ground for single-ended measurements.
Full-Scale Range (FSR) = 2 x VREF/GAIN.
This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured
between the two input pins of the channel selected with the input multiplexer.
6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Sections 2.0 “Typical
Performance Curves”.
7: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
8: DIDD is measured while no transfer is present on the SPI bus.
9: An external buffer is recommended for external use.
10:Start-up time is the reaction time to the SPI command.
11:Settling time depends on bypass caps on the REFIN+/OUT pin.
DS20006401C-page 8
2020-2021 Microchip Technology Inc.
MCP3565R
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C,
AVDD = 2.7V to 3.6V, DVDD = 1.8V to AVDD + 0.1V, DGND = AGND = 0V.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
JA
—
93.7
—
°C/W
Thermal Package Resistance
Thermal Resistance, 12-Lead UQFN
Note 1:
The internal Junction Temperature (TJ) must not exceed the absolute maximum specification of +150°C.
TABLE 1-1:
SPI SERIAL INTERFACE TIMING SPECIFICATIONS FOR DVDD = 2.7V TO 3.6V
Electrical Specifications: DVDD = 2.7V to 3.6V, TA = -40°C to +125°C, CLOAD = 30 pF. See Figure 1-1.
Parameters
Sym.
Min.
Typ.
Max.
Units
Serial Clock Frequency
fSCK
—
—
20
MHz
CS Setup Time
tCSS
25
—
—
ns
CS Hold Time
tCSH
50
—
—
ns
CS Disable Time
tCSD
50
—
—
ns
Data Setup Time
tSU
5
—
—
ns
Data Hold Time
tHD
10
—
—
ns
Serial Clock High Time
tHI
20
—
—
ns
Serial Clock Low Time
tLO
20
—
—
ns
Serial Clock Delay Time
tCLD
50
—
—
ns
Serial Clock Enable Time
tCLE
50
—
—
ns
Conditions
Output Valid from SCK Low
tDO
—
—
25
ns
Output Hold Time
tHO
0
—
—
ns
Output Disable Time
tDIS
—
—
25
ns
Measured with a 1.5 mA
pull-up current source on the
SDO pin
tCSSDO
—
—
25
ns
SDO toggles to logic low at
each communication start (CS
falling edge)
Output Valid from CS Low
2020-2021 Microchip Technology Inc.
DS20006401C-page 9
MCP3565R
TABLE 1-2:
SPI SERIAL INTERFACE TIMING SPECIFICATIONS FOR DVDD = 1.8V TO 2.7V
(10 MHz MAXIMUM SCK FREQUENCY)
Electrical Specifications: DVDD = 1.8V to 2.7V, TA = -40°C to +125°C, CLOAD = 30 pF. See Figure 1-1.
Parameters
Serial Clock Frequency
Sym.
Min.
Typ.
Max.
Units
fSCK
—
—
10
MHz
CS Setup Time
tCSS
50
—
—
ns
CS Hold Time
tCSH
100
—
—
ns
CS Disable Time
tCSD
100
—
—
ns
Data Setup Time
tSU
10
—
—
ns
Data Hold Time
tHD
20
—
—
ns
Serial Clock High Time
tHI
40
—
—
ns
Serial Clock Low Time
tLO
40
—
—
ns
Conditions
Serial Clock Delay Time
tCLD
100
—
—
ns
Serial Clock Enable Time
tCLE
100
—
—
ns
Output Valid from SCK Low
tDO
—
—
50
ns
Output Hold Time
tHO
0
—
—
ns
Output Disable Time
tDIS
—
—
50
ns
Measured with a 1.5 mA
pull-up current source on the
SDO pin
tCSSDO
—
—
50
ns
SDO toggles to logic low at
each communication start (CS
falling edge)
Output Valid from CS Low
TABLE 1-3:
DIGITAL I/O DC SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 1.8V to 3.6V,
TA = -40°C to +125°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Schmitt Trigger High-Level
Input Voltage
VIH
0.7 x DVDD
—
—
V
Schmitt Trigger Low-Level
Input Voltage
VIL
—
—
0.3 x DVDD
V
Hysteresis of Schmitt Trigger
Inputs
VHYS
—
200
—
mV
Low-Level Output Voltage
VOL
—
—
0.2 x DVDD
V
High-Level Output Voltage
VOH
0.8 x DVDD
—
—
V
IOH = -1.5 mA
Input Leakage Current
ILI_D
—
—
1
µA
Pins configured as inputs
or high-impedance outputs
DS20006401C-page 10
Conditions
IOL = +1.5 mA
2020-2021 Microchip Technology Inc.
MCP3565R
tCS D
CS
tSCK
tCLE
tH I
tCS S
tL O
tC SH
tCLD
SPI mode 1,1
SPI mode 1,1
SCK
SPI mode 0,0
SPI mode 0,0
Device Latches SDI
on SCK Rising Edge
tSU
SDI
SDO
tH D
tDO
tHO
tC SSDO
High-Z
tDIS
High-Z
0 (for first two bits on SDO)
FIGURE 1-1:
Device Latches SDO
on SCK Falling Edge
High-Z
0
Serial Output Timing Diagram.
2020-2021 Microchip Technology Inc.
DS20006401C-page 11
MCP3565R
NOTES:
DS20006401C-page 12
2020-2021 Microchip Technology Inc.
MCP3565R
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) therefore outside the warranted range.
Note:
Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;
VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.
Histogram ticks are centered at their bin center.
VIN = -0.5 dBFS at 50 Hz
FFT 16384 samples
-40
-60
-80
-100
-120
-140
-160
0
Output Amplitude (dBFS)
Output Amplitude (dBFS)
0
-20
-180
-40
-60
-80
-100
-120
-140
-160
-180
0
500
1000
1500
Frequency (Hz)
2000
0
2500
FIGURE 2-1:
FFT Output Spectrum,
fin = 50 Hz (External VREF).
500
2000
2500
FIGURE 2-4:
FFT Output Spectrum,
fin = 1 kHz (Internal VREF).
VIN = -0.5 dBFS at 1 kHz
FFT 16384 samples
-20
Occurrence (Counts)
-40
-60
-80
-100
-120
-140
-160
VIN = 0V
Noise = 8.9 PVRMS
CONV_MODE[1:0] = 11
64000 Samples
Bin Size = 4 LSB
5000
4000
3000
2000
1000
-1100
-1084
-1068
-1052
-1036
-1020
-1004
-988
-972
-956
-940
-924
-908
-892
-876
-860
-844
0
-180
0
500
1000
1500
2000
2500
ADC Output Code (LSB)
Frequency (Hz)
FIGURE 2-2:
FFT Output Spectrum,
fin = 1 kHz (External VREF).
FIGURE 2-5:
(External VREF).
0
4000
VIN = -0.5 dBFS @ 50Hz
FFT 16384 samples
-20
-40
-60
-80
-100
-120
-140
-160
Output Noise Histogram
VIN = 0V
Noise = 9.4 ȝVRMS
64000 samples
Bin size = 4 LSB
3500
Occurrence (Counts)
3000
2500
2000
1500
1000
500
0
-180
0
500
1000
1500
Frequency (Hz)
2000
FIGURE 2-3:
FFT Output Spectrum,
fin = 50 Hz (Internal VREF).
2020-2021 Microchip Technology Inc.
2500
-1244
-1228
-1212
-1196
-1180
-1164
-1148
-1132
-1116
-1100
-1084
-1068
-1052
-1036
-1020
-1004
-988
Output Amplitude (dBFS)
1000
1500
Frequency (Hz)
6000
0
Output Amplitude (dBFS)
VIN = -0.5 dBFS @ 1kHz
FFT 16384 samples
-20
ADC Output Code (LSB)
FIGURE 2-6:
(Internal VREF).
Output Noise Histogram
DS20006401C-page 13
MCP3565R
Note:
Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;
VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.
Histogram ticks are centered at their bin center.
AVDD = VREF = 2.7V, -40°C
AVDD = VREF = 2.7V, +125°C
AVDD = VREF = 3.6V, -40°C
AVDD = VREF = 3.6V, +125°C
120
100
FIGURE 2-7:
FIGURE 2-10:
VREF.
Signal-to-Noise Ratio (dB)
Gain = 1x
3
2.5
2
1.5
1
131072
65536
32768
8192
80
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
60
40
20
FIGURE 2-11:
VREF.
Output Noise vs. Input
131072
65536
32768
16384
8192
512
256
Oversampling Ratio (OSR)
Differential Input Voltage (% of VREF)
FIGURE 2-8:
Voltage.
128
100
4096
50
2048
0
1024
-50
64
32
0
-100
SNR vs. OSR External
0
FIGURE 2-9:
DS20006401C-page 14
2
Analog Gain
4
8
Maximum INL vs. Gain.
16
Oversampling Ratio (OSR)
FIGURE 2-12:
131072
1
65536
0.5
-140
32768
2
-120
16384
4
-100
8192
6
-80
4096
8
-60
2048
10
-40
1024
AVDD = VREF = 3.6V, +125°C
512
AVDD = VREF = 3.6V, -40°C
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
-20
256
AVDD = VREF = 2.7V, +125°C
128
Total Harmonic Distortion (dBc)
AVDD = VREF = 2.7V, -40°C
64
20
Maximum INL (ppm of 2*VREF)
100
0
0.5
0
0.25
120
32
RMS Noise (ppm of 2*VREF)
3.5
12
SINAD vs. OSR External
140
AVDD = VREF = 2.7V, -40°C
AVDD = VREF = 2.7V, +125°C
AVDD = VREF = 3.6V, -40°C
AVDD = VREF = 3.6V, +125°C
4
14
16384
Oversampling Ratio (OSR)
5
16
4096
100
INL vs. Input Voltage.
4.5
18
0
2048
-50
0
50
Differential Input Voltage (% of VREF)
20
512
-6
-100
40
1024
-4
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
60
256
-2
80
128
0
64
Gain = 1x
32
4
2
140
Signal-to-Noise and Distortion
Ratio (dB)
Integral Non-Linearity (ppm of
2*VREF)
6
THD vs. OSR External VREF.
2020-2021 Microchip Technology Inc.
MCP3565R
Note:
Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;
VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.
Histogram ticks are centered at their bin center.
FIGURE 2-13:
VREF.
65536
32768
8192
16384
4096
2048
512
Oversampling Ratio (OSR)
THD vs. OSR Internal VREF.
140
120
100
100
35
100
30
SNR vs. OSR Internal VREF.
2020-2021 Microchip Technology Inc.
131072
65536
32768
8192
16384
4096
2048
1024
512
256
20
15
10
5
107.9
107.8
107.7
107.6
107.5
107.4
107.3
0
107.2
131072
Oversampling Ratio (OSR)
FIGURE 2-15:
16384
8192
4096
2048
1024
512
256
128
64
0
65536
20
32768
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
25
107.1
80
SFDR vs. OSR Internal
33 Devices x 3 Lots
Bin Size: 0.1 dB
106.5
Occurrence (Counts)
120
40
128
Oversampling Ratio (OSR)
FIGURE 2-17:
VREF.
SINAD vs. OSR Internal
60
0
107.0
FIGURE 2-14:
VREF.
20
106.9
Oversampling Ratio (OSR)
131072
65536
32768
16384
8192
4096
2048
1024
512
256
128
64
32
0
40
106.8
20
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
60
106.7
40
80
64
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
106.6
60
32
80
32
1024
-140
Spurious-Free Dynamic Range
(dBc)
Signal-to-Noise and Distortion
Ratio (dB)
-120
FIGURE 2-16:
SFDR vs. OSR External
120
Signal-to-Noise Ratio (dB)
-100
131072
Oversampling Ratio (OSR)
-80
256
16384
8192
4096
2048
1024
512
256
64
128
0
-60
128
20
131072
40
65536
60
32768
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
-40
64
80
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
-20
32
100
32
Spurious-Free Dynamic Range (dBc)
120
Total Harmonic Distortion (dBc)
0
140
Signal-to-Noise Ratio (dB)
FIGURE 2-18:
External VREF.
SNR Distribution Histogram
DS20006401C-page 15
MCP3565R
Note:
Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;
VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.
Histogram ticks are centered at their bin center.
33Devices x 3 Lots
Bin Size: 0.1 dB
20
15
10
5
0
20
18
16
14
12
10
8
6
4
2
0
33 Devices x 3 Lots
Bin Size: 0.1 dB
98.8
98.9
99.0
99.1
99.2
99.3
99.4
99.5
99.6
99.7
99.8
99.9
100.0
100.1
100.2
100.3
100.4
100.5
105.8
105.9
106.0
106.1
106.2
106.3
106.4
106.5
106.6
106.7
106.8
106.9
107.0
107.1
107.2
107.3
107.4
107.5
107.6
Occurrence (Counts)
25
Occurrence (Counts)
30
Signal-to-Noise Ratio (dB)
Signal-to-Noise-and-Distortion Ratio (dB)
FIGURE 2-19:
SINAD Distribution
Histogram External VREF.
FIGURE 2-22:
Internal VREF.
30
20
15
10
5
0
25
20
15
10
5
98.2
98.3
98.4
98.5
98.6
98.7
98.8
98.9
99.0
99.1
99.2
99.3
99.4
99.5
99.6
99.7
99.8
99.9
100.0
100.1
100.2
Signal-to-Noise-and-Distortion Ratio (dB)
Total Harmonic Distortion (dBc)
FIGURE 2-20:
External VREF.
THD Distribution Histogram
FIGURE 2-23:
SINAD Distribution
Histogram Internal VREF.
30
33 Devices x 3 Lots
Bin Size: 1.0 dB
30
25
20
15
10
5
Occurrence (Counts)
35
33 Devices x 3 Lots
Bin Size: 0.5 dB
25
20
15
10
5
Spurious-Free Dynamic Range (dBc)
FIGURE 2-21:
SFDR Distribution
Histogram External VREF.
DS20006401C-page 16
-113.5
-113.0
-112.5
-112.0
-111.5
-111.0
-110.5
-110.0
-109.5
-109.0
-108.5
-108.0
-107.5
-107.0
-106.5
-106.0
-105.5
0
0
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
Occurrence (Counts)
33 Devices x 3 Lots
Bin Size: 0.1 dB
0
-120.0
-119.5
-119.0
-118.5
-118.0
-117.5
-117.0
-116.5
-116.0
-115.5
-115.0
-114.5
-114.0
-113.5
-113.0
-112.5
-112.0
Occurrence (Counts)
25
Occurrence (Counts)
30
33 Devices x 3 Lots
Bin Size: 0.5 dB
SNR Distribution Histogram
Total Harmonic Distortion (dBc)
FIGURE 2-24:
Internal VREF.
THD Distribution Histogram
2020-2021 Microchip Technology Inc.
MCP3565R
50
45
40
35
30
25
20
15
10
5
0
33 Devices x 3 Lots
Bin Size: 1.0 dB
Total Harmonic Distortion (dBc)
Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;
VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.
Histogram ticks are centered at their bin center.
0
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
-20
-40
-60
-80
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
-100
105
Occurrence (Counts)
Note:
-120
-50
-25
0
Spurious-Free Dynamic Range (dBc)
FIGURE 2-25:
SFDR Distribution
Histogram Internal VREF.
FIGURE 2-28:
External VREF.
125
THD vs. Temperature,
Spurious-Free Dynamic Range
(dBc)
120
100
100
80
60
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
40
20
0
-50
-25
FIGURE 2-26:
External VREF.
0
25
50
Temperature (°C)
75
100
SINAD vs. Temperature,
120
80
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
60
40
20
0
125
-50
-25
0
25
50
Temperature (°C)
FIGURE 2-29:
External VREF.
75
100
125
SFDR vs. Temperature,
120
100
Signal-to-Noise and Distortion
Ratio (dB)
Signal-to-Noise and Distortion
Ratio (dB)
100
140
120
Signal-to-Noise Ratio (dB)
25
50
75
Temperature (°C)
100
80
60
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
40
20
0
-50
-25
FIGURE 2-27:
External VREF.
0
25
50
Temperature (°C)
75
100
SNR vs. Temperature,
2020-2021 Microchip Technology Inc.
125
80
60
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
40
20
0
-50
-25
FIGURE 2-30:
Internal VREF.
0
25
50
75
Temperature (°C)
100
125
SINAD vs. Temperature,
DS20006401C-page 17
MCP3565R
Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;
VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.
Histogram ticks are centered at their bin center.
140
100
120
100
80
60
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
40
20
0
-50
-25
0
FIGURE 2-31:
Internal VREF.
25
50
75
Temperature (°C)
100
80
60
SINAD (dB)
40
SNR (dB)
-THD (dBc)
20
0
125
-8
-6
-4
-2
0
Analog Input Signal Amplitude (dBFS)
2
FIGURE 2-34:
Dynamic Performance vs.
Input Signal Amplitude.
SNR vs. Temperature,
110
0
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
-20
-40
-60
-80
-100
-120
-50
-25
0
FIGURE 2-32:
Internal VREF.
25
50
75
Temperature (°C)
100
125
BOOST = 0.5x
105
95
90
85
80
75
70
0
110
120
105
100
80
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
40
20
0
-50
-25
0
FIGURE 2-33:
Internal VREF.
DS20006401C-page 18
25
50
75
Temperature (°C)
100
SFDR vs. Temperature,
5
10
15
AMCLK Frequency (MHz)
FIGURE 2-35:
(BOOST = 0.5x).
THD vs. Temperature,
60
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
100
140
Spurious-Free Dynamic Range
(dBc)
VREF = 2.7V
AVDD = 3.3V
SFDR (dBc)
Signal-to-Noise and Distortion
Ratio (dB)
Total Harmonic Distortion (dBc)
Dynamic Performance
120
125
Signal-to-Noise and Distortion
Ratio (dB)
Signal-to-Noise Ratio (dB)
Note:
20
SINAD vs. AMCLK
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN=16
100
95
90
85
80
75
BOOST = 0.66x
70
0
5
10
15
AMCLK Frequency (MHz)
20
FIGURE 2-36:
SINAD vs. AMCLK
(BOOST = 0.66x).
2020-2021 Microchip Technology Inc.
MCP3565R
Note:
Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;
VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.
Histogram ticks are centered at their bin center.
110
105
BOOST = 1x
Signal-to-Noise and Distortion
Ratio (dB)
100
95
90
85
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
80
75
70
0
5
10
15
AMCLK Frequency (MHz)
FIGURE 2-37:
(BOOST = 1x).
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
95
90
85
80
75
70
0
5
10
15
MCLK Frequency (MHz)
105
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
115
110
105
100
95
90
85
80
75
BOOST = 2x
70
0
5
10
15
AMCLK Frequency (MHz)
FIGURE 2-38:
(BOOST = 2x).
BOOST = 1x
100
95
90
85
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
80
75
70
20
0
5
10
15
MCLK Frequency (MHz)
20
FIGURE 2-41:
SINAD vs. AMCLK
(BOOST = 1x, Internal VREF).
SINAD vs. AMCLK
105
105
BOOST = 1x
100
Signal-to-Noise and Distortion
Ratio (dB)
BOOST = 0.5x
Signal-to-Noise and Distortion
Ratio (dB)
20
FIGURE 2-40:
SINAD vs. AMCLK
(BOOST = 0.66x, Internal VREF).
SINAD vs. AMCLK
120
Signal-to-Noise and Distortion
Ratio (dB)
BOOST = 0.66x
100
20
Signal-to-Noise and Distortion
Ratio (dB)
Signal-to-Noise and Distortion
Ratio (dB)
105
100
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
95
90
85
80
75
70
0
5
10
15
MCLK Frequency (MHz)
FIGURE 2-39:
SINAD vs. AMCLK
(BOOST = 0.5x, Internal VREF).
2020-2021 Microchip Technology Inc.
20
95
90
85
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
80
75
70
0
5
10
15
MCLK Frequency (MHz)
20
FIGURE 2-42:
SINAD vs. AMCLK
(BOOST = 2x, Internal VREF).
DS20006401C-page 19
MCP3565R
Note:
Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;
VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.
Histogram ticks are centered at their bin center.
115
Input-Referred Offset Voltage
(μV)
1000
Signal-to-Noise and Distortion
Ratio (dB)
600
105
400
100
200
95
90
85
-400
BOOST = 1x, AVDD = 3.3V
80
BOOST = 1x, AVDD = 3.6V
75
-600
-800
GAIN = 1x
-1000
70
0
5
10
15
AMCLK Frequency (MHz)
FIGURE 2-43:
AVDD.
-50
20
1,200
60
OSR = 32
OSR = 64
OSR = 128
OSR = 256
FIGURE 2-44:
Frequency.
100,000
Analog Input Signal Frequency (Hz)
10,000
1,000
100
10
1
0
Input-Referred Offset Error (nV)
80
20
0
25
50
75
Temperature (°C)
800
0
125
TA = 25°C,
AZ_MUX = 1
600
400
200
0
2.7
3
3.3
AVDD Supply Voltage (V)
FIGURE 2-47:
(AZ_MUX = 1).
SINAD vs. Input Signal
100
Offset Error vs. Temperature
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
1,000
3.6
Offset Error vs. AVDD
1,000
-200
-400
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
-600
-800
-1000
Input-Referred Offset Voltage
(nV)
Signal-to-Noise and Distortion
Ratio (dB)
100
40
-25
FIGURE 2-46:
(AZ_MUX = 0).
SINAD vs. AMCLK vs.
120
Input-Referred Offset Error (μV)
0
-200
BOOST = 1x, AVDD = 2.7V
-1200
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
AVDD = 3.3V
AZ_MUX = 0
800
110
800
600
400
200
0
-200
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
-400
-600
TA = 25°C,
AZ_MUX = 0
AVDD = 3.3V
AZ_MUX = 1
-800
-1400
-1,000
2.7
3
3.3
AVDD Supply Voltage (V)
FIGURE 2-45:
(AZ_MUX = 0).
DS20006401C-page 20
Offset Error vs. AVDD
3.6
-50
-25
FIGURE 2-48:
(AZ_MUX = 1).
0
25
50
Temperature (°C)
75
100
125
Offset Error vs. Temperature
2020-2021 Microchip Technology Inc.
MCP3565R
Note:
Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;
VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.
Histogram ticks are centered at their bin center.
2
Gain Error (%)
1.6
1.4
1.2
1
TA = 25°C
0.8
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
0.6
0.4
0.2
0
2.7
3
3.3
AVDD Supply Voltage (V)
FIGURE 2-49:
Differential Input Impedance (k:)
10K
1.8
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
1K
100
10
1
3.6
1
5
MCLK Frequency (MHz)
FIGURE 2-52:
vs. MCLK.
Gain Error vs. AVDD.
2
25
Differential Input Impedance
10M
Gain Error (%)
1.6
1.4
1.2
1
0.8
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
0.6
0.4
0.2
AVDD = 3.3V
ADC Code Output (LSB)
1.8
0
100K
CS_SEL = 01
10K
CS_SEL = 10
CS_SEL = 11
1K
-50
-25
0
25
50
Temperature (°C)
FIGURE 2-50:
5
75
100
1
125
Gain Error vs. Temperature.
2
1.4
1
1.2
IDD (mA)
1.6
0
-1
-3
0.4
-4
0.2
-5
0
75
100
125
FIGURE 2-51:
Temperature Sensor
Accuracy vs. Temperature (First Order Best Fit).
AIDD BOOST = 1x
0.8
0.6
2020-2021 Microchip Technology Inc.
100M
AIDD BOOST = 2x
1
-2
0
25
50
Temperature (°C)
1M
2
3
-25
10K
FIGURE 2-53:
ADC Output Code vs.
Differential Input Impedance, Burnout Current
Sources Enabled.
1.8
-50
100
Differential Input Impedance (:)
61 Devices
4
TACC (°C)
1M
AIDD BOOST = 0.66x
AIDD BOOST = 0.5x
DIDD
0
FIGURE 2-54:
5
10
15
MCLK Frequency (MHz)
20
DIDD and AIDD vs. MCLK.
DS20006401C-page 21
MCP3565R
Note:
Unless otherwise indicated, AVDD = 3.3V; DVDD = 3.3V; TA = +25°C; MCLK = 4.9152 MHz;
VIN = -0.5 dBFS at 50 Hz; VREF = AVDD; ADC_MODE = 11. All other registers are set to the default value.
Histogram ticks are centered at their bin center.
2.5
2.41186
AIDD BOOST = 2x
2.41185
Internal VREF Output (V)
2
IDD (mA)
1.5
AIDD BOOST = 1x
AIDD BOOST = 0.66x
1
AIDD BOOST = 0.5x
0.5
DIDD
1.8
2.1
2.4
2.7
3
AVDD/DVDD (V)
FIGURE 2-55:
and AVDD.
3.3
2.41182
2.41181
2.4118
2.41179
Output Noise = 14.3 ȝVRMS
100 Samples (100 ms per sample)
0
3.6
2
4
Time (s)
6
8
10
FIGURE 2-58:
VREF Output vs. Time
(T = +25°C, AVDD = 3.3V).
DIDD and AIDD vs. DVDD
2.5
2.415
11 Devices x 3 Lots
AIDD BOOST = 2x
2.41
Internal VREF output (V)
2
AIDD (mA)
2.41183
2.41178
0
1.5
AIDD BOOST = 1x
1
AIDD BOOST = 0.66x
0.5
AIDD BOOST = 0.5x
0
2.405
2.4
2.395
2.39
2.385
2.38
0
5
10
15
MCLK Frequency (MHz)
FIGURE 2-56:
VREF).
20
AIDD vs. MCLK (Internal
-50
1.5
AIDD BOOST = 1x
AIDD BOOST = 0.66x
1
AIDD BOOST = 0.5x
0.5
0
-50
-25
0
FIGURE 2-57:
Temperature.
DS20006401C-page 22
25
50
75
Temperature (ƕC)
DIDD and AIDD vs.
100
125
Internal VREF Output (V)
AIDD BOOST = 2x
2
-25
0
25
50
Temperature (°C)
75
100
125
FIGURE 2-59:
VREF Output Voltage vs.
Temperature (AVDD = 3.3V).
2.5
AIDD (mA)
2.41184
2.3988
2.3987
2.3986
2.3985
2.3984
2.3983
2.3982
2.3981
2.398
2.3979
2.3978
2.7
2.8
2.9
FIGURE 2-60:
Voltage vs. AVDD.
3 3.1 3.2
AVDD (V)
3.3
3.4
3.5
3.6
Internal VREF Output
2020-2021 Microchip Technology Inc.
MCP3565R
2.1
Noise Specifications
Table 2-1 and Table 2-2 summarize the noise
performance of the MCP3565R device. The noise
performance is an analog gain function of the ADC
(digital gain does not change the noise performance
significantly) and the OSR, chosen through the user
interface. With a higher gain, the input referred noise is
reduced. With a higher OSR setting, the noise is also
reduced, as the oversampling diminishes both thermal
noise and the quantization noise induced by the
Delta-Sigma modulator loop.
The noise value generally increases when temperature
is higher as thermal noise is dominant for all OSR
larger than 32. For high OSR settings (> 512), the
thermal noise is largely dominant and increases
proportionally to the square root of the absolute
temperature. The performance in Table 2-1 to
Table 2-4 has been measured with the device placed in
Continuous Conversion mode, with the differential
input voltage equal to VIN = 0V, default conditions for
the register map and MCLK = 4.9152 MHz.
The noise performance is also a function of the
measurement duration. For short duration measurements (low number of consecutive samples), the
peak-to-peak noise is usually reduced, because the crest
factor (ratio between the RMS noise and peak-to-peak
noise) is reduced. This is a consequence of the noise
distribution being Gaussian by nature (see Figure 2-5 for
noise histogram example and fitting with an ideal
Gaussian distribution). The noise specifications have
been measured with a sample size of 16384 samples for
low OSR values and have been capped to approximately
80 seconds for the 16384 samples, leading to a larger
duration. The noise specifications are expressed in two
different values, which lead to the same quantity. It is
more practical to choose one of these representations
depending on the desired application.
In Table 2-1, the RMS (Root Mean Square) noise is the
variance of the ADC output code, expressed in µVRMS
and the input referred to with Equation 5-5. The
peak-to-peak noise values are in parentheses. The
peak-to-peak noise is the difference between the
maximum and minimum code observed during the
complete time of the measurement (see Equation 5-5).
In Table 2-2, the noise is expressed in Effective
Resolution (ER). The Effective Resolution is a ratio of
the full-scale range of the ADC (that depends on VREF
and gain) and the noise performance of the device. The
Effective Resolution can be determined from the RMS
or peak-to-peak noise with Equation 2-1 and
Equation 2-2.
2020-2021 Microchip Technology Inc.
EQUATION 2-1:
ER RMS
2 V REF
ln -----------------------------------------------------
GAIN RMS (Noise)
= ---------------------------------------------------------------ln 2
EQUATION 2-2:
ER pk – pk
2 V REF
ln ----------------------------------------------------------------------
GAIN Peak-to-Peak Noise
= --------------------------------------------------------------------------------ln 2
Due to the nature of the noise, the performance
detailed in the noise tables can vary significantly from
one measurement to another. They present an averaging of the performance over a large distribution of parts
over multiple lots. They give the typical expectation of
the noise performance, but performance can be better
or worse if a limited number of measurements is performed. For large gain and OSR combinations, if the
noise performance is comparable to the quantization
step (1 LSb), the performance is limited to 0.5 LSb for
the RMS noise and 1 LSb for the peak-to-peak noise
(same limits for Effective Resolution values).
These figures correspond to the resolution limit of the
device, as peak-to-peak noise cannot be better than
1 LSb. Similarly, if the intrinsic RMS noise of the device
is much smaller than 0.5 LSb, it can lead to histogram
with either one or two bins, depending on the relative
position of the input voltage versus the possible
quantized outputs of the ADC. If the position is exactly
in between two quantization steps, the histogram of
output noise will have two bins with exactly 50% occurrence on each. This case gives an RMS noise of a
0.5 LSb value, which is therefore, used as a cap of the
performance for the sake of clarity and a better
representation on the noise tables.
The noise specifications are improved by a ratio of
approximately √2 (or 0.5-bit Effective Resolution) when
the AZ_MUX setting is enabled. However, the output
data rate is significantly reduced (see Figure 5-5 and
Table 5-6).
The digital gain added for GAIN = 32x and 64x settings
is not significant for the noise performance, therefore
the noise values can be extracted from the GAIN = 16x
columns. Effective Resolution performance is
degraded by 1 bit for GAIN = 32x and 2 bits for GAIN =
64x, compared to GAIN = 16x performance.
Note:
All Output Noise performance-related
tables and figures are with reference to
the input (i.e., Input Referred).
DS20006401C-page 23
MCP3565R
TABLE 2-1:
OUTPUT NOISE VS. GAIN VS. OSR (AVDD = DVDD = VREF = 3.3V, TA = +25°C)
RMS (Peak-to-Peak) Noise (µV)
TOTAL
OSR
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
32
365.02 (2932.55)
120.80 (981.90)
60.79 (489.77)
30.70 (243.71)
15.69 (125.98)
8.23 (65.94)
64
68.06 (566.05)
23.56 (189.40)
12.54 (101.97)
7.06 (55.09)
4.25 (34.15)
2.77 (22.05)
128
35.21 (313.00)
12.68 (108.08)
7.03 (57.36)
4.19 (33.51)
2.68 (21.43)
1.83 (14.47)
256
24.83 (212.31)
8.94 (73.35)
4.94 (40.62)
2.94 (23.38)
1.88 (15.17)
1.29 (10.11)
512
17.99 (150.04)
6.43 (52.02)
3.53 (28.51)
2.09 (17.02)
1.34 (10.58)
0.92 (7.32)
1024
15.12 (123.74)
5.40 (43.95)
2.97 (23.54)
1.75 (14.05)
1.12 (8.82)
0.77 (6.20)
2048
11.47 (91.51)
4.08 (32.01)
2.26 (18.04)
1.34 (10.69)
0.86 (6.79)
0.59 (4.57)
4096
8.32 (64.97)
2.98 (23.59)
1.66 (13.10)
0.98 (7.85)
0.63 (4.97)
0.43 (3.45)
8192
5.88 (44.39)
2.11 (15.61)
1.18 (8.99)
0.70 (5.39)
0.45 (3.37)
0.31 (2.30)
16384
4.16 (30.56)
1.50 (10.80)
0.84 (6.12)
0.50 (3.65)
0.32 (2.28)
0.22 (1.60)
20480
3.71 (26.82)
1.34 (9.65)
0.75 (5.29)
0.44 (3.27)
0.28 (2.06)
0.19 (1.41)
24576
3.40 (24.24)
1.23 (8.88)
0.69 (4.88)
0.41 (2.94)
0.26 (1.92)
0.18 (1.29)
40960
2.70 (18.79)
0.98 (6.53)
0.55 (3.83)
0.32 (2.22)
0.20 (1.41)
0.14 (0.96)
49152
2.52 (17.44)
0.90 (6.08)
0.50 (3.47)
0.30 (2.07)
0.19 (1.25)
0.13 (0.87)
81920
2.05 (13.19)
0.74 (4.64)
0.40 (2.56)
0.24 (1.52)
0.15 (0.96)
0.10 (0.63)
98304
1.94 (12.20)
0.68 (4.37)
0.38 (2.39)
0.22 (1.37)
0.14 (0.89)
0.09 (0.59)
TABLE 2-2:
EFFECTIVE RESOLUTION VS. GAIN VS. OSR (AVDD = DVDD = VREF = 3.3V,
TA = +25°C)
Effective Resolution RMS (Peak-to-Peak) (bits)
TOTAL
OSR
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
32
15.7 (12.7)
15.7 (12.7)
15.7 (12.7)
15.7 (12.7)
15.7 (12.7)
15.6 (12.6)
64
18.2 (15.1)
18.1 (15.1)
18.0 (15.0)
17.8 (14.9)
17.6 (14.6)
17.2 (14.2)
128
19.1 (16.0)
19.0 (15.9)
18.8 (15.8)
18.6 (15.6)
18.2 (15.2)
17.8 (14.8)
256
19.6 (16.5)
19.5 (16.5)
19.4 (16.3)
19.1 (16.1)
18.7 (15.7)
18.3 (15.3)
512
20.1 (17.0)
20.0 (17.0)
19.8 (16.8)
19.6 (16.6)
19.2 (16.3)
18.8 (15.8)
1024
20.3 (17.3)
20.2 (17.2)
20.1 (17.1)
19.8 (16.8)
19.5 (16.5)
19.0 (16.0)
2048
20.7 (17.7)
20.6 (17.7)
20.5 (17.5)
20.2 (17.2)
19.9 (16.9)
19.4 (16.5)
4096
21.2 (18.2)
21.1 (18.1)
20.9 (17.9)
20.7 (17.7)
20.3 (17.3)
19.9 (16.9)
8192
21.7 (18.8)
21.6 (18.7)
21.4 (18.5)
21.2 (18.2)
20.8 (17.9)
20.4 (17.5)
16384
22.2 (19.3)
22.1 (19.2)
21.9 (19.0)
21.6 (18.8)
21.3 (18.5)
20.9 (18.0)
20480
22.4 (19.5)
22.2 (19.4)
22.1 (19.2)
21.8 (18.9)
21.5 (18.6)
21.0 (18.2)
24576
22.5 (19.7)
22.4 (19.5)
22.2 (19.4)
21.9 (19.1)
21.6 (18.7)
21.1 (18.3)
40960
22.8 (20.0)
22.7 (20.0)
22.5 (19.7)
22.3 (19.5)
21.9 (19.2)
21.5 (18.7)
49152
22.9 (20.1)
22.8 (20.1)
22.7 (19.9)
22.4 (19.6)
22.1 (19.3)
21.6 (18.9)
81920
23.2 (20.5)
23.1 (20.4)
23.0 (20.3)
22.7 (20.1)
22.4 (19.7)
22.0 (19.3)
98304
23.3 (20.6)
23.2 (20.5)
23.1 (20.4)
22.8 (20.2)
22.5 (19.8)
22.1 (19.4)
Note:
To calculate noise RMS level, and Effective Resolution (Bits) for a given GAIN and data rate, refer to the
OSR setting and associated data rate relationship shown in Table 5-6.
DS20006401C-page 24
2020-2021 Microchip Technology Inc.
MCP3565R
TABLE 2-3:
OUTPUT NOISE VS. GAIN VS. OSR (AVDD = DVDD = 3.3V, VREF = 2.4V INTERNAL,
TA = +25°C)
RMS (Peak-to-Peak) Noise (µV)
TOTAL
OSR
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
32
275.92 (2169.18)
91.57 (746.73)
46.26 (373.37)
23.50 (187.97)
12.16 (97.85)
6.52 (55.04)
64
65.13 (536.40)
22.54 (184.73)
12.04 (98.83)
6.76 (55.04)
4.05 (34.12)
2.64 (21.65)
128
38.21 (309.86)
13.47 (109.15)
7.35 (58.99)
4.27 (34.47)
2.66 (21.26)
1.79 (14.39)
256
26.60 (217.70)
9.38 (75.24)
5.14 (42.71)
2.99 (23.78)
1.88 (15.13)
1.27 (10.14)
512
18.94 (149.55)
6.65 (54.08)
3.65 (29.73)
2.13 (17.38)
1.33 (10.46)
0.89 (7.33)
1024
15.90 (126.06)
5.58 (44.03)
3.05 (24.21)
1.78 (14.33)
1.11 (8.98)
0.75 (6.06)
2048
12.06 (93.72)
4.25 (35.36)
2.33 (19.23)
1.35 (11.06)
0.85 (6.87)
0.57 (4.54)
4096
8.75 (68.40)
3.09 (24.49)
1.70 (13.25)
0.98 (7.98)
0.62 (4.85)
0.42 (3.33)
8192
6.31 (47.08)
2.22 (16.88)
1.22 (9.54)
0.71 (5.39)
0.44 (3.51)
0.30 (2.28)
16384
4.55 (35.03)
1.61 (11.70)
0.88 (6.41)
0.51 (3.77)
0.32 (2.32)
0.21 (1.53)
20480
4.11 (29.82)
1.45 (10.76)
0.79 (5.85)
0.46 (3.23)
0.28 (2.06)
0.19 (1.39)
24576
3.79 (27.14)
1.34 (9.87)
0.73 (5.28)
0.42 (3.03)
0.26 (1.85)
0.17 (1.27)
40960
3.02 (21.15)
1.06 (7.24)
0.57 (4.06)
0.33 (2.27)
0.20 (1.43)
0.14 (0.96)
49152
2.79 (19.51)
0.98 (6.58)
0.53 (3.61)
0.30 (2.15)
0.19 (1.32)
0.12 (0.87)
81920
2.27 (14.91)
0.79 (5.01)
0.43 (2.89)
0.24 (1.62)
0.15 (0.99)
0.10 (0.63)
98304
2.09 (14.04)
0.72 (4.49)
0.39 (2.52)
0.22 (1.45)
0.14 (0.93)
0.09 (0.59)
TABLE 2-4:
TOTAL
OSR
EFFECTIVE RESOLUTION VS. GAIN VS. OSR (AVDD = DVDD = 3.3V, VREF = 2.4V
INTERNAL, TA = +25°C)
Effective Resolution RMS (Peak-to-Peak) (bits)
GAIN = 0.33
GAIN = 1
GAIN = 2
GAIN = 4
GAIN = 8
GAIN = 16
32
15.2 (12.7)
15.2 (12.7)
15.2 (12.6)
15.1 (12.6)
15.1 (12.6)
15.0 (12.5)
64
17.3 (14.8)
17.2 (14.7)
17.1 (14.6)
16.9 (14.5)
16.7 (14.2)
16.3 (13.8)
128
18.0 (15.5)
17.9 (15.4)
17.8 (15.3)
17.6 (15.1)
17.3 (14.8)
16.9 (14.4)
17.4 (14.9)
256
18.6 (16.1)
18.5 (16.0)
18.3 (15.8)
18.1 (15.6)
17.8 (15.3)
512
19.1 (16.6)
19.0 (16.4)
18.8 (16.3)
18.6 (16.1)
18.3 (15.8)
17.9 (15.4)
1024
19.3 (16.8)
19.2 (16.7)
19.1 (16.6)
18.9 (16.4)
18.5 (16.1)
18.1 (15.6)
2048
19.7 (17.2)
19.6 (17.1)
19.5 (17.0)
19.3 (16.8)
18.9 (16.4)
18.5 (16.0)
4096
20.2 (17.7)
20.1 (17.6)
19.9 (17.4)
19.7 (17.2)
19.4 (16.9)
19.0 (16.5)
8192
20.6 (18.2)
20.5 (18.1)
20.4 (18.0)
20.2 (17.8)
19.9 (17.4)
19.4 (17.0)
16384
21.1 (18.7)
21.0 (18.7)
20.9 (18.5)
20.7 (18.3)
20.4 (18.0)
19.9 (17.6)
20480
21.3 (18.9)
21.2 (18.8)
21.0 (18.7)
20.8 (18.5)
20.5 (18.2)
20.1 (17.7)
24576
21.4 (19.0)
21.3 (18.9)
21.2 (18.8)
21.0 (18.6)
20.6 (18.3)
20.2 (17.9)
40960
21.7 (19.4)
21.6 (19.3)
21.5 (19.2)
21.3 (19.0)
21.0 (18.7)
20.6 (18.3)
49152
21.8 (19.5)
21.7 (19.5)
21.6 (19.3)
21.4 (19.1)
21.1 (18.8)
20.7 (18.4)
81920
22.1 (19.9)
22.0 (19.8)
21.9 (19.8)
21.8 (19.5)
21.5 (19.3)
21.0 (18.9)
98304
22.2 (20.0)
22.2 (20.0)
22.0 (19.9)
21.9 (19.7)
21.6 (19.4)
21.2 (19.0)
Note:
To calculate noise RMS level and Effective Resolution (Bits) for a given GAIN and data rate, refer to the
OSR setting and associated data rate relationship shown in Table 5-6.
2020-2021 Microchip Technology Inc.
DS20006401C-page 25
MCP3565R
NOTES:
DS20006401C-page 26
2020-2021 Microchip Technology Inc.
MCP3565R
3.0
PIN DESCRIPTIONS
TABLE 3-1:
PIN FUNCTION TABLE
MCP3565R
Symbol
1
AGND
Description
Analog Ground Pin
2
REFIN-
Inverting Reference Input Pin
3
REFIN+
Noninverting Reference Input Pin
4
CH1
Analog Input 1 Pin
5
CH0
Analog Input 0 Pin
6
CS
7
SCK
Serial Interface Digital Clock Input Pin and Master Clock Input/Output Pin
8
SDI
Serial Interface Digital Data Input Pin
Serial Interface Chip Select Digital Input Pin
9
SDO
Serial Interface Digital Data Output Pin
10
DGND
Digital Ground Pin
11
DVDD
Digital Supply Voltage Pin
12
AVDD
Analog Supply Voltage Pin
13
EP
2020-2021 Microchip Technology Inc.
Exposed Thermal Pad, internally connected to AGND
DS20006401C-page 27
MCP3565R
3.1
Differential Reference Voltage
Inputs: REFIN+/OUT, REFIN-
The REFIN+/OUT pin is the noninverting differential
reference input (VREF+) when VREF_SEL = 0. When
VREF_SEL = 1, it is the internal voltage reference
output voltage as well as the ADC voltage noninverting
reference pin.
The REFIN- pin is the inverting differential reference
input (VREF-).
For single-ended reference applications, the REFINpin should be directly connected to AGND.
The differential reference voltage pins must respect
this condition at all times: 0.6V ≤ VREF ≤ AVDD. The
differential reference voltage input is given by
Equation 3-1.
EQUATION 3-1:
V REF = V REF+ – V REFFor optimal ADC accuracy, appropriate bypass
capacitors should be placed between REFIN+/OUT
and AGND at all times. Using a 0.1 µF and a 10 µF
ceramic capacitor can help to decouple the reference
voltage around the sampling frequency (which would
lead to aliasing noise in the base band). These bypass
capacitors are not mandatory for correct ADC operation, but removing these capacitors may degrade the
accuracy of the ADC.
3.2
Analog Inputs (CHn): Differential
or Single-Ended
The CHn pins are the analog input signal pins for the
ADC. Two analog multiplexers are used to connect the
CHn pins to the VIN+/VIN- analog inputs of the ADC.
Each multiplexer independently selects one input to be
connected to an ADC input (VIN+ or VIN-). Each CHn
pin can either be connected to the VIN+ or VIN- inputs
of the ADC. This multiplexer selection is controlled by
either the MUX register in MUX mode or the SCAN
register in Scan mode. See Figure 5-1 for more details
on the multiplexer structure.
When the input is selected by the multiplexer, the differential (VIN) and Common-Mode Voltage (VINCOM) at
the ADC inputs are defined by Equation 3-2.
EQUATION 3-2:
V IN = V IN+ – V INV IN+ + V INV INCOM = ---------------------------------2
DS20006401C-page 28
The input signal level is multiplied by the internal
programmable analog gain at the front end of the
Delta-Sigma modulator. For single-ended input
measurements, the user can select VIN- to be internally
connected to AGND.
The differential input voltage should not exceed an
absolute of ±VREF/GAIN for accurate measurement. If
the input is out of range, the converter output code is
saturated or overloaded, depending on how the output
data format (DATA_FORMAT[1:0]) is selected. See
Section 5.6 “ADC Output Data Format” for further
information on the ADC output coding.
The absolute voltage on each of the analog signal
input pins can range from AGND – 0.1V to VDD + 0.1V.
Any voltage above or below this range causes leakage
currents through the Electrostatic Discharge (ESD)
diodes at the input pins. This ESD current can cause
unexpected performance of the device. The
Common-mode of the analog inputs should be chosen
such that both the differential analog input range and
the absolute voltage range on each pin are within the
specified operating range defined in the Electrical
Characteristics table.
3.3
SPI Serial Interface
Communication Pins
The SPI interface is compatible with both SPI 0,0 and
1,1 modes.
3.3.1
CHIP SELECT (CS)
This is the SPI Chip Select pin that enables/disables
the SPI serial communication. The CS falling edge
initiates the serial communication and the rising edge
terminates the communication. No communication can
take place when this pin is in a Logic High state. This
input is Schmitt Triggered.
3.3.2
SERIAL DATA CLOCK (SCK)
This is the serial clock input pin for SPI communication.
This input has a Schmitt Trigger structure. The maximum SPI clock speed is 20 MHz. Data are clocked into
the device on the rising edge of SCK. Data are clocked
out of the device on the falling edge of SCK. The device
interface is compatible with both SPI 0,0 and 1,1
modes. SPI modes can be changed when CS is in
Logic High state.
This pin is also used to input or output the MCLK clock,
depending on the CLK_SEL[1:0] bits setting.
When CLK_SEL[1:0] = 0x, the SCK pin is defined as
the MCLK input pin, while still working as the SCK input
pin for SPI communications.
2020-2021 Microchip Technology Inc.
MCP3565R
When running conversions, SCK has to be continuously clocking at a constant frequency to ensure proper
ADC accuracy. In this case, communications using the
SPI interface should be synchronized on the
free-running clock and can be framed with a proper
usage of the CS pin.
When CLK_SEL[1:0] = 10, the MCLK is running based
on the internal oscillator and is not attached to the SCK
pin. In this case, SCK and MCLK are asynchronous
and the SCK pin is used only for the SPI interface
communications.
When CLK_SEL[1:0] = 11, the SCK pin becomes an
output for the internal oscillator and sends a
free-running clock at the AMCLK frequency. In this
case, the SCK pin is still working as the SCK input for
SPI communications.
The MCP3565R becomes the host device for the SCK
clock. The SPI communications have to be framed
using this free-running clock as the time base in order
to be correctly interpreted by the device.
3.3.3
SERIAL DATA OUTPUT PIN (SDO)
This pin is used for the SPI Data Output (SDO). The
SDO data are clocked out on the falling edge of SCK.
This pin stays high-impedance under the following
conditions:
• When CS pin is logic high.
• During the entire SPI write or Fast command
communication period after the SPI COMMAND
byte has been transmitted.
• After the two device address bits in the command
are transmitted, if the device address in the command does not match the internal chip device
address.
3.3.4
SERIAL DATA INPUT PIN (SDI)
This is the SPI Data Input (SDI) pin and it uses a
Schmitt Trigger structure. When CS is logic low, this
pin is used to send a COMMAND byte just after the CS
falling edge, which can be followed by data words of
various lengths. Data are clocked into the device on
the rising edge of SCK. Toggling SDI while reading a
register has no effect.
3.4
Digital Ground (DGND)
DGND is the ground connection to internal digital
circuitry. To ensure accuracy and noise cancellation,
DGND must be connected to the same ground as
AGND, preferably with a star connection. If a digital
ground plane is available, it is recommended to tie this
pin to this plane of the Printed Circuit Board (PCB).
This plane should also reference all other digital
circuitry in the system. DGND is not internally connected
to AGND and must be connected externally.
3.5
Digital Power Supply (DVDD)
DVDD is the power supply pin for the digital circuitry
within the device. The voltage on this pin must be
maintained in the range specified by the Electrical
Characteristics table. For optimal performance, it is
recommended to connect appropriate bypass capacitors (typically, a 10 µF ceramic in parallel with a 0.1 µF
ceramic). DVDD is monitored by the DVDD POR
monitoring circuit for the digital section.
3.6
Analog Power Supply (AVDD)
AVDD is the power supply pin for the analog circuitry
within the device. The voltage on this pin must be
maintained in the range specified by the Electrical
Characteristics table. For optimal performance, it is
recommended to connect appropriate bypass capacitors (typically, a 10 µF ceramic in parallel with a 0.1 µF
ceramic). AVDD is monitored by the AVDD POR
monitoring circuit for the analog section.
3.7
Analog Ground (AGND)
AGND is the ground connection to internal analog
circuitry. To ensure accuracy and noise cancellation,
this pin must be connected to the same ground as
DGND, preferably with a star connection. If an analog
ground plane is available, it is recommended to tie this
pin to this plane of the PCB. This plane should also
reference all other analog circuitry in the system. AGND
is the biasing voltage for the substrate of the die and is
not internally connected to DGND.
3.8
Exposed Pad (EP)
The pad is internally connected to AGND. It must be
connected to the analog ground of the PCB for optimal
accuracy and thermal performance. This pad can also
be left floating if necessary.
2020-2021 Microchip Technology Inc.
DS20006401C-page 29
MCP3565R
NOTES:
DS20006401C-page 30
2020-2021 Microchip Technology Inc.
MCP3565R
4.0
TERMINOLOGY AND
FORMULAS
This section defines the terms and formulas used
throughout this document. The following terms are
defined:
•
•
•
•
•
MCLK – Master Clock
AMCLK – Analog Master Clock
DMCLK – Digital Master Clock
DRCLK – Data Rate Clock
OSR – Oversampling Ratio
•
•
•
•
•
•
•
•
•
•
•
Offset Error
Gain Error
Integral Nonlinearity Error (INL)
Signal-to-Noise Ratio (SNR)
Signal-to-Noise and Distortion Ratio (SINAD)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
MCP3565R Delta-Sigma Architecture
Power Supply Rejection Ratio (PSRR)
Common-Mode Rejection Ratio (CMRR)
Digital Pins Output Current Consumption
PRE[1:0]
CLK_SEL[1]
OSR[3:0]
CLK_SEL[1] = 0
SCK
Pad
0
OUT
MCLK
1/PRESCALE
AMCLK
1/4
DMCLK
1/OSR
DRCLK
1
Internal Oscillator
Multiplexer
Clock Divider
Clock Divider
Clock Divider
CLK_SEL[1:0] = 11
AMCLKOUT
FIGURE 4-1:
4.1
System Clock Details.
MCLK – Master Clock
This is the master clock frequency used for clocking the
Delta-Sigma ADC and the timer for the Scan mode. It
can be externally generated (in which case, SCK is the
input pin for this clock) or internally generated by the
internal oscillator (in which case, it can also be clocked
out on the SCK pin).
4.2
AMCLK – Analog Master Clock
This is the clock frequency that is present on the analog
portion of the device after prescaling has occurred via
the PRE[1:0] bits.
EQUATION 4-1:
ANALOG MASTER
CLOCK
MCLK AMCLK = ---------------------Prescale
4.3
DMCLK – Digital Master Clock
EQUATION 4-2:
DIGITAL MASTER CLOCK
MCLK DMCLK = AMCLK
--------------------- = ------------------------------4
4 Prescale
4.4
DRCLK – Data Rate Clock
This is the output data rate in Continuous mode or the
rate at which the ADC outputs new data. This data rate
depends on the OSR and the prescaler as shown in
Equation 4-3.
EQUATION 4-3:
DATA RATE
MCLK
DRCLK = DMCLK
---------------------- = AMCLK
--------------------- = -------------------------------------------------OSR
4 OSR
4 OSR Prescale
Since this is the output data rate and since the
decimation filter is a sinc (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
This is the clock frequency that is present on the digital
portion of the device. This is also the sampling frequency
or the rate at which the modulator outputs are refreshed.
Each period of this clock corresponds to one sample and
one modulator output. See Equation 4-2.
2020-2021 Microchip Technology Inc.
DS20006401C-page 31
MCP3565R
4.5
OSR – Oversampling Ratio
The ratio of the sampling frequency to the output data
rate. OSR = DMCLK/DRCLK in Continuous mode. See
Table 5-6 for the OSR setting effect on sinc filter
parameters.
4.6
Offset Error
This is the error induced by the ADC when the inputs
are shorted together (VIN = 0V). This error varies based
on gain settings, OSR settings and from chip-to-chip. It
can easily be calibrated out by an MCU with a
subtraction.
4.7
Gain Error
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in percentage compared to the ideal transfer function defined
by Equation 5-5. The specification incorporates ADC
gain error contributions, but not the VREF contribution.
This error varies with gain and OSR settings. The gain
error of this device has a low-temperature coefficient.
4.8
Integral Nonlinearity Error (INL)
Integral nonlinearity error is the maximum deviation of
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed, or with the end points equal to zero. It
is the maximum remaining static error after offset and
gain errors calibration for a DC input signal.
4.9
EQUATION 4-4:
SIGNAL-TO-NOISE RATIO
SignalPower
SNR dB = 10 log ----------------------------------
NoisePower
Signal-to-Noise and Distortion
Ratio (SINAD)
SINAD EQUATION
SignalPower
SINAD dB = 10 log ---------------------------------------------------------------------
Noise + HarmonicsPower
The calculated combination of SNR and THD per the
following formula also yields SINAD:
EQUATION 4-6:
SINAD, THD AND SNR
RELATIONSHIP
SINAD dB = 10 log 10
4.11
SNR
-----------
10
+ 10
THD
------------
10
Total Harmonic Distortion (THD)
The THD is the ratio of the output harmonics power to
the fundamental signal power for a sine wave input and
is defined by Equation 4-7.
EQUATION 4-7:
HarmonicsPower
THD dB = 10 log -----------------------------------------------------
FundamentalPower
The THD is usually measured only with respect to the
first ten harmonics. THD is sometimes expressed in
percentage (%). This formula converts the THD from
dB to percentage:
EQUATION 4-8:
Signal-to-Noise Ratio (SNR)
For this device family, the Signal-to-Noise Ratio is a
ratio of the output fundamental signal power to the
noise power (not including the harmonics of the signal)
when the input is a sine wave at a predetermined
frequency; it is measured in dB. Usually, only the
maximum Signal-to-Noise Ratio is specified. The SNR
figure depends mainly on the OSR and gain settings of
the device, as well as the temperature (due to thermal
noise being dominant for high OSR).
4.10
EQUATION 4-5:
THD % = 100 10
4.12
THD dB
-----------------------20
Spurious-Free Dynamic Range
(SFDR)
SFDR is the ratio between the output power of the
fundamental and the highest spur in the frequency
spectrum. The spur frequency is not necessarily a
harmonic of the fundamental, even though that is
usually the case. This figure represents the dynamic
range of the ADC when a full-scale signal is used at the
input. This specification depends mainly on the OSR
and gain settings.
EQUATION 4-9:
FundamentalPower
SFDR dB = 10 log -----------------------------------------------------
HighestSpurPower
Signal-to-Noise and Distortion Ratio is similar to
Signal-to-Noise Ratio, with the exception that the user
must include the harmonics power in the noise power
calculation. The SINAD specification depends mainly
on the OSR and gain settings.
DS20006401C-page 32
2020-2021 Microchip Technology Inc.
MCP3565R
4.13
MCP3565R Delta-Sigma
Architecture
A Delta-Sigma ADC is an oversampling converter that
incorporates a built-in modulator, which digitizes the
quantity of charge integrated by the modulator loop.
The quantizer is the block that performs the
Analog-to-Digital conversion. The quantizer is typically
one bit or a simple comparator, which helps to maintain
the linearity performance of the ADC (the DAC
structure is in this case, inherently linear).
Multibit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR, which leads to better SNR
figures. However, typically the linearity of such
architectures is more difficult to achieve since the DAC
is no more simple to realize and its linearity limits the
THD of such ADC.
The modulator five-level quantizer is a Flash ADC,
composed of four comparators, arranged with equally
spaced thresholds and a thermometer coding. The
device also includes proprietary five-level DAC
architecture that is inherently linear for improved THD
figures.
4.14
Power Supply Rejection Ratio
(PSRR)
This is the ratio between a change in the power supply
voltage and the change in the ADC output codes. It
measures the influence of the power supply voltage on
the ADC outputs. PSRR is defined in Equation 4-10.
The PSRR specification can be DC (the power supply
is taking multiple DC values) or AC (the power supply
is a sine wave at a certain frequency with a certain
Common-mode). In AC, the amplitude of the sine wave
represents the change in the power supply.
EQUATION 4-10:
V OUT
PSRR dB = 20 log -------------------
AV DD
Where VOUT is the equivalent input voltage that the
output code translates to with the ADC transfer
function.
4.15
Common-Mode Rejection Ratio
(CMRR)
This is the ratio between a change in the
Common-mode input voltage and the change in the
ADC output codes. It measures the influence of the
Common-mode input voltage on the ADC outputs.
The CMRR specification can be DC (the Common-mode
input voltage takes multiple DC values) or AC (the
Common-mode input voltage is a sine wave at a certain
frequency with a certain Common-mode). In AC, the
amplitude of the sine wave represents the change in
the Common-mode input voltage. CMRR is defined in
Equation 4-11.
EQUATION 4-11:
V OUT
CMRR dB = 20 log ------------------------
V INCOM
Where VINCOM = (VIN+ + VIN-)/2 is the Common-mode
input voltage and VOUT is the equivalent input voltage
that the output code translates to with the ADC transfer
function.
4.16
Digital Pins Output Current
Consumption
The digital current consumption shown in the Electrical
Characteristics table does not take into account the
current consumption generated by the digital output pins
and the charge of their capacitive loading. The specification is intended with all output pins left floating and no
communication.
In order to estimate the additional current consumption
due to the output pins, see Equation 4-12. This equation specifies the amount of additional current due to
each pin when its output is connected to a Cload
capacitance, with respect to DGND and submitted to an
output signal toggling at an fout frequency.
If a typical 10 MHz SPI frequency is used, with a 30 pF
load and DVDD = 3.3V, the SDO output generates an
additional maximum current consumption of 500 µA
(the maximum toggling frequency of SDO is 5 MHz,
since fSCK = 10 MHz and this is reached when the ADC
output code is a succession of ‘1’s and ‘0’s). The Cload
value includes internal digital output driver capacitance, but this can generally be neglected with respect
to the external loading capacitance.
EQUATION 4-12:
Where:
DIDD SPI = C load DV DD f
out
Cload = Capacitance on the Output Pin
DVDD = Digital Supply Voltage
fout = Output Frequency on the Output Pin
2020-2021 Microchip Technology Inc.
DS20006401C-page 33
MCP3565R
NOTES:
DS20006401C-page 34
2020-2021 Microchip Technology Inc.
MCP3565R
5.0
DEVICE OVERVIEW
5.1
Analog Input Multiplexer
Each of these multiplexers includes the same
possibilities for the input selection, so that any required
combination of input voltages can be converted by the
ADC. The analog multiplexer is composed of parallel
low-resistance input switches, turned on or off, depending on the input channel selection. Their resistance is
negligible compared to the input impedance of the ADC
(caused by the charge and discharge of the input
sampling capacitors on the VIN+/VIN- ADC inputs). The
block diagram of the analog multiplexer is shown in
Figure 5-1.
The MCP3565R device includes a fully configurable
analog input dual multiplexer that can select which
input is connected to each of the two differential input
pins (VIN+/VIN-) of the Delta-Sigma ADC.
The dual multiplexer is divided into two single-ended
multiplexers that are totally independent.
MUX
CH0
CH1
AGND
AVDD
AVDD
REFIN+/OUT
REFIN-
AVDD
ISOURCE
CS_SEL
TEMP diode P
AVDD
ITEMP+
ITEMP-
TEMP diode M
VCM
MUX
=1101
MUX
=1101
VIN+ Analog Multiplexer
MUX
=1110
VIN+
AGND
MUX
VIN-
CH0
CS_SEL
CH1
AGND
MUX
=1110
ISINK
Sigma-Delta ADC
AVDD
REFIN+/OUT
REFIN-
AGND
TEMP diode P
TEMP diode M
VCM
VIN- Analog Multiplexer
AGND
Analog Input Dual Multiplexer
FIGURE 5-1:
Simplified Analog Input Multiplexer Schematic.
2020-2021 Microchip Technology Inc.
DS20006401C-page 35
MCP3565R
The possible selections are described in Table 5-1 and
can be set with the MUX[7:0] register bits during the
MUX mode. The MUX[7:4] bits define the selection for
the VIN+ pin (noninverting analog input of the ADC).
The MUX[3:0] bits define the selection for the VIN- pin
(inverting analog input of the ADC).
TABLE 5-1:
ANALOG INPUT MUX DECODING
MUX[7:4] (VIN+) or
MUX[3:0] (VIN-) Code
Selected
Channel
0000
CH0
0001
0010
0011
0100
0101
Comment
CH1
Reserved
Do not use
Reserved
Do not use
Reserved
Do not use
Reserved
Do not use
Reserved
Do not use
0111
Reserved
Do not use
1001
AVDD
0110
1000
1010
AGND
Reserved
1011
REFIN+/OUT
1101
TEMP Diode P
1100
1110
1111
REFINTEMP Diode M
Internal VCM
During SCAN mode, the two single-ended input multiplexers are automatically set to a certain position,
depending on the SCAN sequence and which channel
has been selected by the user. The SCAN sequence
channels’ configuration corresponds to a certain code
in the MUX[7:0] register, as defined in Table 5-15.
In order to monitor the digital power supply (DVDD), it is
necessary to connect DVDD externally to one of the
CHn analog inputs, since DVDD is not one of the possible selections of the analog multiplexer. A similar
setup can be implemented to monitor DGND if DGND is
not connected externally to AGND.
The TEMP Diodes P and M are two internal diodes that
are biased by a current source, and that can be used to
perform a temperature measurement. If TEMP Diode P
is connected to VIN+ and TEMP Diode M to VIN-, then
the ADC output code is a function of the temperature
using Equation 5-1 (see Section 5.1.2, Internal Temperature Sensor for more details). The VCM selection
measures the internal Common-mode voltage source
that biases the Delta-Sigma modulator (this voltage is
not provided at any output of the part).
DS20006401C-page 36
Do not use
Internal Common-mode voltage for modulator biasing
The possible inputs of the analog multiplexer include,
not only the analog input channels, but also REFIN+/inputs, AVDD and AGND, as well as temperature sensor
outputs and the VCM internal Common-mode. This
large selection offers many possibilities for measuring
internal or external data resources of the system and
can serve as diagnostic purposes to increase the
security of the applications. Some monitor channels
are already predefined in Scan mode to further help
users to integrate diagnostics to their applications (for
example, the analog power supply or the temperature
can be constantly monitored in Scan mode; see
Section 5.15.3 “Scan Mode Internal Resource
Channels” for more details of the different resources
that can be monitored in Scan mode).
Note:
When VREF_SEL = 0 (external VREF) and
REFIN+/OUT and REFIN- are selected as
analog inputs for the ADC, the same
REFIN+/OUT and REF- pin voltages are
used as the reference for the ADC. This
Diagnostic mode is useful for determining
the full-scale gain error of the ADC when
a gain setting of 1/3x or 1x is used.
2020-2021 Microchip Technology Inc.
MCP3565R
5.1.1
BURNOUT CURRENT SOURCES
FOR SENSOR OPEN/SHORT
DETECTION
The ADC inputs, VIN-/VIN+, feature a selectable burnout current source, which enables open or short-circuit
detection, as well as biasing very low-current external
sensors. The bias current is sourced on the VIN+ pin of
the ADC (noninverting output of the analog multiplexer)
and sunk on the VIN- pin of the ADC (inverting output of
the analog multiplexer). Since the same current flows
at the VIN-/VIN+ pins of the ADC, it can sense the
impedance of an externally connected sensor that
would be connected between the selected inputs of the
multiplexer. When the sensor is in short circuit, the
ADC converts signals that are close to 0V. When the
sensor is an open circuit, the ADC converts signals that
are close to the AVDD voltage.
The current source is an independent peripheral of the
ADC. It does not need the ADC to be in Conversion
mode to be present. Once enabled, the source provides current even when the ADC is in Reset or ADC
Shutdown mode. The current source can be configured
at any time through programming the CS_SEL[1:0] bits
in the CONFIG0 register (see Table 5-2).
Since the amount of current selected can be very small,
it may be necessary to diminish the MCLK master clock
frequency to be able to reach the full desired accuracy
during conversions (the settling time of the input structure, including the sensor, can be large if the sensor is
very resistive, which will limit the bandwidth of the
Sample-and-Hold input circuit).
TABLE 5-2:
BURNOUT CURRENT
SOURCE SETTINGS
CS_SEL[1:0]
(Source/Sink)
Burnout Current
Amplitude
00
0 µA
01
0.9 µA
11
15 µA
10
5.1.2
INTERNAL TEMPERATURE
SENSOR
The device includes an on-board temperature sensor,
which is made of two typical P-N junction diodes biased
by fixed current sources (TEMP Diode P and M). The
TEMP Diode P has a current density of 4x of the TEMP
Diode M.
The difference in the current densities of the diodes yields
a voltage that is a function of the absolute temperature.
Once the ADC inputs (VIN-/VIN+) are connected to the
temperature sensor diodes (MUX[7:0] = 0xDE), the
ADC will see a VIN differential input that is the function
of the temperature. The transfer function of the
temperature sensor can be approximated by a linear
equation or a third-order equation for more accuracy.
When the internal temperature sensor is selected for
the MUX or SCAN input, the input sink/source current
source, controlled by the CS_SEL[1:0] bits (see
Section 5.1, Analog Input Multiplexer), is disabled
internally (even though the CS_SEL[1:0] bits are not
modified by the temperature sensor selection). In this
case, the input current source is replaced by a specific
internal current source that will only be sourced to the
diode temperature sensor (see Figure 5-1).
The bias current of the diodes is not calibrated internally
and can lead to a relatively large gain and offset error in
the transfer function of the temperature sensor. Typical
graphs showing the typical error in the temperature
measurement are provided in Section 2.0, Typical Performance Curves (see Figure 2-51 for first-order and
Figure 2-51 for third-order fitting).
The accuracy can also be optimized by using proper
digital gain and offset error calibration schemes.
3.7 µA
The accuracy of the current sources is on the order of
magnitude of ±20% and not very well controlled internally. However, the mismatch between sink and source
is typically around ±1%.
This relatively low accuracy on the current is generally
sufficient for open/short detection applications.
Figure 2-53 shows how the ADC output code varies
when the burnout current sources are enabled (with
Gain = 1x) and the input sensor impedance is swept
with a large dynamic range. This allows the use of the
ADC as an open/short-detection circuit, which is
practical when manufacturing complex remote sensor
systems.
2020-2021 Microchip Technology Inc.
DS20006401C-page 37
MCP3565R
EQUATION 5-1:
TEMPERATURE SENSOR TRANSFER FUNCTION
First-order (linear) fitting: Gain = 1, MCLK = 4.9152 MHz, DATA_FORMAT[1:0] = 00
TEMP C = 4.0096 10
–4
ADCDATA LSb V REF V – 269.13 Where VREF = VREF+ – VREFV IN mV = 0.2973 TEMP ( C) + 80
5.1.3
ADC OFFSET CANCELLATION
ALGORITHM
The input multiplexer and the ADC include an offset
cancellation algorithm that cancels the offset contribution
of the ADC. This offset cancellation algorithm is
controlled by the AZ_MUX bit in the CONFIG2 register.
When AZ_MUX = 0 (default), the offset cancellation
algorithm is disabled and the conversions are not
affected by this setting. When AZ_MUX = 1, the
algorithm is enabled. When the offset cancellation
algorithm is enabled, ADC takes two conversions, one
with the differential input as VIN+/VIN-, one with VIN+/VINinverted. Equation 5-2 calculates the ADC output code.
When AZ_MUX = 1, the Conversion Time, TCONV, is
multiplied by two, compared to the default case where
AZ_MUX = 0.
EQUATION 5-2:
AZ_MUX CONVERSION RESULT
ADC Output at + V IN – ADC Output at -V IN
ADC Output Code (AZ_MUX = 1) = ------------------------------------------------------------------------------------------------------------------------2
This technique allows the cancellation of the ADC
offset error and the achievement of ultra-low offset
without any digital calibration. The resulting offset is the
residue of the difference between the two conversions,
which is on the order of magnitude of the noise floor.
This offset is effectively canceled at every conversion,
so the residual offset error temperature drift is
extremely low.
For One-Shot mode, the conversion time is simply
multiplied by two. Enabling the AZ_MUX bit is not
compatible with the Continuous Conversion mode
(because it effectively multiplexes the inputs in
between each conversion). If AZ_MUX = 1 and
CONV_MODE = 11 (Continuous Conversion mode),
the device will reset the digital filter in between each
conversion, and will therefore, have an output data rate
of 1/(2 * TCONV). The Continuous mode is replaced by
a series of One-Shot mode conversions with no delay
in between each conversion (see Section 5.14 “Conversion Modes” and Figure 5-5 for more details about
the Conversion modes).
DS20006401C-page 38
2020-2021 Microchip Technology Inc.
MCP3565R
5.2
Input Impedance
for more details). The RC network usually uses small R
and large C to avoid additional offset due to IR drop in
the signal path. This anti-aliasing filter will induce a
small systematic gain error on the AC input signals that
can be compensated in the digital section with the
Digital Gain Error Calibration register (GAINCAL).
The ADC inputs (VIN+/VIN-) are directly tied to the
analog multiplexer outputs and are not routed to external pins. The multiplexer input stage contribution to the
input impedance is negligible.
The conversion accuracy can be affected by the input
signal source impedance when any external circuit is
connected to the input pins. The source impedance
adds to the internal impedance and directly affects the
time required to charge the internal sampling capacitor.
Therefore, a large input source impedance connected
to the input pins can increase the system performance
errors, such as offset, gain and Integral Nonlinearity
(INL). Ideally, the input source impedance should be
near zero. This can be achieved by using an operational amplifier with a closed-loop output impedance of
tens of ohms.
5.3
ADC Programmable Gain
The gain of the converter is programmable and
controlled by the GAIN[2:0] bits in the CONFIG2
register. The ADC programmable gain is divided in two
gain stages: one in the analog domain, one in the digital
domain, as per Table 5-3.
After the multiplexer, the analog input signals are
routed to the Delta-Sigma ADC inputs and are
amplified by the analog gain stage (see Section 5.3.1
“Analog Gain” for more details). The digital gain stage
is placed inside the digital decimation filter (see
Section 5.3.2 “Digital Gain” for more details).
A proper anti-aliasing filter must be placed at the ADC
inputs. This will attenuate the frequency contents
around DMCLK and keep the desired accuracy over
the baseband (DRCLK) of the converter.
This anti-aliasing filter can be a simple first-order RC
network with low time constant, which will provide a
high rejection at the DMCLK frequency (see Figure 5-6
TABLE 5-3:
DELTA-SIGMA ADC GAIN SETTINGS
Total Gain
(V/V)
Analog Gain
(V/V)
0
0
GAIN[2:0]
Digital Gain
(V/V)
Total Gain
(dB)
VIN Range (V)
0.333
0.333
1
-9.5
0
0
1
1
1
1
0
±VREF
2
2
1
6
±VREF/2
0
1
1
4
4
1
12
±VREF/4
8
8
1
18
±VREF/8
1
16
16
1
24
±VREF/16
32
16
2
30
±VREF/32
1
64
16
4
36
±VREF/64
0
0
1
1
1
1
0
1
0
0
1
1
0
0
2020-2021 Microchip Technology Inc.
±Min (AVDD, 3 * VREF)
DS20006401C-page 39
MCP3565R
5.3.1
ANALOG GAIN
The gain settings, from 0.33x to 16x, are done in the
analog domain. This analog gain is placed on each
ADC differential input. Each doubling of the gain
improves the thermal noise due to sampling by
approximately 3 dB, which means the lowest noise configuration is obtained when using the highest analog
gain. The SNR, however, is degraded, since doubling
the gain factor reduces the maximum allowable input
signal amplitude by approximately 6 dB.
If the gain is set to 0.33x, the differential input range
theoretically becomes ±3 * VREF. However, the device
does not support input voltages outside of the power
supply voltage range. If large reference voltages are
used with this gain, the input voltage range will be
clipped between AGND and AVDD; therefore, the output
code span will be limited. This gain is useful when the
reference voltage is small and when the input signal
voltage is large.
The analog gain stage can be used to amplify very low
signals, but the differential input range of the
Delta-Sigma modulator must not be exceeded.
5.3.2
DIGITAL GAIN
When the gain setting is chosen from 16x to 64x, the
analog gain stays constant at 16x, and the additional
gain is done in the digital domain by a simple shift and
round of the output code. The digital gain range is
between 1x and 4x.
The output noise is approximately unchanged (except
for the quantization noise, which is slightly decreased).
The SNR is thus degraded by 6 dB per octave from 16x
to 64x settings.
This digital gain is useful for scaling up the signals
without using the host device (MCU) operations, but
they degrade the SNR and resolution (one bit per
octave) and do not significantly improve the noise
performance, except for very large OSR settings.
5.4
5.4.1
Delta-Sigma Modulator
ARCHITECTURE
The Delta-Sigma ADC includes a second-order
modulator with a multibit DAC architecture. Its 5-level
quantizer is a Flash ADC composed of four comparators with equally spaced thresholds and a thermometer
output coding. The proprietary 5-level architecture
ensures minimum quantization noise at the outputs of
the modulators without disturbing the linearity or
inducing additional distortion.
Unlike most multibit DAC architectures, the 5-level
DAC used in this architecture is inherently linear;
therefore, it does not degrade the ADC linearity and
THD performance. The sampling frequency is DMCLK;
therefore, the modulator outputs are refreshed at a
DMCLK rate. Figure 5-2 represents a simplified block
diagram of the Delta-Sigma modulator.
DS20006401C-page 40
Delta-Sigma 2nd Order 5-Level Modulator
Quantizer
Differential Input
Voltage
(from Analog Mux)
Analog
2nd Order
Loop
Filter
4
5-Level Flash
ADC
Output
Bitstream
Thermometer Coding
(to Digital Filter)
5-Level DAC
Analog
FIGURE 5-2:
Block Diagram.
5.4.2
Digital
Simplified Delta-Sigma ADC
MODULATOR OUTPUT BLOCK
The modulator output option enables users to apply
their own digital filtering on the output bit stream. By
setting EN_MDAT = 1 in the IRQ register, the modulator output is available through the ADCDATA register
(0x0) with DMCLK rate. With this configuration, the
digital decimation filter is disabled in order to reduce
the current consumption and no data ready interrupt is
generated on any of the IRQ mechanisms.
Considering that the Delta-Sigma modulator has a
5-level output, given by the state of four comparators
with thermometer coding, the output is represented
using four bits, each bit representing the state of the
corresponding comparator (see Table 5-4). The modulator can be considered as a 5-level output at DMCLK
rate.
When CLK_SEL[1:0] = 11 (internal oscillator with
external clock output), the AMCLK clock is present on
the SCK pin. This configuration allows a correct
synchronization of the bit stream when the internal
oscillator is used as the master clock source.
When CLK_SEL[1:0] = 00, the modulator outputs are
also synchronized with the SCK input, but the ratio
between MCLK and AMCLK must to be taken into
account in the user applications to correctly retrieve the
desired bit stream.
TABLE 5-4:
DELTA-SIGMA MODULATOR
OUTPUT CODING
Modulator
MDAT
Equivalent
COMP[3:0]
Output Code ADCDATA
VREF
Code
(Decimal)
Value
Voltage
1111
+2
0111
+1
0001
-1
0011
0000
0
-2
1111
+VREF
0111
+VREF/2
0001
-VREF/2
0011
0000
0
-VREF
2020-2021 Microchip Technology Inc.
MCP3565R
tD OMD AT tD OMD AT tD OMD AT tD OMD AT tD OMD AT
AMCLK
increase the baseband of the input signals to be
converted. The digital gain (which is enabled at 32x
and 64x gains) has no influence on the achievable
bandwidth.
A typical dependency of the bandwidth depending on
the gain for each BOOST setting combination is shown
from Figure 2-35 to Figure 2-38. Typically, a larger gain
setting requires a higher BOOST setting in order to
achieve the same bandwidth performance.
MDAT
(code = +2)
Figure 2-43 shows the behavior of the achievable
bandwidth at BOOST = 1x with AVDD corner cases.
Since the BOOST settings vary, the internal slew rate
of the modulator components, using a lower VREF
value, will improve the bandwidth if low BOOST
settings are used and show a bandwidth behavior that
is too limited.
MDAT
(code = +1)
MDAT
(code = 0)
5.5
MDAT
(code = -1)
MDAT
(code = -2)
C OMP[3]
C OMP[2]
C OMP[1]
C OMP[0]
FIGURE 5-3:
MDAT Serial Outputs
Depending on the Modulator Output Code.
5.4.3
BOOST MODES
The Delta-Sigma modulator includes a programmable
biasing circuit in order to further adjust the power
consumption to the sampling speed applied through
the MCLK. This can be programmed through the
BOOST[1:0] bits in the CONFIG2 register. The
different BOOST settings are applied to the entire
modulator circuit, including the voltage reference
buffers. The settings of the BOOST[1:0] bits are
described in Table 5-5.
TABLE 5-5:
BOOST SETTINGS
DESCRIPTION
BOOST[1:0]
Bias Current
x0.5
00
01
10
x0.66
x1 (default)
11
x2
The maximum achievable Analog Master Clock
(AMCLK) speed, the maximum sampling frequency
(DMCLK) and the maximum achievable data rate
(DRCLK) are highly dependent on the BOOST[1:0] and
GAIN[2:0] bits setting. A higher BOOST setting allows
the circuit’s bandwidth to be increased and allows a
higher analog master clock rate, which will then
2020-2021 Microchip Technology Inc.
Digital Decimation Filter
The decimation filter decimates the output bit stream of
the modulator to produce 24-bit ADC output data. The
decimation filter present in the device is a cascade of
two filters: a third-order sinc filter with a decimation
ratio of OSR3 (third order moving an average of
3 x OSR3 values), followed by a first-order sinc filter
with a decimation ratio of OSR1, moving an average of
OSR values (third order moving average of 3 x OSR3
values).
Figure 5-4 represents the decimation filter architecture.
OSR 1 = 1
Modulator
Output
(Thermometer
Coding)
SINC 3
SINC 1
OSR 3
OSR 1
4
Decimation
Filter
Output
ADC
Resolution
Decimation Filter
FIGURE 5-4:
Diagram.
Decimation Filter Block
Equation 5-3 is the transfer function of the decimation
filter:
EQUATION 5-3:
FILTER TRANSFER
FUNCTION
3
1 – z -OSR 3
1 – z -OSR 1 OSR 3
H z = -------------------------------------------- -----------------------------------------------------3
–
1
OSR
–
OSR 3 1 – z
3
OSR 1 1 – z
Where:
2 fj
z = exp ----------------------
DMCLK
DS20006401C-page 41
MCP3565R
The resolution (number of possible output codes
expressed in powers of two or in bits) of the digital
filter is 24-bit maximum for any OSR = OSR3 x OSR1
and data format choice. The resolution only depends
on the OSR through the OSR[3:0] bits setting in the
CONFIG1 register per Table 5-6. Once the OSR is
chosen, the resolution is fixed and the output code of
the ADC is encoded with the data format defined by
the DATA_FORMAT[1:0] bits setting in the CONFIG3
register.
In One-Shot mode, each conversion is launched
individually, so the maximum data rate is effectively
1/TCONV if each conversion is launched with no delay.
The digital filter is reset in between each conversion.
However, due to the nature of the digital filter (which
memorizes the sum of the incoming bit stream), the
data rate at the filter output can be maximized if the
filter is never reset. Because of the internal resampling
of the digital filter, the output data rate can be equal to
DMCLK/OSR = DRCLK; this is the case in Continuous
mode. In this case, the first conversion still happens in
the TCONV time, as this is the settling time of the filter.
The subsequent conversions are pipelined and give
their output at a data rate of DRCLK. The Continuous
Conversion mode can optimize the data rate, while
consuming the same power as One-Shot mode, which
is advantageous in applications that require a
continuous sampling of the analog inputs. The
Continuous mode is not compatible with multiplexing
the inputs (see Section 5.15 “Scan Mode” for more
details about the Conversion mode settings in MUX
and Scan modes).
The transfer function of this filter has a unity gain at
each multiple of DMCLK. A proper anti-aliasing filter
must be placed at the ADC inputs. This will attenuate
the frequency contents around each multiple of
DMCLK and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a
simple first-order RC network with low time constant to
provide a high rejection at DMCLK frequency.
The conversion time is a function of the OSR settings
and the DMCLK frequency.
EQUATION 5-4:
CONVERSION TIME FOR
OSR = OSR3 x OSR1
Figure 5-5 shows the fundamental difference between
One-Shot mode and Continuous mode in a simplified
diagram.
T CONV = 3 OSR 3 + OSR 1 – 1 OSR 3 DMCLK
Analog Input
Signal
One-shot mode
Conversions are Serialized,
Filter is Reset after Each Conversion
Group Delay: TCONV
Data Rate: 1/(TCONV)
Conversion1
Conversion2
Conversion3
TCON V
TCONV
TCONV
Conversion1
TCONV= Settling Time
Continuous mode
Conversions are Pipelined,
Filter is Never Reset
Group Delay: TCONV
Data Rate: DRCLK
1/DRCLK
1/DRCLK
Conversion2
TCONV
C onversion3
TCONV
FIGURE 5-5:
DS20006401C-page 42
One-Shot Mode vs. Continuous Mode.
2020-2021 Microchip Technology Inc.
MCP3565R
Since the converter is effectively doing two conversions
when the AZ_MUX bit is enabled, the conversion time
is equal to 2 * TCONV in this mode. As described in
Section 5.1.3 “ADC Offset Cancellation Algorithm”,
this selection is not compatible with the Continuous
Conversion mode; therefore, the output data rate is
equal to 1/(2 * TCONV) in this mode.
Table 5-6 summarizes the possible filter settings and
their associated Conversion Time, TCONV, as well as
their output data rate (DRCLK) in Continuous mode.
When OSR is larger than 20480 for typical master clock
frequency, MCLK = 4.9152 MHz, the device includes
an additional 50/60 Hz rejection by aligning decimation
TABLE 5-6:
OSR[3:0]
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
filter notches with a multiple of 50/60 Hz depending on
the OSR setting. The rejection band strongly depends
on the master clock accuracy and corresponds to a
first-order decimation filter rejection rate.
The high OSR settings can be used for applications
requiring very low noise and slow data rates.
Figure 5-6 shows the frequency response of the
decimation filter with default settings. Figure 5-7
represents the frequency response of the filter with the
highest OSR settings and a line rejection at 60 Hz.
OVERSAMPLING RATIO AND SINC FILTER RELATIONSHIP
OSR3
OSR1
Total
OSR
ADC Resolution
in Bits
(No Missing
Codes)
Conversion
Time
(TCONV)
Data Rate in Continuous
Conversion Mode
Data Rate (Hz)
with
MCLK = 4.9152 MHz
Fastest Data Rate (Hz)
with
MCLK = 19.6608 MHz
153600
32
1
32
16
96/DMCLK
38400
64
1
64
19
192/DMCLK
19200
76800
128
1
128
22
384/DMCLK
9600
38400
256
1
256
24
768/DMCLK
4800
19200
512
1
512
24
1536/DMCLK
2400
9600
512
2
1024
24
2048/DMCLK
1200
4800
512
4
2048
24
3072/DMCLK
600
2400
512
8
4096
24
5120/DMCLK
300
1200
600
512
16
8192
24
9216/DMCLK
150
512
32
16384
24
17408/DMCLK
75
300
512
40
20480
24
21504/DMCLK
60
240
512
48
24576
24
25600/DMCLK
50
200
512
80
40960
24
41984/DMCLK
30
120
512
96
49152
24
50176/DMCLK
25
100
512
160
81920
24
82944/DMCLK
15
60
512
192
98304
24
99328/DMCLK
12.5
50
2020-2021 Microchip Technology Inc.
DS20006401C-page 43
MCP3565R
FIGURE 5-6:
Decimation Filter Frequency Response (OSR = 256, PRE = 1:1, MCLK = 4.9152 MHz).
FIGURE 5-7:
Decimation Filter Frequency Response (OSR = 81920, PRE = 1:1,
MCLK = 4.9152 MHz).
DS20006401C-page 44
2020-2021 Microchip Technology Inc.
MCP3565R
5.6
ADC Output Data Format
The ADC Output Data (ADCDATA) register is located at
the address: 0x0. The default length of the register is
24-bit (23-bit + sign).
Output data are calculated in the digital decimation
filter with a much larger resolution and rounded to the
closest LSb value.
The rounding ensures a maximum 1/2 LSb error
instead of a simple truncation that ensures a 1 LSb
maximum error.
Equation 5-5 calculates the ADC output code as a
function of the input and reference signals for DC
inputs.
For AC sine wave inputs, the decimation filter transfer
function (see Equation 5-3) induces an additional gain
on the ADC output code, which depends on the input
frequency (roll-off of the decimation filter).
When DATA_FORMAT[1:0] = 0x, the ADC data are
represented on 24 bits (23-bit plus sign). The ADC
output code is represented with MSb first signed two’s
complement coding. With these two data formats, the
coding does not allow overrange; the equivalent analog
input range is [-VREF; +VREF – 1 LSb]. When
VIN * Gain > VREF – 1 LSb, the 24-bit ADC code
(SGN+DATA[22:0]) will saturate and be locked at
0x7FFFFF. When VIN * Gain < -VREF, the 24-bit ADC
code will saturate and be locked at 0x800000. Using
these data formats does not permit correctly evaluating
full-scale errors in case of a positive full-scale error.
When DATA_FORMAT[1:0] = 00, the output register
shows
only
the
24-bit
value.
When
DATA_FORMAT[1:0] = 01, the output register is 32 bits
long and the output code is padded with additional
zeros on the last byte. The output code is left justified
in this case. This format is useful for 32-bit MCU
applications.
For any inputs, the VIN+/VIN- voltages are averaged out
during the whole conversion time as the ADC is an
oversampling converter.
ADC output format is set by the DATA_FORMAT[1:0]
bits in the CONFIG3 register. These bits define four
different possible formats for the ADC Data Output
register: three 32-bit formats and one 24-bit format for
the MCP3565R.
Figure 5-8 describes all possible data formats.
EQUATION 5-5:
ADC OUTPUT CODE FOR DC INPUT (DATA_FORMAT[1:0] = 00)
V IN+ – V IN-
ADC_OUTPUT(LSb) = ----------------------------------------- 8,388,608 GAIN
V REF+ – V REF-
00
SGN + DATA[22:0]
SGN+ DATA[22:0]
01
0x00
10
SGN ext (8-bit)
DATA[23:0]
11
CH_ID[3:0] SGN ext (4-bit)
DATA[23:0]
FIGURE 5-8:
ADC Output Format Selection.
2020-2021 Microchip Technology Inc.
DS20006401C-page 45
MCP3565R
When DATA_FORMAT[1:0] = 1x, the ADC data are
represented on 25 bits. For these two data formats, the
output register is 32 bits long. With these two data
formats, the coding allows overrange; the equivalent
analog input range is [-2 x VREF, +2 x VREF – 1 LSb].
When VIN * Gain > 2VREF – 1 LSb, the 25-bit ADC code
(SGN+DATA[23:0]) will saturate and be locked at
0x0FFFFFF. When VIN * Gain < -2VREF, the 24-bit ADC
code will saturate and be locked at 0x1000000. Using
these data formats allows a correct evaluation of the
full-scale errors in case of a positive full-scale error,
since they allow inputs that can be greater than VREF or
less than -VREF.
The ADC accuracy is not maintained on the full
extended [-2 x VREF, +2 x VREF – 1 LSb] range, but only
on a smaller range, which is approximately equal to
±1.05 x VREF. This overrange can be useful in high-side
measurements and gain error cancellation algorithms.
The overrange-capable formatting on 25 bits is fully
compatible with the standard code locked formatting on
24 bits; both coding formats will produce the same
TABLE 5-7:
When DATA_FORMAT[1:0] = 10, the 25-bit
(24-bit + SGN) value is right justified. The first byte of
the 32-bit ADC output code will repeat the Sign bit
(SGN).
In DATA_FORMAT[1:0] = 11, the output code is similar
to the one in DATA_FORMAT[1:0] = 10. The only difference resides in the four MSbs of the first byte, which
are no longer repeats of the Sign bit (SGN). They are
the Channel ID data (CH_ID[3:0]) that are defined in
Table 5-15. This CH_ID[3:0] word can be used to verify
that the right channel has been converted to Scan
mode and can serve easy data retrieval and logging
(see Section 5.15 “Scan Mode” for more details
about the Scan mode). In MUX mode, this 4-bit word is
defaulted to ‘0000’ and does not vary with the
MUX[7:0] selection. This format is useful for 32-bit
MCU applications.
DATA_FORMAT[1:0] = 0x (24-BIT CODING)
Equivalent Input Voltage
> VREF – 1 LSb
VREF – 2 LSbs
ADC Output Code (SGN + DATA[22:0])
Hexadecimal
Decimal
011111111111111111111111
0x7FFFFF
+8388607
0x7FFFFE
+8388606
000000000000000000000001
0x000001
+1
0x000000
0
111111111111111111111111
0xFFFFFF
-1
011111111111111111111110
1 LSb
0
000000000000000000000000
-1 LSb
-VREF + 1 LSb
100000000000000000000001
< -VREF
TABLE 5-8:
24-bit codes for the [-VREF; +VREF – 1 LSb] range and
the MSb on the 25-bit coding can be considered as a
simple Sign bit extension.
100000000000000000000000
DATA_FORMAT[1:0] = 1x (25-BIT CODING)
Equivalent Input Voltage
> 2 VREF – 1 LSb
2 VREF – 2 LSbs
VREF + 1 LSb
VREF
VREF – 1 LSb
VREF – 2 LSbs
1 LSb
0
-1 LSb
-VREF + 1 LSb
-VREF
-VREF – 1 LSb
-2 VREF + 1 LSb
< -2 VREF
DS20006401C-page 46
ADC Output Code (SGN + DATA[21:0])
0xFFFFFF
-8388607
0x800000
-8388608
Hexadecimal
Decimal
0x0FFFFFF
+16777215
0111111111111111111111110
0x0FFFFFE
+16777214
0x0800001
+8388609
0100000000000000000000000
0x0800000
+8388608
0111111111111111111111111
0100000000000000000000001
0x07FFFFF
+8388607
0011111111111111111111110
0x07FFFFE
+8388606
0000000000000000000000001
0x0000001
+1
0000000000000000000000000
0x0000000
0
1111111111111111111111111
0x1FFFFFF
-1
0x1800001
-8388607
0011111111111111111111111
1100000000000000000000001
0x1800000
-8388608
1011111111111111111111111
0x17FFFFF
-8388609
0x1000001
-16777215
1000000000000000000000000
0x1000000
-16777216
1100000000000000000000000
1000000000000000000000001
2020-2021 Microchip Technology Inc.
MCP3565R
5.7
Internal/External Voltage
Reference
5.7.1
VOLTAGE REFERENCE
SELECTION
The voltage reference selection for the ADC is
controlled by the VREF_SEL bit in the CONFIG0
register, as shown in Table 5-9.
TABLE 5-9:
The REFIN- pin is set as an input, directly connected to
the VREF- input of the ADC. For a better noise
immunity, it is recommended to connect this pin to
AGND externally when a single-ended voltage
reference is used. Figure 6-10 shows more details of
the reference selection and reference pins connections.
ADC VOLTAGE REFERENCE SELECTION
VREF_SEL
Reference Input/Output Pins
Description
REFIN- Pin
REFIN+/OUT Pin
0
External reference selected.
Internal reference buffer is
shut down.
Internal reference is only
generating the internal 1.2V
Common-mode voltage for the
ADC.
VREF- Input
VREF+ Input
1
Internal reference selected with
2.4V buffered output.
VREF- Input
(should be tied to AGND)
Internal reference with 2.4V
buffered output
REFINPAD
ADC VREFInput
REFIN+/OUT
PAD
ADC VREF+
Input
Chopped at DMCLK rate if AZ_VREF=1
VREF_SEL=0 Off
VREF_SEL=1 On
VREF_SEL
2x
+
VREF Buffer
1x
ADC Internal
VCM Voltage
+
Internal
Bandgap
Voltage
FIGURE 5-9:
+
-
1.2V
VCM Buffer
Voltage Reference Selection Schematic.
2020-2021 Microchip Technology Inc.
DS20006401C-page 47
MCP3565R
When VREF_SEL = 0, the reference voltage is set to
External mode. The REFIN+/OUT pin becomes an
input. In this case, the REFIN+/OUT pad is directly tied
to the VREF+ input of the ADC. There is no input buffer
in the differential input voltage reference path in this
mode, so the external voltage reference should include
a buffer to be able to charge the internal voltage
reference sampling capacitors.
When VREF_SEL = 1, the REFIN+/OUT is internally
buffered to produce a 2.4V buffered reference voltage
at the VREF+ input of the ADC. Section 5.7.2 “Internal
Voltage Reference Buffer” details the architecture of
the voltage reference buffer.
In this mode, the REFIN+/OUT pin becomes an output
and the reference voltage is generated internally.
The structure of the internal voltage reference is based
on a band gap voltage reference source, giving a 1.2V
output directly connected to a low noise chopper buffer,
configured with a gain of 2x, to give a 2.4V output on
the REFIN+/OUT pad. The internal reference has a
very low typical temperature coefficient of 15 ppm/°C
for extended temperature range and 9 ppm/°C for
industrial temperature range, allowing the ADC output
codes to have the least variation corresponding to the
temperature ranges, since they are proportional to
(1/VREF).
5.7.2
INTERNAL VOLTAGE REFERENCE
BUFFER
When VREF_SEL = 1, the voltage reference buffer is
enabled. It is only powered on when the ADC state is in
Reset or in Conversion mode and is powered off in
Shutdown mode.
The buffer is designed to be able to drive the ADC
reference input that is sampling the reference voltage.
The REFIN- pin is not buffered and is connected
directly to the ADC inverting voltage reference input
(VREF-).
The offset induced by the buffer may slightly vary
between the two possible gain selections, as well as its
temperature dependency and bandwidth; therefore, it
has to be characterized separately. The buffer injects a
certain quantity of 1/f noise into the system that can be
modulated with the incoming input signals and can limit
the SNR performance at higher OSR values
(OSR > 256).
To overcome this limitation, the buffer includes an
auto-zeroing algorithm that greatly reduces (cancels
out) the 1/f noise and cancels the offset value of the
reference buffer. As a result, the SNR of the system is
not affected by this 1/f noise component of the
reference buffer, even at maximum OSR values. This
auto-zeroing algorithm is performed synchronously
with the DMCLK and can be enabled or disabled with
the AZ_VREF bit setting in the CONFIG2 register.
When AZ_VREF = 1 (default), the auto-zeroing is
enabled, which cancels out the 1/f noise and improves
the SNR, while not impacting the THD performance.
This mode is recommended for higher OSR values
(OSR > 256).
When AZ_VREF = 0, the reference auto-zeroing
algorithm is disabled. This setting should be reserved
for lower OSR values, where higher ADC speed is
more important than accuracy.
If the application is susceptible to high-frequency noise,
using AZ_VREF = 0 or a proper low-pass filter at the
VREF output pin (to filter out the chopper frequency
components from the buffered output) is recommended.
DS20006401C-page 48
2020-2021 Microchip Technology Inc.
MCP3565R
5.8
Power-on Reset
operation stops when any of the falling thresholds of
the two POR monitoring circuits is crossed. Figure 5-10
illustrates the power-up and power-down sequences.
The analog and digital power supplies are monitored
separately by two Power-on Reset (POR) monitoring
circuits at all times, except during Full Shutdown mode
(see Section 5.10, Low-Power Shutdown Modes).
If the CS pin is kept logic low during a POR state, a
logic high pulse is necessary to start the first communication sequence after power-up. The CS rising edge
will reset the SPI interface properly.
Each POR circuit has two separate thresholds, one for
the rising voltage supply and one for the falling voltage
supply. They both include hysteresis (the rising
threshold is superior), so that the device is tolerant to a
certain degree of transient noise on each power supply.
The DVDD and AVDD monitoring thresholds are different
since their respective voltage ranges are different. The
AVDD rising threshold is approximately 1.75V ±10% and
the DVDD is 1.2V ±10%. The hysteresis is approximately
150 mV (typical).
If any of the two power supply voltages is below its
respective threshold, the POR state is forced internally.
In this state, the SPI interface is disabled, no command
can be executed by the chip. All registers are cleared
and set to their default values.
Proper decoupling ceramic capacitors (0.1 µF and
10 µF ceramic) should be placed as close as possible
to the power supply pins (AVDD, DVDD) to provide
additional transient immunity.
At power-up, when both power supply voltages are
above the rising thresholds, the device powers up, and
the SPI interface is enabled and can handle communications. Since both thresholds need to be crossed for
the power-up, the power-up sequence is not important
and any power supply voltage can ramp up first. The
detection time for the monitoring circuits (tPOR) is about
1 µs for relatively fast power-up ramp rates. The normal
During Full Shutdown mode, the power supply voltages
are not monitored to be able to reach ultra-low power
consumption. The device cannot generate a POR
event interrupt in this mode, except for cases of
extremely low-power supply voltages. See
Section 5.10.1 “Full Shutdown Mode”.
In order to ensure a proper power-up sequence, the
ramp rate of DVDD must not exceed 3 V/µs when
coming out of the POR state.
Voltage
(AVDD, DV DD)
POR Threshold Up
POR Threshold Down
tPOR
Time
POR State
FIGURE 5-10:
Normal Operation
POR State
Power-on Reset Timing Diagram.
2020-2021 Microchip Technology Inc.
DS20006401C-page 49
MCP3565R
5.9
ADC Operating Modes
The ADC can be placed into three different operating
modes: ADC Shutdown, Standby and Conversion. The
ADC operating mode is controlled by the user through
the ADC_MODE[1:0] bits in the CONFIG0 register. The
user can directly launch conversions or place the ADC
into ADC Shutdown or Standby mode by writing these
bits. Additional Fast commands are available for each
of the three possible states of these bits to allow faster
programming in case of time-sensitive applications
(see Section 6.2.4 “Command-Type Bits (CMD[1:0])”).
Table 5-10 describes the available ADC_MODE[1:0]
bits setting.
The ADC_MODE[1:0] bits do not give an instantaneous
representation of the ADC state. Writing the
ADC_MODE[1:0] bits sets the desired state of the
ADC, but this state is only attained after a start-up time
depending on the current state of the ADC (see
Section 5.11 “ADC Start-up Timer” for details about
the start-up timer). Typically, the device starts in ADC
Shutdown mode after a POR (ADC_MODE[1:0] = 00
by default). To launch conversions in the desired
configuration, the user should program the part in the
desired
configuration
and
then
set
the
ADC_MODE[1:0] bits to ‘11’. In this case, the first
conversion will start after TADC_SETUP = 256 DMCLK
periods. This time is necessary for the part to adjust to
the new programmed settings and settle in to its
operating point to accurately convert the input signals.
Internally, the device tracks the current state of the
ADC, as well as the start-up timer counter, to be able to
optimize the start-up time depending on the desired
transitions and internal configurations required, and set
by the user.
TABLE 5-10:
In MUX mode, overwriting the ADC_MODE[1:0] bits to
‘11’ when the ADC is already in conversion resets and
restarts the current conversion immediately.
In Scan mode (see Section 5.15 “Scan Mode”),
writing the ADC_MODE[1:0] bits to ‘11’ starts the
conversion Scan cycle. During the complete cycle,
even when the Scan timer is enabled, reading the
ADC_MODE[1:0] bits gives a ‘11’ code output,
meaning that the Scan cycle is ongoing. Rewriting
ADC_MODE[1:0] = 11 during Scan mode will immediately reset and restart the entire Scan sequence from
the beginning of the sequence. The restart of the Scan
sequence may induce a TADC_SETUP additional delay if
the ADC is in ADC Shutdown mode when the
ADC_MODE bits are overwritten (this can happen if the
ADC_MODE bits are overwritten during the timer delay
period, where the ADC is placed into ADC Shutdown
mode in between two Scan cycles).
The ADCDATA register is always updated with the last
conversion results. The ADCDATA register cannot
provide incomplete conversion results. The A/D
conversion must be completed to be able to provide a
result in the ADCDATA register. Each end of
conversion generates a data ready interrupt on both
IRQ mechanisms (see Section 6.8.1 “Conversion
Data Ready (DR) Interrupt”). The ADCDATA register
is never cleared when the device transitions from one
mode to another. The only way to clear the ADCDATA
register is a POR event or a Full Reset Fast command
(see Section 6.2.5, Fast Commands Description).
Note:
Since there is no IRQ pin, the IRQ
mechanisms are the STATUS byte and
IRQ register bits.
ADC OPERATING MODES DESCRIPTION
ADC_MODE[1:0]
ADC Mode
Description
11
Conversion
The ADC is placed into Conversion mode and consumes the specified
current. A/D conversions can be reset and restarted immediately once this
mode is effectively reached. This mode may be reached after a maximum of
TADC_SETUP time, depending of the current state of the ADC.
10
Standby
Conversions are stopped. ADC is placed into Reset but consumes almost
as much current as in Conversion mode. A/D conversions can start
immediately once this mode is effectively reached. This mode may be
reached after a maximum of TADC_SETUP time, depending of the current
state of the ADC.
0x
ADC Shutdown
Conversions are stopped. ADC is placed into ADC Shutdown mode and
does not consume any current. A/D conversions can only start after
TADC_SETUP start-up time. This mode is effective immediately after being
programmed.
DS20006401C-page 50
2020-2021 Microchip Technology Inc.
MCP3565R
5.10
Low-Power Shutdown Modes
The device incorporates two low-power modes that can
be activated in order to limit power consumption of the
device when ADC is not used. These two modes are
called Partial Shutdown and Full Shutdown modes.
5.10.1
FULL SHUTDOWN MODE
The Full Shutdown mode can only be enabled by
sending a Fast Command Full Shutdown (Fast
Command code: ‘1101’). Note that the execution of this
Fast command forces the CONFIG0 to be set to 0x00
(no active block is enabled).
Full Shutdown mode is the lowest power mode of the
device. None of the circuits consuming static power are
active in this mode.
As stated in Section 5.8 “Power-on Reset”, the
AVDD/DVDD POR monitoring circuits are not active
while in Full Shutdown mode.
Note:
If the digital power supply resides for a long
time period below the POR threshold and
to a sufficiently low voltage (typically below
0.6V), some bits previously set to ‘1’ can
toggle to ‘0’ and not be set properly.
In order to ensure a safe operation after
the Full Shutdown mode, follow the
sequence of commands:
- Write LOCK register to 0xA5
- Write IRQ register to 0x07
- Send a Fast CMD Full Reset (‘1110’)
- Reconfigure the chip as desired
This sequence ensures a recovery with
the desired settings in any loss-of-power
scenario.
TABLE 5-11:
Device
Low-Power Mode
The part can still be accessed through the SPI interface
during this mode and will accept incoming SPI
commands. The ADCDATA register is not cleared during
Full Shutdown mode and still holds previous conversion
results. The other register settings are not modified or
reset due to entering Full Shutdown mode.
The Full Shutdown mode stops all internal timers and
resets them. Sending a Fast CMD to change the
operating mode exits the Full Shutdown mode.
The user should place all digital inputs to a static value
(logic low or high) in order to optimize power consumption during Full Shutdown mode. The current
consumption specifications during Full Shutdown
mode are intended without any digital pin toggling
during the measurement. In this case, only leakage
current is consumed throughout the device and this
current varies exponentially with respect to absolute
temperature.
5.10.2
PARTIAL SHUTDOWN MODE
Partial Shutdown mode is achieved when CONFIG0 is
set to ‘0000000x’. In this mode, most of the internal
circuits are shut down, with the exception of the POR
monitoring and internal biasing circuits. During the
Partial Shutdown mode, the power supply is continuously monitored, whereas in Full Shutdown mode, the
POR monitoring circuits are powered down. The power
consumption is also much higher in Partial Shutdown
mode due to the POR monitoring circuits being active.
Partial Shutdown mode allows the device to be restarted
and put back in Conversion mode faster than Full
Shutdown mode. Table 5-11 describes the differences
between Partial and Full Shutdown modes. If the current
consumption of Partial Shutdown mode is acceptable for
the application, it is recommended that it is used as an
alternative to Full Shutdown mode, where the POR
monitoring circuits are shut down and no longer monitoring the AVDD and DVDD power supplies.
LOW-POWER MODES(1)
VREF_SEL
CONFIG0[6]
Partial Shutdown
0
0
00
00
0x
All peripherals, except the
POR monitoring circuits and
clock biasing circuits, are shut
down and consume no static
current.The SPI interface
remains active in this mode
and consumes no current
while the bus is Idle.
Full Shutdown
0
0
00
00
00
All analog and digital circuits
are shut down and consume
no static current. The SPI
interface remains active in
this mode and consumes no
current while the bus is Idle.
Note 1:
CLK_SEL[1:0] CS_SEL[1:0] ADC_MODE[1:0]
Description
x = Do not care
2020-2021 Microchip Technology Inc.
DS20006401C-page 51
MCP3565R
5.11
ADC Start-up Timer
The device includes an intelligent start-up timer circuit
for the ADC, which ensures that the ADC is properly
biased and that internal nodes are properly settled
before each conversion. This timer ensures the proper
conditions for the ADC to convert with its full accuracy
for each conversion.
The ADC can operate in three different modes: ADC
Shutdown, Standby and Conversion, as described in
Section 5.9 “ADC Operating Modes”. The ADC
start-up timer manages the time for the transitions
between each mode. These transitions can be
instantaneous or can take a maximum of 256 DMCLK
periods, depending on the type of transition and the
current status of the ADC and of the internal start-up timer.
The timer will always try to reduce the transition time
from one state to another, but will also allow enough
time for the internal circuitry to settle to the proper
internal operating points.
The transitions from Standby or Conversion mode to
ADC Shutdown mode are always immediate. They
reset the internal start-up timer to 256 DMCLK periods
(TADC_SETUP).
The transitions from ADC Shutdown to Standby or
Conversion mode start the internal start-up timer that
decrements from 256 to 0. The timer only decrements
after a small delay of two MCLK periods in case of a
transition caused by an SPI command. This small delay
is necessary to overcome any possible synchronization
issue between the two asynchronous clocks: MCLK
and SCK. The timer will immediately decrement
(without the synchronization delay) if the transitions are
generated by the internal state machine (for example,
when the transitions are generated by the Scan
sequence). Once the timer reaches 0 (when the user
has clocked 256 DMCLK periods), the device reaches
its internal proper operating points and will either stay
in Standby mode (if ADC_MODE[1:0] = 10) or start the
Conversion mode (if ADC_MODE[1:0] = 11).
The transition from Standby to Conversion mode and
vice versa is immediate once the timer has reached 0 (if
ADC_MODE[1:0] = 11). If the transition from Standby to
TABLE 5-12:
Conversion mode occurs, and if the timer has not yet
reached 0, the timer will continue to decrement to 0
before effectively starting the conversion. The timer
cannot decrement faster than 256 DMCLK periods when
the ADC transitions from ADC Shutdown mode to
Conversion mode (from ADC Shutdown mode, the ADC
is allowed 256 DMCLK periods to power-up and settle to
its desired operating point before starting conversions).
The start-up time has been sized at 256 DMCLK clock
periods for the part to be able to settle in all conditions
and with all possible clock frequencies as specified.
Table 5-12 summarizes the behavior of the internal
start-up timer as a function of the ADC_MODE[1:0] bits
setting.
Rewriting the ADC_MODE[1:0] bits without changing
the bit settings does not modify the internal timer and
cannot shorten the start-up delay necessary to start
accurate conversions. A synchronization delay of
two MCLK periods occurs after each rewrite if
ADC_MODE[1:0] = 1x.
In Scan mode, when CONV_MODE[1:0] = 11 (Continuous mode), the ADC may be placed in ADC Shutdown
mode and restarted in between each Scan cycle
depending on the TIMER[23:0] bits setting (see
Section 5.15.5 “Delay Between Scan Cycles
(TIMER[23:0])”). If the TIMER register is programmed
with a decimal code greater than TADC_SETUP = 256,
the internal timer will automatically place the part in
ADC Shutdown mode at the end of the cycle and will
start to transition to the next cycle 256 DMCLK periods
before the end of the timer delay.
This lowers the power consumed during the timer delay
as much as possible. If the value of the timer delay is less
than 256 DMCLK periods, the part will not enter ADC
Shutdown mode and will stay in Standby during the timer
delay (in this case, the power consumed is equivalent to
the Conversion mode power consumption).
Figure 5-11 shows different cases of transitions
between modes and shows the internal state of the
start-up timer for each step.
ADC START-UP TIMER BEHAVIOR AS A FUNCTION OF ADC_MODE[1:0] SETTINGS
ADC_MODE[1:0]
ADC State
11
Conversion
10
Standby
0x
ADC Shutdown
DS20006401C-page 52
ADC Start-up Timer Behavior
The ADC start-up timer decrements to 0. The conversion
starts when it reaches 0.
The ADC start-up timer decrements to 0. The ADC is ready to
convert when it reaches 0.
ADC start-up timer is reset to TADC_SETUP = 256.
2020-2021 Microchip Technology Inc.
MCP3565R
DMCLK
Continuous Clocking
SPI
Wri te
Wri te
Write
AD C _M ODE = 1x
ADC _M ODE = 0x
AD C_M ODE = 1x
0x
1x
0x
1x
Timer Reset
Switching Between ADC_MODE = 10 and 11
has no Effect on the Timer
ADC_MODE
Timer Reset
ADC Start-up
Timer Decimal
Code
Timer
Countdown
Wri te
1X
AD C _M ODE = 1x
256
ADC Ready to Convert
0
FIGURE 5-11:
5.12
ADC Start-up Timer Timing Diagram.
Master Clock Selection/Internal
Oscillator
The device includes three possible clock modes for the
master clock generation. The Master Clock (MCLK) is
used by the ADC to perform conversions and is also used
by the digital portion to generate the different digital
timers. The clock mode selection is made through the
CLK_SEL[1:0] bits located in the CONFIG0 register. The
possible selections are described in Table 5-13.
The master clock is not propagated in the chip when the
chip enters the Full Shutdown mode (see Section 5.10
“Low-Power Shutdown Modes”). MCP3565R is a low
pin count device, targeted to applications requiring a
smaller PCB footprint, so there is no dedicated pin for the
MCLK input/output on this device. The SCK pin is used
for this function, on top of being used as the clock input
for the digital interface. SCK is always the clock input for
the digital interface at all times. Any change to the
CLK_SEL bits is following a specific sequence described
in Section 6.9 “Master Clock Input/Output Modes”.
Each reset and restart resets all internal phases to their
default values and can lead to a possible temporary duty
cycle change at the clock output pin.
TABLE 5-13:
CLOCK SELECTION BITS
CLK_SEL[1:0]
Clock Mode
00 or 01
SCK Pin
External clock
MCLK digital input
10
Internal RC
Oscillator,
no clock output
High-Z MCLK and SCK
are asynchronous
11
AMCLK is present as
Internal RC
Oscillator with clock an output on the SCK
pin
output
2020-2021 Microchip Technology Inc.
5.12.1
EXTERNAL MASTER CLOCK MODE
(CLK_SEL[1:0] = 0x)
The External Clock mode is used to input the MCLK
clock necessary for the ADC conversions and can
accept duty cycles with a large range, since the clock is
redivided internally to generate the different internal
phases.
The external clock can be provided on the SCK pin.
Therefore, the SCK pin in this mode has a dual functionality, as it is also the clock input pin for the digital
interface. In this mode, SCK = MCLK at all times and
the digital interface is synchronous with the master
clock. When running conversions, SCK has to be
continuously clocking at a constant frequency as it is
defined for the MCLK input to ensure proper ADC
accuracy. In this case, communications using the SPI
interface should be synchronized on this free-running
clock and can be framed with a proper usage of CS pin.
5.12.2
INTERNAL OSCILLATOR
The device includes an internal RC-type oscillator
powered by the digital power supply (DVDD/DGND). The
frequency of this internal oscillator ranges from
3.3 MHz to 6.6 MHz. The oscillator is not trimmed in
production; therefore, the precision of the center
frequency is approximately ±30% from chip to chip.
The duty cycle of the internal oscillator is centered
around 50% and varies very slightly from chip to chip.
The internal oscillator has no reset feature and keeps
running once selected.
DS20006401C-page 53
MCP3565R
5.12.3
INTERNAL MASTER CLOCK
MODES (CLK_SEL[1:0] = 1x)
When CLK_SEL[1] = 1, the internal oscillator is
selected and the master clock is generated internally.
The master clock generation is independent of the ADC
as the clock can still be generated, even if the ADC is
in ADC Shutdown mode. The internal oscillator is only
disabled when CLK_SEL[1:0] = 0x. The clock can be
distributed to the SCK pin depending on the
CLK_SEL[0] bit. When the clock output is selected
(CLK_SEL[0] = 1), the AMCLK clock derived from the
MCLK (AMCLK = MCLK/PRESCALE) is available on
the SCK pin. The AMCLK output can serve as the clock
pin to synchronize other MCP3565R devices that are
configured with CLK_SEL[1:0] = 00 or 01.
The AMCLK output is available on the SCK pin as soon
as the Write command (CLK_SEL[1:0] = 11) is
finished. Section 6.9 “Master Clock Input/Output
Modes” describes in detail the transitions from one
clock mode to another.
5.13
Digital System Offset and Gain
Calibrations
The MCP3565R device includes a digital calibration
feature for offset and gain errors. The calibration scheme
for offset error consists of the addition of a fixed offset
value to the ADC output code (ADCDATA at address:
0x0). The offset value added (OFFSETCAL) is determined in the OFFSETCAL register (address: 0x9). The
calibration scheme for gain error consists of the multiplication of a fixed gain value to the ADCDATA code. The
gain value (GAINCAL) multiplied is determined in the
GAINCAL register (address: 0xA).
The digital offset and gain calibration schemes are
enabled or disabled via the EN_OFFCAL and
EN_GAINCAL control bits of the CONFIG3 register.
When both calibration control bits are enabled
(EN_OFFCAL = EN_GAINCAL = 1), the ADCDATA
register is modified with the digital offset and gain
calibration schemes, as described in Equation 5-6.
When a calibration enable bit is off, its corresponding
register becomes a Don’t Care register and the
corresponding calibration is not performed.
EQUATION 5-6:
ADCDATA OUTPUT
AFTER DIGITAL GAIN
AND OFFSET ERROR
CALIBRATION
The calculations are performed internally with proper
management of overloading, so that the overload
detection is done on the output result only and not on
the intermediate results. A sufficient number of
additional overload bits is maintained and propagated
internally to overcome all possible overload and/or
overload recovery situations.
For example, if ADCDATA (pre-calibration) + OFFSETCAL
is out of bounds, but (ADCDATA (pre-calibration) +
OFFSETCAL) x GAINCAL is still in the right range
(possible with 0 < GAINCAL < 1), the result is not
saturated.
5.13.1
DIGITAL OFFSET ERROR
CALIBRATION
The Offset Calibration register (OFFSETCAL,
address: 0x9) is a signed MSb first, two’s complement
coding, 24-bit register that holds the digital offset
calibration value, OFFSETCAL. The OFFSETCAL
equivalent input voltage value is calculated with
Equation 5-7.
EQUATION 5-7:
OFFSETCAL
CALIBRATION VALUE
(EQUIVALENT INPUT
VOLTAGE)
OFFSETCAL (V) = VREF x (OFFSETCAL[23:0]
signed decimal code)/(8388608 x GAIN)
For the MCP3565R device, the offset calibration is
done by adding the OFFSETCAL[23:0] calibration
value to the ADCDATA code bit-by-bit.
The offset calibration value range in equivalent voltage
is [-VREF/GAIN; (+VREF – 1 LSb)/GAIN], which can
cancel any possible offset in the ADC but also in the
system. The offset calibration is realized with a simple
24-bit signed adder and is instantaneous (no pipeline
delay). Enabling the offset calibration will affect the
next conversion result; the conversion result already
held in the ADCDATA register (0x0) is not modified
when the EN_OFFCAL is set to ‘1’, but the next one
will take the offset calibration into account. Changing
the OFFSETCAL register to a new value will not affect
the current ADCDATA value, but the next one (after a
data ready interrupt) will take the new OFFSETCAL
value into account. Figure 5-12 presents the different
cases and their impact on the ADCDATA register and
the Data Ready Event.
ADCDATA (post-calibration) =
[ADCDATA (pre-calibration) + OFFSETCAL] x GAINCAL
DS20006401C-page 54
2020-2021 Microchip Technology Inc.
MCP3565R
SPI
ADC STATUS
Write
OFFSETCA L[23:0] = OFFSETCA L1
Write
EN_OFFCAL = 1
Write
OFFSETCAL[23:0] = OFFSETCA L2
Data 1 Conversion
Data 2 Conversion
Data 3 Conversion
Data 4 Conversion
DATA0
DATA1
DATA2+OFFSETCAL1
DATA3+OFFSETCAL2
Data Ready Event
ADCDATA
REGISTER VALUE
FIGURE 5-12:
5.13.2
ADC Output and Data Ready Event Behavior with Digital Offset Calibration Enabled.
DIGITAL GAIN ERROR
CALIBRATION
The Gain Error Calibration register (GAINCAL,
address: 0xA) is an unsigned 24-bit register that holds
the digital gain error calibration value, GAINCAL.
Equation 5-8 calculates the GAINCAL multiplier.
EQUATION 5-8:
GAINCAL CALIBRATION
VALUE (MULTIPLIER
VALUE)
GAINCAL (V/V) = (GAINCAL[23:0] unsigned decimal
code)/8388608
For the MCP3565R device, the gain error calibration is
done by multiplying the GAINCAL value to the ADC
output code.
The gain error calibration value range in equivalent
voltage is [0; 2-2-23], which can cancel any possible
gain error in the ADC and in the system. The gain
error calibration is made with a simple 24-bit
SPI
ADC STATUS
Write
GAINCAL[23:0] = GAINCAL1
Data 1 Conversion
Write
EN_GAINCAL = 1
add-and-shift circuit clocked on DMCLK, and induces
a pipeline delay of TGCAL = 23 DMCLK periods. This
pipeline delay acts as a delay on the data ready
interrupt position that is shifted by TGCAL = 23 DMCLK
periods.
During this delay, the converter can process the next
conversion, the delay does not shift the next conversion and does not change the Conversion Time,
TCONV. Enabling the gain error calibration will affect
the next conversion result; the conversion result
already held in the ADCDATA register (0x0) is not
modified when the EN_GAINCAL is set to ‘1’, but the
next one will take the offset calibration into account.
Changing the GAINCAL register to a new value will
not affect the current ADCDATA value, but the next
one (after a data ready interrupt) will take the new
GAINCAL value into account. Figure 5-13 shows the
different cases and their associated effects on the
ADCDATA register and the Data Ready Event.
Write
GAINCAL[23:0] = GAINCAL2
Data 2 Conversion
Data 3 Conversion
Data 4 Conversion
Data Ready Event
ADCDATA
DATA0
DATA1
DATA2 x GAINCAL2
TGCAL
FIGURE 5-13:
DATA3 x GAINCAL2
TGCAL
ADC Output and Data Ready Event Behavior with Digital Gain Error Calibration Enabled.
2020-2021 Microchip Technology Inc.
DS20006401C-page 55
MCP3565R
5.14
Conversion Modes
The ADC includes several conversion modes that can
be selected through the CONV_MODE[1:0] bits located
in the CONFIG3 register. The ADC behavior, with
respect to these bits, depends on whether the ADC is
in MUX or Scan mode. Table 5-14 summarizes the
possible configurations.
TABLE 5-14:
ADC CONVERSION MODES IN MUX OR SCAN MODES
CONV_MODE[1:0]
5.14.1
ADC Behavior (MUX Mode)
ADC Behavior
(Scan Mode)
ADC_MODE[1:0] Bits Setting
0x
Performs a one-shot conversion Performs one complete
and automatically returns to
Scan cycle and
ADC Shutdown mode.
automatically returns to
ADC Shutdown mode.
Returns to ‘0x’ after one
conversion (MUX mode) or one
Scan cycle (Scan mode).
10
Performs a one-shot conversion Performs one complete
and automatically returns to
Scan cycle and
Standby mode.
automatically returns to
Standby mode.
Returns to ‘10’ after one
conversion (MUX mode) or one
Scan cycle (Scan mode).
11
Performs continuous
conversions.
Stays at ‘11’.
CONVERSION MODES IN MUX
MODE
In MUX mode, the user can choose between one-shot
and continuous conversions.
A one-shot conversion is a single conversion and takes
a certain Conversion Time, TCONV (or 2 x TCONV when
AZ_MUX = 1; see Section 5.1.3 “ADC Offset Cancellation Algorithm”). Once this conversion is performed,
the part automatically returns to a Standby or ADC
Shutdown state, depending on the CONV_MODE[1:0]
bits setting. The Conversion mode determined by the
CONV_MODE[1:0] bits setting will also affect the state of
the ADC_MODE[1:0] bits, as described in Table 5-14.
The conversion can be preceded by a start-up time that
depends on the ADC state (see Section 5.11 “ADC
Start-up Timer”).
One-Shot mode is recommended for low-power, low
bandwidth applications, requiring a once in a while A/D
conversion.
Performs continuous
Scan cycles with
TIMER[23:0] bits delay
between each cycle.
In Continuous Conversion mode, the ADC is never
placed in Standby or ADC Shutdown mode and
converts continuously without any internal reset. In this
mode, the output data rate of the ADC is defined by
DRCLK (see Figure 5-5). The digital decimation filter
induces a pipeline or group delay of TCONV for the first
data ready and is structured to give a continuous
stream of data at the DRCLK rate after this first data
(the internal registers of the filter are never reset in this
mode, thus the decimation filter acts as a moving
average). Each data ready interrupt corresponds to a
valid and complete conversion that was processed
through the digital filter (the digital filter has no latency
in this respect). This mode allows a faster data rate
than the One-Shot mode, and is therefore, recommended for higher bandwidth applications. The pipeline delay should be carefully determined and adapted
to the user needs, especially in closed-loop,
low-latency applications. This mode is recommended
for applications requiring continuous sampling/averaging of the input signals. If AZ_MUX = 1, the Continuous
Conversion mode is replaced by a series of subsequent One-Shot mode conversions, with a reset in
between each conversion. This makes the group delay
equal to 2 x TCONV and the data rate equal to
1/(2 x TCONV).
Figure 5-14 and Figure 5-15 detail One-Shot and
Continuous Conversion modes for MUX mode.
DS20006401C-page 56
2020-2021 Microchip Technology Inc.
MCP3565R
tD ODR
SPI
MCLK
Write
CONV_MODE = 0X or 10
FIGURE 5-14:
SPI
MCLK
ADC_MODE
ADC STATUS
FIGURE 5-15:
Write
ADC_MODE = 11
Read ADC Dat a
Don’t care
Continuous clocking
Don’t care
00
11
0x or 10
Depending on CONV_MODE[1:0]
ADC_MODE
ADC STATUS
ADC data Read
can be performed during this time
Shutdown
Start-up
Conversion
TAD C_SETU P
T CON V
Shutdown or Reset
Depending on CONV_MODE[1:0]
MUX One-Shot Conversion Mode Timing Diagram.
Write
Write
CONV_MO DE = 11 ADC_MODE = 11
Read ADC
Data 1
Don’t care
Continuous clocking
00
11
Shutdown
Start-up
Data 1 Conversion
TADC_SE TUP
TCONV
Read ADC
Data 2
Data 2 Conversion Data 3 Conversion
1/DRCLK
1/DRCLK
MUX Continuous Conversion Mode Timing Diagram.
2020-2021 Microchip Technology Inc.
DS20006401C-page 57
MCP3565R
5.14.2
CONVERSION MODES IN SCAN
MODE
If CONV_MODE[1:0] = 11, the ADC runs in a Scan
Cycle mode with a TIMER[23:0] delay between cycles.
Writing the CONV_MODE[1:0] bits with the SPI interface within a conversion does not create an internal
reset. It is recommended not to wait for the end of a
conversion to change the CONV_MODE[1:0] bits to the
desired value, but to change to the desired value just
after the data are ready to avoid possible glitches.
Figure 5-16 and Figure 5-17, respectively, detail the
ADC timing behavior in One-Shot and Continuous
Conversion modes when configured for Scan mode,
with N channels chosen among 16 Scan possibilities.
In Scan mode, the device takes one conversion per
channel and multiplexes the input to the next channel
in the Scan sequence. Therefore, all conversions are
One-Shot mode conversions, no matter how the
CONV_MODE[1:0] bits are set. Each conversion takes
the same time, TCONV (or 2 x TCONV when AZ_MUX = 1;
see Section 5.1.3 “ADC Offset Cancellation Algorithm”), to be performed. If CONV_MODE[1:0] = 00,
01 or 10, the Scan cycle is executed once and then the
ADC is placed into Standby or ADC Shutdown mode.
SPI
Write
Write
CONV_MODE = 0X/10 ADC_MODE = 11
MCLK
Read ADC Dat a 1
Don’t care
ADC_MODE
Start-up Channel 1 Conversion Reset Channel 2 Conversion Reset
Channel N Conversion
(Last in Cycle)
TDLY_SCA N
T CONV
TADC_SE TUP
ADC_MODE
TCONV
TCONV
T DLY_SCA N
Shutdown or Reset
Depending on CONV_MO DE
SCAN One-Shot Conversion Mode Timing Diagram.
Write
Write
CONV_MO DE = 11 ADC_MODE = 11
MCLK
0X or 10
Depending on CONV_MO DE
11
Shutdown
FIGURE 5-16:
Read ADC Dat a N
Continuous clocking
00
ADC STATUS
SPI
Read ADC Data N-1
Read ADC Dat a 1
Don’t care
Read ADC Dat a N-1
Read ADC Dat a1
(New Cycle)
Read ADC Dat a N
Continuous clocking
00
11
TADC_SE TUP
ADC STATUS
Shutdown
Start-up Channel 1 Conversion Reset Channel 2 Conversion Reset
Channel N Conversion
(Last in Cycle)
TDLY_SCAN
TCONV
TADC_SE TUP
TCONV
TCONV
TDLY_SCA N
Shutdown or Reset
Depending onTIMER[23:0] sett ings
TTI MER _SCA N
Start-up
Channel 1 Conversion
Channel 2 Conversion
Reset
(New Cycle)
(New Cycle)
TCONV
TDLY_SCA N
TCONV
Start‐Up time is reduced to 0 if
TTIMER_SCAN MCLK = SCK
IF CLK_MODE = 10 => MCLK = Int RC OSC
Hi-Z
Continuous write
Don’t care
Hi-Z
Output
Control By te
Status Byte
Reset MCLK
MCP3565R Transition from CLK_SEL[1:0] = 0x/10 to 11.
2020-2021 Microchip Technology Inc.
DS20006401C-page 79
MCP3565R
CS High aborts SPI
communication but
does n’t stop internal
MCLK
CS
External or internal cloc k (no output) mode validated
Free running SCK comming from internal OSC
SCK
1
8
SCK PAD
direction
SDI
SDO
1
8
Max TC LZ
Continuo
us
clock ing
Outpu t
Don’t care
Hi-Z
Control Byte
Status By te
Write CLK_MODE = 0x (Ext CLK input on pin SCK)
or
Write CLK_MODE = 10 (Int RC without output on pin SCK)
Continuous write
Hi-Z
1
8
Don’t care
Input
Control By te
Status By te
IF CLK_MODE = 0x => MCLK = SCK
Reset MCLK
DS20006401C-page 80
Hi-Z
SPI mode 0,0
Hi-Z
MCLK
FIGURE 6-16:
SPI mode 1,1
IF CLK_MODE = 10 => MCLK = Int
RC OSC
MCP3565R Transition from CLK_SEL[1:0] = 11 to 0x/10.
2020-2021 Microchip Technology Inc.
MCP3565R
7.0
BASIC APPLICATION
CONFIGURATION
for noise filtering and to provide more stability for the
internal voltage reference (see Section 3.1 “Differential
Reference Voltage Inputs: REFIN+/OUT, REFIN-”).
The MCP3565R device can be used for various
precision Analog-to-Digital Converter applications. The
flexibility of its usage is given by the possibility of
configuring the ADC to fit the required application.
7.1
The ADC can be used in Differential or Single-Ended
mode due to the internal dual multiplexer (Figure 5-1).
The user can select the input connection settings from
the MUX register (Section 8.7 “Multiplexer (MUX)
Register”) by using the different settings available on
the positive and negative inputs of the ADC. The
single-ended configuration is achieved by selecting
AGND for the VIN- input of the ADC (MUX[3:0] = 1000)
or by selecting any CHn input channel for VIN- and
connecting the corresponding CHn input channel to
AGND.
Typical Application for Absolute
Voltage Measurement
The MCP3565R is able to measure the signal provided
by sensors with absolute voltage output. For such
applications, the MCP3565R typically uses its internal
voltage reference. For the best performance, an external capacitor is recommended on the REFIN+/OUT pin
3.3A
3.3D
R1
5%
10
R2
5%
10
AVDD
EP
C5
10uF
0603
R7
1k
0603
1 2
J1
CH1
CH0
Anti Aliasing Filters
R8
1k
FIGURE 7-1:
0603
GNDA
C7
0.1uF
0603
GNDA
C6
0.1uF
0603
GNDA
11
0603
0603
C4
0.1uF
GND
U1
SDO
REFIN-
SDI
REFIN+
SCK
CH0
3
AGND
CH1
2
4
1
5
GNDA
GND
DVDD
13
GNDA
10
0603
DGND
C3
0.1uF
0603
C2
0.1uF
9
R3
10
8
R4
10
7
R5
10
RG7/ADC_MISO
RG8/ADC_MOSI
RG6/ADC_SCK
CS
0603
6
C1
0.1uF
12
0603
R6
10
RG9/ADC_CS
MCP3565R
GNDA
C8
0.1uF
0603
MCP3565R Application Example.
2020-2021 Microchip Technology Inc.
DS20006401C-page 81
MCP3565R
7.1.1
HIGH-SIDE AND LOW-SIDE
CURRENT SENSING
The ADC has the ability to perform differential
measurements with an analog input Common-mode
equal to or slightly larger than AVDD, or equal to or slightly
lower than AGND (see the Electrical Characteristics
table).
A differential input structure and a Kelvin connection
are required in order to achieve the most accurate
measurements. An anti-aliasing filter is required to
avoid aliasing of the oversampling frequency (DMCLK)
back into the baseband of the input signal and possible
corruption of the output data. Figure 7-1 provides an
example of an anti-aliasing filter.
For the measurement of voltages that can reach AVDD
or a few mV higher, a gain setting of 0.33x is useful
since it increases the input range to a 3 x VREF value,
so a 1.2V VREF will allow a theoretical input range of
3.6V. However, the maximum voltage that can be
measured is always bounded by AVDD + 0.1V in order
to limit excess leakage current at the input pins created
by the ESD structures. Therefore, in order to properly
measure 3.6V with a 1.2V voltage reference, it is
recommended to use an AVDD supply voltage as close
as possible to 3.6V.
7.1.2
THERMOCOUPLE CONNECTION
One of the most used temperature transducers in the
industry is the thermocouple. Thermocouples provide a
voltage dependent on the temperature difference
between cold junction and hot junction. This voltage is
in the order of magnitude of tens of µV/°C, which
requires amplification that can be provided by the
internal gain stage of the ADC.
7.2
Typical Application for
Ratiometric Voltage Measurement
A wide range of sensors provides an output voltage
directly related to the power supply of the sensors.
These sensors are known as ratiometric output. These
sensors often have a Wheatstone bridge structure,
such as pressure sensors or load cells (Figure 7-3).
R1
RTD
VIN+
Input
Signal
REFIN+/OUT
MCP3565R
REFIN-
VIN-
FIGURE 7-3:
Wheatstone Bridge
Ratiometric Connection.
Others act as a single resistor with a value dependent
on temperature (pure metal resistance thermometer
RTD and negative temperature coefficient resistor
NTC). To accurately measure the signal from these
sensors, REFIN+/OUT is usually connected to the
same power supply of the sensor (Figure 7-4), as long
as this respects the specified voltage range on the
REFIN+/OUT pin (see the Electrical Characteristics
table.
R2
Sensor
VIN+
Anti-aliasing
Filter
REFIN+/OUT
MCP3565R
VIN-
REFIN-
R1
C1
FIGURE 7-4:
FIGURE 7-2:
C2
AGND
DGND
RTD Ratiometric Connection.
Thermocouple Connection.
The connection of the thermocouple to the ADC
requires minimal extra components. A differential input
structure is recommended. The cold junction can be
measured by using a digital temperature sensor, such
as MCP9804, connected to the MCU. If high accuracy
is not required, the cold junction temperature can be
estimated directly with the internal temperature sensor
of the ADC (see Figure 7-2).
DS20006401C-page 82
2020-2021 Microchip Technology Inc.
MCP3565R
7.3
Power Supply Design and
Bypassing
The split between analog and digital can be done under
the device, and AVDD and DVDD can be connected with
lines coming under the ground plane. The two separate
return paths will eventually share a unique connection
point (star connection) in order to minimize coupling
between the two power supply domains.
In any system, the analog ICs (such as references or
operational amplifiers) are always connected to the
analog ground plane. The MCP3565R should also be
considered a sensitive analog component and
connected to the analog ground plane. The ADC
features two pairs of power supply voltage pins: AGND
and AVDD, DGND and DVDD. For best performance, it is
recommended to keep the two pairs of pins connected
to two different networks (see Figure 7-5), so that the
design will feature two ground traces and two power
supplies (see Figure 7-6).
Another possibility, sometimes easier to implement in
terms of PCB layout, is to consider the MCP3565R as
an analog component, and connect AVDD to DVDD and
AGND to DGND with a star connection. In this scheme,
the decoupling capacitors may be larger, due to the
ripple on the digital power supply (caused by the digital
filters and the SPI interface of the MCP3565R), now
causing glitches on the analog power supply.
The analog circuitry (including MCP3565R) and the
digital circuitry (MCU) should have separate power
supplies and return paths to the external ground
reference, as described in Figure 7-5. An example of a
typical power supply circuit, with different paths for
analog and digital return currents, is shown in
Figure 7-6. A possible split example is shown in
Figure 7-7, where the ground star connection can be
located underneath the device with the exposed pad.
Figure 7-6 shows an example of a power supply
schematic with separate DVDD and AVDD. A high-current
LDO (MCP1825) was used for the DVDD line to be able
to power the MCU and other peripherals attached to the
MCU. A high PSRR LDO (MCP1754) is used for the
AVDD that goes to the ADC and a few other components
sensitive to noise. The NET tie is used to separate DGND
from AGND.
ID
IA
0.1 ȝF
C
0.1 ȝF
VD
VA
AV DD DVDD
MCP3565
MCU
AGND
DGND
IA
ID
“Star” Point
D-=
A-=
FIGURE 7-5:
Separating Digital and
Analog Ground by Using a Star Connection.
U2
MCP1825S-3.3V
VIN
VOUT
3
C44
10 μF
5V_USB
GND
VOUT
2
+5V USB
+9V IN
1
U3
MCP1754-3.3V
VIN
VOUT
C14
0.1 μF
0603
GND
GND
GND
TANT-B
GND
GND
3
3.3A
2
C15
10 μF
TANT-B
VIN
3 1
4 2
3
GND
D1
MRA4005
C45
10 μF
J9
1
1
3
2
Power Jack 2.5 mm
U4
LM1117-5V
GND
9V
J10
C10
0.1 μF
TANT-B
0603
GND
GND
3.3D
C11
0.1 μF
0603
2
1
GND
5V
Net Tie
GND
GNDA
GNDA
C12
0.1 μF
0603
GNDA
GNDA
C13
10 μF
TANT-B
GNDA
FIGURE 7-6:
Power Supply with Separate Lines for Analog and Digital Sections (the “Net Tie”
Object Represents the Star Ground Connection).
2020-2021 Microchip Technology Inc.
DS20006401C-page 83
MCP3565R
DVDD
DGND
AGND 1
AVDD
7.4
12
11
10
EP
13
REFIN‐ 2
9 SDO
8 SDI
4
5
6
CH0
CS
7 SCK
CH1
REFIN+ 3
FIGURE 7-7:
Separation of Analog and
Digital Circuits on the Layout (Shown on the
UQFN Package).
When remote sensors are used to reduce the sensitivity
to external influences, such as EMI, the wires that
connect the sensor to the ADC should form a twisted
pair. Ferrite beads can be used between the digital and
analog ground planes to keep high-frequency noise
from entering the device. A low-resistance ferrite bead
is recommended.
DS20006401C-page 84
SPI Interface Digital Crosstalk
The MCP3565R device incorporates a high-speed
20 MHz SPI digital interface. This interface can induce
crosstalk, especially with the outer channels closer to
the SPI digital pins (for example, CH7), if it is run at full
speed without any precautions. The crosstalk is caused
by the switching noise created by the digital SPI
signals. This crosstalk would negatively impact the
SNR in this case. The noise is attenuated if proper
separation between the analog and the digital power
supplies is put in place (see Sections 7.3 “Power
Supply Design and Bypassing”).
In order to further remove the influence of the SPI
communication on measurement accuracy, it is recommended to add series resistors on the SPI lines to
reduce the current spikes caused by the digital switching noise (see Figure 7-1 where these resistors have
been implemented). The resistors also help to keep the
level of electromagnetic emissions low.
The switching noise is also a linear function of the
DVDD supply voltage. In order to further reduce the
influence of the switching noise caused by SPI transmissions, the DVDD digital power supply voltage should
be kept at as a low value as possible.
The measurement graphs provided in this MCP3565R
data sheet have been performed with 10 series resistors connected on each SPI I/O pin. Measurement
accuracy disturbances have not been observed, even
at 20 MHz interfacing.
2020-2021 Microchip Technology Inc.
MCP3565R
8.0
INTERNAL REGISTERS
The MCP3565R has a total of 16 internal registers
made of volatile memory. Table 8-1 includes a summary of the registers. These registers are sequentially
accessible.
3
TABLE 8-1:
INTERNAL REGISTERS SUMMARY
Address Register Name
No. of
Bits
R/W
Description
Latest A/D conversion data output value (24 or 32 bits depending on
DATA_FORMAT[1:0]) or modulator output stream (4-bit wide) in MDAT
Output mode
0x0
ADCDATA
4/24/32
R
0x1
CONFIG0
8
R/W
ADC Operating mode, Master Clock mode and Input Bias Current
Source mode
0x2
CONFIG1
8
R/W
Prescale and OSR settings
0x3
CONFIG2
8
R/W
ADC boost and gain settings, auto-zeroing settings for analog
multiplexer, voltage reference and ADC
0x4
CONFIG3
8
R/W
Conversion mode, data and CRC format settings; enable for CRC on
communications, enable for digital offset and gain error calibrations
0x5
IRQ
8
R/W
IRQ Status bits and IRQ mode settings; enable for Fast commands
0x6
MUX
8
R/W
Analog multiplexer input selection (MUX mode only)
0x7
SCAN
24
R/W
SCAN mode settings
0x8
TIMER
24
R/W
Delay value for TIMER between Scan cycles
0x9
OFFSETCAL
24
R/W
ADC digital offset calibration value
0xA
GAINCAL
24
R/W
ADC digital gain calibration value
0xB
RESERVED
24
R/W
Reserved
0xC
RESERVED
8
R/W
Reserved
0xD
LOCK
8
R/W
Password value for SPI Write mode locking
0xE
RESERVED
16
R/W
Reserved
0xF
CRCCFG
16
R
2020-2021 Microchip Technology Inc.
CRC checksum for device configuration
DS20006401C-page 85
MCP3565R
8.1
ADCDATA REGISTER
Name
Bits
Address
Cof
ADCDATA
4/24/32
0x0
R
REGISTER 8-1:
ADCDATA: ADC CHANNEL DATA OUTPUT REGISTER
R-0
ADCDATA[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 23-0
x = Bit is unknown
ADCDATA[23:0]: ADC Output Code
The data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. The data can be
formatted in 24/32-bit modes depending on the DATA_FORMAT[1:0] settings (see Section 5.6 “ADC
Output Data Format”).
The ADC Channel Data Output registers always contain the most recent A/D conversion data. The
register is updated at each data ready internal signal (it depends on the OSR and CONV_MODE
settings). The register is latched at the start of each SPI Read command. The register is double
buffered to avoid data loss. There is a small time delay, tDODR, after each data ready, where the user
has to wait for the data to be available; otherwise, data corruption can occur (when the internal data
are refreshed).
When EN_MDAT = 1, this register becomes a 4-bit wide register containing the MDAT output codes,
which are the outputs of the modulator that are represented by four comparator outputs (COMP[3:0],
see Section 5.4.2 “Modulator Output Block”).
DS20006401C-page 86
2020-2021 Microchip Technology Inc.
MCP3565R
8.2
CONFIG0 REGISTER
Name
Bits
Address
Cof
CONFIG0
8
0x1
R/W
REGISTER 8-2:
CONFIG0 REGISTER
R/W-1
R/W-1
VREF_SEL
CONFIG0[6]
R/W-0
R/W-0
R/W-0
CLK_SEL[1:0]
R/W-0
R/W-0
CS_SEL[1:0]
R/W-0
ADC_MODE[1:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
VREF_SEL: Internal Voltage Reference
1 = Internal voltage reference is selected and buffered internally. The REFIN+/OUT pin voltage is set
at 2.4V (default).
0 = External voltage reference is selected and not buffered internally. The internal voltage reference
buffer is shut down.
bit 6
CONFIG0[6]: If CONFIG0 = 0x0, the device goes into Partial Shutdown mode. This bit does not have
any other function.
bit 5-4
CLK_SEL[1:0]: Clock Selection
11 = Internal clock is selected and AMCLK is present on the SCK pin, which becomes an output pin.
10 = Internal clock is selected and no clock output is present on the SCK pin, in which case, the SCK
pin becomes the SPI clock input pin only.
01 = External digital clock. In this mode, SCK = MCLK and the clock input pin is SCK. (MCLK needs
to be sent continuously to ensure proper functioning of A/D conversions.)
00 = External digital clock (default). In this mode, SCK = MCLK and the clock input pin is SCK. (MCLK
needs to be sent continuously to ensure proper functioning of A/D conversions.)
bit 3-2
CS_SEL[1:0]: Current Source/Sink Selection for Sensor Bias (source on VIN+/Sink on VIN-)
11 = 15 µA is applied to the ADC inputs
10 = 3.7 µA is applied to the ADC inputs
01 = 0.9 µA is applied to the ADC inputs
00 = No current source is applied to the ADC inputs (default)
bit 1-0
ADC_MODE[1:0]: ADC Operating Mode Selection
11 = ADC Conversion mode
10 = ADC Standby mode
01 = ADC Shutdown mode
00 = ADC Shutdown mode (default)
2020-2021 Microchip Technology Inc.
DS20006401C-page 87
MCP3565R
8.3
CONFIG1 REGISTER
Name
Bits
Address
Cof
CONFIG1
8
0x2
R/W
REGISTER 8-3:
R/W-0
CONFIG1: CONFIGURATION REGISTER 1
R/W-0
R/W-0
PRE[1:0]
R/W-0
R/W-1
R/W-1
OSR[3:0]
R/W-0
R/W-0
RESERVED RESERVED
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
bit 5-2
bit 1-0
x = Bit is unknown
PRE[1:0]: Prescaler Value Selection for AMCLK
11 = AMCLK = MCLK/8
10 = AMCLK = MCLK/4
01 = AMCLK = MCLK/2
00 = AMCLK = MCLK (default)
OSR[3:0]: Oversampling Ratio for Delta-Sigma A/D Conversion
1111 = OSR: 98304
1110 = OSR: 81920
1101 = OSR: 49152
1100 = OSR: 40960
1011 = OSR: 24576
1010 = OSR: 20480
1001 = OSR: 16384
1000 = OSR: 8192
0111 = OSR: 4096
0110 = OSR: 2048
0101 = OSR: 1024
0100 = OSR: 512
0011 = OSR: 256 (default)
0010 = OSR: 128
0001 = OSR: 64
0000 = OSR: 32
RESERVED[1:0]: Must remain set to ‘00’
DS20006401C-page 88
2020-2021 Microchip Technology Inc.
MCP3565R
8.4
CONFIG2 REGISTER
Name
Bits
Address
Cof
CONFIG2
8
0x3
R/W
REGISTER 8-4:
R/W-1
CONFIG2: CONFIGURATION REGISTER 2
R/W-0
R/W-0
BOOST[1:0]
R/W-0
R/W-1
GAIN[2:0]
R/W-0
R/W-1
R/W-1
AZ_MUX
AZ_REF
RESERVED
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
bit 5-3
bit 2
bit 1
bit 0
x = Bit is unknown
BOOST[1:0]: ADC Bias Current Selection
11 = ADC channel has current x 2
10 = ADC channel has current x 1 (default)
01 = ADC channel has current x 0.66
00 = ADC channel has current x 0.5
GAIN[2:0]: ADC Gain Selection
111 = Gain is x64 (x16 analog, x4 digital)
110 = Gain is x32 (x16 analog, x2 digital)
101 = Gain is x16
100 = Gain is x8
011 = Gain is x4
010 = Gain is x2
001 = Gain is x1 (default)
000 = Gain is x1/3
AZ_MUX: Auto-Zeroing MUX Setting
1 = ADC auto-zeroing algorithm is enabled. This setting multiplies the conversion time by two and
does not allow Continuous Conversion mode operation (which is then replaced by a series of
consecutive One-Shot mode conversions).
0 = Analog input multiplexer auto-zeroing algorithm is disabled (default).
AZ_REF: Auto-Zeroing Reference Buffer Setting
1 = Internal voltage reference buffer chopping algorithm is enabled. This setting has no effect when
external voltage reference is selected (VREF_SEL = 0) (default).
0 = Internal voltage reference buffer chopping auto-zeroing algorithm is disabled.
RESERVED: Must remain set to ‘1’
2020-2021 Microchip Technology Inc.
DS20006401C-page 89
MCP3565R
8.5
CONFIG3 REGISTER
Name
Bits
Address
Cof
CONFIG3
8
0x4
R/W
REGISTER 8-5:
R/W-0
R/W-0
CONV_MODE[1:0]
CONFIG3: CONFIGURATION REGISTER 3
R/W-0
R/W-0
DATA_FORMAT[1:0]
R/W-0
R/W-0
R/W-0
R/W-0
CRC_FORMAT
EN_CRCCOM
EN_OFFCAL
EN_GAINCAL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
CONV_MODE[1:0]: Conversion Mode Selection
11 = Continuous Conversion mode or continuous conversion cycle in Scan mode.
10 = One-shot conversion or one-shot cycle in Scan mode. It sets ADC_MODE[1:0] to ‘10’ (standby) at
the end of the conversion or at the end of the conversion cycle in Scan mode.
0x = One-shot conversion or one-shot cycle in Scan mode. It sets ADC_MODE[1:0] to ‘0x’ (ADC
shutdown) at the end of the conversion or at the end of the conversion cycle in Scan mode (default).
bit 5-4
DATA_FORMAT[1:0]: ADC Output Data Format Selection
11 = 32-bit (25-bit right justified data + Channel ID): CHID[3:0] + SGN extension (4 bits) + 24-bit ADC
data. It allows overrange with the SGN extension.
10 = 32-bit (25-bit right justified data): SGN extension (8-bit) + 24-bit ADC data. It allows overrange with
the SGN extension.
01 = 32-bit (24-bit left justified data): 24-bit ADC data + 0x00 (8-bit). It does not allow overrange (ADC
code locked to 0xFFFFFF or 0x800000).
00 = 24-bit (default ADC coding): 24-bit ADC data. It does not allow overrange (ADC code locked to
0xFFFFFF or 0x800000).
bit 3
CRC_FORMAT: CRC Checksum Format Selection on Read Communications
(it does not affect CRCCFG coding)
1 = 32-bit wide (CRC-16 followed by 16 zeros).
0 = 16-bit wide (CRC-16 only) (default).
bit 2
bit 1
bit 0
EN_CRCCOM: CRC Checksum Selection on Read Communications
(it does not affect CRCCFG calculations)
1 = CRC on communications enabled.
0 = CRC on communications disabled (default).
EN_OFFCAL: Enable Digital Offset Calibration
1 = Enabled
0 = Disabled (default)
EN_GAINCAL: Enable Digital Gain Calibration
1 = Enabled
0 = Disabled (default)
DS20006401C-page 90
2020-2021 Microchip Technology Inc.
MCP3565R
8.6
IRQ REGISTER
Name
Bits
Address
Cof
IRQ
8
0x5
R/W
REGISTER 8-6:
U-0
—
R-1
IRQ: INTERRUPT REQUEST REGISTER
R-1
R-1
R/W-0
DR_STATUS CRCCFG_STATUS POR_STATUS EN_MDAT
U-1
R/W-1
U-1
—
EN_FASTCMD
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
DR_STATUS: Data Ready Status Flag
1 = ADCDATA has not been updated since the last reading or last reset (default).
0 = New ADCDATA ready for reading.
bit 5
bit 4
bit 3
CRCCFG_STATUS: CRC Error Status Flag for Internal Registers
1 = CRC error has not occurred for the Configuration registers (default).
0 = CRC error has occurred for the Configuration registers.
POR_STATUS: POR Status Flag
1 = POR has not occurred since the last reading (default).
0 = POR has occurred since the last reading.
EN_MDAT: Modulator Output Data Enable
1 = Places modulator output on the ADCDATA register, which then becomes a 4-bit register, which reads
COMP[3:0].
0 = Modulator output is not provided. ADCDATA shows the ADC output after decimation filter.
bit 2
Unimplemented: Read as ‘1’
bit 1
EN_FASTCMD: Enable Fast Commands in the COMMAND Byte
1 = Fast commands are enabled (default)
0 = Fast commands are disabled
bit 0
Unimplemented: Read as ‘1’
2020-2021 Microchip Technology Inc.
DS20006401C-page 91
MCP3565R
8.7
MULTIPLEXER (MUX) REGISTER
Name
Bits
Address
Cof
MUX
8
0x6
R/W
REGISTER 8-7:
R/W-0
MUX: MULTIPLEXER REGISTER
R/W-0
R/W-0
MUX_VIN+[3:0](2)
R/W-0
R/W-0
R/W-0
R/W-0
MUX_VIN-[3:0](2)
R/W-1
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 7-4
Bit 3-0
Note 1:
2:
x = Bit is unknown
MUX_VIN+[3:0]: Input Selection(2)
1111 = Internal VCM
1110 = Internal Temperature Sensor Diode M (Temp Diode M)(1)
1101 = Internal Temperature Sensor Diode P (Temp Diode P)(1)
1100 = REFIN1011 = REFIN+/OUT
1010 = Reserved (do not use)
1001 = AVDD
1000 = AGND
0111 = Reserved (do not use)
0110 = Reserved (do not use)
0101 = Reserved (do not use)
0100 = Reserved (do not use)
0011 = Reserved (do not use)
0010 = Reserved (do not use)
0001 = CH1
0000 = CH0 (default)
MUX_VIN-[3:0]: Input Selection(2)
1111 = Internal VCM
1110 = Internal Temperature Sensor Diode M (Temp Diode M)(1)
1101 = Internal Temperature Sensor Diode P (Temp Diode P)(1)
1100 = REFIN1011 = REFIN+/OUT
1010 = Reserved (do not use)
1001 = AVDD
1000 = AGND
0111 = Reserved (do not use)
0110 = Reserved (do not use)
0101 = Reserved (do not use)
0100 = Reserved (do not use)
0011 = Reserved (do not use)
0010 = Reserved (do not use)
0001 = CH1 (default)
0000 = CH0
Selects the internal temperature sensor diode and forces a fixed current through it. For a correct
temperature reading, the MUX[7:0] selection should be equal to 0xDE.
The codes, ‘1010/0111/0110/0101/0100/0011/0010’, correspond to a floating input and should be
avoided.
DS20006401C-page 92
2020-2021 Microchip Technology Inc.
MCP3565R
8.8
SCAN REGISTER
Name
Bits
Address
Cof
SCAN
24
0x7
R/W
REGISTER 8-8:
R/W-0
SCAN: SCAN MODE SETTINGS REGISTER
R/W-0
R/W-0
DLY[2:0]
R/W-0
U-0
RESERVED
—
bit 23
bit 16
R/W-0
R/W-0
R/W-0
R/W-0
OFFSET
VCM
AVDD
TEMP
R/W-0
R/W-0
R/W-0
R/W-0
RESERVED RESERVED RESERVED SCAN_DIFF_CHA
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
R/W-0
SCAN_SE_CH[1:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 23-21
Bit 20
x = Bit is unknown
DLY[2:0]: Delay Time (TDLY_SCAN) Between Each Conversion During a Scan Cycle
111 = 512 * DMCLK
110 = 256 * DMCLK
101 = 128 * DMCLK
100 = 64 * DMCLK
011 = 32 * DMCLK
010 = 16 * DMCLK
001 = 8 * DMCLK
000 = 0: No delay (default)
RESERVED: Must remain set to ‘0’
Bit 19-16
Unimplemented: Read as ‘0’
Bit 15-12
SCAN Channel Selection (see Table 5-15 for a complete description)
Bit 11-9
RESERVED: Must remain set to ‘000’
Bit 8
SCAN Channel Selection (see Table 5-15 for a complete description)
Bit 7-2
RESERVED: Must remain set to ‘000000’
Bit 1-0
SCAN Channel Selection (see Table 5-15 for a complete description)
2020-2021 Microchip Technology Inc.
DS20006401C-page 93
MCP3565R
8.9
TIMER REGISTER
Name
Bits
Address
Cof
TIMER
24
0x8
R/W
REGISTER 8-9:
TIMER: TIMER DELAY VALUE REGISTER
R/W-0
TIMER[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 23-0
x = Bit is unknown
TIMER[23:0]: Selection Bits for the Time Interval (TTIMER_SCAN) Between Two Consecutive Scan Cycles
(when CONV_MODE[1:0] = 11):
0xFFFFFF: TTIMER_SCAN = 16777215 * DMCLK periods
0xFFFFFE: TTIMER_SCAN = 16777214 * DMCLK periods
•
•
•
0x000002: TTIMER_SCAN = 2 * DMCLK periods
0x000001: TTIMER_SCAN = 1 * DMCLK periods
0x000000: TTIMER_SCAN = 0 (No delay) – default
DS20006401C-page 94
2020-2021 Microchip Technology Inc.
MCP3565R
8.10
OFFSETCAL REGISTER
Name
Bits
Address
Cof
OFFSETCAL
24
0x9
R/W
REGISTER 8-10:
OFFSETCAL: OFFSET CALIBRATION REGISTER
R/W-0
OFFSETCAL[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
OFFSETCAL[23:0]: Offset Error Digital Calibration Code (two’s complement, MSb first coding)
See Sections 5.13 “Digital System Offset and Gain Calibrations”.
Bit 23-0
8.11
x = Bit is unknown
GAINCAL REGISTER
Name
Bits
Address
Cof
GAINCAL
24
0xA
R/W
REGISTER 8-11:
GAINCAL: GAIN CALIBRATION REGISTER
R/W-1
R/W-0
GAINCAL[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 23-0
x = Bit is unknown
GAINCAL[23:0]: Gain Error Digital Calibration Code (unsigned, MSb first coding)
The GAINCAL default value is 800000, which provides a gain of 1x. See Section 5.13 “Digital
System Offset and Gain Calibrations”.
2020-2021 Microchip Technology Inc.
DS20006401C-page 95
MCP3565R
8.12
RESERVED REGISTER
Name
Bits
Address
Cof
RESERVED
24
0xB
R/W
REGISTER 8-12:
RESERVED REGISTER
R/W-0x900000
RESERVED[23:0]
bit 23
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
RESERVED[23:0]: Must remain set to 0x900000
Bit 23-0
8.13
x = Bit is unknown
RESERVED REGISTER
Name
Bits
Address
Cof
RESERVED
8
0xC
R/W
REGISTER 8-13:
RESERVED REGISTER
R/W-0x30
RESERVED[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 7-0
x = Bit is unknown
RESERVED[7:0]: Must remain set to 0x30
DS20006401C-page 96
2020-2021 Microchip Technology Inc.
MCP3565R
8.14
LOCK REGISTER
Name
Bits
Address
Cof
LOCK
8
0xD
R/W
REGISTER 8-14:
R/W-1
LOCK: SPI WRITE MODE LOCKING PASSWORD VALUE REGISTER
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
LOCK[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
LOCK[7:0]: Write Access Password Entry Code
0xA5 = Write access is allowed on the full register map. CRC on register map values is not calculated
(CRCCFG[15:0] = 0x0000) – default.
Any code, except 0xA5 = Write access is not allowed on the full register map. Only the LOCK register
is writable. CRC on register map is calculated continuously only when DMCLK is running.
Bit 7-0
8.15
x = Bit is unknown
RESERVED REGISTER
Name
Bits
Address
Cof
RESERVED
16
0xE
R/W
REGISTER 8-15:
RESERVED REGISTER
R/W (0x000E)
RESERVED[15:0]
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 15-0
x = Bit is unknown
RESERVED[15:0]: Must remain set to 0x000E
2020-2021 Microchip Technology Inc.
DS20006401C-page 97
MCP3565R
8.16
CRCCFG REGISTER
Name
Bits
Address
Cof
CRCCFG
16
0xF
R
REGISTER 8-16:
CRCCFG: CRC CONFIGURATION REGISTER
R-0
CRCCFG[15:0]
bit 15
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Bit 15-0
x = Bit is unknown
CRCCFG[15:0]: CRC-16 Checksum Value
CRC-16 checksum is continuously calculated internally based on the register map configuration
settings when the device is locked (LOCK[7:0] ≠ 0xA5).
DS20006401C-page 98
2020-2021 Microchip Technology Inc.
MCP3565R
9.0
PACKAGING INFORMATION
9.1
Package Marking Information(1)
12-Lead UQFN (2 mm x 2 mm x 0.55 mm)
Example:
565R
0256
Part Number
Code
SPI Device Address
MCP3565RT-E/SFX
56R
01(1)
Note 1: Denotes the device default SPI address option.
The device only responds to SPI commands if
CMD[7:6] match the SPI device address for each
command (see Section 6.2.2, Device Address
Bits (CMD[7:6])). Contact Microchip Sales
for other device address option ordering
procedures.
Assembled/Packaged Before: 9/15/2020
XXX
NNN(1)
Assembled/Packaged After: 9/15/2020
XXXX
YNNN(2)
Note 1: NNN is the alphanumeric traceability code.
2: is the last digit of the year (e.g., 0NNN for
2020) and NNN is the alphanumeric traceability
code.
Legend: XX...X
Y
YY
WW
NNN
e3
*
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note 1: In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2020-2021 Microchip Technology Inc.
DS20006401C-page 99
MCP3565R
12-Lead Ultra Thin Plastic Quad Flat, No Lead Package (SFX) - 2x2 mm Body [UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
NOTE 1
A
B
N
1
E
2
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.10 C
TOP VIEW
0.10 C
A1
C
A
SEATING
PLANE
12X
(A3)
0.08 C
SIDE VIEW
0.10
C A B
D2
0.10
C A B
E2
2
1
K
NOTE 1
N
12X b
0.07
0.05
L
e
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-438A Sheet 1 of 2
DS20006401C-page 100
2020-2021 Microchip Technology Inc.
MCP3565R
12-Lead Ultra Thin Plastic Quad Flat, No Lead Package (SFX) - 2x2 mm Body [UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
E2
Exposed Pad Width
b
Terminal Width
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.50
0.00
0.82
0.82
0.15
0.24
0.25
MILLIMETERS
NOM
12
0.40 BSC
0.55
0.02
0.152 REF
2.00 BSC
0.92
2.00 BSC
0.92
0.20
0.29
-
MAX
0.60
0.05
1.02
1.02
0.25
0.34
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-438A Sheet 2 of 2
2020-2021 Microchip Technology Inc.
DS20006401C-page 101
MCP3565R
12-Lead Ultra Thin Plastic Quad Flat, No Lead Package (SFX) - 2x2 mm Body [UQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
12
ØV
1
C2 Y2
2
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
X2
Optional Center Pad Width
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X12)
X1
Contact Pad Length (X12)
Y1
Contact Pad to Center Pad (X12)
G1
Thermal Via Diameter
EV
MIN
MILLIMETERS
NOM
0.40 BSC
MAX
1.00
1.00
2.10
2.10
0.20
0.70
0.20
0.30
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2438A
DS20006401C-page 102
2020-2021 Microchip Technology Inc.
MCP3565R
APPENDIX A:
REVISION HISTORY
Revision A (August 2020)
• Initial release of this document.
Revision B (March 2021)
The following is the list of modifications:
• Corrected Table 5-11
• Corrected Register 8-2
• Minor corrections in Section 9.0 “Packaging
Information” and Section “Product
Identification System”
Note:
The SPI standard uses the terminology
“Master” and “Slave”. The equivalent
Microchip terminology used in this
document is “Host” and “Client”,
respectively.
Revision C (April 2021)
• Updated references to Effective Resolution
throughout the document.
• Minor editorial corrections.
2020-2021 Microchip Technology Inc.
DS20006401C-page 103
MCP3565R
NOTES:
DS20006401C-page 104
2020-2021 Microchip Technology Inc.
MCP3565R
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X(1)
PART NO.
Device
Tape and
Reel
X
/XX
Temperature
Range
Package
Device:
MCP3565R:
Tape and Reel:
T
= Tape and Reel
Blank = Standard packaging (tube or tray)
Two Differential Channels,
High-Precision 24-Bit Delta-Sigma ADC
with SPI Device Address ‘01’
Temperature
Range:
E
= -40°C to +125°C (Extended)
Package:
SFX
= Ultra-Small, No Lead Package (UQFN),
2 mm x 2 mm x 0.55 mm, 12-Lead
2020-2021 Microchip Technology Inc.
Examples:
a) MCP3565RT-E/SFX: Two-Channel ADC,
Tape and Reel,
Extended Temperature,
12-Lead UQFN
Note
1:
The Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
2:
The device SPI Address ‘01’ is the default
address option. Contact Microchip Sales for
other device address option ordering
procedures.
DS20006401C-page 105
MCP3565R
NOTES:
DS20006401C-page 106
2020-2021 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip
devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications
contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished
without violating Microchip's intellectual property rights.
•
Microchip is willing to work with any customer who is concerned about the integrity of its code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication is provided for the sole
purpose of designing with and using Microchip products. Information regarding device applications and the like is provided
only for your convenience and may be superseded by updates.
It is your responsibility to ensure that your application meets
with your specifications.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS".
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION INCLUDING BUT NOT
LIMITED TO ANY IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
PARTICULAR PURPOSE OR WARRANTIES RELATED TO
ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
WHATSOEVER RELATED TO THE INFORMATION OR ITS
USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES
ARE FORESEEABLE. TO THE FULLEST EXTENT
ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON
ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION
OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF
ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP
FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and
the buyer agrees to defend, indemnify and hold harmless
Microchip from any and all damages, claims, suits, or expenses
resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights
unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions
Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight
Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,
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TimePictra, TimeProvider, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
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BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive,
CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, Espresso T1S,
EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP,
INICnet, Intelligent Paralleling, Inter-Chip Connectivity,
JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,
NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O,
simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI,
SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total
Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY,
ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2020-2021, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2020-2021 Microchip Technology Inc.
ISBN: 978-1-5224-8149-2
DS20006401C-page 107
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DS20006401C-page 108
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02/28/20
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