ISO2-CMOS
MT9162
5 Volt Single Rail Codec
Data Sheet
Features
May 2006
•
Single 5 volt supply
•
Programmable µ−law/A-law Codec and filters
•
Fully differential output driver
•
SSI digital interface
•
SSI speed control via external pins CSLO-CSL2
•
Individual transmit and receive mute controls
•
0 dB gain in receive path
•
6 dB gain in transmit path
•
Low power operation
•
ITU-T G.714 compliant
Ordering Information
MT9162AE
20 Pin PDIP
MT9162AS
20 Pin SOIC
MT9162AN
20 Pin SSOP
MT9162AN1 20 Pin SSOP*
*Pb Free Matte Tin
Tubes
Tubes
Tubes
Tubes
-40°C to +85°C
Description
The MT9162 5 V single rail Codec incorporates a builtin Filter/Codec, transmit anti-alias filter, a reference
voltage and bias source. The device supports both Alaw and µ-law requirements.
Applications
The analog interface is capable of driving a 20 k ohm
load.
•
Cellular radio sets
•
Local area communications stations
•
Line cards
The MT9162 is fabricated in Zarlink's ISO2-CMOS
technology ensuring low power consumption and high
reliability.
FILTER/CODEC GAIN
VDD
VSS
VBias
VRef
ENCODER
6dB
DECODER
0 dB
AIN+
AINAnalog
Interface
AOUT +
AOUT -
Din
Dout
STB
Timing
PCM
Serial
Interface
CLOCKin
Control
PWRST
IC
A/µ
CSL0
CSL1
CSL2 RXMute TXMute
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MT9162
VBias
VRef
PWRST
IC
A/µ
RXMUTE
TXMUTE
CSL0
CSL1
CSL2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Data Sheet
AIN+
AINVSS
AOUT +
AOUT VDD
CLOCKin
STB
Din
Dout
20 PIN PDIP/SOIC/SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
1
VBias
Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect
0.1 µ F capacitor to VSS. Connect 1 µF capacitor to Vref.
2
VRef
Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.9] volts. Used internally. Connect 0.1
µ F capacitor to VSS. Connect 1 µF capacitor to VBias
3
Description
PWRST Power-up Reset. Resets internal state of device via Schmitt Trigger input (active low).
4
IC
Internal Connection. Tie externally to VSS for normal operation.
5
A/µ
A/µ Law Selection. CMOS level compatible input pin governs the companding law used by the
device. A-law selected when pin tied to VDD or µ-law selected when pin tied to VSS.
6
RXMute Receive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation.
CMOS level compatible.
7
TXMute Transmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation.
CMOS level compatible.
8
9
10
CSL0
CSL1
CSL2
Clock Speed Select. These pins are used to program the speed of the SSI mode as well as the conversion
rate between the externally supplied MCL clock and the 512 kHz clock required by the filter/codec.
Refer to Table 2 for details. CMOS level compatible.
11
Dout
Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1 device.
Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot defined by
STB.
12
Din
Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the falling
edge of BCL during the timeslot defined by STB. CMOS level compatible.
13
STB
Data Strobe. This input determines the 8-bit timeslot used by the device for both transmit and receive
data. This active high signal has a repetition rate of 8 kHz. CMOS level compatible.
14
15
CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions. Connect bit
clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin when the bit clock
is 128 kHz or 256 kHz. CMOS level compatible.
VDD
Positive Power Supply. Nominally 5 volts.
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Zarlink Semiconductor Inc.
MT9162
Data Sheet
Pin Description (continued)
Pin #
Name
Description
16
AOUT-
17
AOUT+ Non-Inverting Analog Output. (balanced).
Inverting Analog Output. (balanced).
18
VSS
Ground. Nominally 0 volts.
19
Ain-
Inverting Analog Input. No external anti-aliasing is required.
20
Ain+
Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required.
Overview
The 5 V single rail Codec features complete Analog/Digital and Digital/Analog conversion of audio signals
(Filter/Codec) and an analog interface to a standard analog transmitter and receiver (Analog Interface). The
receiver amplifier is capable of driving a 20 k ohm load.
Functional Description
Filter/Codec
The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain
compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are
programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion.
The Filter/Codec block also implements a transmit audio path gain in the analog domain. Figure 3 depicts the
nominal half-channel for the MT9162.
The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide
dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the analog
interface section to provide full chip realization of these capabilities for the external functions.
A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for
biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it
may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from VBias to analog
ground at all times. Likewise, although VRef may only be used internally, a 0.1µF capacitor from the VRef pin to
ground is required at all times. The analog ground reference point for these two capacitors must be physically the
same point. To facilitate this the VRef and VBias pins are situated on adjacent pins.
The transmit filter is designed to meet ITU-T G.714 specifications. An anti-aliasing filter is included. This is a second
order lowpass implementation with a corner frequency at 25 kHz.
The receive filter is designed to meet ITU-T G.714 specifications. Filter response is peaked to compensate for the
sinx/x attenuation caused by the 8 kHz sampling rate.
Companding law selection for the Filter/Codec is provided by the A/ µ companding control pin. Table 1 illustrates
these choices.
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Zarlink Semiconductor Inc.
MT9162
Data Sheet
ITU-T (G.711)
Code
µ -Law
A-Law
+ Full Scale
1000 0000
1010 1010
+ Zero
1111 1111
1101 0101
-Zero
(quiet code)
0111 1111
0101 0101
- Full Scale
0000 0000
0010 1010
Table 1 - Law Selection
Analog Interfaces
Standard interfaces are provided by the MT9162. These are:
•
The analog inputs (transmitter), pins AIN+/AIN-. The maximum peak to peak input is 3.667Vpp µ−law and across
AIN+/AIN- 3.8Vpp A-law.
•
The analog outputs (receiver), pins AOUT+/AOUT-. This internally compensated fully differential output driver is
capable of driving a load of 20k ohms.
PCM Serial Interface
A serial link is required to transport data between the MT9162 and an external digital transmission device. The
MT9162 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly
referred to as Simple Serial Interface (SSI).
The required mode of operation is selected via the CSL2-0 control pins. See Table 2 for selections based in CSL20 pin settings.
Quiet Code
The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute
pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the
CSL2
CSL1
CSL0
External
Clock Bit
Rate (kHz)
CLOCKin
(kHz)
1
0
0
128
4096
1
0
1
256
4096
0
0
0
512
512
0
0
1
1536
1536
0
1
0
2048
2048
0
1
1
4096
4096
Figure 2 - Table 2: Bit Clock Rate Selection
TxMute pin is high. When either of these pins are low their respective paths function normally. The -Zero entry of
Table 1 is used for the quiet code definition.
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Zarlink Semiconductor Inc.
MT9162
Data Sheet
SSI Mode
The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input
signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if
the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6.
In SSI mode the MT9162 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel
data are always in the channel defined by the STB input.
The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This
is an active high signal with an 8 kHz repetition rate.
SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is
512 kHz or greater then it is used directly by the internal MT9162 functions allowing synchronous operation. If the
available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal
MT9162 functions.
Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT9162 will re-align its
internal clocks to allow operation when the external master and bit clocks are asynchronous. Control pins CSL2,
CSL1 and CSL0 are used to program the bit rates.
Serial
Filter/Codec and Analog Interface
Port
Aout +
PCM
Decoder
Din
2.05 dB
PCM
Dout
Encoder
-2.05 dB
-2.05 dB
Receiver
Driver
Receive
Filter Gain
0 dB
Transmit
Filter
Transmit Filter
Gain
Gain
0 to0dB
+7 dB
(1 dB steps)
Transmit Gain
-0.37 dB
Transmit
Gain
8.42 dB
Internal To Device
Aout-
AIN+
AIN-
20kΩ
Analog
Input
External To Device
Figure 3 - Audio Gain Partitioning
For synchronous operation, data is sampled from Din, on the falling edge of BCL during the time slot defined by the
STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input.
Dout is tri-stated at all times when STB is not true. If STB is valid, then quiet code will be transmitted on Dout during
the valid strobe period. There is no frame delay through the PCM serial circuit for synchronous operation.
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Zarlink Semiconductor Inc.
MT9162
Data Sheet
For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed output
jitter on Dout is larger. This is due to the resynchronization circuitry activity and will not affect operation since the bit
cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the PCM serial circuit for
asynchronous operation. Refer to the specifications of Figures 5 & 6 for both synchronous and asynchronous SSI
timing.
PWRST
While the MT9162 is held in PWRST no device control or functionality is possible.
Applications
Figure 4 shows the MT9162 in a line card application.
0.1 µF
(
VBias
)
Typical External Gain
AV= 5-10
Input from Subscriber
Line Interface
1 µF
0.1 µF
+5V
1
2
100k
100k
1k
100k
3
4
5
A/µ
RxMUTE
6
7
8
9
10
TxMUTE
1k
100k
1k
100k
1k
100k
MT9162
CS0
20
19
18
17
16
15
14
13
12
11
Out to Subscriber Line
Interface
+5V
CS1
1k
100k
1k
CS2
+5V
DC to DC
Converter
Din
Lin
MT8972
From Digital
Phone
ZT
DNIC
Dout
Frame Pulse
Twisted Pair
Lout
Figure 4 - Line Card Application
6
Zarlink Semiconductor Inc.
Clock
MT9162
Data Sheet
Absolute Maximum Ratings†
Parameter
†
Symbol
Min.
Max.
Units
VDD - VSS
- 0.3
7
V
VI/VO
VSS - 0.3
VDD + 0.3
V
± 20
mA
+ 150
°C
750
mW
1
Supply Voltage
2
Voltage on any I/O pin
3
Current on any I/O pin (transducers excluded)
4
Storage Temperature
TS
5
Power Dissipation (package)
PD
II/IO
- 65
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated
Characteristics
Sym.
Min.
Typ.
Max.
Units
5
5.25
V
1
Supply Voltage
VDD
4.75
2
CMOS Input Voltage (high)
VIHC
4.5
VDD
V
3
CMOS Input Voltage (low)
VILC
VSS
0.5
V
4
Operating Temperature
TA
- 40
+ 85
°C
Typ.
Max.
Units
Test Conditions
Power Characteristics
Characteristics
Sym.
Min.
1
Static Supply Current (clock disabled)
IDDC1
4
20
µA
Outputs unloaded, Input
signals static, not loaded
2
Dynamic Supply Current:
Total all functions enabled
IDDFT
7.0
10
mA
See Note 1
Note 1: Power delivered to the load is in addition to the bias current requirements.
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Zarlink Semiconductor Inc.
Test Conditions
MT9162
Data Sheet
DC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
3.5
Typ.‡
Max.
Units
Test Conditions
1
Input HIGH Voltage CMOS inputs
VIHC
2
Input LOW Voltage CMOS inputs
VILC
3
VBias Voltage Output
VBias
VDD/2
V
Max. Load = 10kΩ
4
VRef Output Voltage
VRef
VDD/21.9
V
No load
5
Input Leakage Current
IIZ
0.1
µA
VIN=VDD to VSS
6
Positive Going Threshold
Voltage (PWRST only)
Negative Going Threshold
Voltage (PWRST only)
VT+
7
Output HIGH Current
IOH
3
7
mA
VOH = 0.9*VDD
See Note 1
8
Output LOW Current
IOL
5
10
mA
VOL = 0.1*VDD
See Note 1
9
Output Leakage Current
IOZ
0.01
µA
VOUT = VDD and VSS
10
Output Capacitance
Co
15
pF
11
Input Capacitance
Ci
10
pF
V
1.5
10
3.7
V
V
VT-
1.3
10
V
† DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1 - Magnitude measurement, ignore signs.
Clockin Tolerance Characteristics†
Characteristics
1
CLOCKin Frequency (Asynchronous
Mode)
Min.
Typ.‡
Max.
Units
Test Conditions
4095.6
4096
4096.4
kHz
(i.e., 100 ppm)
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
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Zarlink Semiconductor Inc.
MT9162
Data Sheet
AC Characteristics† for A/D (Transmit) Path - 0dBm0 = ALo3.17 - 3.17dB = 1.773Vrms for µ-Law and
0dBm0 = ALo3.14
- 3.14dB = 1.843Vrms for A-Law, at the Codec. (VRef=0.6 volts and VBias=2.5 volts.)
Characteristics
Sym.
1
Analog input equivalent to overload
decision
ALi3.17
ALi3.14
2
Absolute half-channel gain
Min.
Typ.‡
Max.
7.334
7.6
Units
Vp-p
Vp-p
Test Conditions
µ-Law
A-Law
Both at Codec
6.8
dB
Transmit filter gain=0dB
setting.
@1020Hz
0.3
0.6
1.6
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
dB
dB
dB
0 to -30 dBm0
-40 dBm0
-45 dBm0
AIN ± to Dout
GAX1
5.2
3
Gain tracking vs. input level
ITU-T G.714 Method 2
GTX
-0.3
-0.6
-1.6
4
Signal to total Distortion vs. input
level.
ITU-T G.714 Method 2
DQX
35
29
24
5
Transmit Idle Channel Noise
NCX
NPX
6
Gain relative to gain at
4600 Hz
GRX
7
Absolute Delay
DAX
360
µs
at frequency of minimum
delay
8
Group Delay relative to DAX
DDX
750
380
130
750
µs
µs
µs
µs
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
9
Power Supply Rejection
f=1020 Hz
f=0.3 to 3 kHz
f=3 to 4 kHz
f=4 to 50 kHz
6.0
8.5
-71
-45
-0.25
-0.9
-23
-40
PSSR
PSSR1
PSSR2
PSSR3
37
37
40
35
40
12
-69
dBrnC0
dBm0p
-25
-30
0.0
0.25
0.25
-12.5
-25
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
µ-Law
A-Law
±100mV peak signal on
VDD
µ-law
PSSR1-3 not production
tested
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
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Zarlink Semiconductor Inc.
MT9162
Data Sheet
AC Characteristics† for D/A (Receive) Path - 0dBm0 = ALo3.17 - 3.17dB = 1.773Vrms for µ-Law and
- 3.14dB = 1.843Vrms for A-Law, at the Codec. (VRef=0.6 volts and VBias=2.5 volts.)
Characteristics
Sym.
Typ.‡
Min.
ALo3.17
ALo3.14
Max.
0dBm0 = ALo3.14
Units
Test Conditions
µ-Law
A-Law
1
Analog output at the Codec full
scale
2
Absolute half-channel gain.
Din to AOUT±
GAR1
-0.8
3
Gain tracking vs. input level
ITU-T G.714 Method 2
GTR
-0.3
-0.6
-1.6
4
Signal to total distortion vs. input
level.
ITU-T G.714 Method 2
GQR
35
29
24
5
Receive Idle Channel Noise
NCR
NPR
6
Gain relative to gain at 1020Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz
GRR
7
Absolute Delay
DAR
240
µs
at frequency of min. delay
8
Group Delay relative to DAR
DDR
750
380
130
750
µs
µs
µs
µs
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
9
CrosstalkD/A to A/D
A/D to D/A
CTRT
CTTR
dB
dB
G.714.16
ITU-T
7.225
7.481
Vp-p
Vp-p
0
7
-84
-0.25
-0.90
0.8
dB
@1020Hz
0.3
0.6
1.6
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
dB
dB
dB
0 to -30 dBm0
-40 dBm0
-45 dBm0
10
-80
dBrnC0
dBm0p
0.25
0.25
0.25
-12.5
-25
dB
dB
dB
dB
dB
-74
-80
µ-Law
A-Law
† AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
Electrical Characteristics† for Analog Outputs
Characteristics
Sym.
Min.
1
Load impedance at Output
EZL
20k
2
Allowable output capacitive
load
ECL
3
Analog output harmonic distortion
ED
Typ.‡
Max
.
Units
ohms
20
0.5
Test Conditions
across AOUT±
pF
each pin:AOUT+, AOUT-
%
20k ohms load across
AOUT±
VO≤693mVRMS
† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
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Zarlink Semiconductor Inc.
MT9162
Data Sheet
Electrical Characteristics† for Analog Inputs
Characteristics
1
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
Maximum input voltage without
overloading Codec
across AIN+/AIN-
2.90
3.00
VIOLH
Vp-p
A/µ = 0
A/µ = 1
2 Input Impedance
ZI
50
kΩ
AIN+/AIN† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
to VSS
AC Electrical Characteristics† - SSI BUS Synchronous Timing (see Figure 5)
Typ.‡
Max.
Units
1953
ns
BCL=4096 kHz to 512 kHz
122
ns
BCL=4096 kHz
tBCLL
122
ns
BCL=4096 kHz
4 BCL Rise/Fall Time
tR/tF
20
ns
Note 1
5 Strobe Pulse Width
tENW
8 x tBCL
ns
Note 1
6 Strobe setup time before BCL falling
tSSS
70
tBCL-80
ns
7 Strobe hold time after BCL falling
tSSH
80
tBCL-80
ns
Characteristics
Sym.
Min.
1 BCL Clock Period
tBCL
244
2 BCL Pulse Width High
tBCLH
3 BCL Pulse Width Low
Test Conditions
8 Dout High Impedance to Active Low
from Strobe rising
tDOZL
50
ns
CL=150 pF, RL=1K
9 Dout High Impedance to Active High
from Strobe rising
tDOZH
50
ns
CL=150 pF, RL=1K
10 Dout Active Low to High Impedance
from Strobe falling
tDOLZ
50
ns
CL=150 pF, RL=1K
11 Dout Active High to High Impedance
from Strobe falling
tDOHZ
50
ns
CL=150 pF, RL=1K
12 Dout Delay (high and low) from BCL
rising
tDD
50
ns
CL=150 pF, RL=1K
13 Din Setup time before BCL falling
tDIS
20
ns
14 Din Hold Time from BCL falling
tDIH
50
ns
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1:Not production tested, guaranteed by design.
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Zarlink Semiconductor Inc.
MT9162
tBCLH
Data Sheet
tBCL
tR
tF
CLOCKin 70%
(BCL)
30%
tBCLL
tDIS
Din
tDIH
70%
30%
tDD
tDOZL
Dout
70%
30%
tDOZH
STB
tDOLZ
tDOHZ
tSSH
tENW
tSSS
70%
30%
NOTE: Levels refer to% VDD (CMOS I/O)
Figure 5 - SSI Synchronous Timing Diagram
AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 6)
Characteristics
1 Bit Cell Period
Sym.
Typ.‡
Min.
Max.
7812
3906
TDATA
Units
ns
ns
Test Conditions
BCL=128 kHz
BCL=256 kHz
Tj
600
ns
3 Bit 1 Dout Delay from STB going
high
tdda1
Tj+600
ns
CL=150 pF, RL=1K
4 Bit 2 Dout Delay from STB going
high
tdda2
600+
TDATA-Tj
600+
TDATA
600 +
TDATA+Tj
ns
CL=150 pF, RL=1K
5 Bit n Dout Delay from STB going
high
tddan
600 +
(n-1) x
TDATA-Tj
600 +
(n-1) x
TDATA
600 +
(n-1) x
TDATA+Tj
ns
CL=150 pF, RL=1K
n=3 to 8
TDATA1
TDATA-Tj
TDATA+Tj
ns
7 Din Bit n Data Setup time from
STB rising
tSU
TDATA\2
+500ns-Tj
+(n-1) x
TDATA
ns
8 Din Data Hold time from STB
rising
tho
TDATA\2
+500ns+Tj
+(n-1) x
TDATA
ns
2 Frame Jitter
6 Bit 1 Data Boundary
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
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Zarlink Semiconductor Inc.
n=1-8
MT9162
Data Sheet
Tj
STB
70%
30%
tdda2
tdha1
tdda1
Dout
70%
Bit 1
30%
Bit 2
Bit 3
TDATA
TDATA1
tho
tsu
Din
70%
D2
D1
30%
TDATA/2
TDATA
D3
TDATA
NOTE: Levels refer to% VDD (CMOS I/O)
Figure 6 - SSI Asynchronous Timing Diagram
13
Zarlink Semiconductor Inc.
MT9162
3
2
Data Sheet
1
E1
E
n-2 n-1 n
D
A2
A
L
C
eA
B1
α
e
B
Notes:
D1
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
Plastic Dual-In-Line Packages (PDIP) - E Suffix
DIM
8-Pin
16-Pin
18-Pin
20-Pin
Plastic
Plastic
Plastic
Plastic
Min
A
A2
B
B1
Max
Min
Max
0.210 (5.33)
Min
0.210 (5.33)
Max
Min
0.210 (5.33)
Max
0.210 (5.33)
0.115 (2.93) 0.195 (4.95) 0.115 (2.93) 0.195 (4.95) 0.115 (2.93) 0.195 (4.95) 0.115 (2.93) 0.195 (4.95)
0.014
(0.356)
0.022
(0.558)
0.014
(0.356)
0.022
(0.558)
0.014
(0.356)
0.022
(0.558)
0.014
(0.356)
0.022
(0.558)
0.045 (1.15) 0.070 (1.77) 0.045 (1.15) 0.070 (1.77) 0.045 (1.15) 0.070 (1.77) 0.045 (1.15) 0.070 (1.77)
C
0.008
(0.204)
0.015
(0.381)
0.008
(0.204)
0.015
(0.381)
0.008
(0.204)
0.015
(0.381)
0.008
(0.204)
0.015
(0.381)
D
0.348 (8.84)
0.430
(10.92)
0.745
(18.93)
0.840
(21.33)
0.845
(21.47)
0.925
(23.49)
0.925
(23.49)
1.060 (26.9)
D1
0.005 (0.13)
E
0.290 (7.37) 0.330 (8.38) 0.290 (7.37) 0.330 (8.38) 0.290 (7.37) 0.330 (8.38) 0.290 (7.37) 0.330 (8.38)
E1
0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11)
e
0.005 (0.13)
0.005 (0.13)
0.005 (0.13)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.100 BSC (2.54)
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
0.300 BSC (7.62)
e1
eA
L
0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.160 (4.06)
14
Zarlink Semiconductor Inc.
MT9162
DIM
Min
Data Sheet
8-Pin
16-Pin
18-Pin
20-Pin
Plastic
Plastic
Plastic
Plastic
Max
Min
Max
Min
Max
Min
Max
S
a
15°
15°
NOTE: ( ) Millimeters
15
Zarlink Semiconductor Inc.
15°
15°
MT9162
Data Sheet
Pin 1
F
E
A
C
L
H
e
D
L
4 mils (lead coplanarity)
G
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) O1 & O2 are SYMMETRY dimensions
5) A & B Maximum dimensions include allowable mold flash
A1
B
16-Pin
18-Pin
20-Pin
24-Pin
28-Pin
DIM
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
A
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
0.093
(2.35)
0.104
(2.65)
A1
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
0.004
(0.10)
0.012
(0.30)
B
0.014
(0.351)
0.019
(0.488)
0.014
(0.351)
0.019
(0.488)
0.014
(0.351)
0.019
(0.488)
0.014
(0.351)
0.019
(0.488)
0.014
(0.351)
0.019
(0.488)
C
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
0.009
(0.231)
0.013
(0.318)
D
0.398
(10.1)
0.413
(10.5)
0.447
(11.35)
0.469
(11.90)
0.496
(12.60)
0.518
(13.00)
0.598
(15.2)
0.614
(15.6)
0.697
(17.7)
0.712
(18.1)
E
0.291
(7.40)
0.305
(7.75)
0.291
(7.40)
0.305
(7.75)
0.291
(7.40)
0.305
(7.75)
0.291
(7.40)
0.305
(7.75)
0.291
(7.40)
0.305
(7.75)
e
F
0.050 BSC
(1.27 BSC)
0.044
(1.125)
0.064
(1.625)
0.050 BSC
(1.27 BSC)
0.044
(1.125)
0.050 BSC
(1.27 BSC)
0.064
(1.625)
0.044
(1.125)
0.064
(1.625)
16
Zarlink Semiconductor Inc.
0.050 BSC
(1.27 BSC)
0.044
(1.125)
0.064
(1.625)
0.050 BSC
(1.27 BSC)
0.044
(1.125)
0.064
(1.625)
MT9162
16-Pin
18-Pin
Data Sheet
20-Pin
24-Pin
28-Pin
DIM
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
G
0.040
(1.016)
0.050
(1.270)
0.040
(1.016)
0.050
(1.270)
0.040
(1.016)
0.050
(1.270)
0.040
(1.016)
0.050
(1.270)
0.040
(1.016)
0.050
(1.270)
H
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
0.394
(10.00)
0.419
(10.65)
L
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
0.016
(0.40)
0.050
(1.27)
Lead SOIC Package - S Suffix
17
Zarlink Semiconductor Inc.
MT9162
Data Sheet
Pin 1
F
E
A
C
L
H
e
D
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) Ref. JEDEC Standard M0-150
5) A & B Maximum dimensions include allowable mold flash
G
A1
B
Dim
20-Pin
Min
A
A1
0.004
(0.1)
B
0.0087
(0.22)
C
24-Pin
Max
Min
Max
0.079
(2)
-
0.079
(2)
0.004
(0.1)
0.013
(0.33)
0.0087
(0.22)
0.008
(0.21)
28-Pin
Min
Max
Min
Max
0.079
(2)
0.095
(2.41)
0.110
(2.79)
0.008
(0.2)
0.015
(0.4)
0.008
(0.2)
0.0135
(0.34)
0.004
(0.1)
0.013
(0.33)
0.0087
(0.22)
0.008
(0.21)
48-Pin
0.013
(0.33)
0.008
(0.21)
0.010
(0.25)
D
0.27
(6.9)
0.295
(7.5)
0.31
(7.9)
0.33
(8.5)
0.39
(9.9)
0.41
(10.5)
0.62
(15.75)
0.63
(16.00)
E
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.2
(5.0)
0.22
(5.6)
0.291
(7.39)
0.299
(7.59)
e
0.025 BSC
(0.65 BSC)
0.025 BSC
(0.65 BSC)
0.025 BSC
(0.65 BSC)
0.025 BSC
(0.65 BSC)
F
0.049 REF
(1.25 REF)
0.049 REF
(1.25 REF)
0.049 REF
(1.25 REF)
0.056 REF
(1.42 REF)
G
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.065
(1.65)
0.073
(1.85)
0.089
(2.25)
0.099
(2.52)
H
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.29
(7.4)
0.32
(8.2)
0.395
(10.03)
0.42
(10.67)
L
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.022
(0.55)
0.037
(0.95)
0.02
(0.51)
0.04
(1.02)
Small Shrink Outline Package (SSOP) - N Suffix
18
Zarlink Semiconductor Inc.
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