MT9162AN

ISO2-CMOS MT9162 5 Volt Single Rail Codec Data Sheet Features • • • • • • • • • • Single 5 volt supply Programmable µ−law/A-law Codec and filters Fully differential output driver SSI digital interface SSI speed control via external pins CSLO-CSL2 Individual transmit and receive mute controls 0 dB gain in receive path 6 dB gain in transmit path Low power operation ITU-T G.714 compliant Ordering Information MT9162AE 20 Pin PDIP MT9162AS 20 Pin SOIC MT9162AN 20 Pin SSOP MT9162AN1 20 Pin SSOP* *Pb Free Matte Tin -40° C to +85 ° C Tubes Tubes Tubes Tubes May 2006 Description The MT9162 5 V single rail Codec incorporates a builtin Filter/Codec, transmit anti-alias filter, a reference voltage and bias source. The device supports both Alaw and µ-law requirements. The analog interface is capable of driving a 20 k ohm load. The MT9162 is fabricated in Zarlink's ISO2-CMOS technology ensuring low power consumption and high reliability. Applications • • • Cellular radio sets Local area communications stations Line cards FILTER/CODEC GAIN VDD VSS VBias VRef ENCODER DECODER 6dB 0 dB Analog Interface AIN+ AIN- AOUT + AOUT - Din Dout STB CLOCKin PCM Serial Interface Timing Control PWRST IC A/µ CSL0 CSL1 CSL2 RXMute TXMute Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved. MT9162 Data Sheet VBias VRef PWRST IC A/µ RXMUTE TXMUTE CSL0 CSL1 CSL2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 AIN+ AINVSS AOUT + AOUT VDD CLOCKin STB Din Dout 20 PIN PDIP/SOIC/SSOP Figure 2 - Pin Connections Pin Description Pin # 1 2 3 4 5 6 7 8 9 10 11 Name VBias VRef Description Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 µ F capacitor to VSS. Connect 1 µF capacitor to Vref. Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.9] volts. Used internally. Connect 0.1 µ F capacitor to VSS. Connect 1 µF capacitor to VBias PWRST Power-up Reset. Resets internal state of device via Schmitt Trigger input (active low). IC A/µ Internal Connection. Tie externally to VSS for normal operation. A/µ Law Selection. CMOS level compatible input pin governs the companding law used by the device. A-law selected when pin tied to VDD or µ-law selected when pin tied to VSS. RXMute Receive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation. CMOS level compatible. TXMute Transmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal operation. CMOS level compatible. CSL0 CSL1 CSL2 Dout Clock Speed Select. These pins are used to program the speed of the SSI mode as well as the conversion rate between the externally supplied MCL clock and the 512 kHz clock required by the filter/codec. Refer to Table 2 for details. CMOS level compatible. Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1 device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot defined by STB. Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the falling edge of BCL during the timeslot defined by STB. CMOS level compatible. Data Strobe. This input determines the 8-bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatible. 12 13 14 Din STB CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions. Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin when the bit clock is 128 kHz or 256 kHz. CMOS level compatible. VDD Positive Power Supply. Nominally 5 volts. 15 2 Zarlink Semiconductor Inc. MT9162 Pin Description (continued) Pin # 16 17 18 19 20 Name AOUTInverting Analog Output. (balanced). Description Data Sheet AOUT+ Non-Inverting Analog Output. (balanced). VSS AinAin+ Ground. Nominally 0 volts. Inverting Analog Input. No external anti-aliasing is required. Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required. Overview The 5 V single rail Codec features complete Analog/Digital and Digital/Analog conversion of audio signals (Filter/Codec) and an analog interface to a standard analog transmitter and receiver (Analog Interface). The receiver amplifier is capable of driving a 20 k ohm load. Functional Description Filter/Codec The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion. The Filter/Codec block also implements a transmit audio path gain in the analog domain. Figure 3 depicts the nominal half-channel for the MT9162. The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the analog interface section to provide full chip realization of these capabilities for the external functions. A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from VBias to analog ground at all times. Likewise, although VRef may only be used internally, a 0.1µF capacitor from the VRef pin to ground is required at all times. The analog ground reference point for these two capacitors must be physically the same point. To facilitate this the VRef and VBias pins are situated on adjacent pins. The transmit filter is designed to meet ITU-T G.714 specifications. An anti-aliasing filter is included. This is a second order lowpass implementation with a corner frequency at 25 kHz. The receive filter is designed to meet ITU-T G.714 specifications. Filter response is peaked to compensate for the sinx/x attenuation caused by the 8 kHz sampling rate. Companding law selection for the Filter/Codec is provided by the A/ µ companding control pin. Table 1 illustrates these choices. 3 Zarlink Semiconductor Inc. MT9162 Code + Full Scale + Zero -Zero (quiet code) - Full Scale ITU-T (G.711) µ -Law 1000 0000 1111 1111 0111 1111 0000 0000 A-Law 1010 1010 1101 0101 0101 0101 0010 1010 Data Sheet Table 1 - Law Selection Analog Interfaces Standard interfaces are provided by the MT9162. These are: • • The analog inputs (transmitter), pins AIN+/AIN-. The maximum peak to peak input is 3.667Vpp µ−law and across AIN+/AIN- 3.8Vpp A-law. The analog outputs (receiver), pins AOUT+/AOUT-. This internally compensated fully differential output driver is capable of driving a load of 20k ohms. PCM Serial Interface A serial link is required to transport data between the MT9162 and an external digital transmission device. The MT9162 utilizes the strobed data interface found on many standard Codec devices. This interface is commonly referred to as Simple Serial Interface (SSI). The required mode of operation is selected via the CSL2-0 control pins. See Table 2 for selections based in CSL20 pin settings. Quiet Code The PCM serial port can be made to send quiet code to the decoder and receive filter path by setting the RxMute pin high. Likewise, the PCM serial port will send quiet code in the transmit path when the External Clock Bit Rate (kHz) 128 256 512 1536 2048 4096 CSL2 1 1 0 0 0 0 CSL1 0 0 0 0 1 1 CSL0 0 1 0 1 0 1 CLOCKin (kHz) 4096 4096 512 1536 2048 4096 Figure 2 - Table 2: Bit Clock Rate Selection TxMute pin is high. When either of these pins are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet code definition. 4 Zarlink Semiconductor Inc. MT9162 SSI Mode Data Sheet The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input signal (CLOCKin), and a framing strobe input (STB). A 4.096 MHz master clock is also required for SSI operation if the bit clock is less than 512 kHz. The timing requirements for SSI are shown in Figures 5 & 6. In SSI mode the MT9162 supports only B-Channel operation. Hence, in SSI mode transmit and receive B-Channel data are always in the channel defined by the STB input. The data strobe input STB determines the 8-bit timeslot used by the device for both transmit and receive data. This is an active high signal with an 8 kHz repetition rate. SSI operation is separated into two categories based upon the data rate of the available bit clock. If the bit clock is 512 kHz or greater then it is used directly by the internal MT9162 functions allowing synchronous operation. If the available bit clock is 128 kHz or 256 kHz, then a 4096 kHz master clock is required to derive clocks for the internal MT9162 functions. Applications where Bit Clock (BCL) is below 512 kHz are designated as asynchronous. The MT9162 will re-align its internal clocks to allow operation when the external master and bit clocks are asynchronous. Control pins CSL2, CSL1 and CSL0 are used to program the bit rates. Serial Port Filter/Codec and Analog Interface Aout + Decoder 2.05 dB Receive Filter Gain 0 dB -2.05 dB Receiver Driver 20kΩ PCM Din Aout- PCM Dout Encoder -2.05 dB Transmit Filter Transmit Filter Gain Gain 0 to0dB dB +7 (1 dB steps) Transmit Gain -0.37 dB Transmit Gain 8.42 dB AIN+ AIN- Analog Input Internal To Device External To Device Figure 3 - Audio Gain Partitioning For synchronous operation, data is sampled from Din, on the falling edge of BCL during the time slot defined by the STB input. Data is made available, on Dout, on the rising edge of BCL during the time slot defined by the STB input. Dout is tri-stated at all times when STB is not true. If STB is valid, then quiet code will be transmitted on Dout during the valid strobe period. There is no frame delay through the PCM serial circuit for synchronous operation. 5 Zarlink Semiconductor Inc. MT9162 Data Sheet For asynchronous operation Dout and Din are as defined for synchronous operation except that the allowed output jitter on Dout is larger. This is due to the resynchronization circuitry activity and will not affect operation since the bit cell period at 128 kb/s and 256 kb/s is relatively large. There is a one frame delay through the PCM serial circuit for asynchronous operation. Refer to the specifications of Figures 5 & 6 for both synchronous and asynchronous SSI timing. PWRST While the MT9162 is held in PWRST no device control or functionality is possible. Applications Figure 4 shows the MT9162 in a line card application. VBias 1 µF 0.1 µF 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 0.1 µF ( Typical External Gain AV= 5-10 ) Input from Subscriber Line Interface +5V 100k 100k 1k 100k 1k 100k 1k 100k 1k 100k 1k 100k 1k CS2 CS0 CS1 A/µ RxMUTE TxMUTE MT9162 Out to Subscriber Line Interface +5V DC to DC Converter +5V Din Lin MT8972 Dout Frame Pulse From Digital Phone Twisted Pair ZT Lout DNIC Clock F igure 4 - Line Card Application 6 Zarlink Semiconductor Inc. MT9162 Absolute Maximum Ratings† Parameter 1 2 3 4 5 † Data Sheet Symbol VDD - VSS VI/VO II/IO TS PD Min. - 0.3 VSS - 0.3 - 65 Max. 7 VDD + 0.3 ± 20 + 150 750 Units V V mA °C mW Supply Voltage Voltage on any I/O pin Current on any I/O pin (transducers excluded) Storage Temperature Power Dissipation (package) Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated Characteristics 1 2 3 4 Supply Voltage CMOS Input Voltage (high) CMOS Input Voltage (low) Operating Temperature Sym. VDD VIHC VILC TA Min. 4.75 4.5 VSS - 40 Typ. 5 Max. 5.25 VDD 0.5 + 85 Units V V V °C Test Conditions Power Characteristics Characteristics 1 2 Static Supply Current (clock disabled) Dynamic Supply Current: Total all functions enabled Sym. IDDC1 Min. Typ. 4 Max. 20 Units µA Test Conditions Outputs unloaded, Input signals static, not loaded See Note 1 IDDFT 7.0 10 mA Note 1: Power delivered to the load is in addition to the bias current requirements. 7 Zarlink Semiconductor Inc. MT9162 DC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 Input HIGH Voltage CMOS inputs Input LOW Voltage CMOS inputs VBias Voltage Output VRef Output Voltage Input Leakage Current Positive Going Threshold Voltage (PWRST only) Negative Going Threshold Voltage (PWRST only) Output HIGH Current Output LOW Current Output Leakage Current Output Capacitance Input Capacitance Sym. VIHC VILC VBias VRef IIZ VT+ VTIOH IOL IOZ Co Ci 3 5 7 10 0.01 15 10 10 3.7 1.3 VDD/2 VDD/21.9 0.1 10 Min. 3.5 1.5 Typ.‡ Max. Units V V V V µA V V mA mA µA pF pF Data Sheet Test Conditions Max. Load = 10kΩ No load VIN=VDD to VSS 7 8 9 10 11 VOH = 0.9*VDD See Note 1 VOL = 0.1*VDD See Note 1 VOUT = VDD and VSS † DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. * Note 1 - Magnitude measurement, ignore signs. Clockin Tolerance Characteristics† Characteristics 1 CLOCKin Frequency (Asynchronous Mode) Min. 4095.6 Typ.‡ 4096 Max. 4096.4 Units kHz Test Conditions (i.e., 100 ppm) † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. 8 Zarlink Semiconductor Inc. MT9162 AC Characteristics† for A/D (Transmit) Path - 0dBm0 = ALo3.17 - 3.17dB = 1.773Vrms for µ-Law and - 3.14dB = 1.843Vrms for A-Law, at the Codec. (VRef=0.6 volts and VBias=2.5 volts.) Data Sheet 0dBm0 = ALo3.14 Characteristics 1 Analog input equivalent to overload decision Absolute half-channel gain AIN ± to Dout 3 Gain tracking vs. input level ITU-T G.714 Method 2 Signal to total Distortion vs. input level. ITU-T G.714 Method 2 Transmit Idle Channel Noise Gain relative to gain at 4600 Hz Absolute Delay Group Delay relative to DAX Sym. ALi3.17 ALi3.14 Min. Typ.‡ 7.334 7.6 Max. Units Vp-p Vp-p Test Conditions µ-Law A-Law Both at Codec Transmit filter gain=0dB setting. @1020Hz 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0 µ-Law A-Law 2 GAX1 GTX 5.2 -0.3 -0.6 -1.6 35 29 24 6.0 6.8 0.3 0.6 1.6 dB dB dB dB dB dB dB 4 DQX 5 6 NCX NPX GRX 8.5 -71 12 -69 -25 -30 0.0 0.25 0.25 -12.5 -25 dBrnC0 dBm0p dB dB dB dB dB dB dB µs µs µs µs µs -45 -0.25 -0.9 -23 -40 DAX DDX 360 750 380 130 750 7 8 at frequency of minimum delay 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz ±100mV peak signal on VDD µ-law PSSR1-3 not production tested 9 Power Supply Rejection f=1020 Hz f=0.3 to 3 kHz f=3 to 4 kHz f=4 to 50 kHz PSSR PSSR1 PSSR2 PSSR3 37 37 40 35 40 dB dB dB dB † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. 9 Zarlink Semiconductor Inc. MT9162 AC Characteristics† for D/A (Receive) Path - 0dBm0 = ALo3.17 - 3.17dB = 1.773Vrms for µ-Law and - 3.14dB = 1.843Vrms for A-Law, at the Codec. (VRef=0.6 volts and VBias=2.5 volts.) Characteristics 1 2 3 Analog output at the Codec full scale Absolute half-channel gain. Din to AOUT± Gain tracking vs. input level ITU-T G.714 Method 2 Signal to total distortion vs. input level. ITU-T G.714 Method 2 Receive Idle Channel Noise Gain relative to gain at 1020Hz 200Hz 300 - 3000 Hz 3000 - 3400 Hz 4000 Hz >4600 Hz Absolute Delay Group Delay relative to DAR Sym. ALo3.17 ALo3.14 GAR1 GTR -0.8 -0.3 -0.6 -1.6 35 29 24 7 -84 10 -80 0.25 0.25 0.25 -12.5 -25 240 750 380 130 750 -74 -80 Min. Typ.‡ 7.225 7.481 0 0.8 0.3 0.6 1.6 Max. Units Vp-p Vp-p dB dB dB dB dB dB dB dBrnC0 dBm0p dB dB dB dB dB µs µs µs µs µs dB dB Data Sheet 0dBm0 = ALo3.14 Test Conditions µ-Law A-Law @1020Hz 3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0 µ-Law A-Law 4 GQR 5 6 NCR NPR GRR -0.25 -0.90 7 8 DAR DDR at frequency of min. delay 500-600 Hz 600 - 1000 Hz 1000 - 2600 Hz 2600 - 2800 Hz G.714.16 ITU-T 9 CrosstalkD/A to A/D A/D to D/A CTRT CTTR † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Electrical Characteristics† for Analog Outputs Characteristics 1 2 3 Load impedance at Output Allowable output capacitive load Analog output harmonic distortion Sym. EZL ECL ED Min. 20k 20 0.5 Typ.‡ Max . Units ohms pF % Test Conditions across AOUT± each pin:AOUT+, AOUT20k ohms load across AOUT± VO≤693mVRMS † Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. 10 Zarlink Semiconductor Inc. MT9162 Electrical Characteristics† for Analog Inputs Characteristics 1 Maximum input voltage without overloading Codec across AIN+/AINVIOLH 2.90 3.00 Vp-p A/µ = 0 A/ µ = 1 Sym. Min. Typ.‡ Max. Units Data Sheet Test Conditions 2 Input Impedance ZI 50 kΩ AIN+/AIN† Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. to VSS AC Electrical Characteristics† - SSI BUS Synchronous Timing (see Figure 5) Characteristics 1 BCL Clock Period 2 BCL Pulse Width High 3 BCL Pulse Width Low 4 BCL Rise/Fall Time 5 Strobe Pulse Width 6 Strobe setup time before BCL falling 7 Strobe hold time after BCL falling 8 Dout High Impedance to Active Low from Strobe rising 9 Dout High Impedance to Active High from Strobe rising 10 Dout Active Low to High Impedance from Strobe falling 11 Dout Active High to High Impedance from Strobe falling 12 Dout Delay (high and low) from BCL rising 13 Din Setup time before BCL falling 14 Din Hold Time from BCL falling Sym. tBCL tBCLH tBCLL tR/tF tENW tSSS tSSH tDOZL tDOZH tDOLZ tDOHZ tDD tDIS tDIH 20 50 70 80 Min. 244 122 122 20 8 x tBCL tBCL-80 tBCL-80 50 50 50 50 50 Typ.‡ Max. 1953 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL=150 pF, RL=1K CL=150 pF, RL=1K CL=150 pF, RL=1K CL=150 pF, RL=1K CL=150 pF, RL=1K Test Conditions BCL=4096 kHz to 512 kHz BCL=4096 kHz BCL=4096 kHz Note 1 Note 1 † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. NOTE 1:Not production tested, guaranteed by design. 11 Zarlink Semiconductor Inc. MT9162 tBCL tF Data Sheet tBCLH tR CLOCKin 70% (BCL) 30% tBCLL tDIS Din 70% 30% tDOZL Dout 70% 30% tDOZH tSSS STB 70% 30% NOTE: Levels refer to% VDD (CMOS I/O) tENW tSSH tDOLZ tDOHZ tDD tDIH Figure 5 - SSI Synchronous Timing Diagram AC Electrical Characteristics† - SSI BUS Asynchronous Timing (note 1) (see Figure 6) Characteristics 1 Bit Cell Period 2 Frame Jitter 3 Bit 1 Dout Delay from STB going high 4 Bit 2 Dout Delay from STB going high 5 Bit n Dout Delay from STB going high Sym. TDATA Tj tdda1 tdda2 tddan 600+ TDATA-Tj 600 + (n-1) x TDATA-Tj TDATA-Tj TDATA\2 +500ns-Tj +(n-1) x TDATA TDATA\2 +500ns+Tj +(n-1) x TDATA 600+ TDATA 600 + (n-1) x TDATA Min. Typ.‡ 7812 3906 600 Tj+600 600 + TDATA+Tj 600 + (n-1) x TDATA+Tj TDATA+Tj Max. Units ns ns ns ns ns ns CL=150 pF, RL=1K CL=150 pF, RL=1K CL=150 pF, RL=1K n=3 to 8 Test Conditions BCL=128 kHz BCL=256 kHz 6 Bit 1 Data Boundary 7 Din Bit n Data Setup time from STB rising TDATA1 tSU ns ns n=1-8 8 Din Data Hold time from STB rising tho ns † Timing is over recommended temperature range & recommended power supply voltages. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. 12 Zarlink Semiconductor Inc. MT9162 Data Sheet Tj STB 70% 30% tdda2 tdha1 tdda1 70% 30% Dout Bit 1 TDATA1 tho tsu Bit 2 Bit 3 TDATA Din 70% 30% TDATA/2 D1 TDATA D2 TDATA D3 NOTE: Levels refer to% VDD (CMOS I/O) Figure 6 - SSI Asynchronous Timing Diagram 13 Zarlink Semiconductor Inc. MT9162 3 2 1 Data Sheet E1 E n-2 n-1 n D A2 L B1 Notes: D1 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) A C eA e B α Plastic Dual-In-Line Packages (PDIP) - E Suffix 8-Pin DIM Min A A2 B B1 C D D1 E E1 e e1 eA L 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) 0.300 BSC (7.62) Plastic Max 0.210 (5.33) Min 16-Pin Plastic Max 0.210 (5.33) Min 18-Pin Plastic Max 0.210 (5.33) Min 20-Pin Plastic Max 0.210 (5.33) 0.115 (2.93) 0.195 (4.95) 0.115 (2.93) 0.195 (4.95) 0.115 (2.93) 0.195 (4.95) 0.115 (2.93) 0.195 (4.95) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.045 (1.15) 0.070 (1.77) 0.045 (1.15) 0.070 (1.77) 0.045 (1.15) 0.070 (1.77) 0.045 (1.15) 0.070 (1.77) 0.008 (0.204) 0.348 (8.84) 0.005 (0.13) 0.015 (0.381) 0.430 (10.92) 0.008 (0.204) 0.745 (18.93) 0.005 (0.13) 0.015 (0.381) 0.840 (21.33) 0.008 (0.204) 0.845 (21.47) 0.005 (0.13) 0.015 (0.381) 0.925 (23.49) 0.008 (0.204) 0.925 (23.49) 0.005 (0.13) 0.015 (0.381) 1.060 (26.9) 0.290 (7.37) 0.330 (8.38) 0.290 (7.37) 0.330 (8.38) 0.290 (7.37) 0.330 (8.38) 0.290 (7.37) 0.330 (8.38) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.100 BSC (2.54) 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.160 (4.06) 14 Zarlink Semiconductor Inc. MT9162 8-Pin DIM Min S a NOTE: ( ) Millimeters Data Sheet 18-Pin Plastic 20-Pin Plastic Max Min Max 16-Pin Plastic Max Min Max Min Plastic 15° 15° 15° 15° 15 Zarlink Semiconductor Inc. MT9162 Pin 1 F Data Sheet E A L H C e D G 4 mils (lead coplanarity) Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) O1 & O2 are SYMMETRY dimensions 5) A & B Maximum dimensions include allowable mold flash L A1 B 16-Pin DIM Min A A1 B C D E e F 0.093 (2.35) 0.004 (0.10) 0.014 (0.351) 0.009 (0.231) 0.398 (10.1) 0.291 (7.40) Max 0.104 (2.65) 0.012 (0.30) 0.019 (0.488) 0.013 (0.318) 0.413 (10.5) 0.305 (7.75) Min 18-Pin Max 0.104 (2.65) 0.012 (0.30) 0.019 (0.488) 0.013 (0.318) 0.469 (11.90) 0.305 (7.75) Min 20-Pin Max 0.104 (2.65) 0.012 (0.30) 0.019 (0.488) 0.013 (0.318) 0.518 (13.00) 0.305 (7.75) Min 24-Pin Max 0.104 (2.65) 0.012 (0.30) 0.019 (0.488) 0.013 (0.318) 0.614 (15.6) 0.305 (7.75) Min 28-Pin Max 0.104 (2.65) 0.012 (0.30) 0.019 (0.488) 0.013 (0.318) 0.712 (18.1) 0.305 (7.75) 0.093 (2.35) 0.004 (0.10) 0.014 (0.351) 0.009 (0.231) 0.447 (11.35) 0.291 (7.40) 0.093 (2.35) 0.004 (0.10) 0.014 (0.351) 0.009 (0.231) 0.496 (12.60) 0.291 (7.40) 0.093 (2.35) 0.004 (0.10) 0.014 (0.351) 0.009 (0.231) 0.598 (15.2) 0.291 (7.40) 0.093 (2.35) 0.004 (0.10) 0.014 (0.351) 0.009 (0.231) 0.697 (17.7) 0.291 (7.40) 0.050 BSC (1.27 BSC) 0.044 (1.125) 0.064 (1.625) 0.050 BSC (1.27 BSC) 0.044 (1.125) 0.064 (1.625) 0.050 BSC (1.27 BSC) 0.044 (1.125) 0.064 (1.625) 0.050 BSC (1.27 BSC) 0.044 (1.125) 0.064 (1.625) 0.050 BSC (1.27 BSC) 0.044 (1.125) 0.064 (1.625) 16 Zarlink Semiconductor Inc. MT9162 16-Pin DIM Min G H L 0.040 (1.016) 0.394 (10.00) 0.016 (0.40) Max 0.050 (1.270) 0.419 (10.65) 0.050 (1.27) Min 0.040 (1.016) 0.394 (10.00) 0.016 (0.40) Max 0.050 (1.270) 0.419 (10.65) 0.050 (1.27) Min 0.040 (1.016) 0.394 (10.00) 0.016 (0.40) Max 0.050 (1.270) 0.419 (10.65) 0.050 (1.27) Min 0.040 (1.016) 0.394 (10.00) 0.016 (0.40) Max 0.050 (1.270) 0.419 (10.65) 0.050 (1.27) Min 18-Pin 20-Pin 24-Pin Data Sheet 28-Pin Max 0.050 (1.270) 0.419 (10.65) 0.050 (1.27) 0.040 (1.016) 0.394 (10.00) 0.016 (0.40) Lead SOIC Package - S Suffix 17 Zarlink Semiconductor Inc. MT9162 Pin 1 Data Sheet F E A L H C e D G A1 B Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard M0-150 5) A & B Maximum dimensions include allowable mold flash Dim A A1 B C D E e F G H L 20-Pin Min Max 0.079 (2) 0.004 (0.1) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.21) 0.27 (6.9) 0.2 (5.0) 0.295 (7.5) 0.22 (5.6) 24-Pin Min 0.004 (0.1) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.21) 0.31 (7.9) 0.2 (5.0) 0.33 (8.5) 0.22 (5.6) Max 0.079 (2) 28-Pin Min Max 0.079 (2) 0.004 (0.1) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.21) 0.39 (9.9) 0.2 (5.0) 0.41 (10.5) 0.22 (5.6) 48-Pin Min 0.095 (2.41) 0.008 (0.2) 0.008 (0.2) Max 0.110 (2.79) 0.015 (0.4) 0.0135 (0.34) 0.010 (0.25) 0.62 (15.75) 0.291 (7.39) 0.63 (16.00) 0.299 (7.59) 0.025 BSC (0.65 BSC) 0.049 REF (1.25 REF) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.65 BSC) 0.049 REF (1.25 REF) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.65 BSC) 0.049 REF (1.25 REF) 0.065 (1.65) 0.29 (7.4) 0.022 (0.55) 0.073 (1.85) 0.32 (8.2) 0.037 (0.95) 0.025 BSC (0.65 BSC) 0.056 REF (1.42 REF) 0.089 (2.25) 0.395 (10.03) 0.02 (0.51) 0.099 (2.52) 0.42 (10.67) 0.04 (1.02) Small Shrink Outline Package (SSOP) - N Suffix 18 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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