VSC8489-02 Datasheet
Dual Channel WAN/LAN/Backplane RXAUI/XAUI to
SFP+/KR 10 GbE SerDes PHY
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Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of
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VMDS-10502. 4.0 11/18
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
Revision 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1
2.2
Major Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
Data Path Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.1
Ingress Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.2
Egress Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.3
Interface Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Physical Medium Attachment (PMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1
VScope Input Signal Monitoring Integrated Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WAN Interface Sublayer (WIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.2
Section Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.3
Line Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.4
SPE Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.5
Path Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.6
Defects and Anomalies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3.7
Interrupt Pins and Interrupt Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3.8
Overhead Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3.9
Pattern Generator and Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10G Physical Coding Sublayer (64B/66B PCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.1
Control Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.2
Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.3
Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.4
PCS Standard Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1G Physical Coding Sublayer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Rate Compensating Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Cross-Connect (Non-Hitless Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Host-Side Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.9.1
RXAUI Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.10.1 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.10.2 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.10.3 Synchronous Ethernet Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.11.1 10G LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.11.2 10G WAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.11.3 1 GbE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Management Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.12.1 MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.12.2 SPI Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.12.3 Two-Wire Serial (Slave) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.12.4 Two-Wire Serial (Master) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.12.5 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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3.12.6
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1
5.2
5.3
5.4
6
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1
DC Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1
Receiver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2
Transmitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3
Timing and Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.4
Two-Wire Serial (Slave) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.5
MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.6
SPI Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
59
60
60
60
64
68
69
70
71
73
73
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1
6.2
6.3
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Pins by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.1
7.2
7.3
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
Low-power mode and SerDes calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-power mode should not be enabled when failover switching is enabled . . . . . . . . . . . . . . . . . . . .
Flow control with failover switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XAUI BIST Checker Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI bus speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO as TOSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10GBASE-KR auto negotiation and training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loopbacks in 10G WAN mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10/100M mode not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limited access to registers during failover cross-connect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limited auto negotiation support in 1G mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limited 1G status reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RXCKOUT squelching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
94
94
94
94
94
94
94
94
95
95
95
95
9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Figures
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Figure 40
Figure 41
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Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
VSC8489-02 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SFP/SFP+ Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Backplane Equalization Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
10GBASE-KR Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
KR Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WIS Transmit and Receive Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WIS Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
STS-192c/STM-64 Section and Line Overhead Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Path Overhead Octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Primary Synchronization State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Secondary Synchronization State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16-bit Designations within Payload Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pointer Interpreter State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TOSI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ROSI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PCS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
64B/66B Block Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Host-Side and Line-Side Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Cross-Connect Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Host-Side I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10G LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10G WAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1 GbE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SPI Single Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI Multiple Register Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI Multiple Register Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI Read Following Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI Write Following Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI Slave Default Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SPI Slave Fast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Two-Wire Serial Bus Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Two-Wire Serial Slave Register Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Two-Wire Serial Write Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Two-Wire Serial Read Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SFI Datacom Sinusoidal Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
XAUI Receiver Input Sinusoidal Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SFI Transmit Differential Output Compliance Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
XAUI Output Compliance Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
XREFCK to Data Output Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Two-Wire Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Timing with MDIO Sourced by STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Timing with MDIO Sourced by MMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3-Pin Push-Out SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
iii
Tables
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
Table 85
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Table 93
Table 94
Table 95
Table 96
Table 97
Table 98
Table 99
Table 100
Table 101
Table 102
Table 103
Table 104
Table 105
Table 106
Table 107
Table 108
Table 109
Table 110
Interface Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Section Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Framing Parameter Description and Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Line Overhead Octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
K2 Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SONET/SDH Pointer Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
H1/H2 Pointer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Concatenation Indication Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pointer Interpreter State Diagram Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STS Path Overhead Octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Path Status (G1) Byte for RDI-P Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Path Status (G1) Byte for ERDI-P Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
RDI-P and ERDI-P Bit Settings and Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PMTICK Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Defects and Anomalies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
TOSI/ROSI Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Control Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Host-Side Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Line-Side Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Failover and Broadcasting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
RXAUI Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Supported Reference Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
XREFCK Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Supported Clock Rates and Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MDIO Port Addresses Per Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SPI Slave Instruction Bit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
GPIO Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
JTAG Instructions and Register Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
LVTTL Input and Push/Pull Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
LVTTLOD Input and Open-Drain Output DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Reference Clock DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Line-Side 10G Receiver Input (SFI Point D 9.95328G) AC Characteristics . . . . . . . . . . . . . . . . . . 60
Line-Side SONET 10G Input Jitter AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Host-Side RXAUI Receiver AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Host-Side XAUI Receiver AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Line-Side 1.25 Gbps SFI Input AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Host-Side 1.25 Gbps (1000BASE-KX) Receiver Input AC Characteristics . . . . . . . . . . . . . . . . . . . 64
Line-Side 10G Transmitter Output (SFI Point B) AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 64
Transmitter SFP+ Direct Attach Copper Output AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 65
10 Gbps Transmitter 10GBASE-KR AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Line-Side SONET 10G Output Jitter AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Near-end RXAUI Transmitter Output AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Far-end RXAUI Transmitter Output AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Far-end XAUI Transmitter Output AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Line-Side 1.25 Gbps SFI Output AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Host-Side Transmitter 1000BASE-KX AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Reference Clock AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Two-Wire Serial Interface AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
MDIO Interface AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Clock Output AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI Slave Interface AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3-Pin Push-Out SPI AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
iv
Table 111
Table 112
Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
v
Revision History
1
Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1
Revision 4.1
Revision 4.1 was published in September 2018. In revision 4.1 of this document, the registers were
attached. For more information, see Registers, page 58.
1.2
Revision 4.0
Revision 4.0 was published in November 2017. The following is a summary of the changes in
revision 4.0 of this document.
•
•
•
•
•
•
•
•
1.3
Low-voltage transistor-to-transistor logic (LVTTL) updated to low-voltage transistor-to-transistor logic
with open-drain output (LVTTLOD) where appropriate.
The two-wire serial slave interface register address illustrations and 24-bit addressing scheme
details were updated. For more information, see Two-Wire Serial (Slave) Interface, page 52.
Line-side 10G receiver input AC characteristics were updated. For more information, see Table 32,
page 60.
Conditions for transmitter SFP+ direct attach copper output AC characteristics were updated. For
more information, see Table 39, page 65.
Reference clock AC characteristics were updated. For more information, see Table 47, page 68.
The SPI interface timing diagram was updated. For more information, see Figure 43, page 72.
Some pin description information was updated. For more information, see Pins by Function,
page 76.
Moisture sensitivity level (MSL) was corrected from 2 to 4. For more information, see Moisture
Sensitivity, page 93.
Revision 2.0
Revision 2.0 was published in September 2017. It was the first publication of this document.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
1
Overview
2
Overview
The VSC8489-02 device is a dual-port 10G/1G WAN/LAN/Backplane RXAUI/XAUI to SFP+/KR 10 GbE
SerDes PHY. It supports IEEE 802.3ae.
The VSC8489-02 is a dual-channel device for timing-critical applications. It is also well suited for optical
module, copper Twinax cable, and backplane applications with support for a wide variety of protocols,
including 10 GbE LAN, 10 Gb WAN, and 1 Gb Legacy Ethernet.
The VSC8489-02 device meets the SFP+ limiting and linear SR/LR/ER/ZR/220MMF host requirements
in accordance with the SFF-8431 specifications. It also compensates for electrical and optical
impairments in SFP+ applications, along with imperfections of the PCB and connectors.
The VSC8489-02 device provides a complete suite of BIST functionality, including line and client
loopbacks, along with pattern generation and error detection. Highly flexible clocking options support
LAN and WAN operation using single 156.25 MHz reference clock rate inputs for seamless Synchronous
Ethernet support. The VSC8489-02 device also includes a failover switching capability for protection
routing, along with selectable lane ordering.
The serial side supports 1.25 Gbps and various 10 Gbps modes. Each channel consists of a receiver
(Rx) and a transmitter (Tx) subsection. Three programmable reference clock inputs (XREFCK, SREFCK,
and WREFCK) support the various modes along with clock and data recovery (CDR) in the Rx and Tx
subsections of all channels.
The following illustration shows a high-level block diagram for the VSC8489-02 device.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
2
2.1
•
SPI/MDIO/
Two-Wire Serial
XAUI/RXAUI/
4/2/1
1 GbE
2x 2 × 6.25G
2x 4 × 3.125G
2x 1 × 1.25G
XAUI/RXAUI/
4/2/1
1 GbE
SD6G
SD6G
SD6G
SD6G
SD6G
SD6G
SD6G
MDIO
Two-Wire Serial Slave
1G
PCS
XGXS
XGXS
1G
PCS
1G
PCS
10G
PCS
10G
PCS
1G
PCS
SPI
WIS
WIS
SD10G
SD10G
Line LC-PLL
Two-Wire Serial Master
Switch
Clocking Network for Timing and Retiming Including SyncE Support
Two-Wire Serial
SFP/SFP+
2 × 10G
2 × 1G
SFP/SFP+
Figure 1 •
SD6G
Host LC-PLL
Overview
VSC8489-02 Block Diagram
Line
Host/Client
Major Applications
Multiple-port RXAUI/XAUI to SFI/SFP+ line cards or network interface controllers
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
3
Overview
•
•
•
Carrier Ethernet networks
Secure data center-to-data center interconnects
10 GbE switch cards, router cards, and NICs
The following illustrations show the various applications for the VSC8489-02 device.
Figure 2 •
SFP/SFP+ Application
2 × 10G
2 × 1G
RXAUI/XAUI
Dual
10 GbE
MAC/NIC
Figure 3 •
2/4
SFP/SFP+/XFP
VSC8489-02
2/4
10 GbE
10 GbE Line Card or NIC
SFP/SFP+/XFP
Backplane Equalization Application
Switch Module
2/4
VSC8489-02
2 × 10G/
2 × 1G
2/4
RXAUI/
XAUI
RXAUI/
XAUI
Switch
10GBASE-KR
Backplane
2.2
Features and Benefits
The main features of the VSC8489-02 device are as follows:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Compliant to IEEE 802.3ae and SFF-8431 electrical (SFI) specifications
9.95 Gbps WAN, 10.3125 Gbps LAN, and 1.25 Gbps Ethernet support
Supports all standard SFP+ applications
Adaptive receive equalization with programmable, multitap transmit pre-emphasis
Extended WIS support
MDIO, SPI, and two-wire serial slave management interfaces
Failover switching for protection routing, along with selectable lane ordering (non-hitless switching)
VScope™ input signal monitoring integrated circuit
Host-side and line-side loopbacks with BIST functions
I/O programmability for lane swap, invert, amplitude, slew, pre-emphasis, and equalization
Optional forward error correction (FEC)
Flexible clocking options for Synchronous Ethernet support
Passive copper cable compliant to SFF-8431 is supported for minimum transmission cost
Pin-friendly with VSC8488
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
4
Functional Descriptions
3
Functional Descriptions
This section describes the functional aspects of the VSC8489-02 device, including the functional block
diagram, operating modes, and major functional blocks.
The VSC8489-02 device host-side interface is either four-lane XAUI, two-lane RXAUI, or one-lane
1 GbE. The line-side interface is 10G SFP+ or 1 GbE SFP.
Each lane has the following main sections:
•
•
•
•
•
•
•
•
•
•
•
3.1
PMA
The PMA section contains the high-speed serial I/O interfaces, an input equalization circuit, a KRcompliant output buffer, and a SerDes. Additionally, the PMA also generates all the line-side clocks,
including the clocks required for Synchronous Ethernet applications.
WIS
The WIS section contains the framing and de-framing circuits and control and status registers to
convert the data to be IEEE 802.3ae WIS-compliant.
10G PCS
The 10G PCS section is composed of the PCS transmit, PCS receive, block synchronization, and
BER monitor processes. The PCS functions can be further broken down into encode or decode,
scramble or descramble, and gearbox functions, as well as various test and loopback modes.
1G PCS
The 1G PCS section describes the 1000BASE-X/SGMII coding and auto-negotiation processes.
There are two instances per channel, one for the host and one for the line.
FIFO
The FIFO section contains a rate-compensating FIFO between the line rate and the host rate.
Cross Connect
The cross connect connects one port to the adjacent port to enable routing data/clock to and from
port 1 and 0. This cross connect only supports broadcasting from PMA to XAUI but NOT from XAUI
to PMA. The failover supported by this cross connect is not hitless.
XGXS
The XGXS implements the PHY XGXS referenced in IEEE 802.3 Clause 47, and contains a
10GBASE-X PCS as defined in Clause 48. It provides the necessary translation between the
external XAUI interface and the on-chip XGMII interface. In addition to standard 4-lane XAUI, it also
supports 2-lane RXAUI/DDR-XAUI.
XAUI/RXAUI
The XAUI and RXAUI section contains the parallel XAUI/RXAUI I/O interface and a SerDes.
KR
The KR driver includes programmable equalization accomplished by a three-tap finite impulse
response (FIR) structure. Three-tap delays are achieved by three flip-flops clocked by a high-speed
serial clock (10 GHz in 10G mode; 1 GHz in 1G mode).
Loopback
The loopback sections describe the different loopbacks available in the VSC8489-02 device,
including system and network loopbacks. The various loopbacks enhance the engineering
debugging and manufacturing testing capability.
Management
The management section contains the status and configuration registers and the serial management
interface logic to access them.
Data Path Overview
The following sections provide data path information for the VSC8489-02 device. Ingress and egress
data flow is relative to the line-side interface.
3.1.1
Ingress Operation
Data is received by the line-side interface (SFP+/1 GbE), processed by core logic, and transmitted from
the host-side interface (XAUI/RXAUI/1 GbE) in the ingress (or line-side receive) data path.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
5
Functional Descriptions
High-speed serial data is received by the PMA. Data can be equalized and is delivered to the clock
recovery unit (CRU). The received serial data must be a 66B/64B encoded ethernet frame at
10.3125 Gbps in 10G LAN mode, a SONET/SDH STS-192c frame at 9.953 Gbps in 10G WAN mode, or
8B/10B encoded data at 1.25 Gbps in 1 GbE mode.
In 10G WAN mode, the CRU data is processed by the WIS where 66B/64B encoded ethernet data is
extracted from SONET/SDH STS-192c frames and overhead bytes are processed. The extracted
payload data is then processed by the 10G PCS. In 10G LAN mode, the CRU data is processed by a
10G PCS. In 1G mode, the CRU data is processed by the line-side 1G PCS.
In 10G LAN and WAN modes, data from the core is 8B/10B encoded by the XGXS logic and serialized in
the host-side SerDes. The host interface can be configured as a XAUI interface where four lanes of
3.125 Gbps data is transmitted, or as a RXAUI interface where two lanes of 6.25 Gbps data is
transmitted. Data is transmitted on XAUI lanes 0 and 2 when the host interface is configured to be
RXAUI.
In 1 GbE mode, data from the core is 8B/10B encoded by the host-side 1G PCS logic and serialized in
the host-side SerDes. 1.25 Gbps data is transmitted from the host interface on either XAUI lane 0 or 3.
When 1 GbE data is transmitted from XAUI lane 0, data received by the host interface must enter on lane
0. When 1 GbE data is transmitted from XAUI lane 3, data received by the host interface must enter on
lane 3.
3.1.2
Egress Operation
Data is received by the host-side interface (XAUI/RXAUI/1 GbE), processed by core logic, and
transmitted from the line-side interface (SFP+/1 GbE) in the egress (or line-side transmit) data path.
The host-side interface can be configured to receive XAUI or RXAUI data when in 10G LAN or 10G WAN
modes. Data enters the part on XAUI lanes 0 and 2 when using the RXAUI interface. The host-side
interface receives 1 GbE data when the VSC8489-02 device is in the 1G operating mode. XAUI lane 0 or
lane 3 may be selected to receive the 1.25 Gbps data at the host interface. When receiving data on XAUI
lane 0, 1 GbE data will be transmitted from XAUI lane 0 in the ingress data path. When receiving data on
XAUI lane 3, 1 GbE data will be transmitted from XAUI lane 3 in the ingress data path.
In 10G mode, a clock is recovered from each lane of XAUI/RXAUI data in the host-side SerDes. The data
is 8B/10B decoded and lane aligned in the XGXS logic. The data is then 66B/64B encoded by the 10G
PCS logic. The data is serialized by the PMA in 10G LAN mode and transmitted from the line interface at
10.3125 Gbps. When the WIS logic is enabled in 10G WAN mode, a SONET/SDH STS-192c frame is
created using the 66B/64B encoded data as the frame's payload. The WIS data is serialized by the PMA
and transmitted from the line interface at 9.953 Gbps.
In 1G mode, a clock is recovered from 1 GbE data in the host-side SerDes. The data is 8B/10B decoded
by the host-side 1G PCS, then optionally processed by the The data is 8B/10B encoded by the line-side
1G PCS logic, serialized by the PMA, and transmitted from the line interface at 1.25 Gbps.
3.1.3
Interface Data Rates
The following table shows the interface data rates supported by the VSC8489-02 device.
Table 1 •
Interface Data Rates
Operating Mode Line-Side Datarate (Gbps) Host-Side Interface
Host-Side Datarate (Gbps)
10G LAN
1 × 10.3125
XAUI
4 × 3.125
10G LAN
1 × 10.3125
RXAUI
2 × 6.25
10G WAN
1 × 9.95328
XAUI
4 × 3.125
10G WAN
1 × 9.95328
RXAUI
2 × 6.25
1 GbE
1 × 1.25
1 GbE
1 × 1.25
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
3.2
Physical Medium Attachment (PMA)
The VSC8489-02 PMA section consists of a receiver (Rx) and a transmitter (Tx) subsection. The receiver
accepts data from the serial data input RXIN and sends the parallel data to the WIS, 10G PCS, or 1G
PCS block. A data rate clock also accompanies the parallel data. The transmitter accepts parallel data
from the WIS or PCS block and transmits at serial data output TXOUT. A loopback at the data path is
also provided, connecting the Rx and the Tx subsection.
Serial data is pre-equalized in the input buffer, and clock and data are recovered in the deserializer,
which provides 32-bit data. A demux then deserializes the data into a parallel core data interface. A PLL
in the Rx subsection is used as reference for clock and data recovery. Locked to the incoming
datastream, a lane sync signal is derived from the PLL clock, which may be used for source synchronous
data transmission to one or multiple transmitters.
The Tx subsection is made up of the serializer, the output buffer, and the PLL. The high-speed serial
stream is forwarded to a 3-tap filter output buffer. The PLL in the Tx subsection is used to generate the
high-speed clock used in the serializer.
To support different data rates, a frequency synthesizer inside the Rx and Tx subsection takes the
reference clock input XREFCK and generates all necessary clock rates.
The PMA also has two fully programmable clock outputs, TXCKOUT and RXCKOUT, that may be used
to output various clock domains from the PMA. For more information about the reference clock, see
Reference Clock, page 45.
3.2.1
VScope Input Signal Monitoring Integrated Circuit
The VScope™ input signal monitoring integrated circuit displays the input signal before it is digitized by
the CDR. The two primary configurations are as follows:
•
Unity Gain Amplifier monitors the 10 Gbps input signals before signal processing and equalization.
VScope input signal monitoring integrated circuit acts as a virtual scope to effectively observe the
received data signal before it has been processed. The autonomous adaptive filter taps must first be
disabled and the front-end receiver must be set for operation as a linear, unity gain amplifier. In this
mode, all DFE taps are set to zero. This mode does not require an adaptive algorithm.
•
Link Monitor provides the link margin.
VScope input signal monitoring integrated circuit enables design engineers and system developers
to monitor signals remotely without disrupting the data integrity of a live data path. By monitoring the
health of a given link (optical or electrical), various types of signal degradation can be identified and
corrected.
Note: The VScope input signal monitoring integrated circuit feature is only available in the 10G operation
mode.
3.2.1.1
10GBASE-KR Output Driver
The high-speed output driver includes programmable equalization accomplished by a three-tap finite
impulse response (FIR) structure. The three-tap delays are achieved by three flip-flops clocked by a
high-speed serial clock, as shown in the following illustration. Coefficients C(–1), C(0) and C(+1) adjust
the pre-cursor, main-cursor, and post-cursor of the output waveform. The coefficients are independently
adjusted by control bits. The bits for each coefficient are decoded in a thermometer fashion to achieve
linear coefficient adjustment. The three delayed data streams, after being properly strength adjusted by
their coefficients, are summed by a summing amplifier. The output driver meets the requirements defined
in IEEE 802.3ap Clause 72.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
Figure 4 •
10GBASE-KR Output Driver
DIN
T
T
T
CKIN
C –1
C +1
C0
decode
decode
decode
KR_COEFF_C–1
KR_COEFF_C+1
KR_COEFF_C0
VDD18TX
Slew
Control
Summing
Junction
decode
50 Ω
50 Ω
KR_SLEW[3:0]
TXOUTP
TXOUTN
The final output stage has 50 Ω back-termination with inductor peaking. The output slew rate is
controlled by adjusting the effectiveness of the inductors.
The test pattern for the transmitter output waveform is the square wave test pattern with at least eight
consecutive 1s. The following illustration shows the transmitter output waveform test, based on voltages
V1 through V6, ∆V2, and ∆V5.
Figure 5 •
KR Test Pattern
V1
V3
V2
∆|V2
0V
∆|V5
V5
V6
V4
t1
t1 + T
t1 + 2T
t2 - 2T
t2 - T
t2
t2 + 2T
t2 + 2T
t3 - 2T
t3 - T
t3
The output waveform is manipulated through the state of the coefficient C(-1), C(0), and C(+1).
3.3
WAN Interface Sublayer (WIS)
The WAN interface sublayer (WIS) is defined in IEEE 802.3ae Clause 50. The VSC8489-02 WIS block is
fully compliant with this specification. The VSC8489-02 offers additional controls, ports, and registers to
allow integration into a wider array of SONET/SDH equipment.
In addition to the SONET/SDH features addressed by WIS as defined by IEEE, most SONET/SDH
framers/mappers contain additional circuitry for implementing operation, administration, maintenance,
and provisioning (OAM&P). These framers/mappers also support special features to enable compatibility
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
with legacy SONET/SDH solutions. Because the VSC8489-02 WIS leverages Microsemi’s industry
leading framer/mapper technology, it contains suitable features for standard SONET/SDH equipment.
This includes the transmit/receive overhead serial interfaces (TOSI/ROSI) commonly used for network
customization and OAM&P support for SONET/SDH errors not contained in the WIS standard, support
for common legacy SONET/SDH implementations, and SONET/SDH jitter and timing quality.
3.3.1
Operation
WAN mode is enabled by asserting 2x0007.0 (SPI/MDIO/TWS) or wis_ctrl2.wan_mode. Status register
bit 1xA101.3 (SPI/MDIO/TWS) or Vendor_Specific_PMA_Status_2.WAN_ENABLED_status indicates
whether WAN mode is enabled or not. The Rx and Tx paths both have WAN mode enabled or disabled.
It is not possible to have WAN mode in the Tx path enabled while the Rx path is disabled, or vice versa.
The transmit portion of the WIS does the following:
•
•
•
•
Maps data from the PCS through the WIS service interface and to the SONET/SDH synchronous
payload envelope (SPE)
Generates path, line, and section overhead octets
Scrambles the frame
Transmits the frame to the PMA service interface
The receive portion of the WIS does the following:
•
•
•
•
•
•
Receives data from the PMA service interface
Delineates octet and frame boundaries
Descrambles the frame
Processes section, line, and path overhead information that contain alarms and parity errors
Interprets the pointer field
Extracts the payload for transmittal to the PCS through the WIS service interface
The following illustration shows the WIS block diagram.
Figure 6 •
WIS Transmit and Receive Functions
W I S S e r v ic e I n te r fa c e
tx_ d a ta -u n it< 1 5:0 >
TR A N S M IT P A Y LO A D
MAP PIN G
T R A N S M IT
PR OC ESS
GENERATE PATH
O V ER H EA D & FIX ED
S TU FF
IN S E R T P A T H
O VERHEAD &
F IX E D S T U F F
R E C E IV E
PR O C ESS
PRO CESS
PATH
DEFECT S
R EC EIV E P A Y LO A D
M A P P IN G
PRO CESS PATH
O VERHEAD
C H E C K B 3 (B I P - 8 )
REM O VE PATH
O VERHEAD &
F IX E D S T U F F
P R O C E S S H1 , H 2
PO IN TER
C O M P U T E B3 (B I P-8 )
G EN ER A T E LIN E
O VERHEAD
r x _ d a ta- u n it< 1 5 :0 >
PRO CESS
LIN E
D EFECT S
P RO CESS LIN E
O VERHEAD
R E M O V E L IN E
O VERHEAD
IN S E R T L IN E
O VERHEAD
IN S E R T
S E C T IO N
O VERHEAD
C O M P U T E B2 (B I P-N )
C H E C K B 2 (B I P- N )
G EN ER A T E S ECT IO N
O VERHEAD
P R O CES S S EC TIO N
O VERHEAD
X7 + X6 + 1
SCRAMBLER
X7 + X6 + 1
DESCRAMBLER
C O M P U T E B1 (B I P-8 )
tx _ d a ta -g r o u p< 1 5 :0 >
REM O VE
S E C T IO N
O VERHEAD
C H E C K B 1 (B I P - 8 )
P M A S e r v ic e I n te r fa c e
s y n c_ b its< 1 5:0 >
The following illustration shows the WIS frame structure.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
Figure 7 •
WIS Frame Structure
16, 704 Octets
576 Octets
Section
Overhead
Line
Overhead
Payload
9.58464 Gb/s
Fixed Stuffing
Path Overhead
Pointer
63
Octets
16, 640 Octets
The following illustration shows the positions of the section and line overhead octets within the WIS
frame.
Figure 8 •
STS-192c/STM-64 Section and Line Overhead Structure
576 Octets
A1
9
Octets
A1
A1
A1
A1
A1
A2
A2
A2
A2
A2
A2
J0
(C1)
B1
E1
F1
D1
D2
D3
H1
H1
H1
H1
H1
H1
H2
B2
B2
B2
B2
B2
B2
K1
K2
D4
D5
D6
D7
D8
D9
D10
D11
D12
S1
Z2
E2
H2
H2
H2
H2
H2
H3
Bytes reserved for national use
Z0
(C1)
H3
H3
H3
H3
H3
Bytes undefined/unused by IEEE802.3ae
M0 M1 Z2
The following illustration shows the path overhead octet positions.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
Figure 9 •
Path Overhead Octets
J1
B3
C2
G1
N in e
O c te ts
F2
H4
Z 3 /F 3
Z4 /K 3
N1
3.3.2
Section Overhead
The section overhead portion of the SONET/SDH frame supports frame synchronization, a tandem
connection monitor (TCM) known as the Section Trace, a high-level parity check, and some OAM&P
octets. The following table lists each of the octets, including their function, specification, and related
information.
The VSC8489-02 device provides a mechanism to transmit a static value as programmed by the MDIO
interface. However, by definition, MDIO is not fast enough to alter the octet on a frame-by-frame basis.
Table 2 •
Section Overhead
IEEE 802.3ae
WIS Usage
Overhead Octet Function
Recommended
Value
WIS Extension
A1
Frame alignment Supported
0xF6
Register (EWIS_TX_A1_A2) TOSI and
ROSI access.
A2
Frame alignment Supported
0x28
Register (EWIS_TX_A1_A2) TOSI and
ROSI access.
J0
Section trace
Specified value
For more
information, see
Section Trace
(J0), page 16
A 1-byte, 16-byte, or 64-byte trace
message can be sent using registers
WIS_Tx_J0_Octets_1_0 to
WIS_Tx_J0_Octets_15_14,
EWIS_TX_MSGLEN, or
EWIS_Tx_J0_Octets_17_16 to
EWIS_Tx_J0_Octets_63_62 and
received using registers
WIS_Rx_J0_Octets_1_0 to
WIS_Rx_J0_Octets_15_14,
EWIS_RX_MSGLEN, and
EWIS_Rx_J0_Octets_17_16 to
EWIS_Rx_J0_Octets_63_62. TOSI and
ROSI access.
Z0
Reserved for
section growth
Unsupported
0xCC
Register EWIS_TX_Z0_E1 TOSI and
ROSI access.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
Table 2 •
Section Overhead (continued)
Overhead Octet Function
IEEE 802.3ae
WIS Usage
Recommended
Value
B1
Supported
Bit interleaved
parity - 8 bits, as
specified in
T1.416
Section error
monitoring
(Section BIP-8)
WIS Extension
Using the TOSI, the B1 byte can be
masked for test purposes. For each B1
mask bit that is cleared to 0 on the TOSI
interface, the transmitted bit is left
unchanged. For each B1 mask bit that is
set to 1 on the TOSI interface, the
transmitted bit is inverted.
Using the ROSI, the B1 error locations
can be extracted. Periodically latched
counter (EWIS_B1_ERR_CNT1EWIS_B1_ERR_CNT0) is available.
E1
Orderwire
Unsupported
0x00
Register EWIS_TX_Z0_E1 TOSI and
ROSI access.
F1
Section user
channel
Unsupported
0x00
Register EWIS_TX_F1_D1 TOSI and
ROSI access.
D1-D3
Section data
Unsupported
communications
channel (DCC)
0x00
Register EWIS_TX_F1_D1 to
EWIS_TX_D2_D3 TOSI and ROSI
access.
3.3.2.1
Frame Alignment (A1, A2)
The SONET/SDH protocol is based upon a frame structure that is delineated by the framing octets, A1
and A2. The framing octets are defined to be 0xF6 and 0x28 respectively. In the transmit direction, all
192 A1 octets are sourced from the TX_A1 (EWIS_TX_A1_A2.TX_A1) register while the A2 octets are
sourced from the TX_A2 (EWIS_TX_A1_A2.TX_A2) register.
In the receive direction, the frame aligner monitors the input bus from the PMA and performs word
alignment. The frame alignment architecture is composed of a primary and secondary state machine.
The selected frame alignment and synchronization pattern have implications on the tolerated input BER.
The higher the input BER, the less likely the frame boundary can be found. The chances of finding the
frame boundary are improved by reducing the number of A1/A2 bytes required to be detected (using a
smaller pattern width). According to the WIS specification, the minimum for all parameters allows a signal
with an error tolerance of 10-12 to be framed.
The following illustration shows the primary synchronization state diagram.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
12
Functional Descriptions
Figure 10 • Primary Synchronization State Diagram
power_on = TRUE + signal_fail = TRUE
HUNT
sync_start
in_HUNT
FALSE
TRUE
found_Hunt = FALSE
found_Hunt = TRUE
A1_ALIGN
in_HUNT
FALSE
found_Presync = FALSE
found_Presync = TRUE
PRESYNC
sync_start
TRUE
bad_sync_cnt = 1
bad_sync_cnt = m
SYNC
sync_start
FALSE
bad_sync_cnt = n
The following table lists the variables for the primary state diagram. The variables are reflected in
registers EWIS_RX_FRM_CTRL1 and EWIS_RX_FRM_CTRL2 that can be alternately reconfigured.
Table 3 •
Framing Parameter Description and Values
IEEE 802.3ae IEEE 802.3ae
Parameter
Range
Range
Name
Description
Sync_Pattern width
Sequence of f
consecutive A1s
followed immediately
by a sequence of f
consecutive A2s. If
f = 2, Sync_Pattern is
A1A1A2A2.
f
2 to 192
0 to 16
2
Exceptions:
If f = 0, Sync_Pattern
is A1 + 4 MSBs of
A2.
If f = 1, Sync_Pattern
is A1A1A2.
Hunt_Pattern width
Sequence of i
consecutive A1s.
i
1 to 192
1 to 16.
4
Presync_Pattern A1 width
Presync_Pattern
j
consists of a sequence
of j consecutive A1s
followed immediately
by a sequence of k
consecutive A2s.
16 to 190
1 to 16
If set to 0, behaves
as if set to 1.
If set to 17 to 31,
behaves as if set
to 16.
16
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
Default
13
Functional Descriptions
Table 3 •
Framing Parameter Description and Values (continued)
IEEE 802.3ae IEEE 802.3ae
Parameter
Range
Range
Name
Description
Default
Presync_Pattern A2 width
Presync_Pattern
k
consists of a sequence
of j consecutive A1s
followed immediately
by a sequence of k
consecutive A2s.
16 to 192
0 to 16
16
0 means only 4 MSB
of A2 are used.
If set to 17 to 31,
behaves as if set
to 16.
SYNC state entry
Number of consecutive m
frame boundaries
needed to be found
after entering the
PRESYNC state in
order to enter the
SYNC state.
4 to 8
4
1 to 15
If set to 0, behaves as
if set to 1.
SYNC state exit
Number of consecutive n
frame boundary
location errors detected
before exiting the
SYNC state.
1 to 8
1 to 15
4
If set to 0, behaves as
if set to 1.
The following illustration shows the secondary synchronization state diagram.
Figure 11 • Secondary Synchronization State Diagram
power_on = TRUE + reset = TRUE + signal_fail = TRUE
WAIT
good_sync_cnt
bad_sync_cnt
octet_cnt
0
0
0
sync_start = TRUE
DELAY_1
in_HUNT = TRUE
in_HUNT = FALSE *
octet_cnt = (155520+f–k) *
found_Sync = TRUE
in_HUNT = FALSE *
octet_cnt = (155520+f–k) *
found_Sync = FALSE
MISSED
FOUND
good_sync_cnt
bad_sync_cnt ++
octet_cnt
bad_sync_cnt
0
good_sync_cnt ++
octet_cnt
0
UCT
0
0
UCT
DELAY_2
in_HUNT = FALSE *
octet_cnt = 155520 *
found_Sync = TRUE
in_HUNT = FALSE *
octet_cnt = 155520 *
found_Sync = FALSE
in_HUNT = TRUE
3.3.2.2
Loss of Signal (LOS)
WIS_STAT3.LOS alarm status is a latch-high register; back-to-back reads provide both the event as well
as status information. The LOS event also asserts register EWIS_INTR_PEND1.LOS_PEND until read.
This event can propagate an interrupt to either WIS_INTA or WIS_INTB based upon mask enable bits
EWIS_INTR_MASKA_1.LOS_MASKA and EWIS_INTR_MASKB_1.LOS_MASK.
There is no hysteresis on the LOS detection, and so it is recommended to have the system software to
implement a sliding window to check on the LOS before qualifying the presence of a signal. As an
alternative, Rx_LOS can be used from the optical module (through LOPC) to qualify the input signal. In
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
14
Functional Descriptions
addition to using analog detection, digital detection such as PCS_Rx_Fault is recommended to
determine if the input signal is good.
When the near-end device experiences LOS, it is possible to automatically transmit a remote defect
indication (RDI-L) to the far-end for notification purposes. The EWIS_RXTX_CTRL.TXRDIL_ON_LOS, if
asserted, overwrites the outgoing K2 bits with the RDI-L code. In the receive path, it is possible to trigger
an AIS-L state (alarm assertion plus forcing the payload to an all ones state) upon a detection of an LOS
condition. This is accomplished by asserting EWIS_RXTX_CTRL.RXAISL_ON_LOS.
3.3.2.3
Loss of Optical Carrier (LOPC)
The input pin LOPC can be used by external optic components to directly assert the loss of optical power
to the physical media device. Any change in level on the LOPC input asserts register
EWIS_INTR_PEND2.LOPC_PEND until read. The current status of the LOPC input pin can be read in
register EWIS_INTR_STAT2.LOPC_STAT. The LOPC input can be active high or active low by setting
the Vendor_Specific_LOPC_Control.LOPC_state_inversion_select bit appropriately. The LOPC_PEND
bit can propagate an interrupt to either WIS_INTA or WIS_INTB based upon mask enable bits
EWIS_INTR_MASKA_2.LOPC_MASKA and EWIS_INTR_MASKB_2.LOPC_MASKB.
When the near-end device experiences LOPC, it is possible to automatically transmit a remote defect
indication (RDI-L) to the far-end to notify it of a problem. The EWIS_RXTX_CTRL.TXRDIL_ON_LOPC
register bit, if asserted, overwrites the outgoing K2 bits with the RDI-L code. In the receive path, it is
possible to force the receive framer into an LOF state, thereby squelching subsequent alarms and invalid
payload data processing. This is accomplished by asserting EWIS_RX_ERR_FRC1.RXLOF_ON_LOPC.
Similar to the LOF condition forced upon an LOPC, the EWIS_RXTX_CTRL.RXAISL_ON_LOPC can
force the AIS-L alarm assertion, plus force the payload to an all ones state to indicate to the PCS the lack
of valid data upon an LOPC condition.
3.3.2.4
Severely Errored Frame (SEF)
Upon reset, the VSC8489-02 device Rx WIS enters the out-of-frame (OOF) state with both the severely
errored frame (SEF) and loss of frame (LOF) alarms active. The SEF state is terminated when the framer
enters the SYNC state. The framer enters the SYNC state after
EWIS_RX_FRM_CTRL2.SYNC_ENTRY_CNT plus 1 consecutive frame boundaries are identified. An
SEF state is declared when the framer enters the out-of-frame (OOF) state. The frame changes from the
SYNC state to the OOF state when EWIS_RX_FRM_CTRL2.SYNC_EXIT_CNT consecutive frames with
errored frame alignment words are detected. The SEF alarm condition is reported in WIS_STAT3.SEF.
This register latches high providing a combination of interrupt pending and status information within
consecutive reads.
An additional bi-stable interrupt pending bit SEF_PEND (EWIS_INTR_PEND1.SEF_PEND) is provided
to propagate an interrupt to either WIS_INTA or WIS_INTB based upon mask enable bits SEF_MASKA
(EWIS_INTR_MASKA_1.SEF_MASKA) and SEF_MASKB (EWIS_INTR_MASKB_1.SEF_MASKB).
3.3.2.5
Loss of Frame (LOF)
An LOF occurs when an out-of-frame state persists for an integrating period of
EWIS_LOF_CTRL1.LOF_T1 frames. To provide for the case of intermittent OOFs when not in the LOF
state, the integrating timer is not reset to zero until an in-frame condition persists continuously for
EWIS_LOF_CTRL1.LOF_T2 frames. The LOF state is exited when the in-frame state persists
continuously for EWIS_LOF_CTRL2.LOF_T3 frames. The LOF state is indicated by the
WIS_STAT3.LOF register being asserted. This register latches high, providing a combination of pending
and status information over consecutive reads.
An additional bi-stable interrupt pending bit, EWIS_INTR_PEND1.LOF_PEND, is provided to propagate
an interrupt to either WIS_INTA or WIS_INTB based upon mask enable bits
EWIS_INTR_MASKA_1.LOF_MASKA and EWIS_INTR_MASKB_1.LOF_MASKB.
When the near-end device experiences an LOF condition, it is possible to automatically transmit a
remote defect indication (RDI-L) to the far end to notify it of a problem. The
EWIS_RXTX_CTRL.TXRDIL_ON_LOF, if asserted, overwrites the outgoing K2 bits with the RDI-L code.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
In the receive path, it is possible to force a AIS-L state (alarm assertion plus forcing the payload to an all
ones state) upon a detection of an LOF condition. This is accomplished by asserting
EWIS_RXTX_CTRL.RXAISL_ON_LOF.
3.3.2.6
Section Trace (J0)
The J0 octet often carries a repeating message called the Section Trace message. The default
transmitted message length is 16 octets whose contents are defined in WIS_TXJ0
(WIS_Tx_J0_Octets_1_0-WIS_Tx_J0_Octets_15_14). If no active message is being broadcast, a default
section trace message is transmitted. This section trace message consists of 15 octets of zeros and a
header octet formatted according to Section 5 of ANSI T1.269-2000. The header octet for the 15-octets
of zero is 0x89. The default values of WIS_TXJ0 (WIS_Tx_J0_Octets_1_0-WIS_Tx_J0_Octets_15_14)
do not contain the 0x89 value of the header octet, so software must write this value.
The J0 octet in the receive direction is assumed to be carrying a 16-octet continuously-repeating section
trace message. The message is extracted from the incoming WIS frames and stored in WIS_RXJ0
(WIS_Rx_J0_Octets_1_0-WIS_Rx_J0_Octets_15_14). The WIS receive process does not delineate the
message boundaries, thus the message might appear rotated between new frame alignment events.
The VSC8489-02 device supports two alternate message types, a single repeating octet and a 64-octet
message. The message type can be independently selected for the transmit and receive direction. The
transmit direction is configured using EWIS_TX_MSGLEN.J0_TXLEN, while
EWIS_RX_MSGLEN.J0_RX_LEN configures the receive path.
When the transmit direction is configured for a 64-octet message, the first 16 octets are programmed in
WIS_TXJ0 (WIS_Tx_J0_Octets_1_0-WIS_Tx_J0_Octets_15_14), while the 48 remaining octets are
programmed in EWIS_TXJ0 (EWIS_Tx_J0_Octets_17_16-EWIS_Tx_J0_Octets_63_62). Likewise, the
first 16 octets of the receive message are stored in WIS_RXJ0 (WIS_Rx_J0_Octets_1_0WIS_Rx_J0_Octets_15_14), while the other 48 octets are stored in EWIS_RXJ0
(EWIS_Rx_J0_Octets_17_16-EWIS_Rx_J0_Octets_63_62). The receive message is updated every
125 µs with the recently received octet. Any persistency or message matching is expected to take place
within the station manager.
3.3.2.7
Reserved for Section Growth (Z0)
The WIS standard does not support the Z0 octet and requires transmission of 0xCC in the octet
locations. A different Z0 value can be transmitted by configuring EWIS_TX_Z0_E1.TX_Z0. The TX_Z0
default is 0xCC.
3.3.2.8
Scrambling/Descrambling
The transmit signal (except for row 1 of the section overhead) is scrambled according to the standards
when register bit EWIS_TXCTRL2.SCR is asserted, which is the default state. When deasserted, the
scrambler is disabled.
The receive signal descrambler is enabled by default. The descrambler can be bypassed by deasserting
register bit EWIS_RX_CTRL1.DSCR_ENA.
Enabling loopback H4 and turning off the WIS scrambler and descrambler may yield an interesting data
point when debugging board setups. The CRU in the ingress PMA path would not have enough edge
transitions in the data to reliably recover the clock if the chip were receiving non-scrambled data. The
same would be true for any far-end device connected to the egress PMA if the scrambler were turned off.
The WIS scrambler and descrambler should be left on under normal operating conditions.
3.3.2.9
Section Error Monitoring (B1)
The B1 octet is a bit interleaved parity-8 (BIP-8) code using even parity calculated over the previous
STS-192c frame, post scrambling. The computed BIP-8 is placed in the following outgoing SONET frame
before scrambling.
In the receive direction, the incoming frame is processed, and a BIP-8 is calculated. The calculated value
is then compared with the B1 value received in the following frame. The difference between the
calculated and received octets are accumulated into the WIS_B1_CNT register. This counter rolls over
after the maximum count. This counter is cleared upon device reset.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
The EWIS_B1_ERR_CNT1 and EWIS_B1_ERR_CNT0 registers provide a count of the number of
received B1 parity errors. This register is updated with the internal count value upon a PMTICK condition,
after which the internal counter is reset to zero. When the counter is nonzero, the
EWIS_INTR_PEND2.B1_NZ_PEND event register is asserted until read. A non-latch high version of this
event, EWIS_INTR_STAT2.B1_NZ_STAT, is also available. This event can propagate an interrupt to
either WIS_INTA or WIS_INTB based upon mask enable bits EWIS_INTR_MASKA_2.B1_NZ_MASKA
and EWIS_INTR_MASKB_2.B1_NZ_MASKB.
The B1_ERR_CNT can optionally be configured to increment on a block count basis, a maximum
increment of 1 per errored frame regardless of the number of errors received. This mode is enabled by
asserting EWIS_CNT_CFG.B1_BLK_MODE.
3.3.2.10
Section Orderwire (E1)
The WIS standard does not support the E1 octet and requires transmission of 0x00 in the octet location.
A different E1 value can be transmitted by configuring EWIS_TX_Z0_E1.TX_E1 (whose default is 0x00).
3.3.2.11
Section User Channel (F1)
The WIS standard does not support the F1 octet and requires transmission of 0x00 in the octet location.
A different F1 value can be transmitted by configuring EWIS_TX_F1_D1.TX_F1 (whose default is 0x00).
3.3.2.12
Section Data Communication Channel (DCC-S)
The WIS standard does not support the DCC-S octets and requires transmission of 0x00 in the octet
locations. Different DCC-S values can be transmitted by configuring EWIS_TX_F1_D1.TX_D1,
EWIS_TX_D2_D3.TX_D2, and EWIS_TX_D2_D3.TX_D3 (all of which default to 0x00).
3.3.2.13
Reserved, National, and Unused Octets
The VSC8489-02 device transmits 0x00 for all reserved, national, and unused overhead octets.
3.3.3
Line Overhead
The line overhead portion of the SONET/SDH frame supports pointer interpretation, a per channel parity
check, protection switching information, synchronization status messaging, far-end error reporting, and
some OAM&P octets.
The VSC8489-02 device provides a mechanism to transmit a static value as programmed by the MDIO
interface. However, by definition, MDIO is not fast enough to alter the octet on a frame-by-frame basis.
The following table lists each of the octets including their function, specification, and related information.
Table 4 •
Line Overhead Octets
Overhead Octet
Function
IEEE 802.3ae
WIS Usage
H1-H2
Pointer
H3
Pointer action
Recommended Value
WIS Extension
Specified value
SONET mode:
STS-1: 0x62, 0x0A
STS-n: 0x93, 0xFF SDH
mode:
STS-1: 0x6A, 0x0A
STS-n: 0x9B, 0xFF
Registers
EWIS_TX_C2_H1.TX_H1 and
EWIS_TX_H2_H3.TX_H2 TOSI
and ROSI access.
Specified value
0x00
Register
EWIS_TX_H2_H3.TX_H3 TOSI
and ROSI access.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
Table 4 •
Line Overhead Octets (continued)
IEEE 802.3ae
WIS Usage
Overhead Octet
Function
Recommended Value
WIS Extension
B2
Line error
monitoring (line
BIP-1536)
BIP-8, as specified in
T1.416
Using the TOSI, the B2 bytes
can be masked for test
purposes. For each B2 mask bit
that is cleared to 0 on the TOSI
interface, the transmitted bit is
left unchanged. For each B2
mask bit that is set to 1 on the
TOSI interface, the transmitted
bit is inverted.
Using the ROSI, the B2 error
locations can be extracted.
Periodically latched counter
(EWIS_B1_ERR_CNT1EWIS_B1_ERR_CNT0) is
available.
K1, K2
Automatic
Specified value
protection switch
(APS) channel
and line remote
defect identifier
(RDI-L)
For more information
about K2 coding, see
Table 5, page 20
Register Registers
EWIS_TX_G1_K1.TX_K1 and
EWIS_TX_K2_F2.TX_K2 TOSI
and ROSI access.
D4-D12
Line data
Unsupported
communications
channel (DCC)
0x00
Registers EWIS_TX_D4_D5
and EWIS_TX_D6_H4 TOSI
and ROSI access.
S1
Synchronization Unsupported
messaging
0x0F
Register
EWIS_TX_S1_Z1.TX_S1 TOSI
and ROSI access.
Z1
Reserved for
Line growth
Unsupported
0x00
Register
EWIS_TX_S1_Z1.TX_Z1 TOSI
and ROSI access.
M0/M1
STS-1/N line
remote error
indication (REI)
M0 unsupported, 0x00/number of
M1 supported
detected B2 errors in the
receive path, as
specified in T1.416
TOSI and ROSI access. The
VSC8489-02 device supports a
mode that uses only M1 to back
report REI-L
(EWIS_MODE_CTR.REI_MOD
E = 0) and another mode which
uses both M0 and M1 to back
report REI-L
(EWIS_MODE_CTR.REI_MOD
E = 1). For more information,
see Line Error Monitoring (B2),
page 19.
E2
Orderwire
Unsupported
0x00
Register
EWIS_TX_Z2_E2.TX_E2 TOSI
and ROSI access.
Z2
Reserved for
Line growth
Unsupported
0x00
Register
EWIS_TX_Z2_E2.TX_Z2 TOSI
and ROSI access.
Supported
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
3.3.3.1
Line Error Monitoring (B2)
The B2 octet is a BIP-8 value calculated over each of the previous STS-1 channels excluding the section
overhead and pre-scrambling. As the B2 octet is calculated on an STS-1 basis, there are 192 B2 octets
within an STS-192/STM-64 frame. Each of the 192 calculated BIP-8 octets are then placed in the
outgoing SONET/SDH frame.
Note: For SONET mode, when the number of errors detected in the B2 octet of a receive frame is greater than
255, the total count of detected errors is transmitted in more than one frame. Even when no B2 errors are
detected in subsequent frames, the number of detected B2 errors going into an accumulator will be
limited to 255 if more than 255 errors are detected in a frame. The Tx framer pulls the REI-L count out of
the accumulator when REI-L is transmitted to be compliant with T1-105.
In the receive direction, the incoming frame is processed, a per STS-1 BIP-8 is calculated (excluding
section overhead and after descrambling), and then compared to the B2 value in the following frame.
Errors are accumulated in the WIS_B2_CNT1 and WIS_B2_CNT0 registers. This counter is nonsaturating and so rolls over after its maximum count. The counter is cleared only on device reset.
An additional 32-bit B2 error counter is provided in B2_ERR_CNT (EWIS_B2_ERR_CNT1 and
EWIS_B2_ERR_CNT0), which is a saturating counter and is latched and cleared based upon a PMTICK
event. Errors are accumulated from the previous PMTICK event. When the counter is nonzero, the
EWIS_INTR_PEND2.B2_NZ_PEND event register is asserted until read. A non-latch high version of this
event is available in EWIS_INTR_STAT2.B2_NZ_STAT. This event can propagate an interrupt to either
WIS_INTA or WIS_INTB, based on mask enable bits EWIS_INTR_MASKA_2.B2_NZ_MASKA and
EWIS_INTR_MASKB_2.B2_NZ_MASKB.
The B2_ERR_CNT can optionally be configured to increment on a block count basis, a maximum
increment of 1 per errored frame regardless of the number of errors received. This mode is enabled by
asserting EWIS_CNT_CFG.B2_BLK_MODE.
It is possible that two sets of B2 bytes (from two SONET/SDH frames) are received by the Rx WIS logic
in a period of time when only one M0/M1 octet is transmitted. In this situation, one of the two B2 error
counts delivered to the Tx WIS logic is discarded. This situation occurs when the receive data rate is
faster than the transmit data rate. Similarly, when the transmit data rate is faster than the receive data
rate, a B2 error count is not available for REI-L insertion into the M0/M1 octets of the transmitted
SONET/SDH frame. A value of zero is transmitted in this case. This behavior is achieved by using a
FIFO to transfer the detected B2 error count from the receive to transmit domains.
A FIFO overflow or underflow condition is not considered an error. Instead, it is recovered from gracefully,
as described above. A FIFO overflow or underflow eventually occurs unless the transmit and receive
interfaces are running at the same average data rate. Because the received and transmitted frames can
differ by, at most, 40 ppm (±20 ppm) and still meet the industry standards, this “slip” can happen no more
often than once every 3.1 seconds.
3.3.3.2
APS Channel and Line Remote Defect Identifier (K1, K2)
The K1 and K2 octets carry information regarding automatic protection switching (APS) and line remote
defect identifier (RDI-L). The K1 octet and the most significant five bits of the K2 octet contain the APS
channel information. The transmitted values can be configured at EWIS_TX_G1_K1.TX_K1 and
EWIS_TX_K2_F2.TX_K2. The default values of all zeros are compliant with the WIS standard.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
The three least significant bits within the K2 octet carry the RDI-L encoding, as defined by section 7.4.1
of ANSI T1.416-1999 and as shown in the following table.
Table 5 •
K2 Encodings
Indicator
K2 Value for Bits 6, 7, 8
Interpretation
RDI-L
110
Remote error indication.
For the receive process, an RDI-L defect occurs after a
programmable number of RDI-L signals are received in contiguous
frames and is terminated when no RDI-L is received for the same
number of contiguous frames.
An RDI-L can be forced by asserting
EWIS_RX_ERR_FRC1.FRC_RX_RDIL.
For the transmit process, the WIS standard does not indicate when
or how to transmit RDI-L. VSC8489-02 provides the option of
transmitting K2 by programming it through the TOSI, by
programming it using the K2_TX MDIO register, or by programming
it based on the contents of the K2_TX register with bits 6, 7, and 8
modified depending on the status of the following: LOPC, LOS, LOF,
AIS-L and their associated transmit enable bits enable bits
TXRDIL_ON_LOPC, TXRDIL_ON_LOS, TXRDIL_ON_LOF and
TXRDIL_ON_AISL in register EWIS_RXTX_CTRL.
AIS-L
111
Alarm indication signal (line).
For the receive process, this is detected based on the settings of the
K2 byte. When AIS-L is detected, the WIS link status is down and
WIS_STAT3.AISL is set high. This also contributes to errored
second (ES) and severally errored second (SES) reports.
For standard WIS operation, this is never transmitted.
Idle
(normal)
000
Unless RDI-L exists, the standard WIS transmits idle.
Although the transmission of RDI-L is not explicitly defined within the WIS standard, the VSC8489-02
device allows the automatic transmission of RDI-L upon the detection of LOPC, LOS, LOF, or AIS-L
conditions. These features are enabled by asserting TXRDIL_ON_LOPC, TXRDIL_ON_LOS,
TXRDIL_ON_LOF and TXRDIL_ON_AISL in register EWIS_RXTX_CTRL.
Note: The RDI-L code of 110 is transmitted by the DUT only when Rx AIS-L is asserted. For example, if AIS-L
is detected by the DUT for five continuous frames in the Rx direction, then the RDI-L code is transmitted
for five frames in the Tx direction (not 20 frames as stated in the ANSI T1.105 specification).
The VSC8489-02 device can force a RDI-L condition independent of the K2 transmit value by asserting
EWIS_TXCTRL2.FRC_TX_RDI. Likewise, a AIS-L condition can be forced by asserting
EWIS_TXCTRL2.FRC_TX_AISL. If both conditions are forced, the AIS-L value is transmitted.
In the receive direction, the RDI-L alarm (K2[6:8] = 110, using SONET nomenclature) and the AIS-L
alarm (K2[6:8] = 111, using SONET nomenclature) are not asserted until the condition persists for a
programmable number of contiguous frames. This value is programmable at
EWIS_RX_ERR_FRC1.APS_THRES and is typically set to values of 5 or 10. The AIS-L is detected by
the receiver after the programmable number of frames is received, and results in the reporting of AIS-P.
The WIS standard defines WIS_STAT3.RDIL and WIS_STAT3.AISL as a read-only latch-high register, so
a read of a one in this register indicates that an error condition occurred since the last read. A second
read of the register provides the current status of the event as to whether the alarm is currently asserted.
EWIS_INTR_PEND1.RDIL_PEND and EWIS_INTR_PEND1.AISL_PEND assert whenever the RDI-L or
AIS-L state changes (assert or deassert). These interrupts have associated mask enable bits
(EWIS_INTR_MASKA_1.RDIL_MASKA, EWIS_INTR_MASKB_1.RDIL_MASKB,
EWIS_INTR_MASKA_1.AISL_MASKA and EWIS_INTR_MASKB_1.AISL_MASKB), which, if enabled,
propagate an interrupt to the WIS_INTA/B pins.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
For test purposes, the VSC8489-02 device can induce a RDI-L condition in the receive direction
independent of the received K2 value by asserting EWIS_RX_ERR_FRC1.FRC_RX_RDIL. Likewise, a
AIS-L condition can be forced in the receive direction by asserting
EWIS_RX_ERR_FRC1.FRC_RX_AISL.
3.3.3.3
Line Data Communications Channel (D4 to D12)
The WIS standard does not support Line Data Communications Channel (L-DCC) octets (D4-D12) and
recommends transmitting 0x00 within these octets. The D4-D12 transmitted values can be programmed
in registers EWIS_TX_D4_D5 - EWIS_TX_D12_Z4. The register defaults are all 0x00. The receive LDCC octets are only accessible through the ROSI port.
3.3.3.4
STS-1/N Line Remote Error Indication (M0 and M1)
The M0 and M1 octets are used for back reporting the number of B2 errors received, known as remote
error indication (REI-L). The value in this octet comes from the B2 error FIFO, as discussed with the B2
octet. The WIS standard does not support the M0 octet and recommends transmitting 0x00 in place of
the M0 octet. However, the WIS standard supports the M1 octet in accordance with T1.416.
Two methods for back-reporting exist and are controlled by EWIS_TXCTRL2.SDH_TX_MODE. Because
a single frame can contain up to 1536 B2 errors while the M1 byte alone can only back report a maximum
of 255 errors, a discrepancy exists. When G707_2000_REIL is deasserted, only the M1 byte is used and
a maximum of 255 errors are back-reported. When G707_2000_REIL is asserted, two octets per frame
are used for back reporting- the M1 octet and the M0 octet (not the first STS-1 octet, but the second STS1 octet). In this mode, a total of 1536 errors can be back-reported per frame.
In the receive direction, the VSC8489-02 device detects and accumulates errors according to the
EWIS_MODE_CTRL.REI_MODE setting. The VSC8489-02 device deviates from the G.707 standard by
not interpreting REI-L values greater than 1536 as zero. The WIS standard defines a 32-bit REI-L
counter in registers WIS_REIL_CNT1 and WIS_REIL_CNT0. This counter is non-saturating and so rolls
over after its maximum count. The counter is cleared only on device reset.
An additional 32-bit REI-L counter is provided in registers EWIS_REIL_CNT1 and EWIS_REIL_CNT0,
which is a saturating counter and is latched and cleared based upon a PMTICK event. Errors are
accumulated since the previous PMTICK event. When the counter is nonzero, the
EWIS_INTR_PEND2.REIL_NZ_PEND event register is asserted until read. A non-latch high version of
this event (EWIS_INTR_STAT2.REIL_NZ_STAT) is also available. This event can propagate an interrupt
to either WIS_INTA or WIS_INTB based upon mask enable bits
EWIS_INTR_MASKA_2.REIL_NZ_MASKA and EWIS_INTR_MASKB_2.REIL_NZ_MASKB.
The REIL_ERR_CNT can optionally be configured to increment on a block count basis, a maximum
increment of 1 per errored frame regardless of the number of errors received. This mode is enabled by
asserting EWIS_CNT_CFG.REIL_BLK_MODE.
3.3.3.5
Synchronization Messaging (S1)
The S1 octet carries the synchronization status message and provides synchronization quality measures
of the transmission link in the least significant 4 bits. The WIS standard does not support the S1 octet and
requires the transmission of a 0x0F within the S1 octet. A value other than 0x0F can be programmed in
TX_S1 (2xE61F).
3.3.3.6
Reserved for Line Growth (Z1 and Z2)
The WIS standard does not support the Z1 or Z2 octets and requires the transmission of 0x00 in their
locations. Different Z1 and Z2 values can be transmitted by programming the values at
EWIS_TX_S1_Z1.TX_Z1 and EWIS_TX_Z2_E2.TX_Z2 respectively.
3.3.3.7
Orderwire (E2)
The WIS standard does not support the E2 octet and recommends transmitting 0x00 in place of the E2
octet. A value other than 0x00 can be transmitted by programming the intended value at
EWIS_TX_Z2_E2.TX_E2.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
3.3.4
SPE Pointer
The H1 and H2 octets are used as a pointer within the SONET/SDH frame to locate the beginning of the
path overhead and the beginning of the synchronous payload envelope (SPE). Within SONET/SDH the
SPE can begin anywhere within the payload area. However, IEEE 802.3ae specifies that a transmitted
SPE must always be positioned solely within a single SONET/SDH frame. The constant pointer value of
522 decimal (0x20A) must be contained in the first channel’s H1 and H2 octets. Together these
conditions result in the H1 and H2 octets being 0x62 and 0x0A, respectively. These are the default
values of EWIS_TX_C2_H1.TX_H1 and EWIS_TX_H2_H3.TX_H2. Programming these registers with
alternate values does not alter the positioning of the SPE, but it might induce a loss of pointer (LOP-P) at
the far-end, or at least prevent the far-end from extracting the proper payload. Furthermore, the WIS
standard specifies the frame structure be a concatenated payload. For this reason, the H1 and H2 octets
in channels 2 through 192 contain the concatenation indicator.
The VSC8489-02 device supports forcing the loss of pointer (LOP-P) and path alarm indication signal
(AIS-P) state.
The WIS standard specifies that a 0×00 be transmitted in the H3 octet. An alternate value can be
transmitted by programming EWIS_TX_H2_H3.TX_H3.
The WIS specification does not limit the pointer position within the receive SONET/SDH frame to allow
interoperability to other SONET/SDH equipment. In addition to supporting the required SONET pointer
rules, the VSC8489-02 device pointer interpreter optionally supports SDH pointers. This is selectable
using the EWIS_MODE_CTRL.RX_SS_MODE bit. The following table shows the differences between
SONET and SDH modes.
Table 6 •
SONET/SDH Pointer Mode Differences
SONET
SDH
SS bits are ignored by the device pointer
interpreter and not used
SS bits are set to 10 and are checked by the device pointer
interpreter to determine the pointer type
All 192 bytes of H1 and H2 are checked by the The first 64 bytes are checked by the pointer interpreter to
pointer interpreter to determine the pointer type determine the pointer type (first Au-4 of an AU-4-64c)
Uses ‘8 out of 10’ GR-253-core objective
increment/decrement rule
Uses majority detect increment/decrement rule
The H1 and H2 octets combine to form a word with several fields, as shown in Figure 12, page 23.
3.3.4.1
Bit Designations within Payload Pointer
The N bits [15:12] carry a new data flag (NDF). This mechanism allows an arbitrary change in the
location of the payload. NDF is indicated by at least three out of the four N bits matching the code ‘1001’
(NDF enabled). Normal operation is indicated by three out of the four N bits matching the code ‘0110’
(normal NDF).
The last ten bits of the pointer word (D bits and I bits) carry the pointer value. The pointer value has a
range from 0 to 782 that indicates the offset between the first byte after the H3 byte and the first byte of
the SPE.
The SS bits are located in bits 11 and 10, and are unused in SONET mode. In SDH mode, these bits are
compared with pattern ‘10’, and the pointer is considered invalid if it does not match.
Because the VSC8489-02 device only supports concatenated frames, only the first pair of bytes (H1, H2)
are called the primary pointer and have a normal format. The
rest of the H1/H2 bytes contain the concatenation indication (CI). The format for the CI is NDF enabled
with a pointer value of all ones.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
22
Functional Descriptions
Figure 12 • 16-bit Designations within Payload Pointer
H1
3.3.4.2
H2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
N
N
N
N
S
S
I
D
I
D
I
D
I
D
I
D
Pointer Types
The VSC8489-02 device supports five different pointer types, as described in the following table. A
normal pointer indicates the current pointer, a new data flag indicates a new pointer location, and an AIS
pointer indicates AIS. The pointer increment and pointer decrement mechanism adjusts the frequency
offset between the frame overhead and SPE. A pointer increment is indicated by a normal NDF that has
the currently accepted pointer with the I bits inverted. A pointer decrement is indicated by a normal NDF
that has the currently accepted pointer with D bits inverted.
Table 7 •
H1/H2 Pointer Types
Pointer Type
nnnn Value
Normal
Three out of the four bits 0 to 782
matching 0110
Matching in SDH mode,
ignored in SONET mode
New data flag (NDF) Three out of the four bits 0 to 782
matching 1001
Matching in SDH mode,
ignored in SONET mode
AIS pointer
1111
11
Pointer increment
Three out of the four bits Current pointer with Matching in SDH mode,
matching 0110
I bits inverted
ignored in SONET mode
Pointer decrement
Three out of the four bits Current pointer with Matching in SDH mode,
matching 0110
D bits inverted
ignored in SONET mode
Table 8 •
Pointer Value
1111 1111 11
SS bits
Concatenation Indication Types
Pointer Type
nnnn Value
Normal concatenation indication Three out of the four
bits matching 1001
AIS concatenation indication
Pointer Value
SS bits
1111 1111 11
Matching in SDH mode,
ignored in SONET mode
Pointer value, nnnn value, and SS bits are the same as the AIS pointer
Invalid concatenation indication Any other concatenation indication other than normal CI or AIS CI
3.3.4.3
Pointer Adjustment Rule
The VSC8489-02 device pointer interpreter adjusts the current pointer value according to rules listed in
Section 9.1.6 of ANSI T1.105-1995. In addition, no increment/decrement is accepted for at least three
frames following an increment/decrement or NDF operation.
3.3.4.4
Pointer Increment/Decrement Majority Rules
In SONET mode, the pointer interpreter uses more restrictive GR-253-CORE objective rules, as follows:
•
•
An increment is indicated by eight or more bits matching non-inverted D bits and inverted I bits.
A decrement is indicated by eight or more bits matching non-inverted I bits and inverted D bits.
In SDH mode, the majority rules are:
•
•
•
An increment is indicated by three or more inverted I bits and two or fewer inverted D bits.
A decrement is indicated by three or more inverted D bits and two or fewer inverted I bits.
If three or more D bits are inverted and three or more I bits are inverted, no action is taken.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
23
Functional Descriptions
3.3.4.5
Pointer Interpretation States
The pointer interpreter algorithm for state transitions can be modeled as a finite state machine with three
states, as shown in the following illustration. The three states are normal (NORM), loss of pointer (LOP),
and alarm indication state (AIS).
Figure 13 • Pointer Interpreter State Diagram
a, b, e
NORM
a, b
b
c
d
c
AIS
LOP
d
The conditions for transitions between these states are summarized in the following table
Table 9 •
Pointer Interpreter State Diagram Transitions
Transitions
States
Description
a
NORM NORM
AIS NORM
=. NDF
1 frame
enabled with pointer in range (0 to 782). SS bit match
(if enabled).
b
NORM NORM
LOP NORM
AIS NORM
=. NDF
3 frames
disabled (NORM pointer) with the same pointer value
in range (0 to 782). SS bit match (if enabled).
c
NORM AIS
LOP AIS
=. AIS pointer
(0xFFFF).
d
NORM LOP
AIS LOP
Anything other than transitions b and c or NDF
8 frames
enabled (transition a) or AIS pointer when not in AIS
state or NORM pointer when not in NORM state or
NORM pointer with pointer value not equal to current
or increment/decrement or CONC pointer or SS bit
mismatch (if comparison is enabled).
e
Justification
Valid increment or decrement indication.
3.3.4.6
Required Persistence
3 frames
1 frame
Valid Pointer Definition for Interpreter State Diagram Transitions
During an AIS state, only an AIS pointer is a valid pointer. In NORM state, several definitions of “valid
pointer” for purpose of LOP detection are possible, according to GR-253-CORE. The VSC8489-02
device follows the GR-253-CORE intended definition, but adds a single normal pointer that exactly
matches the current valid pointer value.
Any change in the AIS state is reflected in the alarm bit WIS_STAT3.AISP. This latch-high register reports
both the event and status information in consecutive reads. The EWIS_INTR_PEND1.AISP_PEND bit
remains asserted until read. This event can propagate an interrupt to either WIS_INTA or WIS_INTB,
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
based on mask enable bits EWIS_INTR_MASKA_1.AISP_MASKA and
EWIS_INTR_MASKB_1.AISP_MASKB.
Similarly, any change in the LOP state is reflected in the alarm bit WIS_STAT3.LOPP. This latch-high
register reports both the event and status information in consecutive reads. The
EWIS_INTR_PEND1.LOPP_PEND bit remains asserted until read. This event can propagate an
interrupt to either WIS_INTA or WIS_INTB, based upon the mask enable bits
EWIS_INTR_MASKA_1.LOPP_MASKA and EWIS_INTR_MASKB_1.LOPP_MASKB.
3.3.5
Path Overhead
The path overhead portion of the SONET/SDH frame supports an end-to-end trace identifier, a payload
parity check, a payload type indicator, a status indicator, and a user channel. The following table lists
each of the octets, including their function.
Note: The VSC8489-02 device provides a mechanism to transmit a static value as programmed by the MDIO
interface. However, by definition, MDIO is not fast enough to alter the octet on a frame-by-frame basis.
Extended WIS TOSI and ROSI do not support path overhead.
Table 10 •
STS Path Overhead Octets
Overhead
Octet
Function
IEEE 802.3ae
WIS Usage
Recommended
Value
WIS Extension
J1
Path trace message Specified value For more
information, see
Overhead Octet
(J1), page 26
A 1-, 16-, or 64-byte trace message
can be sent using registers
(EWIS_TX_MSGLEN.J1_TXLEN,
WIS_Tx_J1_Octets_1_0WIS_Tx_J1_Octets_15_14 and
EWIS_Tx_J1_Octets_17_16EWIS_Tx_J1_Octets_63_62) and
received using registers
(EWIS_RX_MSGLEN.J1_RX_LEN,
WIS_Rx_J1_Octets_1_0WIS_Rx_J1_Octets_15_14,
EWIS_Rx_J1_Octets_17_16EWIS_Rx_J1_Octets_63_62).TOSI
and ROSI access.
B3
Path error
monitoring (path
BIP-8)
Supported
C2
Path signal label
Specified value 0x1A
Register (EWIS_TX_C2_H1.TX_C2).
Supports persistency and mismatch
detection
(EWIS_MODE_CTRL.C2_EXP).
G1
Path status
Supported
As specified in
T1.416
Ability to select between RDI-P and
ERDI-P formats.
F2
Path user channel
Unsupported
0x00
Register (EWIS_TX_K2_F2.TX_F2).
H4
Multiframe indicator Unsupported
0x00
Register (EWIS_TX_D6_H4.TX_H4).
Z3-Z4
Reserved for path
growth
Unsupported
0x00
Register (EWIS_TX_D9_Z3.TX_Z3,
EWIS_TX_D12_Z4.TX_Z4).
N1
Tandem connection Unsupported
maintenance and
path data channel
0x00
Register (EWIS_TX_N1.TX_N1).
TOSI and ROSI access.
Both SONET and SDH mode B3
Bit interleaved
parity - 8 bits, as calculation is supported.
specified in
T1.416
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
3.3.5.1
Overhead Octet (J1)
The J1 transmitted octet contains a 16-octet repeating path trace message whose contents are defined
in WIS Tx J1s (WIS_Tx_J1_Octets_1_0-WIS_Tx_J1_Octets_15_14). If no active message is being
broadcast, a default path trace message is transmitted, consisting of 15 octets of zeros and a header
octet formatted according to Section 5 of ANSI T1.269-2000. The header octet for the 15-octets of zero is
0x89. The default values of WIS Tx J1s do not contain the 0x89 value of the header octet, thus software
must write this value.
By default, the J1 octet in the receive direction is assumed to be carrying a 16-octet continuously
repeating path trace message. The message is extracted from the incoming WIS frames and presented
in WIS Rx J1s (WIS_Rx_J1_Octets_1_0-WIS_Rx_J1_Octets_15_14). The WIS receive process does
not delineate the message boundaries, thus the message might appear rotated between new frame
alignment events.
The VSC8489-02 device supports two alternate message types, a single repeating octet and a 64-octet
message. The message type can be independently selected for the transmit and receive direction. The
transmit direction is configured using EWIS_TX_MSGLEN.J1_TXLEN while
EWIS_RX_MSGLEN.J1_RX_LEN configures the receive path.
When the transmit direction is configured for a 64-octet message, the first 16 octets are programmed in
WIS_Tx_J1_Octets_1_0-WIS_Tx_J1_Octets_15_14, while the 48 remaining octets are programmed in
EWIS_Tx_J1_Octets_17_16-EWIS_Tx_J1_Octets_63_62. Likewise, the first 16-octets of the receive
message are stored in J1_RXMSG (WIS_Rx_J1_Octets_1_0-WIS_Rx_J1_Octets_15_14), while the
other 48 octets are stored in EWIS_Rx_J1_Octets_17_16-EWIS_Rx_J1_Octets_63_62. The receive
message is updated every 125 µs with the recently received octet. Any persistence or message
matching is expected to take place within the station manager.
3.3.5.2
STS Path Error Monitoring (B3)
The B3 octet is a bit interleaved parity-8 (BIP-8) code, using even parity, calculated over the previous
STS-192c SPE before scrambling. The computed BIP-8 is placed in the B3 byte of the following frame
before scrambling.
In the receive direction, the incoming frame is processed and a B3 octet is calculated over the received
frame. The calculated value is then compared with the B3 value received in the following frame. The
difference between the calculated and received octets are accumulated in block (maximum increment of
1 per errored frame) fashion into a B3 error register, WIS_B3_CNT. This counter is non-saturating and so
rolls over. The counter is cleared upon a device reset.
An additional 32-bit B3 error counter is provided at B3_ERR_CNT (EWIS_B3_ERR_CNT1 and
EWIS_B3_ERR_CNT0), a saturating counter that is latched and cleared based upon a PMTICK event.
Errors are accumulated starting from the previous PMTICK event. When the counter is nonzero, the
EWIS_INTR_PEND2.B3_NZ_PEND event register is asserted until read. A non-latch high version of this
event EWIS_INTR_STAT2.B3_NZ_STAT is also available. This event may propagate an interrupt to
either WIS_INTA or WIS_INTB, based on the mask enable bits EWIS_INTR_MASKA_2.B3_NZ_MASKA
and EWIS_INTR_MASKB_2.B3_NZ_MASKB.
The B3_ERR_CNT may optionally be configured to increment on a block count basis, a maximum
increment of 1 per errored frame regardless of the number of errors received. The
EWIS_CNT_CFG.B3_BLK_MODE control bit, if asserted, places the B3_ERR_CNT counter in block
increment mode.
It is possible that two sets of B3 bytes (from two SONET/SDH frames) are received by the Rx WIS logic
in a period of time when only one G1 octet is transmitted. In this situation, one of the two B3 error counts
delivered to the Tx WIS logic is discarded. This situation occurs when the receive data rate is faster than
the transmit data rate. Similarly, when the transmit data rate is faster than the receive data rate, a B3
error count is not available for REI-P insertion into the G1 octets of the transmitted SONET/SDH frame. A
value of zero is transmitted in this case. This behavior is achieved by using a FIFO to transfer the
detected B3 error count from the receive to transmit domains.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
26
Functional Descriptions
3.3.5.3
STS Path Signal Label and Path Label Mismatch (C2)
The C2 octet contains a value intended to describe the type of payload carried within the SONET/SDH
frame. The WIS standard calls for a 0x1A to be transmitted. This is the default value of
EWIS_TX_C2_H1.TX_C2.
As specified in T1.416, a path label mismatch (PLM-P), register WIS_STAT3.PLMP, event occurs when
the C2 octet in five consecutive frames contain a value other than the expected one. The expected value
is set in EWIS_MODE_CTRL.C2_EXP, whose default value 0x1A is compliant with the WIS standard.
When a value of 0x00 is accepted (received for five or more consecutive frames) the unequipped path
pending (EWIS_INTR_PEND2.UNEQP_PEND) event is asserted until read. A non-latch high version of
this event (EWIS_INTR_STAT2.UNEQP_STAT) is also available. This event can propagate an interrupt
to either WIS_INTA or WIS_INTB, based on the mask enable bits
EWIS_INTR_MASKA_2.UNEQP_MASKA and EWIS_INTR_MASKB_2.UNEQP_MASKB.
If the accepted value is not an unequipped label (0x00) and it differs from the programmed expected
value, EWIS_MODE_CTRL.C2_EXP, then a path label mismatch (WIS_STAT3.PLMP) is asserted.
Similarly the EWIS_INTR_PEND1.PLMP_PEND event is asserted until read. This event can propagate
an interrupt to either WIS_INTA or WIS_INTB, based on the mask enable bits
EWIS_INTR_MASKA_1.PLMP_MASKA and EWIS_INTR_MASKB_1.PLMP_MASKB.
Although PLMP is not a path level defect, it does cause a change in the setting of one of the ERDI-P
codes. For more information, see Table 13, page 28.
3.3.5.4
Remote Path Error Indication (G1)
The most significant four bits of the G1 octet are used for back reporting the number of B3 block errors
received at the near-end. This is typically known as path remote error indication (REI-P). The value in
this octet comes from the B3 error FIFO. The WIS standard defines a 16-bit REI-P counter, register
WIS_REIP_CNT. The WIS standard defines this counter to operate as a block counter as opposed to an
individual errored bit counter. This counter is non-saturating and so rolls over after its maximum count.
The counter does not clear upon a read, but instead only upon reset as defined in the WIS specification.
When the counter is nonzero, the EWIS_INTR_PEND2.REIP_PEND event register is asserted until
read. A non-latch high version of this event EWIS_INTR_STAT2.REIP_STAT is also available. This event
may propagate an interrupt to either WIS_INTA or WIS_INTB, based on the mask enable bits
EWIS_INTR_MASKA_2.REIP_MASKA and EWIS_INTR_MASKB_2.REIP_MASKB, respectively.
An additional 32-bit REI-P counter is provided at REIP_ERR_CNT (EWIS_REIP_CNT1 and
EWIS_REIP_CNT0), which is a saturating counter, and is latched and cleared based upon a PMTICK
event. Errors are accumulated since the previous PMTICK event. When the counter is nonzero, the
EWIS_INTR_PEND2.REIP_NZ_PEND event register is asserted until read. A non-latch high version of
this event (EWIS_INTR_STAT2.REIP_NZ_STAT) is also available. This event may propagate an
interrupt to either WIS_INTA or WIS_INTB, based on the mask enable bits
EWIS_INTR_MASKA_2.REIP_NZ_MASKA and EWIS_INTR_MASKB_2.REIP_NZ_MASKB,
respectively.
The REIP_ERR_CNT may optionally be configured to increment on a block count basis, a maximum
increment of 1 per errored frame, regardless of the number of errors received. This mode is enabled by
asserting EWIS_CNT_CFG.REIP_BLK_MODE.
3.3.5.5
Path Status (G1)
In addition to back-reporting the far-end B3 BIP-8 error count, the G1 octet carries status information
from the far-end device known as path remote defect indicator (RDI-P). T1.416 allows either support of 1bit RDI-P or 3-bit ERDI-P, but indicates ERDI-P is preferred. The VSC8489-02 device supports both
modes and may be independently configured for the Rx and Tx directions by configuring
EWIS_MODE_CTRL.RX_ERDI_MODE and EWIS_TXCTRL2.ERDI_TX_MODE. ERDI-P is the default
for both directions.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
The following tables show the different structures for this octet.
Path Status (G1) Byte for RDI-P Mode
Table 11 •
G1 REI (B3)
1
2
3
4
Remote Error Indicator count from B3
(0–8 value)
RDI-P
Reserved
Spare
5
6
8
7
Remote Defect Set to 00 by
indicator
transmitter
Ignored by
receiver
Path Status (G1) Byte for ERDI-P Mode
Table 12 •
G1 REI (B3)
1
ERDI-P
2
3
4
Remote Error Indicator count from B3
(0–8 value)
5
Spare
6
7
Enhanced Remote Defect
Indicator (see following table)
8
Ignored by
receiver
Enhanced RDI is defined for SONET-based systems as listed in GR-253-CORE (Issue 3), reproduced
here in the following table, and as a possible enhancement of SDH-based systems (G.707/Y.1322
(10/2000) Appendix VII (not an integral part of that recommendation)).
Table 13 •
RDI-P and ERDI-P Bit Settings and Interpretation
Priority of
G1 Bits 5, 6, and 7 ERDI-P Codes
Trigger
Interpretation
000/011
Not applicable
No defects.
No RDI-P defect
100/111
Not applicable
Path alarm indication signal (AIS-P). The
remote device sends all ones for H1, H2, H3,
and the entire STS SPE.
Path loss of pointer (LOP-P).
One-bit RDI-P
defect
001
4
No defects.
No ERDI-P defect
010
3
Path label mismatch (PLM-P). Path loss of code ERDI-P payload
group delineation (LCD-P).
defect
101
1
Path alarm indication signal (AIS-P). The
remote device sends all ones for H1, H2, H3
and entire STS SPE.
Path loss of pointer (LOP-P).
110
2
Path unequipped (UNEQ-P). The received C2 ERDI-P
connectivity
byte is 0x00.
defect
Path trace identifier mismatch (TIM-P). This
error is not automatically generated, but can be
forced using MDIO.
ERDI-P server
defect
In the receive direction, with EWIS_MODE_CTRL.RX_ERDI_MODE = 0, an RDI-P defect is the
occurrence of the RDI-P signal in ten contiguous frames. An RDI-P defect terminates when no RDI-P
signal is detected in ten contiguous frames. An RDI-P event asserts
EWIS_INTR_PEND2.FERDIP_PEND until read. A non-latch high version of the far-end RDI-P status can
be found in EWIS_INTR_STAT2.FERDIP_STAT. This event may propagate an interrupt to either
WIS_INTA or WIS_INTB, based on the mask enable bits EWIS_INTR_MASKA_2.FERDIP_MASKA and
EWIS_INTR_MASKB_2.FERDIP_MASKB.
When EWIS_MODE_CTRL.RX_ERDI_MODE = 1, an ERDI-P defect is the occurrence of any one of
three ERDI-P signals in ten contiguous frames. An ERDI-P defect terminates when no ERDI-P signal is
detected in ten contiguous frames.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
28
Functional Descriptions
The 010 code triggers the latch high register bit WIS_STAT3.FEPLMP_LCDP. It also asserts
EWIS_INTR_PEND1.FEPLMP_LCDP_PEND until read. This event may propagate an interrupt to either
WIS_INTA or WIS_INTB, based on the mask enable bits
EWIS_INTR_MASKA_1.FEPLMP_LCDP_MASKA and
EWIS_INTR_MASKB_1.FEPLMP_LCDP_MASKB, respectively.
The 101 code triggers the latch high register bit WIS_STAT3.FEAISP_LOPP. It also asserts
EWIS_INTR_PEND1.FEAISP_LOPP_PEND until read. This event may propagate an interrupt to either
WIS_INTA or WIS_INTB, based on the mask enable bits
EWIS_INTR_MASKA_1.FEAISP_LOPP_MASKA and EWIS_INTR_MASKB_1.FEAISP_LOPP_MASKB,
respectively.
The 110 code asserts the EWIS_INTR_PEND2.FEUNEQP_PEND until read. A non-latch-high version of
this register (EWIS_INTR_STAT2.FEUNEQP_STAT) is also available. This event may propagate an
interrupt to either WIS_INTA or WIS_INTB, based on the mask enable bits
EWIS_INTR_MASKA_2.FERDIP_MASKA and EWIS_INTR_MASKB_2.FERDIP_MASKB, respectively.
3.3.5.6
Path User Channel (F2)
The WIS standard does not support the F2 octet and recommends transmitting 0x00 in place of the F2
octet. A value other than 0x00 may be transmitted by programming the intended value at
EWIS_TX_K2_F2.TX_F2.
3.3.5.7
Multi-frame Indicator (H4)
The WIS standard does not support the H4 multi-frame octet and recommends transmitting 0x00 in place
of the H4 octet. A value other than 0x00 may be transmitted by programming the intended value at
EWIS_TX_D6_H4.TX_H4.
3.3.5.8
Reserved for Path Growth (Z3-Z4)
The WIS standard does not support the Z3-Z4 octets and recommends transmitting 0x00 in their place. A
value other than 0x00 may be transmitted by programming the intended value at
EWIS_TX_D9_Z3.TX_Z3 and EWIS_TX_D12_Z4.TX_Z4 respectively.
3.3.5.9
Tandem Connection Maintenance/Path Data Channel (N1)
The WIS standard does not support the N1 octet and recommends transmitting 0x00 in place of the N1
octet. A value other than 0x00 may be transmitted by programming the intended value at
EWIS_TX_N1.TX_N1.
3.3.5.10
Loss of Code Group Delineation
After the overhead is stripped, the payload is passed to the PCS. If the PCS block loses synchronization
and cannot delineate valid code groups, the PCS passes a loss of code group delineation (LCD-P) alarm
to the WIS. This alarm triggers the latch high register bit WIS_STAT3.LCDP. It also asserts
EWIS_INTR_PEND1.LCDP_PEND until read. This event may propagate an interrupt to either WIS_INTA
or WIS_INTB, based on the mask enable bits EWIS_INTR_MASKA_1.LCDP_MASKA and
EWIS_INTR_MASKB_1.LCDP_MASKB, respectively.
The WIS specification calls for a LCD-P defect persisting continuously for more than 3 ms to be back
reported to the far-end. Upon device reset, a LCD-P is back reported until the PCS signals that valid
code groups are being delineated. The LCD-P defect deasserts (and is not back reported) after the
condition is absent continuously for at least 1 ms.
3.3.5.11
Reading Statistical Counters
The VSC8489-02 device contains several counters that may be read using the MDIO interface. For each
error count, there are two sets of counters. The first set is the standard WIS counter implemented
according to IEEE 802.3ae, and the second set is for statistical counts using PMTICK.
To read the IEEE 802.3ae counters, the station manager must read the most significant register of the
32-bit counter first. This read action latches the internal error counter value into the MDIO readable
registers. A subsequent read of the least significant register does not latch new values, but returns the
value latched at the time of the most significant register read.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
29
Functional Descriptions
It may be difficult to get a clear picture of the timeframes in which errors were received because the IEEE
802.3ae counters are independently latched. The PMTICK counters are all latched together, thereby
providing a complete snapshot in time. When PMTICK is asserted, the internal error counter values are
copied into their associated registers and the internal counters are reset.
There are three methods of asserting PMTICK.
•
The station manager may asynchronously assert EWIS_PMTICK_CTRL.PMTICK_FRC to latch the
values at a given time, regardless of the EWIS_PMTICK_CTRL.PMTICK_ENA setting.
The VSC8489-02 device may be configured to latch and clear the statistical counters at a periodic
interval as determined by the timer (count) value in EWIS_PMTICK_CTRL.PMTICK_DUR. In this
mode, the EWIS_PMTICK_CTRL.PMTICK_SRC must be configured for internal mode and the
EWIS_PMTICK_CTRL.PMTICK_ENA bit must be asserted. The receive path clock is used to drive
the PMTICK counter, thus the periodicity of the timer can vary during times of loss of lock and loss of
frame.
The VSC8489-02 device may be configured to latch and clear the statistical counters at the
occurrence of a rising edge detected at a GPIO pin configured as a PMTICK input pin. In this mode,
the EWIS_PMTICK_CTRL.PMTICK_SRC bit must be deasserted, and the
EWIS_PMTICK_CTRL.PMTICK_ENA must be asserted. Corresponding GPIO must be configured
as the PMTICK input pin.
•
•
Regardless of EWIS_PMTICK_CTRL.PMTICK_SRC, when the PMTICK event occurs, the
EWIS_INTR_PEND2.PMTICK_PEND is asserted until read. This event may propagate an interrupt to
either WIS_INTA or WIS_INTB, based on the mask enable bits
EWIS_INTR_MASKA_2.PMTICK_MASKA and EWIS_INTR_MASKB_2.PMTICK_MASKB, respectively.
Given the size of the error counters and the maximum allowable error counts per frame, care must be
taken in the frequency of polling the registers to ensure accurate values. All PMTICK counters saturate at
their maximum values.
Table 14 •
PMTICK Counters
Maximum
Increase
Count Per
Frame
Maximum
Increase
Count Per
Second
Time Until
Overflow
67,109
Counter Name
Description
Registers
B1_ERR_CNT
B1 section error count
EWIS_B1_ERR_CNT1 8
EWIS_B1_ERR_CNT0
64,000
B2_ERR_CNT
B2 line error count
EWIS_B2_ERR_CNT1 1536
EWIS_B2_ERR_CNT0
12,288,000 350
B3_ERR_CNT
B3 path error count
EWIS_B3_ERR_CNT1 8
EWIS_B3_ERR_CNT0
64,000
67,109
EWIS_REIP_CNT Far-end B3 path error count
EWIS_REIP_CNT1
EWIS_REIP_CNT0
8
64,000
67,109
EWIS_REIL_CNT Far-end B2 line error count
EWIS_REIL_CNT1
EWIS_REIL_CNT0
1536
12,288,000 350
Both individual and block mode accumulation of B1, B2, and B3 error indications are supported and
selectable using the control bits EWIS_CNT_CFG.B1_BLK_MODE, EWIS_CNT_CFG.B2_BLK_MODE,
and EWIS_CNT_CFG.B3_BLK_MODE. In individual accumulation mode 0, the counter is incremented
for each bit mismatch between the calculated B1, B2, and/or B3 error and the extracted B1, B2, and/or
B3. In block accumulation mode 1, the counter is incremented only once for any nonzero number of bit
mismatches between the calculated B1, B2, and/or B3 and the extracted B1, B2, and/or B3 (maximum of
one error per frame).
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
30
Functional Descriptions
3.3.6
Defects and Anomalies
All defects and anomalies listed in the following table can be forced and masked by the user. The
VSC8489-02 device does not automatically generate TIM-P, but does support forcing defects using
MDIO.
Table 15 •
Defects and Anomalies
Defect or
Anomaly
Description
Type
Force Bit
Far-end PLM-P These two errors are indistinguishable when
or LCD-P
reported by the far-end through the G1 octet
(ERDI-P), because the far-end reports both
PLM-P and LCD-P with the same error code.
Far-end defect
EWIS_RX_ER WIS_STAT3.
R_FRC2.FRC_ FEPLMP_LC
RX_FE_PLMP DP
Far-end AIS-P
or LOP-P
These two errors are indistinguishable when
reported by the far-end through the G1 octet
(ERDI-P), because the far-end reports both
AIS-P and LOP-P with the same error code.
Far-end defect
EWIS_RX_ER WIS_STAT3.
R_FRC2.FRC_ FEAISP_LOP
RX_FE_AISP P
PLM-P
Path label mismatch. The detection and
reporting of the PLM-P defect follows section
7.5 of ANSI T1.416-1999.
Near-end
defect;
propagated to
PCS
EWIS_RX_ER WIS_STAT3.
R_FRC2.FRC_ PLMP
RX_PLMP
AIS-L
Generated on LOPC, LOS, LOF, if enabled by
EWIS_RXTX_CTRL.RXAISL_ON_LOPC,
EWIS_RXTX_CTRL.RXAISL_ON_LOS,
EWIS_RXTX_CTRL.RXAISL_ON_LOF, or
when forced by user.
Near-end defect The AIS-L
defect is only
processed and
reported by the
WIS Receive
process; it is
never
transmitted by
the WIS
Transmit
process,
according to
IEEE 802.3ae.
AIS-P
Path alarm indication signal.
Near-end
defect;
propagated to
PCS
EWIS_RX_ER WIS_STAT3.
R_FRC1.FRC_ AISP
RX_AISP
LOP-P
Path loss of pointer. Nine consecutive invalid
pointers result in loss of pointer detection. See
Figure 13, page 24 for the pointer interpreter
state machine.
Near-end
defect;
propagated to
PCS
EWIS_RX_ER WIS_STAT3.
R_FRC1.FRC_ LOPP
RX_LOP
LCD-P
Path loss of code group delineation. See
Table 13, page 28. This is also reported to the
far-end if it persists for at least 3 ms.
Near-end defect EWIS_RX_ER WIS_STAT3.
R_FRC2.FRC_ LCDP
LCDP
LOPC
Loss of optical carrier alarm. This is an input
from the XFP module’s loss of signal output.
The polarity can be inverted for use with other
module types. This defect can be used
independently or in place of LOS.
Near-end defect EWIS_RX_ER EWIS_INTR_
R_FRC1.FRC_ STAT2.LOPC
LOPC
_STAT
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
Status Bit
EWIS_RX_E
RR_FRC1.F
RC_RX_AISL
/WIS_STAT3.
AISL
31
Functional Descriptions
Table 15 •
Defects and Anomalies (continued)
Defect or
Anomaly
Description
Type
Force Bit
Status Bit
LOS
The PMA circuitry detects a loss of signal (LOS) Near-end defect EWIS_RX_ER WIS_STAT3.
defect if the input signal falls below the assert
R_FRC1.FRC_ LOS
threshold. When a PMA LOS is declared the
LOS
framer is held in reset to prevent it from looking
for a frame boundary.
SEF
Severely errored frame. Generated when
device cannot frame to A1 A2 pattern. SEF
indicates synchronization process is not in the
SYNC state, as defined by the state diagram of
IEEE 802.3ae clause 50.4.2.
Near-end
defect;
propagated to
PCS
LOF
Generated when SEF persists for 3 ms.
Terminated when no SEF occurs for 1 ms to
3 ms.
Near-end defect EWIS_RX_ER WIS_STAT3.
R_FRC2.FRC_ LOF
RX_LOF
B1 PMTICK
error count is
nonzero
BIP-N(S) - 32-bit near-end section BIP error
counter is nonzero.
Near-end
anomaly
EWIS_RX_ER EWIS_INTR_
R_FRC2.FRC_ STAT2.B1_N
Z_STAT
RX_B1
B2 PMTICK
error count is
nonzero
BIP-N(L) - 32-bit near-end line BIP error
counter is nonzero.
Near-end
anomaly
EWIS_RX_ER EWIS_INTR_
R_FRC2.FRC_ STAT2.B2_N
Z_STAT
RX_B2
B3 PMTICK
error count is
nonzero
BIP-N(P) - 32-bit near-end path BIP error
counter is nonzero.
Near-end
anomaly
EWIS_RX_ER EWIS_INTR_
R_FRC2.FRC_ STAT2.B3_N
RX_B3
Z_STAT
REI-L
Line remote error indicator octet is nonzero.
Far-end BIP-N(L).
Far-end
anomaly
EWIS_RX_ER EWIS_INTR_
R_FRC2.FRC_ STAT2.REIL_
RX_REIL
STAT
REI-L PMTICK Line remote error indicator is nonzero. Far-end Far-end
error count is
BIP-N(L).
anomaly
nonzero
EWIS_RX_ER EWIS_INTR_
R_FRC2.FRC_ STAT2.REIL_
NZ_STAT
REIL
RDI-L
Line remote defect indicator.
Far-end defect
EWIS_RX_ER WIS_STAT3.
R_FRC1.FRC_ RDIL
RX_RDIL
REI-P
Path remote error indicator octet is nonzero.
Far-end BIP-N(P).
Far-end
anomaly
EWIS_RX_ER EWIS_INTR_
R_FRC2.FRC_ STAT2.REIP_
RX_REIP
STAT
REI-P PMTICK Path remote error indicator. Far-end BIP-N(P). Far-end
error count is
anomaly
nonzero
EWIS_RX_ER EWIS_INTR_
R_FRC2.FRC_ STAT2.REIP_
REIP
NZ_STAT
EWIS_RX_ER WIS_STAT3.
R_FRC2.FRC_ SEF
RX_SEF
UNEQ-P
Unequipped path.
Near-end defect EWIS_RX_ER EWIS_INTR_
R_FRC2.FRC_ STAT2.UNEQ
RX_UNEQP
P_STAT
Far-end
UNEQ-P
Far-end unequipped path.
Far-end defect
3.3.7
EWIS_RX_ER EWIS_INTR_
R_FRC2.FRC_ STAT2.FEUN
RX_FE_UNEQ EQP_STAT
P
Interrupt Pins and Interrupt Masking
The VSC8489-02 device generates interrupts for each defect and anomaly. The interrupts for the BIP
error counts (B1, B2, and B3 counters) and the interrupts for the far-end error counts (REI-L and REI-P)
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
32
Functional Descriptions
are generated when the PMTICK counters become nonzero. Mask enable bits propagate the interrupt
pending event to GPIO pins configured as WIS_INTA and WIS_INTB. Each event may be optionally
masked for each WIS_INTA/B pin.
The WIS_INTA and WIS_INTB signals are routed off-chip through GPIO pins. Many specialized
functions share the GPIO pins. The WIS_INTA and WIS_INTB signals do not go to dedicated pins.
For each defect or anomaly defined in IEEE 802.3ae, the VSC8489-02 device supports the standard WIS
register. In addition, the VSC8489-02 device supports another set of registers in the WIS Vendor Specific
area. These registers provide a STATUS bit to indicate the current real-time status of the event, a
PENDING bit to indicate if the STATUS bit has changed state, and two mask enable bits for each
interrupt pin (WIS_INTA and WIS_INTB). The STATUS bit is set if and only if the interrupt currently
exists. This STATUS bit does not latch.
The defects and anomalies are constructed in a hierarchy such that lower order alarms are squelched
when higher order events are detected. For more information about the dependencies between
squelches and events, see the WIS interrupt registers.
3.3.8
Overhead Serial Interfaces
The VSC8489-02 device includes provisions for off-chip processing of the critical SONET/SDH transport
overhead 9-bit words through two independent serial interfaces. The transmit overhead serial interface
(TOSI) is used to insert 9-bit words into the transmit frames, and the receive overhead serial interface
(ROSI) is used to recover the 9-bit words from the received frames. Each interface consists of three pins:
a clock output, a frame pulse output, and a data input (Tx) /output (Rx). These I/O are LVTTL compatible
for easy connection to an external device such as an FPGA.
Note: Extended WIS TOSI and ROSI do not support path overhead bytes.
The TOSI / ROSI signals are routed off-chip through GPIO pins. If the ROSI/TOSI interfaces are to be
used, there are no GPIO pins left in the design for any other function—loss-of-lock for Sync-E
applications, activity LED drivers, WIS_interrupts, or two-wire serial (slave) interface.
All references to TCLKOUT, TFPOUT, TDAIN, RCLKOUT, RFPOUT and RDAOUT are the TOSI/ROSI
signals routed through GPIO pins.
3.3.8.1
Transmit Overhead Serial Interface (TOSI)
The TOSI port enables the user to individually program 222 separate 9-bit words in the SONET/SDH
overhead. The SONET/SDH frame rate is 8 kHz as signaled by the frame pulse (TFPOUT) signal. The
TOSI port is clocked from a divided-down version of the WIS transmit clock made available on
TCLKOUT. To provide a more standard clock rate, 9-bit dummy words are added per frame, resulting in a
clock running at one five-hundred-twelfth of the line rate (or 19.44 MHz). For each 9-bit word, the external
device indicates the desire to transmit that byte by using an enable indicator bit (EIB) that is appended to
the beginning of the 9-bit word. If EIB = 0, the data on the serial interface is ignored for that overhead 9bit word. If EIB = 1, the serial interface data takes precedence over the value generated within the
VSC8489-02 device. The EIB is present before the 9-bit dummy words too, however its value has no
effect as the 9-bit dummy words are ignored within the device. The first EIB bit should be transmitted by
the external device on the first rising edge of TCLKOUT after TFPOUT, as shown in the following
illustration. The data should be provided with the most significant bit (MSB) first. After reception of the
TOSI data for a complete frame, the values are placed in the overhead for the next transmitted frame.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
33
Functional Descriptions
Figure 14 • TOSI Timing Diagram
TCLKOUT
TFPOUT
A1
Bit 1
A1
EIB
Padding
Dummy Bits
TDAIN
A1
Bit 2
A1
Bit 3
Some 9-bit words are error masks, such that the transmitted 9-bit word is the XOR of the TOSI 9-bit word
and the pre-defined value within the chip if the EIB is enabled. This feature is best used for test purposes
only.
The order of the 9-bit word required by the TOSI port is summarized in the following table, where the
number of registers is the number of bytes on the serial interface and the number of bytes is the number
of STS channels on which the byte is transmitted. For H1 and H2 pointers, bytes 2 to 192 are
concatenation indication bytes consistent with STS-192c frames. There are not 192 different point
locations as in STS-192 frames.
Table 16 •
TOSI/ROSI Addresses
Byte Name
9-Bit
Word
TOSI/
ROSI
Byte
Order
Frame boundary
A1
0
1
192
Programmable byte that is
identical for all locations
Frame boundary
A2
1
1
192
Programmable byte that is
identical for all locations
Section trace
J0
2
1
1
Programmable byte
Section growth
Z0
3
1
191
Programmable byte that is
identical for all locations
4
1
1
Programmable byte
Dummy byte
Number of Number
Registers of Bytes
Type
Section BIP-8
B1
5
1
1
TOSI inserts error mask; ROSI
extracts XOR of B1 value and
received data
Orderwire
E1
6
1
1
Programmable byte
Section user channel
F1
7
1
1
Programmable byte
8
1
1
Programmable bytes
Dummy byte
Section DCC 1
D1
9
1
1
Programmable byte
Section DCC 2
D2
10
1
1
Programmable byte
Section DCC 3
D3
11
1
1
Programmable byte
12
1
1
Programmable byte
13
1
1
Programmable byte affecting the
first H1 byte
Dummy byte
Pointer 1
H1
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
34
Functional Descriptions
Table 16 •
TOSI/ROSI Addresses (continued)
Byte Name
9-Bit
Word
TOSI/
ROSI
Byte
Order
Pointer 2
H2
14
1
1
Programmable byte affecting the
first H2 byte
Pointer action
H3
15
1
192
Programmable byte that is
identical for all locations
16
1
1
Programmable byte
17 to 208 192
192
TOSI inserts error mask for each
byte; ROSI extracts XOR of B2
value and received data for each
byte
Automatic protection K1
switching (APS)
channel and remote
defect indicator (RDI)
209
1
1
Programmable byte
Automatic protection K2
switching (APS)
channel and remote
defect indicator (RDI)
210
1
1
Programmable byte
Dummy byte
211
1
1
Programmable byte
Dummy byte
Line BIP-8
B2
Number of Number
Registers of Bytes
Type
Line DCC 4
D4
212
1
1
Programmable byte
Line DCC 5
D5
213
1
1
Programmable byte
Line DCC 6
D6
214
1
1
Programmable byte
215
1
1
Programmable byte
Dummy byte
Line DCC 7
D7
216
1
1
Programmable byte
Line DCC 8
D8
217
1
1
Programmable byte
Line DCC 9
D9
218
1
1
Programmable byte
219
1
1
Programmable byte
Dummy byte
Line DCC 10
D10
220
1
1
Programmable byte
Line DCC 11
D11
221
1
1
Programmable byte
Line DCC 12
D12
222
1
1
Programmable byte
223
1
1
Programmable byte
Dummy byte
Synchronization
message
S1
224
1
1
Programmable byte
Growth 1
Z1
225
1
191
Programmable byte that is
identical for all locations
Growth 2
Z2
226
1
190/191
Programmable byte that is
identical for all locations;
dependent upon 2xEC40.12
STS-1 REI-L
M0
227
1
1
Programmable byte
STS-N REI-L
M1
228
1
1
Programmable byte
Orderwire 2
E2
229
1
1
Programmable byte
230
1
1
Programmable byte
Dummy byte
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
35
Functional Descriptions
Table 16 •
TOSI/ROSI Addresses (continued)
9-Bit
Word
Byte Name
Padding dummy bytes
3.3.8.2
TOSI/
ROSI
Byte
Order
231 to
269
Number of Number
Registers of Bytes
Type
39
No function
Receive Overhead Serial Interface (ROSI)
The ROSI port extracts the same 222 overhead 9-bit words from the SONET/SDH frame, and consists of
the clock output (RCLKOUT), frame pulse output (RFPOUT), and data output (RDAOUT). The ROSI port
is clocked from a divided-down version of the WIS receive clock, and is valid during in-frame conditions
only. As with the TOSI port, 9-bit dummy words are provided each frame period resulting in a 19.44 MHz
RCLKOUT frequency. For each 9-bit word, including the 9-bit dummy words, an extra 0 bit is added at
the beginning of each byte so that the TOSI and ROSI clock rates are identical. The first stuff bit for each
frame is transmitted by RDAOUT on the first rising edge of RCLKOUT after the frame pulse (RFPOUT),
as shown in the following illustration.
Because the receive path overhead can be split across two frames, the VSC8489-02 device buffers the
overhead for an additional frame time so that a complete path overhead is presented. Table 16, page 34
outlines the order for each of the 9-bit words presented on the ROSI port. With the exception of the
M0/M1 9-bit words, the extracted 9-bit words are from the first channel position. In place of parity and
error 9-bit words, the VSC8489-02 device outputs the result of an XOR between the calculated BIP and
the received value. Therefore, a count of ones within each of the BIP 9-bit words should correspond with
the internal error accumulators. The following illustration shows the functional timing for the ROSI port.
Figure 15 • ROSI Timing Diagram
RCLKOUT
RFPOUT
RDAOUT
3.3.9
Padding
Dummy Bits
‘0’
Stuff
A1
Bit 1
A1
Bit 2
A1
Bit 3
Pattern Generator and Checker
The VSC8489-02 device implements the square wave, PRBS31, and mixed-frequency test patterns as
described in section 50.3.8 of IEEE 802.3ae as well as the test signal structure (TSS) and continuous
identical digits (CID) pattern.
The square wave pattern is selected asserting WIS_CTRL2.TEST_PAT_SEL and the generator is
enabled by asserting WIS_CTRL2.TEST_PAT_GEN. When WIS_CTRL2.TEST_PAT_SEL is deasserted,
the mixed frequency test pattern is selected. The square wave frequency is configured according to
EWIS_TXCTRL2.SQ_WV_PW. The WIS_CTRL2.TEST_PAT_ANA bit is used to enable the test pattern
checker in the receive path. The checker does not operate on square wave receive traffic. Error counts
from the mixed frequency pattern are presented in the SONET/SDH BIP-8 counters, B1_CNT
WIS_B1_CNT, WIS_B2_CNT, and WIS_B3_CNT.
The VSC8489-02 device supports the PRBS31 test pattern as reflected in
WIS_STAT2.PRBS31_ABILITY. The transmitter/generator is enabled by asserting
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
36
Functional Descriptions
WIS_CTRL2.TEST_PRBS31_GEN, while the receiver/checker is enabled by asserting
WIS_CTRL2.TEST_PRBS31_ANA. Because the mixed frequency/square wave test patterns have
priority over the PRBS31 pattern, WIS_CTRL2.TEST_PAT_GEN must be disabled for the PRBS31 test
pattern to be sent. Error counts from the PRBS31 checker are available in WIS_TSTPAT_CNT. This
register does not roll over after reaching its maximum count and is cleared after every read operation.
Two status bits are available from the PRBS checker. The EWIS_PRBS31_ANA_STAT.PRBS31_ERR bit
indicates whether the error counter is nonzero. The EWIS_PRBS31_ANA_STAT.PRBS31_ANA_STATE
bit if asserted indicates that checker is synchronized and actively checking received bits. For test
purposes, the PRBS generator can inject single bit errors. By asserting
EWIS_PMTICK_CTRL.PMTICK_SRC, a single bit error is injected, resulting in three bit errors being
detected within the checker. The value of three comes from the specification, which indicates one error
should be detected for each tap within the checker.
3.4
10G Physical Coding Sublayer (64B/66B PCS)
The 10G physical coding sublayer (PCS) is defined in IEEE 802.3ae Clause 49. It is composed of the
PCS transmit, PCS receive, block synchronization, and BER monitor processes. The PCS functions can
be further broken down into encode or decode, scramble or descramble, and gearbox functions, as well
as various test and loopback modes.
The PCS is responsible for transferring data between the XAUI clock domain and the WIS/PMA clock
domain. In addition, the PCS encodes and scrambles the data for efficient transport across the given
medium.
The following illustration provides a block diagram of the 10G PCS block.
Figure 16 • PCS Block Diagram
Tx PCS and EPCS
LAN 64b/66b
Encoder and
Scrambler
64
66
66
66:64 Gear Box
64
XGXS
WIS/PMA
Buffer
Rx PCS and EPCS
Buffer
3.4.1
LAN 64b/66b
Decoder and
Descrambler
64
66
66:64 Gear Box
64
Control Codes
The VSC8489-02 device supports the use of all control codes and ordered sets necessary for 10 GbE
and 10 GFC operation. The following table lists the control characters, notation, and control codes.
Table 17 •
Control Codes
Control Codes
Control
Character
Notation1
XGMII Control
Code
10-G BASE-R
Control Code
8b/10b Code2
Idle
/I/
0x07
0x00
K28.0 or
K28.3 or
K28.5
Start
/S/
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
10-G BASE-R
O Code
0xfb
37
Functional Descriptions
Table 17 •
Control Codes (continued)
Control Codes
(continued)
Notation1
XGMII Control
Code
10-G BASE-R
Control Code
10-G BASE-R
O Code
Encoded by block type
field
K27.7
Terminate
/T/
0xfd
Encoded by block type
field
K29.7
Error
/E/
0xfe
0x1e
K30.7
Sequence
ordered_set
/Q/
0x9c
K28.4
Reserved 0
/R/
0x1c
0x2d
K28.0
Reserved 1
0x33
K28.1
Reserved 2
/A/
0x7c
0x4b
K28.3
Reserved 3
/K/
0xbc
0x55
K28.5
Reserved 4
0xdc
0x66
K28.6
Reserved 5
0xf7
0x78
K23.7
Signal
ordered_set3
Encoded by block type
field plus O code
Encoded by block type
field plus O code
1.
2.
3.
3.4.2
Control
Character
0x0
0xF
0x3c
/Fsig/
0x5c
K28.2
The codes for /A/, /K/ and /R/ are used on the XAUI interface to signal idle.
For information only. The 8b/10b code is specified in Clause 36. Usage of the 8b/10b code for 10 Gbps operation
is specified in Clause 4.
Reserved for INCITS T11 - 10 GFC µs.
Transmit Path
In the transmit direction, the PCS accepts data from the XGXS interface, which runs off the XAUI
recovered clock and transfers the data onto the PMA transmit clock domain, through the rate-disparity
compensating FIFO. Based on the FIFO’s fill level, idle characters are added or removed as needed.
Once in the PMA clock domain, the de-serialized XAUI input data (64-bit) is checked for validity.
Transmitted data is handled according to IEEE 802.3ae Clause 49.
The characters are then processed in a two-step manner. First, the 64 bits are encoded and a 2-bit
header is calculated to form a single 66-bit block. The two header bits are used for block delineation and
classification. The only valid header codes are 01 to indicate a payload of all data octets and 10 to
indicate the presence of one or more control characters within the payload. To maintain a DC balanced
signal on the serial line, the 64-bit encoded payload is scrambled using a self-synchronizing scrambler
that implements the polynomial G(x) = 1 + x39 + x58. The header bits are not scrambled as they are
already DC balanced. For debug purposes, the scrambler can be disabled by deasserting SCR_DIS
(3x8005.9).
The 66-bit blocks are then passed to the PMA through a 66:64 gearbox. The gearbox merely feeds the
66-bit data into the WIS/PMA’s 64-bit data path.
3.4.3
Receive Path
In the receive direction, the PCS accepts data from the WIS/PMA block and reformats it for transmission
to the XGXS interface. Because of the data path width mismatches between the WIS/PMA and the PCS,
a 64:66 gearbox is needed. The gearbox also performs block synchronization/alignment based upon the
2-bit synchronization header. When the receive logic receives 64 continuous valid sync headers, the
BLOCK_LOCK (3x0021.15) bit is asserted. This bit is a latch-low bit; therefore, a second read of the bit
returns the current status. If 16 invalid block sync headers are detected within a 125 µs period, the
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
38
Functional Descriptions
PCS_HIGHBER (3x0021.14) bit is asserted. This bit is a latch-high bit, and therefore a second read of
the bit returns the current status.
Once block synchronization is achieved, the occurrence of errored blocks are accumulated in the
PCS_ERRORED_BLOCKS (3x0021.7:0) counter. An errored block is one that has one or more of the
following defects:
•
•
•
•
•
The sync field has a value of 00 or 11.
The block type field contains a reserved value (for more information, see Table 17, page 37).
Any control character contains an incorrect value.
Any O code contains an incorrect value.
The set of eight XGMII characters does not have a corresponding block format shown in the
following illustration.
Figure 17 • 64B/66B Block Formats
Input Data
Block Payload
Sync
Bit Position :
0
1
2
65
Data Block Format :
D0
D1
D2
D3/D4
D5
D6
D7
01
D1
D2
D3
0x1e
C0
C1
C2
C3
C4
0x2d
C0
C1
C2
C3
O4
0x33
C0
C1
C2
C3
D1
D2
D3
O0
D1
D2
D3
O0
D1
D2
D1
D2
D0
D4
D5
D6
D7
Block
Type
Field
Control Block Formats:
C0
C1
C2
C3/C4
C5
C6
C7
10
C0
C1
C2
C3/O4
D5
D6
D7
10
C0
C1
C2
C3/S4
D5
D6
D7
10
O0
D1
D2
D3/D4
D5
D6
D7
10
O0
D1
D2
D3/O4
D5
D6
D7
10
S0
D1
D2
D3/D4
D5
D6
D7
10
O0
D1
D2
D3/C4
C5
C6
C7
10
T0
C1
C2
C3/C4
C5
C6
C7
10
D0
T1
C2
C3/C4
C5
C6
C7
10
D0
D1
T2
C3/C4
C5
C6
C7
10
0xaa
D0
D1
D2
T3/C4
C5
C6
C7
10
0xb4
D0
D1
D2
D3/T4
C5
C6
C7
10
0xcc
D0
D1
D2
D3/D4
T5
C6
C7
10
0xd2
D0
D1
D2
D3/D4
D5
T6
C7
10
D0
D1
D2
D3/D4
D5
D6
T7
10
0x66
0x55
0x78
0x4b
0x87
0x99
0xe1
0xff
C1
D0
C5
O4
D4
D3
O0
D3
C6
C7
D5
D6
D7
D5
D6
D7
D5
D6
D7
D5
D6
D7
D5
D6
D7
C4
C5
C6
C7
C4
C5
C6
C7
C7
C2
C3
C2
C3
C4
C5
C6
C3
C4
C5
C6
C7
C4
C5
C6
C7
C5
C6
C7
D0
D1
D0
D1
D2
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D0
D1
D2
D4
C7
C6
D3
D4
D5
D3
D4
D5
C7
D6
Valid blocks recover their original payload data by being descrambled. The descrambler is the same
polynomial used by the transmitter. For test purposes, the descrambler may be disabled by asserting
DSCR_DIS (3x8005.10). The data is checked for valid characters and sequencing.
The data is passed from the PMA/WIS clock domain to the XAUI clock domain through a FIFO. Based
upon the FIFO’s fill level, idle characters are added or removed as needed.
3.4.4
PCS Standard Test Modes
The PCS block offers all of the standard defined test pattern generators and analyzers. In addition, the
VSC8489-02 device supports a 64-bit static user pattern and the optional PRBS31 pattern. Two error
counters are available. Each is a saturating counter that is cleared upon a read operation. The first,
PCS_ERR_CNT, is located in the IEEE Standard area while the 32-bit
PCS_VSERR_CNT_0/PCS_VSERR_CNT_1 is located in the vendor specific area.
The IEEE specification defines two test pattern modes, a square wave generator and a pseudo-random
test pattern. The square wave generator is enabled by first selecting the square wave pattern by
asserting PCS_TSTPAT_SEL, and then enabling the test pattern generator, PCS_TSTPAT_GEN. The
period of the square wave can be controlled in terms of bit times by writing to PCS_SQPW. There is no
associated square wave checker within the VSC8489-02 device.
The pseudo-random test pattern is selected by deasserting PCS_TSTPAT_SEL. The pseudo-random
test pattern contains two data modes. When PCS_TSTDAT_SEL is deasserted, the pseudo-random
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
39
Functional Descriptions
pattern is a revolving series of four blocks with each block 128-bits in length. The four blocks are the
resultant bit sequence produced by the PCS scrambler when pre-loaded with the following seeds:
•
•
•
•
PCS_SEEDA_0, PCS_SEEDA_1, PCS_SEEDA_2, PCS_SEEDA_3
PCS_SEEDA invert
PCS_SEEDB_0, PCS_SEEDB_1, PCS_SEEDB_2, PCS_SEEDB_3
PCS_SEEDB invert
The pattern generator is enabled by asserting PCS_TSTPAT_GEN while the analyzer is enabled by
asserting PCS_TSTPAT_ANA. Errors are accumulated in the clear-on-read saturating counter,
PCS_ERR_CNT. In pseudo-random pattern mode, the error counter counts the number of errored
blocks.
Support for the optional PRBS31 pattern is indicated by PRBS31_pattern_testing_ability register whose
default is high. The PRBS31 test generator is selected by asserting PCS_PRBS31_GEN, while the
checker is enabled by asserting PCS_PRBS31_ENA. IEEE standards specify that the error counter
should increment for each linear feedback shift register (LFSR) tap that a bit is in error. Therefore, a
single bit error increments the counter by three because there are three taps in the PRBS31 polynomial.
The user-defined 64-bit static pattern can be written to PCS_USRPAT registers and enabled by asserting
PCS_USRPAT_ENA and PCS_TSTPAT_GEN. Enabling the user-defined pattern enables both the
generator and analyzer.
3.5
1G Physical Coding Sublayer
The 1G physical coding sublayer (PCS) implements 1000BASE-X as specified by IEEE 802.3 Clause 36,
and auto-negotiation as specified by IEEE 802.3 Clause 37. It provides for the encoding (and decoding)
of GMII data octets to (and from) ten-bit code-groups (8B/10B) for communication with the underlying
PMA. It also manages link control and the auto-negotiation process.
In addition to these standard 1000BASE-X functions, the 1G PCS also includes a conversion function
that maps the standard GMII data to (and from) an internal XGMII-like interface. This allows the
processing core to be largely agnostic to whether a channel is operating in 1G or 10G operation.
3.6
Rate Compensating Buffers
Rate compensating buffers are used in the data paths. The rate compensating buffers add and drop idle
characters between ethernet packets when necessary to address clock rate differences between the lineside and host-side interfaces. Rate offsets from ideal frequencies measured in ppm (not MHz) can be
tolerated.
The maximum data throughput on the line interface is less in 10G WAN mode than 10G LAN mode. The
line's data rate is reduced to 9.953 Gbps from 10.3125 Gbps. Part of that bandwidth includes
SONET/SDH frame overhead data.
Note: Care must be taken by the device sending data to the host interface in the egress data path to ensure the
rate compensating buffer does not overflow.
3.7
Loopback
The VSC8489-02 device has several options available for routing traffic between the host-side and the
line-side. The following table shows the name and location of the loopback modes. These modes may be
extremely useful for both test and debug purposes.
Table 18 •
Host-Side Loopbacks
Name
Location
Line-Side Tx
Notes
H2
XAUI-PHY interface (1G and 10G)
Mirror XAUI data
1G and 10G modes
H3
PCS after the gearbox (10G)
0xFF00 repeating
IEEE PCS system loopback
(10G mode)
H4
WIS-PMA interface (10G)
0xFF00 repeating
IEEE WIS system loopback
(10G mode)
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
40
Functional Descriptions
Table 19 •
Line-Side Loopbacks
Name
Location
Host-Side Tx
Notes
L1
XAUI loopback (10G)
Mirror SFP+ data
IEEE PHY-XS network loopback
(1G and 10G modes)
L2
XGMII interface (10G)
Mirror SFP+ data
10G mode
L3
PMA interface (1G and 10G)
Mirror SFP+ data
1G and 10G modes
The following illustration shows the host and line-side loopbacks.
Figure 18 • Host-Side and Line-Side Loopbacks
XRX[3:0]
Tx
XGXS
XAUI
L1
XTX[3:0]
3.8
XAUI
H2
PCS
L2
Tx
XGXS
WIS
H3
PMA
TXDOUT
H4 L3
TXDIN
PCS
WIS
PMA
Cross-Connect (Non-Hitless Operation)
The VSC8489-02 device features a cross-connect between the two adjacent ports to support protectionswitching applications and failover capabilities. It supports cross-connect and line broadcast (bridge and
select) to host-side between the two adjacent ports.
In the cross-connect configuration, each port's line-side, which is normally connected to its own port hostside, is connected to the other port's host-side. In a broadcast configuration, a line-side of one port is
connected to both port's host-sides.
XAUI interfaces in the VSC8489-02 device support the following failover capabilities:
•
•
Network traffic on Chan0 is switchable between XAUI channel 0 or 1.
Network traffic on Chan1 is switchable between XAUI channel 1 or 0.
The VSC8489-02 device supports failover and SFI to XAUI broadcasting.
The XAUI data at channel_0 can be routed to either SFI of channel_0 or SFI of channel_1, but not both
at the same time. Similarly, the XAUI data at channel_1 can be routed to ether SFI of channel_1 or SFI of
channel_0, but not both at the same time. However, the SFI data of either channel_0 or channel_1 can
be routed to XAUI of channel_0, or XAUI of channel_1, or broadcast to XAUI of both channel_0 and
channel_1.
For example, in normal operation, the XAUI of channel_0 is routed to SFI of channel_0. When a problem
occurs on the link connecting to SFI of channel_0, re-route the XAUI of channel_0 to SFI of channel_1.
Or, if there is a problem at the MAC interfacing to the XAUI of channel_0, re-route the SFI data of
channel_0 to XAUI of channel_1. Broadcasting from SFI to both XAUI ports enables the passing of traffic
between XAUI of channel_0 and SFI of channel_0, and to use XAUI of channel_1 to snoop the incoming
data from SFI of channel_0, if so desired.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
41
Functional Descriptions
The following table lists the available settings for failover/broadcasting modes.
Table 20 •
Failover and Broadcasting Modes
Setting
Mode
1Ex0003 =0x00
XAUI channel_0 to/from SFI channel_0 interface
XAUI channel_1 from SFI channel_0 interface
SFI channel_1 from XAUI channel_1
1Ex0003 = 0x01
XAUI channel_0 from SFI channel_0 interface
XAUI channel_1 to/from SFI channel_0 interface
SFI channel_1 from XAUI channel_0
1Ex0003 =0x20
XAUI channel_0 to/from SFI channel_0 interface
XAUI channel_1 to/from SFI channel_1
1Ex0003 =0x21
XAUI channel_0 from SFI channel_0
XAUI channel_1 from SFI channel_1
SFI channel_0 from XAUI channel_1
SFI channel_1 from XAUI channel_0
1Ex0003 =0x10
XAUI channel_0 from SFI channel_1
XAUI channel_1 from SFI channel_0
SFI channel_0 from XAUI channel_0
SFI channel_1 from XAUI channel_1
1Ex0003 =0x11
XAUI channel_0 to/from SFI channel_1
XAUI channel_1 to/from SFI channel_0
1Ex0003 =0x30
XAUI channel_0 from SFI channel_1
XAUI channel_1 to/from SFI channel_1
SFI channel_0 from XAUI channel_0
1Ex0003 =0x31
XAUI channel_0 to/from SFI channel_1
XAUI channel_1 from SFI channel_1
SFI channel_0 from XAUI channel_1
The following illustration shows the cross-connect configurations.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
42
Functional Descriptions
Figure 19 • Cross-Connect Configuration
NORMAL TRAFFIC: Data _Switches_Clock_Control = 0x20 (default)
XRX0[3:0]
/4
XTX0[3:0]
/4
XAUI RX
1
0
CORE TX
PMA
TX
BROADCAST FROM XFI0 : Data_Switches_Clock_Control = 0x00 or 0x01
TXDOUT0
XRX0[3:0]
/4
XTX0[3:0]
/4
XAUI RX
CORE RX
PMA RX
1
0
XAUI0_DOUT_SRC = 0
XRX1[3:0]
/4
XTX1[3:0]
/4
XAUI RX
RXDIN0
XAUI
TX
PMA
TX
1
0
TXDOUT1
CORE RX
XRX1[3:0]
/4
XTX1[3:0]
/4
XAUI RX
RXDIN1
XTX0[3:0]
/4
XAUI RX
1
0
CORE TX
CORE RX
/4
XTX1[3:0]
/4
XAUI RX
XAUI
TX
CORE RX
PMA
TX
TXDOUT0
XRX0[3:0]
/4
XTX0[3:0]
/4
XAUI RX
RXDIN0
XAUI
TX
1
0
1
0
PMA
TX
TXDOUT1
CORE RX
PMA
TX
PMA RX
1
0
XAUI0_DOUT_SRC = 1
PMA_DOUT_SRC = 1
RXDIN1
TXDOUT0
XRX1[3:0]
/4
XTX1[3:0]
/4
XAUI RX
RXDIN0
PMA_DOUT_SRC = 0 or 1
1
0
CORE TX
PMA
TX
TXDOUT1
Channel 1
PMA RX
1
0
RXDIN1
XAUI
TX
CORE RX
1
0
PMA RX
RXDIN1
XAUI1_DOUT_SRC = 1
XAUI1_DOUT_SRC = 0
3.9
TXDOUT1
Channel 0
CORE TX
CORE RX
PMA
TX
PMA RX
1
0
CORE TX
Channel 1
XAUI
TX
1
0
BROADCAST FROM XFI1 : Data_Switches_Clock_Control = 0x31 or 0x30
PMA RX
1
0
XAUI0_DOUT_SRC = 1
XRX1[3:0]
PMA_DOUT_SRC = 0 or 1
CORE TX
Channel 0
XAUI
TX
RXDIN0
XAUI1_DOUT_SRC = 0
CROSS-CONNECT : Data _Switches_Clock_Control = 0x11
/4
TXDOUT0
Channel 1
PMA RX
1
0
XAUI1_DOUT_SRC = 0
XRX0[3:0]
PMA RX
1
0
XAUI0_DOUT_SRC = 0
PMA_DOUT_SRC = 0
CORE TX
CORE RX
Channel 1
XAUI
TX
PMA
TX
Channel 0
Channel 0
XAUI
TX
1
0
CORE TX
Host-Side Interface
The XAUI, RXAUI, and 1 GbE host interfaces in the VSC8489-02 device support the following rates:
•
•
•
XAUI: 4 × 3.125 Gbps
RXAUI: 2 × 6.25 Gbps
1 GbE: 1 × 1.25 Gbps
In RXAUI mode, the two RXAUI lanes are XAUI lane 0 and lane 2. XAUI lane 0 is the RXAUI lane 0 and
XAUI lane 2 is RXAUI lane 1. The LSB are sent on lane 0, while MSB are sent on late 1. In 1 GbE mode,
the 1 GbE lanes may be either XAUI lane 0 or lane 3. The following illustration shows the host-side I/O
interface.
The XAUI lane order could be swapped through register 4xF002, where bit 2 is to map lane 0 on 3, lane
1 on 2, lane 2 on 1, and lane 3 on 0 of the XAUI output. Bit 0 of same register is to map lane 0 on 3, lane
1 on 2, lane 2 on 1, and lane 3 on 0 of the XAUI input. Furthermore, bit 2 of 4xF002 could be used to
invert the polarity of the differential pairs of all four XAUI outputs, and bit 1 of 4xF002 could be used to
invert the polarity of the differential pairs of all four XAUI inputs. There is an API function call to assist
with setting the lane swap and polarity inversion.
Note: Use AC-coupling for the receive and transmit sides of the host-side interface. For optional DC-coupling,
contact your Microsemi representative.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
43
Functional Descriptions
Figure 20 • Host-Side I/O Interface
RXAUI
XAUI
3.9.1
NC
NC
NC
NC
XRX_2
XRX_1
NC
NC
XRX_3
XTX_0
XTX_1
NC
XTX_0
NC
OR
1G_TX
1x 1.25 Gbps
1G_RX
1x 1.25 Gbps
XRX_0
XRX_1
2x 6.25 Gbps
4x 3.125 Gbps
XRX_0
1 GbE
1G_RX
NC
NC
NC
NC
XTX_2
XTX_1
NC
NC
XTX_3
NC
NC
1G_TX
RXAUI Interoperability
The RXAUI implementation is fully interoperable with the Dune network mode 1 and mode 2 RXAUI
specification, as summarized in the following table.
Table 21 •
RXAUI Interoperability
Mode1
Mode2
De-interleaving uses XAUI ||A|| column
(align column).
Transmitter: No internal logic modification. Transmitter: Replaces some |K| code groups with
Two 10b characters are presented to one other code groups to allow receiver to perform
physical lane at a time.
de-interleaving (comma replacement).
Receiver: Separates two characters in
double rate lane into two physical standard
rate lanes. Lane byte ordering block
ensures first |A| character mapped to first
logical lane and |A| column aligned for the
deskew block.
Obeys 6.25 Gbps disparity rules.
Obeys 6.25 Gbps disparity rules.
A host-side SerDes macro (SD6G) is used by each XAUI lane. The SerDes macros are automatically
configured to send/receive the proper data rate when the host interface changes between the
XAUI/RXAUI/1 GbE modes. The appropriate lanes are also powered down when not in use. For
example, XAUI lanes 1 and 3 are powered down when the RXAUI interface is in use.
3.10
Clocking
The following sections describe the clocking functionality of the VSC8489-02 device.
3.10.1
PLL
The VSC8489-02 device includes two PLLs, one on the line-side and another on the host-side. The lineside PLL uses either XREFCK or WREFCK as its reference clock. The host-side PLL uses XREFCK. The
following table shows the supported reference clock frequencies.
Table 22 •
Supported Reference Clock Frequencies
Clock
Applications
Frequencies
XREFCK
Mainly LAN mode
125 MHz and 156.25 MHz
WREFCK LAN or WAN mode Synchronous Ethernet
155.52 MHz and 161.13 MHz
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
44
Functional Descriptions
Supported Reference Clock Frequencies (continued)
Table 22 •
Clock
Applications
Frequencies
SREFCK
Synchronous Ethernet
125 MHz, 155.52 MHz, and 156.25 MHz
3.10.2
Reference Clock
The VSC8489-02 device uses three differential input CML level reference clocks: XREFCK, WREFCK,
and SREFCK. The XREFCK is required all the time and may be either 156.25 MHz or 125 MHz.
The VSC8489-02 device features an internal frequency synthesizer that enables operation in 10G
LAN/10G WAN/1G LAN modes using a single reference clock input (XREFCK). The host-side PLL is
always driven by XREFCK. It is recommended to have the line-side PLL be driven by XREFCK.
For backward compatibility with previous generation PHY chips, WREFCK may be used to drive the lineside PLL. For Synchronous Ethernet applications with non-hitless XREFCK, SREFCK could be used to
drive the line-side PLL.
The XREFCK frequency has to be decided before power up, and is selected using the MODE1 and
MODE0 pins. The following table shows the MODE pin settings for the various XREFCK frequencies.
Table 23 •
XREFCK Frequency Selection
MODE1 Pin
MODE0 Pin
XREFCK Frequency
0
0
156.25 MHz (default)
0
1
Reserved
1
0
125 MHz
1
1
Reserved
The following table shows the supported clock rates and modes.
Table 24 •
Supported Clock Rates and Modes
Mode
XREFCK
10.3125G LAN single ref
Tx CMU REF
Rx CMU REF
156.25 MHz
XREFCK
XREFCK
9.95328G WAN single ref
156.25 MHz
XREFCK
XREFCK
1.25G LAN single ref
156.25 MHz
XREFCK
XREFCK
10.3125G LAN single ref
125 MHz
XREFCK
XREFCK
9.95328G WAN single ref
125 MHz
XREFCK
XREFCK
1.25G LAN single ref
125 MHz
XREFCK
XREFCK
10.3125G Sync-E LAN single ref
156.25 MHz
(Hitless)
XREFCK
XREFCK
10.3125G Sync-E LAN dual ref
156.25 MHz
161.13 MHz
SREFCK
XREFCK
156.25 MHz
156.25 MHz
SREFCK
XREFCK
156.25 MHz
125 MHz
SREFCK
XREFCK
XREFCK
XREFCK
SREFCK
XREFCK
WREFCK
WREFCK
XREFCK
XREFCK
9.95328G Sync-E WAN single ref
156.25 MHz
(Hitless)
9.95328G Sync-E WAN dual ref
156.25 MHz
9.95328G Sync-E WAN dual ref
156.25 MHz
1.25G Sync-E LAN single ref
156.25 MHz
(Hitless)
WREFCK
SREFCK
155.52 MHz
155.52 MHz
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
45
Functional Descriptions
Table 24 •
Supported Clock Rates and Modes (continued)
Mode
XREFCK
1.25G Sync-E LAN dual ref
156.25 MHz
3.10.3
WREFCK
SREFCK
Tx CMU REF
Rx CMU REF
125 MHz
SREFCK
XREFCK
Synchronous Ethernet Support
The VSC8489-02 device supports several synchronous Ethernet configurations for 1G and 10G modes
of operation. In synchronous Ethernet applications, only one master at a time may be selected from one
of the internal line-side Rx or the SREFCK.
•
•
•
•
3.11
Single device, internal master: in this configuration, the line-side Rx captures the serial data input
and generates a lane-synchronization signal that contains information about the incoming data
rates. The signal is then distributed to all ports of the line-side Tx to form a source-synchronous
operation.
Single clock LAN, external master: in this configuration, the XREFCK is gradually changed to the
externally generated synchronous Ethernet clock using an external clock distribution chip. The
change has to be hitless to avoid data corruption. The XREFCK source may come from one of the
port recovered clocks through the RXCKOUT pin.
Dual clock LAN, external master: in this configuration, the XREFCK remains connected to the
stable 156.25 MHz system clock or crystal. All the line-side transmits are then synchronized to
SREFCK. The F to delta F block accepts the SREFCK clock from external synchronous Ethernet
master and generates the lane Sync signal to effectively synchronize all the line-side Tx to this
external clock. SREFCK must be 156.25 MHz.
Dual clock WAN, external master: in this configuration, the XREFCK remains connected to the
stable 156.25 MHz system clock or crystal. The XREFCK is configured to drive the host-side PLL,
while the WREFCK is configured to drive the line-side PLL. The synchronous Ethernet clock is then
routed through the SREFCK clock to synchronize all the line-side transmits. SREFCK must be
155.52 MHz.
Operating Modes
The VSC8489-02 device has three main operation modes: LAN, WAN, and 1 GbE.
3.11.1
10G LAN
In 10G LAN mode, the host interface is XAUI (4 × 3.125 Gbps) or RXAUI (2 × 6.250 Gbps), and the line
interface is LAN SFP+ (10.3125 Gbps). A single reference clock input pin, XREFCK, is used by both the
line-and host-side interfaces to transmit appropriate rates. For more information about supported
reference clock frequencies, Table 24, page 45.
Figure 21 • 10G LAN
SerDes
XR X [3 :0]
SerDes
XGXS
FIFO
SerDes
10G
PCS
TXOUT
SerDes
SerDes
HO ST
XAUI /R XAUI
LIN E
SFP+ /K R
LAN : 10 .3125 Gbps
XAUI : 4 x 3 .125 Gbps
R XAUI : 2x 6.25 Gbps (Ln 0 and Ln2 )
SerDes
XTX [3:0 ]
SerDes
SerDes
XGXS
FIFO
10G
PCS
SerDes
TXIN
SerDes
3.11.2
10G WAN
In 10G WAN mode, the host interface is XAUI (4 × 3.125 Gbps) or RXAUI (2 × 6.250 Gbps), and the line
interface is SONET/SDH STS-192c (9.95328 Gbps). A single reference clock input pin, XREFCK, is
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
46
Functional Descriptions
used by both the line-and host-side interfaces to transmit appropriate rates. For more information about
supported reference clock frequencies, see Table 24, page 45. Optionally, WREFCK may be used as the
155.52 MHz reference clock for the line interface. A 622 MHz WREFCK reference frequency is not
supported.
Figure 22 • 10G WAN
SerDes
SerDes
XRX[3:0]
XGXS
SerDes
10G
PCS
FIFO
WIS
TXOUT
SerDes
SerDes
HOST
XAUI /RXAUI
LINE
SONET/SDH STS -192c
XAUI: 4x 3.125 Gbps
RXAUI: 2x 6.25 Gbps (Ln0 and Ln2)
WAN: 9.95328 Gbps
SerDes
SerDes
XTX[3:0]
SerDes
10G
PCS
FIFO
XGXS
WIS
SerDes
RXIN
SerDes
3.11.3
1 GbE
In 1 GbE mode, one XAUI lane on the host interface services the 1 GbE signal (1.25 Gbps). A single
reference clock input pin, XREFCK, is used by both the line-and host-side interfaces to transmit
appropriate rates. For more information about supported reference clock frequencies, see Table 24,
page 45. MACs should be enabled to meet the pause turn around time spec, as defined in the IEEE
specifications.
Figure 23 • 1 GbE
XRX[3]
or
XRX[0]
SerDes
1G PCS
Host
MAC
Flow
Control
Buffer
Line
MAC
1G PCS
HOST
1 GbE
3.12
TXOUT
LINE
SFP
1G/SGMII 1.25 Gbps
XTX[3]
or
XTX[0]
SerDes
1G/SGMII 1.25 Gbps
SerDes
1G PCS
Host
MAC
Flow
Control
Buffer
Line
MAC
1G PCS
SerDes
TXIN
Management Interfaces
This section contains information about the low-speed serial interfaces of the VSC8489-02 device. The
primary control and monitor interfaces in the design are as follows:
•
•
•
•
•
•
MDIO
SPI slave
Two-wire serial (slave)
Two-wire serial (master)
GPIO
JTAG
The VSC8489-02 device supports three different interfaces for accessing status and configuration
registers: MDIO, SPI slave, and two-wire serial slave. Only one of the interfaces can be active at a time.
The VSC8489-02 device doesn't arbitrate between these interfaces.
Note: Users must exercise caution, and ensure that multiple interfaces are not active at the same time.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
3.12.1
MDIO Interface
The MDIO interface in the VSC8489-02 device complies with IEEE 802.3ae Clause 45. For more
information, see the IEEE standard. The MDIO management interface consists of a bi-directional data
path (MDIO) and a clock reference (MDC).
MDIO instructions can be used to read registers, write registers, and perform
post-read-increment-address instructions. Due to its slow bandwidth and high latency, the MDIO
interface is not recommended as the only interface to access the VSC8489-02 device.
Note: The maximum data rate of the MDIO interface is 2.5 Mbps.
The PADDR[4:1] pins select the MDIO port addresses to which the VSC8489-02 device will respond. A
single VSC8489-02 device requires the use of two MDIO port addresses, one for each channel. The port
address transmitted in MDIO read/write commands to access registers in a particular VSC8489-02
channel is shown in the following table. The port address is a function of the PADDR pins and a
pre-programmed number indicating the channel number. Up to sixteen VSC8489-02 devices can be
controlled by a single MDIO host.
Table 25 •
3.12.1.1
MDIO Port Addresses Per Channel
Channel Number
Channel’s Port Address
1
0
{PADDR[4:1], 1}
{PADDR[4:1], 0}
Accessing 32-Bit Data Registers
Even though the MDIO interface is defined to access 16-bit data registers, 32-bit configuration and status
registers are present in the line and host MACs in 1G mode and line-side SerDes. Use the following
steps when accessing registers in 32-bit blocks.
3.12.1.1.1 Write to 32-Bit Register
1. Issue address instruction specifying the MDIO address for bits [31:16].
2. Issue write instruction to write data to register bits [31:16].
3. Issue address instruction specifying the MDIO address for bits [15:0].
4. Issue write instruction to write data to register bits [15:0].
Note: Writing to the two halves of the 32-bit register in the opposite order is not permitted. Nor is it possible to
write to only one-half of the register. All four MDIO instructions must be issued to write to a 32-bit
register.
3.12.1.1.2 Read 32-Bit Register
1. Issue address instruction specifying the MDIO address for bits [15:0].
2. Issue read-increment instruction. The data read is the contents of register bits [15:0].
3. Issue read instruction. The data read is the contents of register bits [31:16].
Note: Perform all three steps to read a 32-bit register even when reading consecutive addresses. Issuing backto-back read-increment instructions to read consecutive 32-bit register addresses is not supported.
Register addresses listed for the line and host MACs in 1G mode and line-side SerDes apply to the SPI
slave and two-wire serial slave interfaces, which support direct access to 32-bit data registers. There are
two MDIO addresses for each of these 32-bit data registers: one address to access data bits [31:16] and
one address to access data bits [15:0]. Contact Microsemi for support using the MDIO interface to
access line and host MACs in 1G mode and line-side SerDes registers.
3.12.1.2
MDIO Device and Register Addresses
The VSC8489-02 device registers are arranged according to the MDIO devices as defined in IEEE 802.3
clause 45, as shown in the following list:
•
•
•
•
•
Device 1: PMA and line-side interface registers
Device 2: WIS registers
Device 3: 10G PCS, 1G PCS, FC buffers
Device 4: XGXS PCS and host-side interface registers
Device 1E: Global, SFP+, and PLLs
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
3.12.2
SPI Slave Interface
The VSC8489-02 device supports the serial parallel interface (SPI) for reading and writing registers for
high bandwidth tasks. The SPI interface is also capable of accessing all status and configuration
registers. The SPI slave port consists of a clock input (SCK), data input (MOSI), data output (MISO), and
slave select input (SSN).
Note: The SPI slave interface is the recommended interface to access status and configuration registers for the
rest of the device.
Drive the SSN pin low to enable the interface. The interface is disabled when SSN is high and MISO is
placed into a high impedance state. The VSC8489-02 device captures the state of the MOSI pin on the
rising edge of SCK. 56 data bits are captured on the MOSI pin and transmitted on the MISO pin for each
SPI instruction. The serial data bits consist of 1 read/write command bit, 23 address bits and 32 register
data bits.
The 23-bit addressing scheme consists of a 2-bit channel number, a 5-bit MDIO device number, and a
16-bit register number. For example, the 23-bit register address for accessing the
GPIO_0_Config_Status register in channel 1 (device number is 0x1E and register number is 0x0100) is
0x3E0100. The notion of device number conforms to MDIO register groupings. For example, device 2 is
assigned to WIS registers.
The following table shows the order in which the bits are transferred on the interface. Bit 55 is transferred
first, and bit 0 is transferred last. This sequence applies to both the MOSI and MISO pins.
Table 26 •
SPI Slave Instruction Bit Sequence
Bit
Name
Description
55
Read/Write
0: Read
1: Write
54:53
Port/Channel Number
00: Port/Channel 0
01: Port/Channel 1
10, 11: Reserved
52:48
Device Number
5 bit device number
Bit 4 corresponds to SPI instruction bit 52
Bit 0 corresponds to SPI instruction bit 48
47:32
Register Number
16 bit register number
Bit 15 corresponds to SPI instruction bit 47
Bit 0 corresponds to SPI instruction bit 32
31:0
Data
32 bit data
Bit 31 corresponds to SPI instruction bit 31
Bit 0 corresponds to SPI instruction bit 0
The register data received on the MOSI pin during a write operation is the data value to be written to a
VSC8489-02 register. Register data received on the MOSI pin during a read operation is not used, but
must still be delivered to the device.
The VSC8489-02 device SPI slave has a pipelined read process. Two read instructions must be sent to
read a single register. The first read instruction identifies the register address to be read. The MISO data
transmitted on the second read instruction contains the register contents from the address specified in
the first instruction. While a pipelined read implementation is not the most efficient use of bandwidth to
read a single register, it is very efficient when performing multiple back-to-back reads. The second read
instruction contains the address for the second register to be read, plus the data read from the first
register. The third read instruction contains the address for the third register to be read, plus the data
read from the second register. Register reads can continue in this fashion indefinitely. The following
illustrations show the situations where back-to-back read instructions are issued.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
Figure 24 • SPI Single Register Read
R
MOSI
(Don t
care)
ADDR A
Depends on previous
instruction
MISO
R
ADDR B
(Don t
care)
R
ADDR A
Read
DATA A
SPI Read
Instruction
#1
SPI Read
Instruction #2
Figure 25 • SPI Multiple Register Reads
R
MOSI
ADDR A
(Dont
care)
Depends on previous
instruction
MISO
R
ADDR B
(Dont
care)
R
ADDR C
(Dont
care)
R
ADDR D
(Dont
care)
R
ADDR A
Read
DATA A
R
ADDR B
Read
DATA B
R
ADDR C
Read
DATA C
The SPI read instruction illustrations also point out the read/write state and address bits on the MISO
output match the information received in the previous instruction. The SPI master could use this data to
verify the device captured the previous instruction properly, or simply ignore the data. The following
illustration shows the MISO output during write instructions reporting the previous instruction's read/write
state, address, and register write data.
Figure 26 • SPI Multiple Register Writes
MOSI
W
ADDR A
Write
DATA A
Depends on previous
instruction
MISO
W
ADDR B
Write
DATA B
W
ADDR C
Write
DATA C
W
ADDR A
Write
DATA A
W
ADDR B
Write
DATA B
The following illustration shows that when a read instruction followings a write instruction, the MISO data
during the read instruction is the data field from the previous write.
Figure 27 • SPI Read Following Write
MOSI
W
ADDR A
Write
DATA A
Depends on previous
instruction
MISO
W
ADDR B
Write
DATA B
R
ADDR C
(Don t
care)
W
ADDR A
Write
DATA A
W
ADDR B
Write
DATA B
The following illustration shows that when a write instruction followings a read instruction, the MISO data
during the write instruction is not pipelined read data. MISO contains all 0's in the data field.
Figure 28 • SPI Write Following Read
MOSI
MISO
R
ADDR A
(Don t
care)
Depends on previous
instruction
R
ADDR B
(Don t
care)
W
ADDR C
Write
DATA C
R
ADDR A
Read
DATA A
R
ADDR B
0's
Some VSC8489-02 registers are made up of less than 32 data bits. Any bits not defined for a register will
return a 0 when the register is read. Reading an invalid register address will return 0x0.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
50
Functional Descriptions
There is one hazard condition to be aware of when issuing two read instructions to read a single clearon-read register. Issuing two read instructions internally fetches data twice, even though valid read data
is present only in the second instruction. Fetching data also resets a clear-on-read register. The address
specified in the second read instruction should be something other than the clear-on-read register
address. This prevents an event causing register re-assertion occurring between the two read
instructions from being cleared and never detected. The address in the second instruction can be any
register not having a clear-on-read function. Device_ID is one example. The same address can be used
in each read instruction when continuously polling a clear-on-read register. This works because
subsequently fetched data is transmitted from the interface, allowing assertion between reads to be
detected. Only the last read instruction where fetched data is not transmitted, should some other address
in the instruction be used.
3.12.2.1
MISO Output Timing Modes
MISO changes state when SCK transitions from high to low in the default SPI operating mode. This aids
in meeting hold time at the SPI master, assuming the master captures the data on the rising SCK edge.
The SPI port can run up to a maximum of 30 Mbps, depending upon the VSC8489-02 device SCK-toMISO timing, SCK duty cycle, the board layout, and the external SPI master's interface timing
requirements. For more information about SPI timing, see Table 51, page 71.
The SPI slave port has an alternate operating mode that allows the interface to run faster. Setting register
bit SPI_CTRL.FAST_MODE=1 configures the SPI slave such that MISO changes state when SCK
transitions from low to high. Thus, data is both transmitted from the SPI slave and captured by the SPI
master on a rising SCK edge. The interface can run faster in this mode by using the entire SCK clock
period instead of half the period to transfer data from the slave to the master. Care must be taken to
ensure the SPI master's hold time requirement is met. The maximum data transfer rate for the SPI slave
in this mode is 30 Mbps. The following illustrations show MISO timing in the default and slave modes.
Figure 29 • SPI Slave Default Mode
SSN
MOSI
R/W
...
ADDR[22]
...
DATA[31]
R/W
ADDR[22]
DATA[1]
DATA[0]
...
...
SCK
MISO
ADDR[0]
...
ADDR[21]
DATA[31]
...
DATA[30]
DATA[0]
R/W
MISO data based on previous
instruction
R/W data matches this instruction and carries over to next instruction
Figure 30 • SPI Slave Fast Mode
SSN
MOSI
R/W
ADDR[22]
ADDR[0]
DATA[31]
...
SCK
MISO
...
R/W
ADDR[22]
ADDR[21]
...
DATA[1]
DATA[0]
...
...
DATA[31]
DATA[30]
...
DATA[0]
R/W
MISO data based on previous
instruction
R/W data matches this instruction and carries over to next instruction
MISO output timing is the only difference between the two SPI modes. Sampling of MOSI on the rising
SCK clock edge remains the same, so writing to the VSC8489-02 device registers is identical in both
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
51
Functional Descriptions
modes. Thus, the SPI_CTRL.FAST_MODE register setting may be modified using the SPI slave port to
change the port's MISO output timing.
3.12.3
Two-Wire Serial (Slave) Interface
The VSC8489-02 device registers may be read and written using a two-wire serial slave interface. The
two-wire serial slave SCL and SDA pins are multifunction general purpose I/O (GPIO) pins, GPIO_3 and
GPIO_2, respectively. The GPIO pins are configured to serve SCL and SDA functions following device
reset.
The slave address assigned to the VSC8489-02 device is a function of four fixed values and the MDIO
port address pins. The 7-bit slave address is {1000, PADDR4, PADDR3, PADDR2}. The use of the port
address pins allows multiple VSC8489-02 devices to be serviced by a single two-wire serial (master).
The maximum data transfer rate for the interface is 400 kbps.
Note: The two-wire serial slave interface does not work with two-wire serial masters using 10-bit slave
addresses.
A valid START condition is generated by a two-wire serial master device by transitioning the SDA line
from high to low while the SCL line is high. Data is then transferred on the SDA line, most significant bit
(MSB) first, with the SCL line clocking data. Data transitions during SCL low periods are valid (read) or
latched (write) when SCL pulses high then low. Data transfers are acknowledged (ACK) by the receiving
device for data writes and by the master for data reads. An acknowledge is signaled by holding the SDA
signal low while pulsing SCL high then low. The master terminates data transfer by generating a STOP
condition by transitioning SDA low to high while SCL is high.
Note: If the external two-wire serial master device gets out of sync with the two-wire serial slave interface, the
master device must issue a bus reset sequence. This puts the two-wire serial slave interface back into a
state that allows it to receive future two-wire serial instructions. The external two-wire serial master
device and the two-wire serial slave interface can become out-of-sync and freeze the bus if either device
is reset during an instruction.
The following illustration shows a two-wire serial bus reset sequence. The reset sequence consists of a
START symbol, nine SCK clock pulses while SDA is high, another START symbol, and a STOP symbol.
Figure 31 • Two-Wire Serial Bus Reset Sequence
Nine Clock Pulse
START
START
1
SCL
2
8
STOP
9
SDA
Registers in the VSC8489-02 device are accessed using the 24-bit addressing scheme. The first 8 bits
consist of one logic LOW, the channel number (00, 01, 10, 11), and the 5-bit MDIO device number of the
register to be accessed. The next 16 bits are the register number. For example, the 24-bit register
address for accessing the GPIO_0_Config_Status register in channel 1 (device number 0x1E and
register number 0x0100) is 0x3E0100. The notion of device number conforms to MDIO register
groupings. For example, device 2 is assigned to WIS registers. The following illustration shows the 24-bit
addressing scheme used to access registers.
Figure 32 • Two-Wire Serial Slave Register Address Format
S
slv_addr[6:0], W
“0”, ch[1:0], dev[4:0]
reg_addr[15:8]
reg_addr[7:0]
An illegal two-wire serial slave read instruction to an invalid channel number, device number, or register
address will return a read value of 0x0000 when the slave address matches this device.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
52
Functional Descriptions
Four bytes of data are transferred on the two-wire serial bus after the address when a register is read or
written. Data register bits [31:24] are transferred first, followed by bits [23:16], bits [15:8] and finally bits
[7:0]. An ACK symbol is sent between each byte of data. Any bits not defined in a register will return a 0
when the register is read.
The following illustration shows the data transferred on the SDA pin during a register write operation. The
R/W bit following the slave address is set to logic low to specify a write operation.
Figure 33 • Two-Wire Serial Write Instruction
S
T
A
R
T
W
R
I
T
E
Slave Address
1 0 0
0
Register Address
0
0
A
C
K
R A
/ C
W K
A
C
K
A
C
K
S
T
O
P
B
I
T
A
C
K
A
C
K
B A
I C
T K
A
C
K
0
3
1
Data Written to Register
The register address to be accessed is specified by initiating a write operation. After the slave address
and three register address bytes are sent to the VSC8489-02 device, a START condition must be resent, followed by the slave address with the read/write bit set to logic high. The four-byte data register
contents are then transmitted from the VSC8489-02 device. The two-wire serial (master) sends NO ACK
after the fourth data byte to indicate it has finished reading data. The following illustration shows data
transferred on the SDA pin during a register read operation.
Figure 34 • Two-Wire Serial Read Instruction
S
T
A
R
T
Slave Address
1 0 0 0
W
R
I
T
E
0
S
T
A
R
T
Register Address
Slave Address
1 0 0
0 0
A
C
K
R A
/ C
W K
A
C
K
0
R
E
A
D
1
R A
/ C
W K
A
C
K
Dummy Write to set Read Address
S
T
O
P
B
I
T
A
C
K
A
C
K
A
C
K
3
1
B N
I O
T
A
0 C
K
Data Read from Register
The two-wire serial slave interface supports sequential read and sequential write instructions.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
53
Functional Descriptions
3.12.4
Two-Wire Serial (Master) Interface
A two-wire serial master interface in the VSC8489-02 channel is available for SFP+/XFP module
management. A two-wire serial master interface per channel is required, because the slave address in
the optics modules are identical. Two-wire serial interface instructions used to access optics module
registers are initiated by writing to VSC8489-02 registers. The two-wire serial interface busses are
brought out through GPIO pins. Channel 0's two-wire serial interface is enabled by configuring GPIO_6
to function as SDA and GPIO_7 to function as SCL. Channel 1's two-wire serial interface is enabled by
configuring GPIO_10 to function as SDA and GPIO_11 to function as SCL.
The two-wire serial master interface must be configured before initiating any instructions. The slave ID to
be transmitted in the first byte of every instruction is selectable in the SLAVE_ID register. The default
setting is 0x50. The interface's data rate is determined by the PRESCALE register. The default data rate
is 400 kbps.
The two-wire serial master transmits instructions for slave devices with 8-bit data registers and 256
register addresses per slave ID. Always read register I2C_BUS_STATUS.I2C_BUS_BUSY or
I2C_READ_STATUS_DATA.I2C_BUS_BUSY to verify the previous instruction has finished prior to
initiating a new instruction. Instructions initiated when the interface is busy will be ignored. Both registers
report the same interface busy status. The same busy status is reported in two registers for user
convenience.
The two-wire serial master initiates a write instruction when the I2C_WRITE_CTRL register is written.
The value written to I2C_WRITE_CTRL.WRITE_ADDR is the register address to be modified in the slave
device. The value written to I2C_WRITE_CTRL.WRITE_DATA is the data to be written to the slave
device's register. The I2C_BUS_STATUS register reports the status of the write instruction.
I2C_BUS_STATUS.I2C_BUS_BUSY indicates when the instruction has finished.
I2C_BUS_STATUS.I2C_WRITE_ACK=1 means the two-wire serial master received ACKs from the slave
at appropriate times. I2C_BUS_STATUS.I2C_WRITE_ACK is cleared each time a new instruction is
issued. If the two-wire serial master did not receive ACKs from the slave at appropriate times
(I2C_BUS_STATUS.I2C_WRITE_ACK=0), the interface is likely stuck in a state waiting for the ACK.
Writing a 1 to the BLOCK_LEVEL_RESET1.I2CM_RESET register will reset the two-wire serial master
and release it from its stuck state. The slave device should then be put into a known state by writing any
value to the I2C_RESET_SEQ register. The two-wire serial master issues a bus reset sequence when
this register is written. For more information, see Two-Wire Serial (Slave) Interface, page 52.
The two-wire serial master initiates a read instruction when the I2C_READ_ADDR register is written. The
value written to I2C_READ_ADDR.READ_ADDR is the register address to be accessed in the slave
device. I2C_READ_STATUS_DATA.READ_DATA contains the data read from the slave device.
READ_DATA is not valid until I2C_READ_STATUS_DATA.I2C_BUS_BUSY=0 to indicate the instruction
completed. The two-wire serial master does not support read-increment instructions.
3.12.5
GPIO
General purpose input/output (GPIO) pins in the VSC8489-02 device serve multiple functions. The GPIO
pins are bidirectional where the driver portion is an open-drain buffer. The following table shows the
functions that each pin supports and the registers used to configure the pin functions. Leave GPIO pins
unconnected when not in use. When configured as output, they are open-drained and a pull-up is
required.
Table 27 •
GPIO Functions
Pin
Configuration Registers
Functions
GPIO_0
GPIO_0_Config_Status
GPIO_0_Config2
Traditional I/O (default)
Observed internal signals
MOD_ABS_Channel_0
PMTICK
ROSI frame pulse 0
Tx Activity LED
WIS_INTB
Leave unconnected when not used
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Functional Descriptions
Table 27 •
GPIO Functions (continued)
Pin
Configuration Registers
Functions
GPIO_1
GPIO_1_Config_Status
GPIO_1_Config2
Traditional I/O (default)
Observed internal signals
ROSI_CLK_0
Rx Activity LED
WIS_INTA
Leave unconnected when not used
GPIO_2
GPIO_2_Config_Status
GPIO_2_Config2
Traditional I/O
Observed internal signals
Slave two-wire serial - SDA (default)
ROSI_DATA_0
Tx Activity LED
WIS_INTB
GPIO_3
GPIO_3_Config_Status
GPIO_3_Config2
Traditional I/O
Observed internal signals
Slave two-wire serial - SCL (default)
TOSI_FRAME_PULSE_0
Rx Activity LED
WIS_INTB
GPIO_4
GPIO_4_Config_Status
GPIO_4_Config2
Traditional I/O (default)
Observed internal signals
TOSI_CLK_0
Tx Activity LED
WIS_INTB
GPIO_5
GPIO_5_Config_Status
GPIO_5_Config2
Traditional I/O (default)
Observed internal signals
TOSI_INPUT_0
Rx Activity LED
WIS_INTA
Leave unconnected when not used
GPIO_6
GPIO_6_Config_Status
GPIO_6_Config2
Traditional I/O (default)
Observed internal signals
Ch0 SFP I2C SDA
ROSI_FRAME_PULSE_1
Tx Activity LED
WIS_INTB
GPIO_7
GPIO_7_Config_Status
GPIO_7_Config2
Traditional I/O (default)
Observed internal signals
Ch0 SFP I2C SCL
ROSI_CLK_1
Rx Activity LED
WIS_INTA
GPIO_8
GPIO_8_Config_Status
GPIO_8_Config2
Traditional I/O (default)
Observed internal signals
MOD_ABS_Channel_0
PMTICK
ROSI_DATA_1
Tx Activity LED
WIS_INTA
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
55
Functional Descriptions
Table 27 •
GPIO Functions (continued)
Pin
Configuration Registers
Functions
GPIO_9
GPIO_9_Config_Status
GPIO_9_Config2
Traditional I/O (default)
Observed internal signals
Mod_ABS channel 1
PMTICK
TOSI_FRAME_PULSE_1
Rx Activity LED
WIS_INTA
GPIO_10
GPIO_10_Config_Status
GPIO_10_Config2
Traditional I/O (default)
Observed internal signals
Ch1 SFP I2C SDA
TOSI_CLK_1
Tx Activity LED
WIS_INSTB
GPIO_11
GPIO_11_Config_Status
GPIO_11_Config2
Traditional I/O (default)
Observed internal signals
Ch1 SFP I2C SCL
TOSI_INPUT_1
Rx Activity LED
WIS_INTA
GPIO_12
GPIO_12_Config_Status
GPIO_12_Config2
Traditional I/O (default)
Observed internal signals
Tx Activity LED
WIS_INTA
GPIO_13
GPIO_13_Config_Status
GPIO_13_Config2
Traditional I/O (default)
Observed internal signals
Rx Activity LED
WIS_INTA
GPIO_14
GPIO_14_Config_Status
GPIO_14_Config2
Traditional I/O (default)
Observed internal signals
Tx Activity LED
WIS_INTA
GPIO_15
GPIO_15_Config_Status
GPIO_15_Config2
Traditional I/O (default)
Observed internal signals
Rx Activity LED
WIS_INTA
When a GPIO pin is programmed to be a traditional I/O, the pin may be driven high or low. It may also
serve as an input and an LED driver capable of blinking at various rates. An interrupt pending register
may optionally be asserted when the pin is in input mode and the pin changes state. All of these
functions are configured using the pin configuration register settings shown in the preceding table.
The GPIO pin's output driver is automatically enabled when the pin function is set to observe internal
signals. The second configuration register listed for each pin selects which internal signal is transmitted
from the pin.
3.12.6
JTAG
The VSC8489-02 device has a IEEE 1149.1–2001 compliant JTAG interface. The following table shows
the supported instructions and corresponding instruction register codes. The code's least significant bit is
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
56
Functional Descriptions
shifted into TDI first when loading an instruction (the 0 is shifted in first when loading the IDCODE
instruction).
Table 28 •
JTAG Instructions and Register Codes
Instruction
Register Code
IDCODE
111111111111111111111110
BYPASS
111111111111111111111111
EXTEST
111111111111111111101000
Notes
EXTEST_PULSE
111111101111111111101000
EXTEST_TRAIN
111111011111111111101000
SAMPLE
111111111111111111111000
PRELOAD
111111111111111111111000
LV_HIGHZ
111111111111111111001111
Provides the ability to place outputs in a high
impedance state to facilitate manufacturing
test and PC board diagnostics. The XAUI
and SFP+ serial data outputs are not put into
the high impedance state when this
instruction is loaded in the JTAG TAP
controller.
CLAMP
111111111111111111101111
Provides the ability to place all outputs in a
predefined state when the scan process is
being used to test other devices on a PC
board.
The RESETN pin must be driven to logic high before shifting data out of the DEVICE ID data register
when the IDCODE instruction is loaded in the JTAG TAP controller.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
57
Registers
4
Registers
Information about the registers for this product is available in the attached Adobe Acrobat file. To view or
print the information, double-click the attachment icon.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
58
Electrical Specifications
5
Electrical Specifications
This section provides the DC characteristics, AC characteristics, recommended operating conditions,
and stress ratings for the VSC8489-02 device.
5.1
DC Characteristics
This section contains the DC specifications for the VSC8489-02 device.
5.1.1
DC Inputs and Outputs
The following table lists the DC specifications for the LVTTL inputs and outputs for the VSC8489-02
device. The LVTTL inputs are 3.3 V tolerant.
Table 29 •
LVTTL Input and Push/Pull Output DC Characteristics
Parameter
Symbol
Minimum
Maximum
Unit
Condition
Output high voltage,
LVTTL
VOH_TTL
1.8
VDDTTL
V
VDDTTL = 2.5 V and
IOH = –4 mA
Output low voltage,
LVTTL
VOL
0.5
V
VDDTTL/VDDMDIO = 2.5 V
and IOL = 4 mA
Input high voltage
VIH
VDDTTL
V
VDDTTL/VDDMDIO = 2.5 V
Input low voltage
VIL
0.8
V
VDDTTL/VDDMDIO = 2.5 V
Input high current
IIH
500
µA
VIH = VDDTTL/VDDMDIO
Input low current
IIL
µA
VIL = 0 V
Table 30 •
1.7
–100
LVTTLOD Input and Open-Drain Output DC Characteristics
Parameter
Symbol
Minimum
Output high voltage,
open drain
VOH_OD
note1
Maximum
Unit
Condition
VDDTTL
V
VDDTTL/VDDMDIO = 2.5 V
and IOH = –4 mA
Input high leakage
current, open drain
IOZH
100
µA
Output low voltage,
open drain
VOL
0.5
V
See
Input high voltage
VIH
VDDTTL
V
VDDTTL/VDDMDIO = 2.5 V
Input low voltage
VIL
0.8
V
VDDTTL/VDDMDIO = 2.5 V
Input high current
IIH
500
µA
VIH = VDDTTL/VDDMDIO
Input low current
IIL
µA
VIL = 0 V
1.
1.7
VDDTTL/VDDMDIO = 2.5 V
and IOL = 4 mA
–100
Determined by the loading current of the other devices connecting to this pin, the IOZH current of this pin, and
the value of the pull-up resistor used.
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Electrical Specifications
5.1.2
Reference Clock
The following table lists the DC specifications for the reference clock for the VSC8489-02 device.
Table 31 •
Reference Clock DC Characteristics
Parameter
Symbol
Minimum
XREFCK/WREFCK
differential input swing, low1
∆VI_DIFF_LOW 200
XREFCK/WREFCK
∆VI_DIFF_HIGH 1100
differential input swing, high1
SREFCK differential input
swing
1.
5.2
∆VI_DIFF
200
Maximum
Unit
Condition
1200
mVP-P CML reference
clock input
2400
mVP-P LVPECL
reference clock
input
2400
mVP-P
An API call is used to set the input swing to be high or low.
AC Characteristics
This section contains the AC specifications for the VSC8489-02 device. The specifications apply to all
channels. All the XAUI/RXAUI/SFI I/Os should be AC-coupled and work in differential.
5.2.1
Receiver Specifications
The specifications in the following table correspond to line-side 10G receiver input, SFI point D. Point D
assumes that the input is from a compliant point C output and a compliant SFI or XFI channel according
to the SFP+ standard (SFF-8431) or the XFP multisource agreement (INF-8077i). The measurement is
done with a 9 dB channel loss unless stated otherwise. The jitter and amplitude measurements are
calibrated at point C”, as specified in SFF-8431 revision 4.1.
Table 32 •
Line-Side 10G Receiver Input (SFI Point D 9.95328G) AC Characteristics
Parameter
Symbol
RXIN input data rate,
10 Gbps
Minimum
Typical
Maximum
Unit
Condition
9.95328 –
100 ppm
10.3125
10.3125 + 100 pp Gbps
m
10 Gbps LAN/WAN
mode
RXIN linear mode
differential input data
swing
∆VRXINLINEAR
180
600
mV
Voltage modulation
amplitude (VMA)
RXIN limiting mode
differential input data
swing
∆VRXINLIMITING 300
850
mV
Measured
peak-to-peak
RXIN AC
common-mode
voltage
VCM
15
mVRMS
Differential return loss RLSDD11
–12
dB
0.01 GHz to 2.0 GHz
Differential return loss RLSDD11
dB
–6.68 +
12.1 x log10(f/5.5)
2.0 GHz to 11.1 GHz
Reflected differential
to common-mode
conversion
RLSCD11
–10
dB
0.1 GHz to 11.1 GHz
99% jitter
99%JIT_p-p
0.42
UI
Pulse width shrinkage DDPWSJIT_p-p
jitter
0.3
UI
Total jitter tolerance
0.70
UI
TOLJIT_P-P
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Electrical Specifications
Line-Side 10G Receiver Input (SFI Point D 9.95328G) AC Characteristics (continued)
Table 32 •
Parameter
Symbol
Minimum
Typical
Maximum
Unit
0.35
UI
Eye mask X1
X1
Eye mask Y1
Y1
Eye mask Y2
Y2
425
mV
Waveform distortion
penalty
WDPc
9.3
dBe
BER 1E–12. This
parameter of DAC is
measured with 7 dB
SFI channel loss.
Voltage modulation
amplitude
VMA
mV
BER 1E–12. This
parameter of DAC is
measured with 7 dB
SFI channel loss.
Optical sensitivity
(ROP), back-to-back,
10.3 Gbps
SB2B
–24
dBm
BER 1E–12, PRBS31
and 10 GbE frame,
5.76 dB SFI channel
loss.
Optical sensitivity
(ROP), with fiber
plant, 10.3 Gbps
SFIBER
–21
dBm
95 km single-mode
fiber, BER 1E–12,
PRBS31 and 10 GbE
frame, 5.76 dB SFI
channel loss.
Chromatic dispersion
penalty
FCDP
3
dB
1600 ps/nm, 5.76 dB
SFI channel loss.
dB
95 km single-mode
fiber, BER 7E–4,
5.76 dB SFI channel
loss.
150
mV
180
1.5
OSNR vs BER with
OSNRFEC
fiber plant, 10.3 Gbps
Condition
16
The following illustration shows the sinusoidal jitter tolerance for the SFI datacom.
Sinusoidal Jitter Tolerance (UIp-p)
Figure 35 • SFI Datacom Sinusoidal Jitter Tolerance
–20 dB/Dec
5.0
0.05
0.04
0.4
4
40
Frequency (MHz)
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Electrical Specifications
The following table lists the 10G input jitter specifications for the VSC8489-02 device.
Table 33 •
Line-Side SONET 10G Input Jitter AC Characteristics
Parameter
Symbol
Minimum
Typical
Maximum
Unit
RXIN input data rate,
10 Gbps WAN
9.95328 –
100 ppm
9.95328
9.95328 + 100 ppm Gbps
Sinusoidal jitter tolerance, SJT
9.95 Gbps
1.5x jitter
mask
Condition
GR-253 according
to SONET OC-192
standard
The host-side 6.25 Gbps receiver operating in RXAUI mode complies with the AC characteristics
specified for CEI-6G-SR interfaces according to OIF-CEI-02.0.
Table 34 •
Host-Side RXAUI Receiver AC Characteristics
Parameter
Symbol
Minimum
Maximum
Unit
6.25 – 100 ppm
6.25 + 100 ppm
Gbps
125
750
mV
AC-coupled, measured
peak-to-peak each side
(both sides driven)
Differential input return loss RLISDD11
–8
dB
100 MHz to 4.6875 GHz
Differential input return loss RLISDD11
–8 + 16.6 x
log(f/4.6875)
dB
4.6875 GHz to 6.25 GHz
100 MHz to 4.6875 GHz
Data rate
Differential peak-to-peak
input voltage
VI_DIFF
Common-mode return loss
RLSCC11
–6
dB
Random jitter
RJ
0.15
UIP-P
Uncorrelated bounded high- UBHPJ
probability jitter
0.15
UIP-P
Correlated bounded highprobability jitter
CBHPJ
0.30
UIP-P
Total jitter
TJ
0.60
UIP-P
Eye mask X1
R_X1
0.30
UIP-P
Eye mask Y1
R_Y1
Eye mask Y2
R_Y2
62.5
Condition
mV
375
mV
The following table lists the host-side 3.125 Gbps receiver characteristics when operating in XAUI mode
following IEEE 802.3 clauses 47, 54, and 71.
Table 35 •
Host-Side XAUI Receiver AC Characteristics
Parameter
Symbol
Data rate
Differential peak-to-peak
input voltage
VI_DIFF
Minimum
Maximum
Unit
Condition
3.125 –
100 ppm
3.125 +
100 ppm
Gbps
75
1600
mV
AC-coupled, measured
peak-to-peak each side
(both sides driven)
Differential input return loss RLISDD11
–10
dB
100 MHz to 2.5 GHz
Common-mode return loss RLSCC11
–6
dB
100 MHz to 2.5 GHz
Random jitter
0.18
UIP-P
RJ
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Electrical Specifications
Host-Side XAUI Receiver AC Characteristics (continued)
Table 35 •
Parameter
Symbol
Deterministic jitter
Total jitter tolerance1
1.
Minimum
Maximum
Unit
DJ
0.37
UIP-P
TJ
0.65
UIP-P
Condition
Total jitter includes sinusoidal jitter according to IEEE 802.3 clause 47.3.4.6.
The following illustration shows the sinusoidal jitter tolerance for the XAUI receiver input.
Sinusoidual Jitter Amplitude (UIp-p)
Figure 36 • XAUI Receiver Input Sinusoidal Jitter Tolerance
8.5
0.1
22.1 k
1.875 M
20 M
Frequency (Hz)
The following table lists the line-side 1.25 Gbps SFI input specifications for the VSC8489-02 device.
Table 36 •
Line-Side 1.25 Gbps SFI Input AC Characteristics
Parameter
Symbol
RXIN input
data rate,
1.25 Gbps
Minimum
Typical
Maximum
Unit
Condition
1.25 –
100 ppm
1.25
1.25 + 100 ppm Gbps 1.25 Gbps mode
Differential
input return
loss
RLISDD11
–10
dB
50 MHz to 625 MHz
Differential
input return
loss
RLISDD11
–10 + 10 x
log(f/625 MHz)
dB
625 MHz to 1250 MHz
Total jitter
tolerance
TJT
0.749
UI
Jitter above 637 kHz
(IEEE 802.3 clause
38.5)
Deterministic
jitter
DJ
0.462
UIP-P Jitter above 637 kHz
(IEEE 802.3 clause
38.5)
Eye mask Y1
Y1
Eye mask Y2
Y2
125
mV
600
mV
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Electrical Specifications
The host-side 1.25 Gbps receiver operating in 1000BASE-KX mode complies with IEEE 802.3 clause 70.
Table 37 •
Host-Side 1.25 Gbps (1000BASE-KX) Receiver Input AC Characteristics
Parameter
Symbol
Data rate
Minimum
Maximum
Unit
1.25 – 100 ppm
1.25 + 100 ppm
Gbps
Condition
Differential input
return loss
RLISDD11
–10
dB
50 MHz to 625 MHz
Differential input
return loss
RLISDD11
–10 + 10 x
log(f/625 MHz)
dB
625 MHz to 1250 MHz
Total jitter
tolerance1
TOLTJ
0.749
UI
Measured according to
IEEE 802.3 clause
38.5
Deterministic jitter TOLDJ
tolerance1
0.462
UI
Measured according to
IEEE 802.3 clause
38.5
1.
5.2.2
Jitter requirements represent high-frequency jitter (above 637 kHz) and not low-frequency jitter or wander.
Transmitter Specifications
This section includes the transmitter specifications.
The specifications in the following table correspond to line-side 10G transmitter output, SFI point B. Point
B is after a standard-compliant SFI or XFI channel, as defined in the SFP+ standard (SFF-8431) or the
XFP multisource agreement (INF-8077i). The measurement is done with a 9 dB channel loss unless
stated otherwise.
Table 38 •
Line-Side 10G Transmitter Output (SFI Point B) AC Characteristics
Parameter
Symbol
Termination mismatch
Maximum
Unit
∆ZM
5
%
AC common-mode voltage
VOCM_AC
15
mVRMS
Differential return loss
SDD22
–12
Differential return loss
Minimum
SDD22
dB
0.01 GHz to 2.0 GHz
See
note1
dB
2.0 GHz to 11.1 GHz
note2
db
0.01 GHz to 2.5 GHz
2.5 GHz to 11.1 GHz
Common-mode return loss
SCC22
See
Common-mode return loss
SCC22
–3
db
Total jitter
TJ
0.28
UI
Data-dependent jitter
DDJ
0.1
UI
Pulse shrinkage jitter
DDPWS
0.055
UI
Uncorrelated jitter
UJ
0.023
UIRMS
Eye mask X1
X1
0.12
UI
Eye mask X2
X2
0.33
UI
Eye mask Y1
Y1
Eye mask Y2
Y2
1.
2.
Condition
95
mV
350
mV
Reflection coefficient given by the equation SDD22(dB) = –6.68 + 12.1 Log10(f/5.5), with f in GHz.
S-parameter equation SCC22(dB) = -7 + 1.6 × f, with f in GHz.
The following illustration shows the compliance mask associated with the Tx SFI transmit differential
output.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
64
Electrical Specifications
Figure 37 • SFI Transmit Differential Output Compliance Mask
Y2
Voltage
Y1
0
–Y1
–Y2
0.0
X1
X2
1–X2
1–X1
1.0
Normalized Time (UI)
The following table shows the transmit path output specifications for SFI point B with 7 dB SFI channel
loss.
Table 39 •
Transmitter SFP+ Direct Attach Copper Output AC Characteristics
Parameter
Symbol
Minimum
SFP+ direct attach
copper voltage
modulation
amplitude, peak-topeak
VMA
300
SFP+ direct attach
copper transmitter
QSQ
QSQ
63.1
SFP+ direct attach
copper output AC
common-mode
voltage
SFP+ direct attach
copper host output
TWDPc
TWDPc
Maximum
Unit
Condition
mV
See SFF-8431 section D.7.
See SFF-8431 section D.8.
12
mV
See SFF-8431 section D.15.
(RMS)
10.7
dB
Electrical output measured
using SFF-8431 Appendix G,
including copper direct attach
stressor.
The following table shows that the 10 Gbps transmitter operating in 10GBASE-KR mode complies with
IEEE 802.3 clause 72.7.
Table 40 •
10 Gbps Transmitter 10GBASE-KR AC Characteristics
Parameter
Symbol
Minimum
Maximum
Signalling speed
TBAUD
10.3125 – 100 ppm
10.3125 + 100 ppm Gbps
Differential output
return loss
RLOSDD22 9
9 – 12 x log(f/2.5)
dB
50 MHz to 2.5 GHz
2.5 GHz to 7.5 GHz
RL = 100 Ω ± 1%
Common mode
return loss
RLOCM
6
6 – 12 x log(f/2.5)
dB
50 MHz to 2.5 GHz
2.5 GHz to 7.5 GHz
RL = 100 Ω ± 1%
Transition time
TR, TF
24
ps
20% to 80%
47
Unit
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
Condition
65
Electrical Specifications
Table 40 •
10 Gbps Transmitter 10GBASE-KR AC Characteristics (continued)
Parameter
Symbol
Random jitter
RJ
Deterministic jitter
DJ
Minimum
Maximum
Unit
Condition
0.15
UI
BER 1E–12
0.15
UI
Duty cycle distortion DCD
(part of DJ)
0.035
UI
Total jitter
0.28
UI
TJ
The following table shows the transmit path SONET jitter specifications for point A, measured with
register optimization and using a clock rate of 156.25 MHz or 155.52 MHz.
Table 41 •
Line-Side SONET 10G Output Jitter AC Characteristics
Parameter
Symbol
Maximum
Unit
Total jitter, 20 kHz to 80 MHz
TJ
150
mUI
Total jitter, 4 MHz to 80 MHz
TJ
80
mUI
The near-end 6.25 Gbps transmitter output operating in RXAUI mode complies with the AC
characteristics specified for CEI-6G-SR interfaces according to OIF-CEI-02.0.
Table 42 •
Near-end RXAUI Transmitter Output AC Characteristics
Parameter
Symbol
Data rate
Minimum
Maximum
Unit
6.25 – 100 ppm
6.25 + 100 ppm
Gbps
Condition
Differential output return loss
RLOSDD22
–8
dB
100 MHz to 4.6875 GHz
Differential output return loss
RLOSDD22
–8 + 16.6 x
log(f/4.6875)
dB
4.6875 GHz to 6.25 GHz
Common-mode output return
loss
RLOSCC22
–6
dB
100 MHz to 4.6875 GHz
Rise time and fall time
tR, tF
130
ps
20% to 80%
Uncorrelated bounded highprobability jitter
UBHPJ
0.15
UIP-P
Duty cycle distortion
DCD
0.05
UIP-P
30
Total jitter
TJ
0.30
UIP-P
Eye mask X1
X1
0.15
UIP-P
Eye mask X2
X2
0.40
UIP-P
Eye mask Y1
Y1
Eye mask Y2
Y2
200
mV
375
mV
The far-end 6.25 Gbps transmitter output operating in RXAUI mode complies with the AC characteristics
specified for CEI-6G-SR interfaces according to OIF-CEI-02.0.
Table 43 •
Far-end RXAUI Transmitter Output AC Characteristics
Parameter
Symbol
Uncorrelated bounded highprobability jitter
UBHPJ
Minimum
Maximum
Unit
0.15
UIP-P
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Condition
66
Electrical Specifications
Table 43 •
Far-end RXAUI Transmitter Output AC Characteristics (continued)
Parameter
Symbol
Correlated bounded highprobability jitter
Minimum
Maximum
Unit
CBHPJ
0.30
UIP-P
Total jitter
TJ
0.60
UIP-P
Eye mask X1
R_X1
0.30
UIP-P
Eye mask Y1
R_Y1
Eye mask Y2
R_Y2
62.5
Condition
mV
375
mV
The following table lists the far-end XAUI output specifications for the VSC8489-02 device.
Table 44 •
Far-end XAUI Transmitter Output AC Characteristics
Parameter
Symbol
Data rate
Minimum
Maximum
Unit
3.125 – 100 ppm
3.125 + 100 ppm
Gbps
Condition
Differential output
voltage
VOUT_DIFF 600
1600
mV
Near-end
Differential output
return loss
RLOSDD11
–10
dB
312.5 MHz to
625 MHz
Differential output
return loss
RLOSDD11
–10 + 10 x
log(f/625 MHz)
dB
625 MHz to
3.125 GHz
Rise time and fall
time
tR, tF
130
ps
20% to 80%
Total jitter
TJ
0.55
UI
Deterministic jitter
DJ
0.37
UI
Eye mask X1
X1
0.275
UI
Eye mask X2
X2
0.4
UI
Eye mask A1
A1
Eye mask A2
A2
60
100
mV
800
mV
The following illustration shows the compliance mask for the XAUI output.
Differential Signal Amplitude (V)
Figure 38 • XAUI Output Compliance Mask
A2
A1
0
−A1
−A2
0
X1
X2
1-X2 1-X1
1
Normalized Bit Time (UI)
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Electrical Specifications
The following table lists the line-side 1.25 Gbps SFI output specifications for the VSC8489-02 device.
Table 45 •
Line-Side 1.25 Gbps SFI Output AC Characteristics
Parameter
Symbol
Differential output
return loss
Minimum
Maximum
Unit
Condition
RLOSDD22
–10
dB
50 MHz to 625 MHz
Differential output
return loss
RLOSDD22
–10 + 10 x
log(f/625 MHz)
dB
625 MHz to 1250 MHz
Common mode
return loss
RLOCM
–6
dB
50 MHz to 625 MHz
Deterministic jitter
DJ
0.1
UI
Measured according to
IEEE 802.3 clause 38.5
Total jitter
TJ
0.24
UI
Measured according to
IEEE 802.3 clause 38.5
Eye mask Y1
Y1
mV
SFF-8431 1G
specification
Eye mask Y2
Y2
mV
SFF-8431 1G
specification
150
500
The host-side transmitter operating in 1000BASE-KX mode complies with IEEE 802.3 clause 70.
Table 46 •
Host-Side Transmitter 1000BASE-KX AC Characteristics
Parameter
Symbol
Data rate
Minimum
Maximum
Unit
1.25 – 100 ppm
1.25 + 100 ppm
Gbps
Condition
Differential output
return loss
RLOSDD22
–10
dB
50 MHz to 625 MHz
Differential output
return loss
RLOSDD22
–10 + 10 x
log(f/625 MHz)
dB
625 MHz to
1250 MHz
Random jitter
RJ
0.15
UIP-P At BER 10 –12
Deterministic jitter
DJ
0.10
UIP-P
Total jitter
TJ
0.25
UIP-P
5.2.3
Timing and Reference Clock
The following table lists the reference clock specifications (XREFCK, SREFCK, and WREFCK) for the
VSC8489-02 device.
Table 47 •
Reference Clock AC Characteristics
Parameter
Symbol
Minimum
XREFCK, SREFCK, and
WREFCK frequency1
ƒREFCLK
XREFCK, SREFCK, and
WREFCK frequency accuracy1
ƒR
Rise time and fall time
t R , tF
XREFCK and WREFCK Clock
duty cycle
DC
Maximum
Unit
120
156.25
MHz
– 100 ppm
100 ppm
MHz
0.4
ns
Within ± 200 mV
relative to VDD x 2/3
60
%
At 50% threshold
40
Typical
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
Condition
68
Electrical Specifications
Reference Clock AC Characteristics (continued)
Table 47 •
Parameter
Symbol
Minimum
SREFCK Clock duty cycle
DCSREFCK
45
Jitter tolerance for XREFCLK,
WREFCLK, and SREFCLK
JTLXREF
1.
Typical
Maximum
Unit
Condition
55
%
At 50% threshold
0.7
ns
For frequency 2 KHz to
20 MHz
XREFCK (LAN mode applications) frequency may be set to 125 MHz or 156.25 MHz. WREFCK (LAN or WAN mode Synchronous
Ethernet applications) frequency may be set to 155.52 MHz. SREFCK (LAN mode Synchronous Ethernet applications) frequency
is 156.25 MHz.
The following illustration shows the worst-case clock jitter transfer characteristic for the XREFCK input.
Figure 39 • XREFCK to Data Output Jitter Transfer
3.0 dB
0 dB
-3.0 dB
-6.0 dB
gain
-9.0 dB
-12.0 dB
-15.0 dB
-18.0 dB
-21.0 dB
-24.0 dB
.01 MHz
.1 MHz
1.0 MHz
10.0 MHz
100.0 MHz
frequency
5.2.4
Two-Wire Serial (Slave) Interface
This section contains information about the AC specifications for the two-wire serial slave interface for
the VSC8489-02 device.
Table 48 •
Two-Wire Serial Interface AC Characteristics
Standard
Parameter
Symbol
Serial clock frequency
ƒSCL
Minimum
Fast Mode
Maximum
Minimum
100
Maximum
Unit
400
kHz
Hold time START condition tHD:STA
after this period, the first
clock pulse is generated
4.0
0.6
µs
Low period of SCL
tLOW
4.7
1.3
µs
High period of SCL
tHIGH
4.0
0.6
µs
Data hold time
tHD:DAT
0
Data setup time
tSU:DAT
250
3.45
0
0.9
100
µs
ns
Rise time for SDA and SCL tR
1000
300
ns
Fall time for SDA and SCL tF
300
300
ns
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
69
Electrical Specifications
Table 48 •
Two-Wire Serial Interface AC Characteristics (continued)
Standard
Fast Mode
Parameter
Symbol
Minimum
Setup time for STOP
condition
tSU:STO
4.0
0.6
µs
Bus free time between a
STOP and START
tBUF
4.7
1.3
µs
Capacitive load for SCL
and SDA bus line
CB
External pull-up resistor1
RP
1.
Maximum
Minimum
Maximum
400
8 x 10–7/CB
900
900
Unit
330
pF
3 x 10–7/CB
Ω
Minimum value is determined from IOL and internal reliability requirements. Maximum value is determined by
load capacitance. Microsemi recommends 10 kΩ for typical applications in which capacitance loads are
below the specified minimums.
Figure 40 • Two-Wire Serial Interface Timing
SDA
tF
tLOW
tR
tF
tSU;DAT
tHD;STA
tR
tBUF
SCL
S
tHD;STA
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
S = START, P = STOP, and Sr = repeated START .
5.2.5
MDIO Interface
This section contains information about the AC specifications for the MDIO interface for the VSC8489-02
device.
Table 49 •
MDIO Interface AC Characteristics
Parameter
Symbol
Minimum
Maximum
Unit
MDIO data hold time
tHOLD
10
ns
MDIO data setup time
tSU
10
ns
Delay from MDC rising edge to MDIO data change
tDELAY
300
ns
MDC clock rate
ƒ
2.5
MHz
The following illustration shows the timing with the MDIO sourced by STA.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
70
Electrical Specifications
Figure 41 • Timing with MDIO Sourced by STA
VIH (MIN)
MDC
VIH (MIN)
VIH (MIN)
MDIO
VIH (MIN)
10 ns minimum
10 ns minimum
The following illustration shows the timing with the MDIO sourced by MMD.
Figure 42 • Timing with MDIO Sourced by MMD
VIH (MIN)
MDC
VIH (MIN)
VIH (MIN)
MDIO
VIH (MIN)
0 ns Minimum
300 ns Maximum
The following table lists the clock output specifications (RX0CKOUT, RX1CKOUT, TX0CKOUT,
TX1CKOUT) for the VSC8489-02 device.
Clock Output AC Characteristics
Table 50 •
Parameter
Symbol
RX0CKOUT, RX1CKOUT, TX0CKOUT, and
TX1CKOUT jitter generation
JGC64
RX0CKOUT, RX1CKOUT, TX0CKOUT, and
TX1CKOUT differential output swing
∆V
5.2.6
Minimum
650
Maximum
Unit
Condition
10
psRMS
from
10 KHz to
10 MHz
900
mVP-P
SPI Slave Interface
This section contains information about the AC specifications for the four-pin SPI slave interface used to
read and write registers. The maximum clock rate is 30 MHz and it is configurable.
Table 51 •
SPI Slave Interface AC Characteristics
Parameter
Symbol
Minimum
Maximum
Unit
MOSI data setup time
tSU, MOSI
10
ns
MOSI data hold time
tHD, MOSI
10
ns
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
Condition
71
Electrical Specifications
Table 51 •
SPI Slave Interface AC Characteristics (continued)
SSN data setup time
tSU, SSN
15
ns
SSN transition low to
enable interface
SSN data hold time
tHD, SSN
SCK clock
period + 15.0
ns
SSN transition high to
enable interface
SSN transition low to
MISO valid
tON, MISO
SSN transition high to
MISO high impedance
tOFF, MISO 18
17
ns
ns
Falling SCK to valid MISO tDLY, NORM 14
data, normal mode
30
ns
Maximum capacitance
loading of 5 pF
Rising SCK to valid MISO tDLY, FAST
data, fast mode
30
ns
Maximum capacitance
loading of 5 pF
14
The following illustration shows the SPI interface timing.
Figure 43 • SPI Interface Timing
tSU,SSN
tHD,SSN
SSN
MOSI
tHD,MOSI
tSU,MOSI
SCK
tDLY,NORM
MISO,
Normal
Mode
tDLY,FAST
tON,MISO
tOFF,MISO
MISO,
Fast
Mode
The following table lists the AC characteristics for the 3-pin push-out SPI.
Table 52 •
Parameter
3-Pin Push-Out SPI AC Characteristics
Symbol
Minimum
Maximum
Unit
SPI_DO to
tDO, CLK
SPI_CLK delay
–1
6.5
ns
SPI_CS to
tCS, CLK
SPI_CLK delay
0.5
8
ns
The following illustration shows the 3-pin push-out SPI timing.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
72
Electrical Specifications
Figure 44 • 3-Pin Push-Out SPI Timing
SPI_CLK
SPI_DO
SPI_CS
5.3
Operating Conditions
To ensure that the control pins remain set to the desired configured state when the VSC8489-02 device
is powered up, perform a reset using the reset pin after power-up and after the control pins are steady for
1 ms.
Recommended Operating Conditions
Table 53 •
Parameter
Symbol
Minimum
Typical
Maximum
Unit
1.0 V power supply voltage
VDDAH
VDDAL
VDDL
0.95
1.0
1.05
V
1.2 V power supply voltage
VDDHSL
1.14
1.2
1.26
V
1.2 V power supply current
IDD12
98
150
mA
2.5 V TTL I/O power supply
voltage
VDDTTL
2.375
VDDMDIO
2.5
2.625
V
TTL I/O power supply current
IDDTTL
40
Operating
1.
5.4
temperature1
T
–40
Condition
mA
110
°C
Minimum specification is ambient temperature, and the maximum is junction temperature.
Stress Ratings
This section contains the stress ratings for the VSC8489-02 device.
Warning Stresses listed in the following table may be applied to devices one at a time without causing
permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these
values for extended periods may affect device reliability
Table 54 •
Stress Ratings
Parameter
Symbol
Minimum
Maximum
Unit
1.0 V power supply voltage, potential to ground
VDDAH
VDDAL
VDDL
–0.3
1.1
V
1.2 V power supply voltage, potential to ground
VDDHSL
–0.3
1.32
V
2.5 V TTL I/O power supply voltage
VDDTTL
VDDMDIO
–0.3
2.75
V
Storage temperature
TS
–55
125
°C
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
73
Electrical Specifications
Table 54 •
Stress Ratings (continued)
Electrostatic discharge voltage, charged device
model
VESD_CDM –250
Electrostatic discharge voltage, human body model
VESD_HBM
1.
See note1
250
V
V
This device has completed all required testing as specified in the JEDEC standard JESD22-A114,
Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), and complies with a Class 2
rating. The definition of Class 2 is any part that passes an ESD pulse of 2000 V, but fails an ESD pulse of
4000 V.
Warning This device can be damaged by electrostatic discharge (ESD) voltage. Microsemi
recommends that all integrated circuits be handled with appropriate precautions. Failure to observe
proper handling and installation procedures may adversely affect reliability of the device.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
74
Pin Descriptions
6
Pin Descriptions
The VSC8489-02 device has 196 pins, which are described in this section.
The pin information is also provided as an attached Microsoft Excel file, so that you can copy it
electronically. In Adobe Reader, double-click the attachment icon.
6.1
Pin Diagram
The following illustration is a representation of the VSC8489-02 device, as seen from the top view.
Figure 45 • Pin Diagram
1
6.2
2
3
4
5
6
7
8
9
10
11
12
13
14
A GND
GND
XTX0_3P
XTX0_2P
XTX0_1P
XTX0_0P
TDIOP
RX0CKOUTN
GND
TX0CKOUTN
GND
GND
GND
GND
B
GND
GND
XTX0_3N
XTX0_2N
XTX0_1N
XTX0_0N
TDION
RX0CKOUTP
GND
TX0CKOUTP
GND
GND
RXIN0N
RXIN0P
C
XRX0_0P XRX0_0N
GND
GND
GND
RESETN
VDDMDIO
PADDR2
GPIO_13
GND
GND
GND
D
XRX0_1P XRX0_1N
GND
GPIO_0
GPIO_1
LOPC0
MDC
NC
SSN
PADDR1
SC K
GND
E
XRX0_2P XRX0_2N
GND
GPIO_2
GPIO_3
PADDR4
MDIO
NC
MOSI
PADDR3
MISO GND
F
XRX0_3P XRX0_3N
GND
GPIO_4
GPIO_5
GND
VDDAL
GND
VDDHSL
VDDHSL
GND
GND
VDDAH
VDDAH
GND
VDDAL
VDDTTL GPIO_12
TXOUT0P TXOUT0N
GND
GND
XREFCKP XREFCKN
G GND
GND
GND
GND
VDDAL
VDDHSL
GND
GND
GND
GND
H
XTX1_0P
XTX1_0N
GND VDDL VDDL GND VDDL GND
VDDAL
VDDHSL
GND
SREFCKP
GND
WREFCKP
J
XTX1_1P
XTX1_1N
GND
VDDAH
VDDAH
GND
VDDAL
GND
VDDHSL
VDDHSL
GND
SREFCKN
GND
WREFCKN
K
XTX1_2P
XTX1_2N
GND
GPIO_6
GPIO_7
GPIO_8
NC
TDO
TC K
TRSTB
MODE0
GND
GND
GND
L
XTX1_3P
XTX1_3N
GND
GPIO_9
GPIO_10
GPIO_11
NC
TDI
SCAN_EN
NC
RCOMPP
GND
RXIN1P
RXIN1N
M GND
GND
GND
GND
TMS
VDDTTL
LOPC1
NC
MODE1
GND
RCOMPN
GND
GND
GND
N GND
XRX1_0P
XRX1_1P
XRX1_2P
XRX1_3P
GND
RX1CKOUTP
GND
TX1CKOUTP
GND
GPIO_14
GND
P
XRX1_0N XRX1_1N XRX1_2N XRX1_3N
GND
RX1CKOUTN
GND
TX1CKOUTN
GND
GPIO_15
GND
GND
TXOUT1N TXOUT1P
GND
GND
Pin Identifications
This section contains the pin descriptions for the device, sorted according to their functional group.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
75
Pin Descriptions
The following table lists the definitions for the pin type symbols.
Table 55 •
Pin Identifications
Symbol
Pin Type
Description
A
Analog I/O
Analog input for sensing variable voltage levels.
I
Input
Input signal.
O
Output
Output signal.
B
Bidirectional
Bidirectional input or output signal.
CML
Current mode logic
NC
No connect
LVTTL
Low voltage transistor-to-transistor logic
LVTTLOD Low-voltage transistor-to-transistor logic with
open-drain output
6.3
Pins by Function
This section contains the functional pin descriptions for the VSC8489-02 device.
Note: All the differential clock signals and differential data signals should be AC-coupled. A cap of 0.1 uF would
be sufficient.
Functional Group Name
Number Type Level
Description
1588
CLK1588N
E8
I
CML
1588 logic clock input, complement
1588
CLK1588P
D8
I
CML
1588 logic clock input, true
1588
SPI_CLK
K7
O
LVTTL
Pushout SPI clock output for 1588 timestamp
1588
SPI_CS
L10
O
LVTTL
Pushout SPI chip select output for 1588 timestamp
1588
SPI_DO
L7
O
LVTTL
Clock Signal
RX0CKOUTN A8
O
CML
Clock Signal
RX0CKOUTP B8
O
CML
Clock Signal
SREFCKN
J12
I
CML
Pushout SPI data output for 1588 timestamp
Selectable clock output channel 0, complement. See
register device 1, address A008.
Selectable clock output channel 0, true. See register
device 1, address A008.
SyncE reference clock input, complement
Clock Signal
SREFCKP
H12
I
CML
Clock Signal
TX0CKOUTN A10
O
CML
Clock Signal
TX0CKOUTP B10
O
CML
Clock Signal
WREFCKN
J14
I
CML
SyncE reference clock input, true
Selectable clock output channel 0, complement. See
register device 1, address A009.
Selectable clock output channel 0, true. See register
device 1, address A009.
WAN reference clock input, complement
Clock Signal
WREFCKP
H14
I
CML
WAN reference clock input, true
Clock Signal
XREFCKN
F14
I
CML
Reference clock input, complement
Clock Signal
XREFCKP
F13
I
CML
Reference clock input, true
JTAG
TCK
K9
I
LVTTL
Boundary scan, test clock input. Internally pulled high.
JTAG
TDI
L8
I
LVTTL
Boundary scan, test data input. Internally pulled high.
JTAG
TDO
K8
O
LVTTL
Boundary scan, test data output.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
76
Pin Descriptions
JTAG
TMS
M5
I
LVTTL
Boundary scan, test mode select. Internally pulled high.
JTAG
TRSTB
K10
I
LVTTL
Boundary scan, test reset input. Internally pulled high.
MDIO
MDC
D7
I
LVTTL
MDIO clock input
MDIO
MDIO
E7
B
LVTTLOD MDIO data I/O
Miscellaneous
GPIO_0
D4
B
LVTTLOD General purpose I/O 0
Miscellaneous
GPIO_1
D5
B
LVTTLOD General purpose I/O 1
Miscellaneous
GPIO_2
E4
B
LVTTLOD General purpose I/O 2
Miscellaneous
GPIO_3
E5
B
LVTTLOD General purpose I/O 3
Miscellaneous
GPIO_4
F4
B
LVTTLOD General purpose I/O 4
Miscellaneous
GPIO_5
F5
B
LVTTLOD General purpose I/O 5
Miscellaneous
GPIO_6
K4
B
LVTTLOD General purpose I/O 6
Miscellaneous
GPIO_7
K5
B
LVTTLOD General purpose I/O 7
Miscellaneous
GPIO_8
K6
B
LVTTLOD General purpose I/O 8
Miscellaneous
GPIO_9
L4
B
LVTTLOD General purpose I/O 9
Miscellaneous
GPIO_10
L5
B
LVTTLOD General purpose I/O 10
Miscellaneous
GPIO_11
L6
B
LVTTLOD General purpose I/O 11
Miscellaneous
GPIO_12
C10
B
LVTTLOD General purpose I/O 12
Miscellaneous
GPIO_13
C11
B
LVTTLOD General purpose I/O 13
Miscellaneous
GPIO_14
N11
B
LVTTLOD General purpose I/O 14
Miscellaneous
GPIO_15
P11
B
LVTTLOD General purpose I/O 15
Miscellaneous
MODE0
K11
I
LVTTL
Mode select input bit 0
Miscellaneous
MODE1
M9
I
LVTTL
Mode select input bit 1
Miscellaneous
PADDR1
D10
I
LVTTL
MDIO port address bit 1. Internally pulled low.
Miscellaneous
PADDR2
C8
I
LVTTL
MDIO port address bit 2. Internally pulled low.
Miscellaneous
PADDR3
E10
I
LVTTL
MDIO port address bit 3. Internally pulled low.
Miscellaneous
PADDR4
E6
I
LVTTL
MDIO port address bit 4. Internally pulled low.
Miscellaneous
RCOMPN
M11
Analog
Resistor comparator, complement
Miscellaneous
RCOMPP
L11
Analog
Resistor comparator, truth
Miscellaneous
RESETN
C6
I
LVTTL
Miscellaneous
SCAN_EN
L9
I
LVTTL
Miscellaneous
TDION
B7
Analog
Reset. Low= reset. Internally pulled high.
Scan enable input, factory test purposes only. Keep
connected to Ground.
Temperature diode, complement
Miscellaneous
TDIOP
A7
Analog
Temperature diode, truth
Power and Ground GND
A1
P
GND
Ground
Power and Ground GND
A2
P
GND
Ground
Power and Ground GND
A9
P
GND
Ground
Power and Ground GND
A11
P
GND
Ground
Power and Ground GND
A12
P
GND
Ground
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
77
Pin Descriptions
Power and Ground GND
A13
P
GND
Ground
Power and Ground GND
A14
P
GND
Ground
Power and Ground GND
B1
P
GND
Ground
Power and Ground GND
B2
P
GND
Ground
Power and Ground GND
B9
P
GND
Ground
Power and Ground GND
B11
P
GND
Ground
Power and Ground GND
B12
P
GND
Ground
Power and Ground GND
C4
P
GND
Ground
Power and Ground GND
C5
P
GND
Ground
Power and Ground GND
C12
P
GND
Ground
Power and Ground GND
C13
P
GND
Ground
Power and Ground GND
C14
P
GND
Ground
Power and Ground GND
D3
P
GND
Ground
Power and Ground GND
D12
P
GND
Ground
Power and Ground GND
E3
P
GND
Ground
Power and Ground GND
E12
P
GND
Ground
Power and Ground GND
E13
P
GND
Ground
Power and Ground GND
E14
P
GND
Ground
Power and Ground GND
F3
P
GND
Ground
Power and Ground GND
F6
P
GND
Ground
Power and Ground GND
F8
P
GND
Ground
Power and Ground GND
F11
P
GND
Ground
Power and Ground GND
F12
P
GND
Ground
Power and Ground GND
G1
P
GND
Ground
Power and Ground GND
G2
P
GND
Ground
Power and Ground GND
G3
P
GND
Ground
Power and Ground GND
G6
P
GND
Ground
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
78
Pin Descriptions
Power and Ground GND
G8
P
GND
Ground
Power and Ground GND
G11
P
GND
Ground
Power and Ground GND
G12
P
GND
Ground
Power and Ground GND
G13
P
GND
Ground
Power and Ground GND
G14
P
GND
Ground
Power and Ground GND
H3
P
GND
Ground
Power and Ground GND
H6
P
GND
Ground
Power and Ground GND
H8
P
GND
Ground
Power and Ground GND
H11
P
GND
Ground
Power and Ground GND
H13
P
GND
Ground
Power and Ground GND
J3
P
GND
Ground
Power and Ground GND
J6
P
GND
Ground
Power and Ground GND
J8
P
GND
Ground
Power and Ground GND
J11
P
GND
Ground
Power and Ground GND
J13
P
GND
Ground
Power and Ground GND
K3
P
GND
Ground
Power and Ground GND
K12
P
GND
Ground
Power and Ground GND
K13
P
GND
Ground
Power and Ground GND
K14
P
GND
Ground
Power and Ground GND
L3
P
GND
Ground
Power and Ground GND
L12
P
GND
Ground
Power and Ground GND
M1
P
GND
Ground
Power and Ground GND
M2
P
GND
Ground
Power and Ground GND
M3
P
GND
Ground
Power and Ground GND
M4
P
GND
Ground
Power and Ground GND
M10
P
GND
Ground
Power and Ground GND
M12
P
GND
Ground
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
79
Pin Descriptions
Power and Ground GND
M13
P
GND
Ground
Power and Ground GND
M14
P
GND
Ground
Power and Ground GND
N1
P
GND
Ground
Power and Ground GND
N6
P
GND
Ground
Power and Ground GND
N8
P
GND
Ground
Power and Ground GND
N10
P
GND
Ground
Power and Ground GND
N12
P
GND
Ground
Power and Ground GND
P1
P
GND
Ground
Power and Ground GND
P6
P
GND
Ground
Power and Ground GND
P8
P
GND
Ground
Power and Ground GND
P10
P
GND
Ground
Power and Ground GND
P12
P
GND
Ground
Power and Ground GND
P13
P
GND
Ground
Power and Ground GND
P14
P
GND
Ground
Power and Ground VDDAH
G4
P
Supply
1.0 V power supply for host side analog
Power and Ground VDDAH
G5
P
Supply
1.0 V power supply for host side analog
Power and Ground VDDAH
J4
P
Supply
1.0 V power supply for host side analog
Power and Ground VDDAH
J5
P
Supply
1.0 V power supply for host side analog
Power and Ground VDDAL
F7
P
Supply
1.0 V power supply for line side analog
Power and Ground VDDAL
G7
P
Supply
1.0 V power supply for line side analog
Power and Ground VDDAL
G9
P
Supply
1.0 V power supply for line side analog
Power and Ground VDDAL
H9
P
Supply
1.0 V power supply for line side analog
Power and Ground VDDAL
J7
P
Supply
1.0 V power supply for line side analog
Power and Ground VDDHSL
F9
P
Supply
1.2 V power supply for line side IOs
Power and Ground VDDHSL
F10
P
Supply
1.2 V power supply for line side IOs
Power and Ground VDDHSL
G10
P
Supply
1.2 V power supply for line side IOs
Power and Ground VDDHSL
H10
P
Supply
1.2 V power supply for line side IOs
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
80
Pin Descriptions
Power and Ground VDDHSL
J9
P
Supply
1.2 V power supply for line side IOs
Power and Ground VDDHSL
J10
P
Supply
1.2 V power supply for line side IOs
Power and Ground VDDL
H4
P
Supply
1.0 V power supply for chip core
Power and Ground VDDL
H5
P
Supply
1.0 V power supply for chip core
Power and Ground VDDL
H7
P
Supply
1.0 V power supply for chip core
Power and Ground VDDMDIO
C7
P
Supply
MDIO power supply
Power and Ground VDDTTL
C3
P
Supply
LVTTL power supply
Power and Ground VDDTTL
C9
P
Supply
LVTTL power supply
Power and Ground VDDTTL
M6
P
Supply
LVTTL power supply
LOPC0
D6
I
LVTTL
Loss of optical carrier, channel 0. Internally pulled high.
RXIN0N
B13
I
CML
Receive channel 0 input data, complement
RXIN0P
B14
I
CML
Receive channel 0 input data, true
TXOUT0N
D14
O
CML
Transmit channel 0 output data, complement
TXOUT0P
D13
O
CML
Transmit channel 0 output data, true
NC
L13
No connect
NC
L14
No connect
NC
M7
No connect (could also be grounded)
NC
M8
No connect (formerly labeled as ANATEST)
NC
N7
No connect
NC
N9
No connect
NC
N13
No connect
NC
N14
No connect
NC
P7
No connect
No connect
Receive and
Transmit Path
Receive and
Transmit Path
Receive and
Transmit Path
Receive and
Transmit Path
Receive and
Transmit Path
Reserved/No
Connect
Reserved/No
Connect
Reserved/No
Connect
Reserved/No
Connect
Reserved/No
Connect
Reserved/No
Connect
Reserved/No
Connect
Reserved/No
Connect
Reserved/No
Connect
Reserved/No
Connect
SPI
NC
P9
MISO
E11
O
LVTTL
SPI slave data output
SPI
MOSI
E9
I
LVTTL
SPI slave data input
SPI
SCK
D11
I
LVTTL
SPI slave clock input
SPI
SSN
D9
I
LVTTL
SPI slave chip select input
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
81
Pin Descriptions
XAUI Channel
XRX0_0N
C2
I
CML
XAUI channel 0, Rx path lane 0, serial data input,
complement
XAUI Channel
XRX0_0P
C1
I
CML
XAUI channel 0, Rx path lane 0, serial data input, true
XAUI Channel
XRX0_1N
D2
I
CML
XAUI channel 0, Rx path lane 1, serial data input,
complement
XAUI Channel
XRX0_1P
D1
I
CML
XAUI channel 0, Rx path lane 1, serial data input, true
XAUI Channel
XRX0_2N
E2
I
CML
XAUI channel 0, Rx path lane 2, serial data input,
complement
XAUI Channel
XRX0_2P
E1
I
CML
XAUI channel 0, Rx path lane 2, serial data input, true
XAUI Channel
XRX0_3N
F2
I
CML
XAUI channel 0, Rx path lane 3, serial data input,
complement
XAUI Channel
XRX0_3P
F1
I
CML
XAUI channel 0, Rx path lane 3, serial data input, true
XAUI Channel
XRX1_0N
P2
I
CML
XAUI channel 1, Rx path lane 0, serial data input,
complement
XAUI Channel
XRX1_0P
N2
I
CML
XAUI channel 1, Rx path lane 0, serial data input, true
XAUI Channel
XRX1_1N
P3
I
CML
XAUI channel 1, Rx path lane 1, serial data input,
complement
XAUI Channel
XRX1_1P
N3
I
CML
XAUI channel 1, Rx path lane 1, serial data input, true
XAUI Channel
XRX1_2N
P4
I
CML
XAUI channel 1, Rx path lane 2, serial data input,
complement
XAUI Channel
XRX1_2P
N4
I
CML
XAUI channel 1, Rx path lane 2, serial data input, true
XAUI Channel
XRX1_3N
P5
I
CML
XAUI channel 1, Rx path lane 3, serial data input,
complement
XAUI Channel
XRX1_3P
N5
I
CML
XAUI channel 1, Rx path lane 3, serial data input, true
XAUI Channel
XTX0_0N
B6
O
CML
XAUI channel 0, Tx path lane 0, serial data output,
complement
XAUI Channel
XTX0_0P
A6
O
CML
XAUI channel 0, Tx path lane 0, serial data output, true
XAUI Channel
XTX0_1N
B5
O
CML
XAUI channel 0, Tx path lane 1, serial data output,
complement
XAUI Channel
XTX0_1P
A5
O
CML
XAUI channel 0, Tx path lane 1, serial data output, true
XAUI Channel
XTX0_2N
B4
O
CML
XAUI channel 0, Tx path lane 2, serial data output,
complement
XAUI Channel
XTX0_2P
A4
O
CML
XAUI channel 0, Tx path lane 2, serial data output, true
XAUI Channel
XTX0_3N
B3
O
CML
XAUI channel 0, Tx path lane 3, serial data output,
complement
XAUI Channel
XTX0_3P
A3
O
CML
XAUI channel 0, Tx path lane 3, serial data output, true
XAUI Channel
XTX1_0N
H2
O
CML
XAUI channel 1, Tx path lane 0, serial data output,
complement
XAUI Channel
XTX1_0P
H1
O
CML
XAUI channel 1, Tx path lane 0, serial data output, true
XAUI Channel
XTX1_1N
J2
O
CML
XAUI channel 1, Tx path lane 1, serial data output,
complement
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
82
Pin Descriptions
XAUI Channel
XTX1_1P
J1
O
CML
XAUI channel 1, Tx path lane 1, serial data output, true
XAUI Channel
XTX1_2N
K2
O
CML
XAUI channel 1, Tx path lane 2, serial data output,
complement
XAUI Channel
XTX1_2P
K1
O
CML
XAUI channel 1, Tx path lane 2, serial data output, true
XAUI Channel
XTX1_3N
L2
O
CML
XAUI channel 1, Tx path lane 3, serial data output,
complement
XAUI Channel
XTX1_3P
L1
O
CML
XAUI channel 1, Tx path lane 3, serial data output, true
Functional Group Name
Number Type Level
Description
Clock Signal
RX0CKOUTN A8
O
CML
Selectable clock output channel 0, complement. See
register device 1, address A008.
Clock Signal
RX0CKOUTP B8
O
CML
Selectable clock output channel 0, true. See register
device 1, address A008.
Clock Signal
RX1CKOUTN P7
O
CML
Selectable clock output channel 1, complement. See
register device 1, address A008.
Clock Signal
RX1CKOUTP N7
O
CML
Selectable clock output channel 1, true. See register
device 1, address A008.
Clock Signal
SREFCKN
J12
I
CML
SyncE reference clock input, complement
Clock Signal
SREFCKP
H12
I
CML
SyncE reference clock input, true
Clock Signal
TX0CKOUTN A10
O
CML
Selectable clock output channel 0, complement. See
register device 1, address A009.
Clock Signal
TX0CKOUTP B10
O
CML
Selectable clock output channel 0, true. See register
device 1, address A009.
Clock Signal
TX1CKOUTN P9
O
CML
Selectable clock output channel 1, complement. See
register device 1, address A009.
Clock Signal
TX1CKOUTP N9
O
CML
Selectable clock output channel 1, true. See register
device 1, address A009.
Clock Signal
WREFCKN
J14
I
CML
WAN reference clock input, complement
Clock Signal
WREFCKP
H14
I
CML
WAN reference clock input, true
Clock Signal
XREFCKN
F14
I
CML
Reference clock input, complement
Clock Signal
XREFCKP
F13
I
CML
Reference clock input, true
JTAG
TCK
K9
I
LVTTL
Boundary scan, test clock input. Internally pulled
high.
JTAG
TDI
L8
I
LVTTL
Boundary scan, test data input. Internally pulled high.
JTAG
TDO
K8
O
LVTTL
Boundary scan, test data output.
JTAG
TMS
M5
I
LVTTL
Boundary scan, test mode select. Internally pulled
high.
JTAG
TRSTB
K10
I
LVTTL
Boundary scan, test reset input. Internally pulled
high.
MDIO
MDC
D7
I
LVTTL
MDIO clock input
MDIO
MDIO
E7
B
LVTTLOD MDIO data I/O
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Pin Descriptions
Miscellaneous
GPIO_0
D4
B
LVTTLOD General purpose I/O 0
Miscellaneous
GPIO_1
D5
B
LVTTLOD General purpose I/O 1
Miscellaneous
GPIO_2
E4
B
LVTTLOD General purpose I/O 2
Miscellaneous
GPIO_3
E5
B
LVTTLOD General purpose I/O 3
Miscellaneous
GPIO_4
F4
B
LVTTLOD General purpose I/O 4
Miscellaneous
GPIO_5
F5
B
LVTTLOD General purpose I/O 5
Miscellaneous
GPIO_6
K4
B
LVTTLOD General purpose I/O 6
Miscellaneous
GPIO_7
K5
B
LVTTLOD General purpose I/O 7
Miscellaneous
GPIO_8
K6
B
LVTTLOD General purpose I/O 8
Miscellaneous
GPIO_9
L4
B
LVTTLOD General purpose I/O 9
Miscellaneous
GPIO_10
L5
B
LVTTLOD General purpose I/O 10
Miscellaneous
GPIO_11
L6
B
LVTTLOD General purpose I/O 11
Miscellaneous
GPIO_12
C10
B
LVTTLOD General purpose I/O 12
Miscellaneous
GPIO_13
C11
B
LVTTLOD General purpose I/O 13
Miscellaneous
GPIO_14
N11
B
LVTTLOD General purpose I/O 14
Miscellaneous
GPIO_15
P11
B
LVTTLOD General purpose I/O 15
Miscellaneous
MODE0
K11
I
LVTTL
Mode select input bit 0
Miscellaneous
MODE1
M9
I
LVTTL
Mode select input bit 1
Miscellaneous
PADDR1
D10
I
LVTTL
MDIO port address bit 1. Internally pulled low.
Miscellaneous
PADDR2
C8
I
LVTTL
MDIO port address bit 2. Internally pulled low.
Miscellaneous
PADDR3
E10
I
LVTTL
MDIO port address bit 3. Internally pulled low.
Miscellaneous
PADDR4
E6
I
LVTTL
MDIO port address bit 4. Internally pulled low.
Miscellaneous
RCOMPN
M11
Analog
Resistor comparator, complement
Miscellaneous
RCOMPP
L11
Analog
Resistor comparator, truth
Miscellaneous
RESETN
C6
I
LVTTL
Reset. Low= reset. Internally pulled high.
Miscellaneous
SCAN_EN
L9
I
LVTTL
Scan enable input, factory test purposes only. Keep
connected to Ground.
Miscellaneous
TDION
B7
Analog
Temperature diode, complement
Miscellaneous
TDIOP
A7
Analog
Temperature diode, truth
Power and
Ground
GND
A1
P
GND
Ground
Power and
Ground
GND
A2
P
GND
Ground
Power and
Ground
GND
A9
P
GND
Ground
Power and
Ground
GND
A11
P
GND
Ground
Power and
Ground
GND
A12
P
GND
Ground
Power and
Ground
GND
A13
P
GND
Ground
Power and
Ground
GND
A14
P
GND
Ground
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Pin Descriptions
Power and
Ground
GND
B1
P
GND
Ground
Power and
Ground
GND
B2
P
GND
Ground
Power and
Ground
GND
B9
P
GND
Ground
Power and
Ground
GND
B11
P
GND
Ground
Power and
Ground
GND
B12
P
GND
Ground
Power and
Ground
GND
C3
P
GND
Ground
Power and
Ground
GND
C4
P
GND
Ground
Power and
Ground
GND
C5
P
GND
Ground
Power and
Ground
GND
C12
P
GND
Ground
Power and
Ground
GND
C13
P
GND
Ground
Power and
Ground
GND
C14
P
GND
Ground
Power and
Ground
GND
D3
P
GND
Ground
Power and
Ground
GND
D12
P
GND
Ground
Power and
Ground
GND
E3
P
GND
Ground
Power and
Ground
GND
E12
P
GND
Ground
Power and
Ground
GND
E13
P
GND
Ground
Power and
Ground
GND
E14
P
GND
Ground
Power and
Ground
GND
F3
P
GND
Ground
Power and
Ground
GND
F6
P
GND
Ground
Power and
Ground
GND
F8
P
GND
Ground
Power and
Ground
GND
F11
P
GND
Ground
Power and
Ground
GND
F12
P
GND
Ground
Power and
Ground
GND
G1
P
GND
Ground
Power and
Ground
GND
G2
P
GND
Ground
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
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Pin Descriptions
Power and
Ground
GND
G3
P
GND
Ground
Power and
Ground
GND
G6
P
GND
Ground
Power and
Ground
GND
G8
P
GND
Ground
Power and
Ground
GND
G11
P
GND
Ground
Power and
Ground
GND
G12
P
GND
Ground
Power and
Ground
GND
G13
P
GND
Ground
Power and
Ground
GND
G14
P
GND
Ground
Power and
Ground
GND
H3
P
GND
Ground
Power and
Ground
GND
H6
P
GND
Ground
Power and
Ground
GND
H8
P
GND
Ground
Power and
Ground
GND
H11
P
GND
Ground
Power and
Ground
GND
H13
P
GND
Ground
Power and
Ground
GND
J3
P
GND
Ground
Power and
Ground
GND
J6
P
GND
Ground
Power and
Ground
GND
J8
P
GND
Ground
Power and
Ground
GND
J11
P
GND
Ground
Power and
Ground
GND
J13
P
GND
Ground
Power and
Ground
GND
K3
P
GND
Ground
Power and
Ground
GND
K12
P
GND
Ground
Power and
Ground
GND
K13
P
GND
Ground
Power and
Ground
GND
K14
P
GND
Ground
Power and
Ground
GND
L3
P
GND
Ground
Power and
Ground
GND
L12
P
GND
Ground
Power and
Ground
GND
M1
P
GND
Ground
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
86
Pin Descriptions
Power and
Ground
GND
M2
P
GND
Ground
Power and
Ground
GND
M3
P
GND
Ground
Power and
Ground
GND
M4
P
GND
Ground
Power and
Ground
GND
M10
P
GND
Ground
Power and
Ground
GND
M12
P
GND
Ground
Power and
Ground
GND
M13
P
GND
Ground
Power and
Ground
GND
M14
P
GND
Ground
Power and
Ground
GND
N1
P
GND
Ground
Power and
Ground
GND
N6
P
GND
Ground
Power and
Ground
GND
N8
P
GND
Ground
Power and
Ground
GND
N10
P
GND
Ground
Power and
Ground
GND
N12
P
GND
Ground
Power and
Ground
GND
P1
P
GND
Ground
Power and
Ground
GND
P6
P
GND
Ground
Power and
Ground
GND
P8
P
GND
Ground
Power and
Ground
GND
P10
P
GND
Ground
Power and
Ground
GND
P12
P
GND
Ground
Power and
Ground
GND
P13
P
GND
Ground
Power and
Ground
GND
P14
P
GND
Ground
Power and
Ground
VDDAH
G4
P
Supply
1.0 V power supply for host side analog
Power and
Ground
VDDAH
G5
P
Supply
1.0 V power supply for host side analog
Power and
Ground
VDDAH
J4
P
Supply
1.0 V power supply for host side analog
Power and
Ground
VDDAH
J5
P
Supply
1.0 V power supply for host side analog
Power and
Ground
VDDAL
F7
P
Supply
1.0 V power supply for line side analog
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
87
Pin Descriptions
Power and
Ground
VDDAL
G7
P
Supply
1.0 V power supply for line side analog
Power and
Ground
VDDAL
G9
P
Supply
1.0 V power supply for line side analog
Power and
Ground
VDDAL
H9
P
Supply
1.0 V power supply for line side analog
Power and
Ground
VDDAL
J7
P
Supply
1.0 V power supply for line side analog
Power and
Ground
VDDHSL
F9
P
Supply
1.2 V power supply for line side IOs
Power and
Ground
VDDHSL
F10
P
Supply
1.2 V power supply for line side IOs
Power and
Ground
VDDHSL
G10
P
Supply
1.2 V power supply for line side IOs
Power and
Ground
VDDHSL
H10
P
Supply
1.2 V power supply for line side IOs
Power and
Ground
VDDHSL
J9
P
Supply
1.2 V power supply for line side IOs
Power and
Ground
VDDHSL
J10
P
Supply
1.2 V power supply for line side IOs
Power and
Ground
VDDL
H4
P
Supply
1.0 V power supply for chip core
Power and
Ground
VDDL
H5
P
Supply
1.0 V power supply for chip core
Power and
Ground
VDDL
H7
P
Supply
1.0 V power supply for chip core
Power and
Ground
VDDMDIO
C7
P
Supply
MDIO power supply
Power and
Ground
VDDTTL
C9
P
Supply
LVTTL power supply
Power and
Ground
VDDTTL
M6
P
Supply
LVTTL power supply
Receive and
Transmit Path
LOPC0
D6
I
LVTTL
Loss of optical carrier, channel 0. Internally pulled
high.
Receive and
Transmit Path
LOPC1
M7
I
LVTTL
Loss of optical carrier, channel 1. Internally pulled
high.
Receive and
Transmit Path
RXIN0N
B13
I
CML
Receive channel 0 input data, complement
Receive and
Transmit Path
RXIN0P
B14
I
CML
Receive channel 0 input data, true
Receive and
Transmit Path
RXIN1N
L14
I
CML
Receive channel 1 input data, complement
Receive and
Transmit Path
RXIN1P
L13
I
CML
Receive channel 1 input data, true
Receive and
Transmit Path
TXOUT0N
D14
O
CML
Transmit channel 0 output data, complement
Receive and
Transmit Path
TXOUT0P
D13
O
CML
Transmit channel 0 output data, true
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
88
Pin Descriptions
Receive and
Transmit Path
TXOUT1N
N13
O
CML
Transmit channel 1 output data, complement
Receive and
Transmit Path
TXOUT1P
N14
O
CML
Transmit channel 1 output data, true
Reserved/No
Connect
NC
D8
No connect
Reserved/No
Connect
NC
E8
No connect
Reserved/No
Connect
NC
K7
No connect
Reserved/No
Connect
NC
L7
No connect
Reserved/No
Connect
NC
L10
No connect
Reserved/No
Connect
NC
M8
No connect (formerly labeled as ANATEST)
SPI
MISO
E11
SPI
MOSI
E9
I
LVTTL
SPI slave data input
SPI
SCK
D11
I
LVTTL
SPI slave clock input
SPI
SSN
D9
I
LVTTL
SPI slave chip select input
XAUI Channel
XRX0_0N
C2
I
CML
XAUI channel 0, Rx path lane 0, serial data input,
complement
XAUI Channel
XRX0_0P
C1
I
CML
XAUI channel 0, Rx path lane 0, serial data input,
true
XAUI Channel
XRX0_1N
D2
I
CML
XAUI channel 0, Rx path lane 1, serial data input,
complement
XAUI Channel
XRX0_1P
D1
I
CML
XAUI channel 0, Rx path lane 1, serial data input,
true
XAUI Channel
XRX0_2N
E2
I
CML
XAUI channel 0, Rx path lane 2, serial data input,
complement
XAUI Channel
XRX0_2P
E1
I
CML
XAUI channel 0, Rx path lane 2, serial data input,
true
XAUI Channel
XRX0_3N
F2
I
CML
XAUI channel 0, Rx path lane 3, serial data input,
complement
XAUI Channel
XRX0_3P
F1
I
CML
XAUI channel 0, Rx path lane 3, serial data input,
true
XAUI Channel
XRX1_0N
P2
I
CML
XAUI channel 1, Rx path lane 0, serial data input,
complement
XAUI Channel
XRX1_0P
N2
I
CML
XAUI channel 1, Rx path lane 0, serial data input,
true
XAUI Channel
XRX1_1N
P3
I
CML
XAUI channel 1, Rx path lane 1, serial data input,
complement
XAUI Channel
XRX1_1P
N3
I
CML
XAUI channel 1, Rx path lane 1, serial data input,
true
XAUI Channel
XRX1_2N
P4
I
CML
XAUI channel 1, Rx path lane 2, serial data input,
complement
O
LVTTL
SPI slave data output
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
89
Pin Descriptions
XAUI Channel
XRX1_2P
N4
I
CML
XAUI channel 1, Rx path lane 2, serial data input,
true
XAUI Channel
XRX1_3N
P5
I
CML
XAUI channel 1, Rx path lane 3, serial data input,
complement
XAUI Channel
XRX1_3P
N5
I
CML
XAUI channel 1, Rx path lane 3, serial data input,
true
XAUI Channel
XTX0_0N
B6
O
CML
XAUI channel 0, Tx path lane 0, serial data output,
complement
XAUI Channel
XTX0_0P
A6
O
CML
XAUI channel 0, Tx path lane 0, serial data output,
true
XAUI Channel
XTX0_1N
B5
O
CML
XAUI channel 0, Tx path lane 1, serial data output,
complement
XAUI Channel
XTX0_1P
A5
O
CML
XAUI channel 0, Tx path lane 1, serial data output,
true
XAUI Channel
XTX0_2N
B4
O
CML
XAUI channel 0, Tx path lane 2, serial data output,
complement
XAUI Channel
XTX0_2P
A4
O
CML
XAUI channel 0, Tx path lane 2, serial data output,
true
XAUI Channel
XTX0_3N
B3
O
CML
XAUI channel 0, Tx path lane 3, serial data output,
complement
XAUI Channel
XTX0_3P
A3
O
CML
XAUI channel 0, Tx path lane 3, serial data output,
true
XAUI Channel
XTX1_0N
H2
O
CML
XAUI channel 1, Tx path lane 0, serial data output,
complement
XAUI Channel
XTX1_0P
H1
O
CML
XAUI channel 1, Tx path lane 0, serial data output,
true
XAUI Channel
XTX1_1N
J2
O
CML
XAUI channel 1, Tx path lane 1, serial data output,
complement
XAUI Channel
XTX1_1P
J1
O
CML
XAUI channel 1, Tx path lane 1, serial data output,
true
XAUI Channel
XTX1_2N
K2
O
CML
XAUI channel 1, Tx path lane 2, serial data output,
complement
XAUI Channel
XTX1_2P
K1
O
CML
XAUI channel 1, Tx path lane 2, serial data output,
true
XAUI Channel
XTX1_3N
L2
O
CML
XAUI channel 1, Tx path lane 3, serial data output,
complement
XAUI Channel
XTX1_3P
L1
O
CML
XAUI channel 1, Tx path lane 3, serial data output,
true
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
90
Package Information
7
Package Information
The VSC8489YJU-02 package is a lead-free (Pb-free), 196-pin, flip chip ball grid array (FCBGA) with a
15 mm × 15 mm body size, 1 mm pin pitch, and 1.4 mm maximum height.
Lead-free products from Microsemi comply with the temperatures and profiles defined in the joint IPC
and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
This section provides the package drawing, thermal specifications, and moisture sensitivity rating for the
VSC8489-02 device.
7.1
Package Drawing
The following illustration shows the package drawing for the VSC8489-02 device. The drawing contains
the top view, bottom view, side view, dimensions, tolerances, and notes.
VMDS-10502 VSC8489-02 Datasheet Revision 4.0
91
Package Information
Figure 46 • Package Drawing
Top View
Bottom View
Pin A1 corner
Pin A1 corner
14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
e
D
E
F
G
D D1
H
J
K
L
M
N
P
e
B
E1
A
0.20 (4×)
E
Øb
C
C
A
B
0.20 C
Side View
0.35 C
Ø 0.10 M
Ø 0.25 M
Dimensions and Tolerances
C
Seating plane
A1
A
Notes
1. All dimensions and tolerances are in millimeters (mm).
2. Radial true position is represented by typical values.
7.2
Reference Minimum Nominal Maximum
A
1.40
A1
0.31
0.41
D
15.00
E
15.00
D1
13.00
E1
13.00
e
1.00
b
0.50
Thermal Specifications
Thermal specifications for this device are based on the JEDEC JESD51 family of documents. These
documents are available on the JEDEC Web site at www.jedec.org. The thermal specifications are
modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p
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Package Information
PCB). For more information about the thermal measurement method used for this device, see the
JESD51-1 standard.
Table 56 •
Thermal Resistances
Symbol
°C/W
Parameter
θJCtop
3.35
Die junction to package case top
θJB
13.3
Die junction to printed circuit board
θJA
22.74
Die junction to ambient
θJMA at 1 m/s
18.6
Die junction to moving air measured at an air speed of 1 m/s
θJMA at 2 m/s
17.03
Die junction to moving air measured at an air speed of 2 m/s
To achieve results similar to the modeled thermal measurements, the guidelines for board design
described in the JESD51 family of publications must be applied. For information about applications using
FCBGA packages, see the following:
•
•
•
•
7.3
JESD51-2A, Integrated Circuits Thermal Test Method Environmental Conditions, Natural Convection
(Still Air)
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions, Forced Convection
(Moving Air)
JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions, Junction-to-Board
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Moisture Sensitivity
This device is rated moisture sensitivity level 4 as specified in the joint IPC and JEDEC standard
IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
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Design Considerations
8
Design Considerations
This section provides information about design considerations for the VSC8489-02 device.
8.1
Low-power mode and SerDes calibration
SerDes re-initialization and re-calibration is required when the PHY comes out of the low power mode.
Use the API to enable the required low power and re-calibration functionality instead of the low power
enabling bits at 1x0000.11, 2x0000.11, 3x0000.11, or 4x0000.11, which force a reset of the SerDes
registers.
8.2
Low-power mode should not be enabled when failover
switching is enabled
The device design was not intended to support the low power mode of operation when the failover switch
is enabled. When low power mode is enabled in one channel, the data flow of the other channel could be
adversely affected if the failover switch is enabled, leading to data errors.
Do not enable the low power mode when the failover switch is enabled.
8.3
Flow control with failover switching
Both Tx and Rx data paths of the channel have to be switched at the same time when flow control is
enabled. The Tx data path of one channel in one direction and the Rx data path of another channel in the
opposite direction cannot be mixed.
8.4
XAUI BIST Checker Compatibility
The XAUI BIST checker fails when checking the mixed frequency test pattern. This mixed frequency test
pattern is optional in the IEEE802.3ae specifications.
8.5
SPI bus speeds
The maximum speed enabled on the 4-pin slave SPI bus is 15.4 MHz in normal mode and 30 MHz in fast
mode. The maximum speed for the 3-pin push out only SPI is 40 MHz.
8.6
GPIO as TOSI
A small value pull-up is needed when a GPIO pin is used as TOSI. For more information, contact your
Microsemi representative.
8.7
10GBASE-KR auto negotiation and training
10GBASE-KR negotiation and training (IEEE802.3 Clause 72 and Clause 73) is only available for 10G. It
is not available for 1G.
8.8
Loopbacks in 10G WAN mode
Loopbacks L1, L2, and L2C are not available in 10G WAN mode if jumbo frames are used.
8.9
10/100M mode not supported
The PHY does not support modes of 10/100M in CuSFP. The autoneg feature is only supported in
1000BASE-X mode but not in SGMII mode. When interfacing with 1G SGMII mode (such as with
CuSFP), the autoneg feature has to be turned off.
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Design Considerations
8.10
Limited access to registers during failover crossconnect mode
The following register bits should not be used if failover cross-connect is enabled (that is, if PMA0 is
connected to channel_1 and PMA1 I connected to channel_0).
•
•
•
•
•
•
8.11
1x0001.2
1x0008.10
1x000A.0
1x9003.4
1x0008.11
1x9004.4
Limited auto negotiation support in 1G mode
In 1G mode, the device is specified to support basic auto negotiation for 1000BASE-X (optical interface)
only. For an SGMII interface employed in interfacing CuSFP, auto negotiation is not supported.
Otherwise, auto negotiation must be disabled on both the device and the CuSFP in order to have the
data link be established.
8.12
Limited 1G status reporting
In 1G mode, the 1G status signal from the 1G PCS block is driven by a sticky bit rather than a latched bit,
and so is useful only for link down (and not useful for link up conditions). Also, in 1000BASE-X mode, the
link up indicator does not include AN done status.
8.13
RXCKOUT squelching
RXCKOUT (positive and negative) can be squelched by varying link status (LOPC, PCS_Fault) in the
device through the use of the API.
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Ordering Information
9
Ordering Information
The VSC8489YJU-02 package is a lead-free (Pb-free), 196-pin, flip chip ball grid array (FCBGA) with a
15 mm × 15 mm body size, 1 mm pin pitch, and 1.4 mm maximum height.
Lead-free products from Microsemi comply with the temperatures and profiles defined in the joint IPC
and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
The following table lists the ordering information for the VSC8489-02 device.
Table 57 •
Ordering Information
Part Order Number
Description
VSC8489YJU-02
Lead-free, 196-pin FCBGA with a 15 mm × 15 mm body size, 1 mm pin
pitch, and 1.4 mm maximum height.
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