AD4632-24BBCZ

Data Sheet AD4630-24/AD4632-24 24-Bit, 2 MSPS/500 kSPS, Dual Channel SAR ADCs FEATURES ► FUNCTIONAL BLOCK DIAGRAM High performance Throughput: 2 MSPS (AD4630-24) or 500 kSPS (AD4632-24) per channel maximum ► INL: ±0.9 ppm maximum from −40°C to +125°C ► SNR: 105.7 dB typical ► THD: −127 dB typical ► NSD: −166 dBFS/Hz typical Low power ► 15 mW per channel at 2 MSPS ► 5 mW per channel at 500 kSPS ► 1.5 mW per channel at 10 kSPS Easy Drive features reduce system complexity ► Low 0.6 μA input current for dc inputs at 2 MSPS ► Wide input common-mode range: −(1/128) × VREF to +(129/128) × VREF Flexible external reference voltage range: 4.096 V to 5 V ► Accurate integrated reference buffer with 2 μF bypass capacitor Programmable block averaging filter with up to 216 decimation ► Extended sample resolution to 30 bits ► Overrange and synchronization bits Flexi-SPI digital interface ► 1, 2, or 4 SDO lanes per channel allows slower SCK ► Echo clock mode simplifies use of digital isolator ► Compatible with 1.2 V to 1.8 V logic 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint ► ► ► ► ► ► ► APPLICATIONS ► ► ► ► ► ► Automatic test equipment Digital control loops Medical instrumentation Seismology Semiconductor manufacturing Scientific instrumentation Figure 1. Functional Block Diagram GENERAL DESCRIPTION The AD4630-24/AD4632-24 are two-channel, simultaneous sampling, Easy Drive™, 2 MSPS or 500 kSPS successive approximation register (SAR) analog-to-digital converters (ADCs). With a guaranteed maximum ±0.9 ppm INL and no missing codes at 24 bits, the AD4630-24/AD4632-24 achieve unparalleled precision from −40°C to +125°C. Figure 1 shows the functional architecture of the AD4630-24/AD4632-24. A low drift, internal precision reference buffer eases voltage reference sharing with other system circuitry. The AD4630-24/ AD4632-24 offer a typical dynamic range of 106 dB when using a 5 V reference. The low noise floor enables signal chains requiring less gain and lower power. A block averaging filter with programmable decimation ratio can increase dynamic range up to 153 dB. The wide differential input and common-mode ranges allow inputs to use the full voltage reference (±VREF) range without saturating, simplifying signal conditioning requirements and system calibration. The improved settling of the Easy Drive analog inputs broadens the selection of analog front-end components compatible with the AD4630-24/AD4632-24. Both single-ended and differential signals are supported. The versatile Flexi-SPI serial peripheral interface (SPI) eases host processor and ADC integration. A wide data clocking window, multiple SDO lanes, and optional dual data rate (DDR) data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 MSPS or 500 kSPS. Echo clock mode and ADC host clock mode relax the timing requirements and simplify the use of digital isolators. The 64-ball chip scale package ball grid array (CSP_BGA) of the AD4630-24/AD4632-24 integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout. Rev. B DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet AD4630-24/AD4632-24 TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 Functional Block Diagram......................................1 General Description...............................................1 Specifications........................................................ 4 Timing Specifications......................................... 6 Absolute Maximum Ratings.................................12 Thermal Resistance......................................... 12 Electrostatic Discharge (ESD) Ratings.............12 ESD Caution.....................................................12 Pin Configuration and Function Descriptions...... 13 Typical Performance Characteristics................... 15 Terminology......................................................... 20 Theory of Operation.............................................21 Overview.......................................................... 21 Converter Operation.........................................21 Transfer Function............................................. 22 Analog Features............................................... 22 Digital Sample Processing Features................ 22 Applications Information...................................... 25 Typical Application Diagrams........................... 25 Analog Front-End Design................................. 26 Multiplexed Applications...................................26 Reference Circuitry Design ............................. 27 Device Reset.................................................... 28 Power Supplies................................................ 28 Serial Interface.................................................... 29 SPI Signals.......................................................29 Sample Conversion Timing and Data Transfer.......................................................... 32 Clocking Modes ...............................................33 Data Clocking Requirements and Timing.........36 Layout Guidelines................................................42 Registers............................................................. 43 Register Details................................................... 44 Interface Configuration A Register................... 44 Interface Configuration B Register................... 44 Device Configuration Register..........................45 Chip Type Register...........................................45 Product ID Low Register.................................. 45 Product ID High Register..................................46 Chip Grade Register.........................................46 Scratchpad Register.........................................46 SPI Revision Register...................................... 46 Vendor ID Low Register................................... 47 Vendor ID High Register...................................47 Stream Mode Register..................................... 47 Interface Configuration C Register................... 48 Interface Status A Register.............................. 48 Exit Configuration Mode Register.....................48 Averaging Mode Register.................................49 Channel 0 Offset Registers.............................. 49 Channel 1 Offset Registers.............................. 50 Channel 0 Gain Registers................................ 51 Channel 1 Gain Registers................................ 51 Modes Register................................................ 52 Internal Oscillator Register............................... 52 Output Driver Register......................................53 Test Pattern Registers...................................... 53 Digital Diagnostics Register............................. 54 Digital Errors Register...................................... 54 Outline Dimensions............................................. 55 Ordering Guide.................................................55 Evaluation Boards............................................ 55 REVISION HISTORY 5/2023—Rev. A to Rev. B Deleted Power Supply Rejection Ratio (PSRR) Section................................................................................20 Changes to Analog Features Section............................................................................................................ 22 Changes to Figure 44.................................................................................................................................... 25 Added Easy Drive Features Section.............................................................................................................. 26 Added Precharge Buffer Section................................................................................................................... 26 Change to Long Acquisition Phase Section...................................................................................................26 Changes to Driver Amplifier Choice Section..................................................................................................26 Added Figure 45; Renumbered Sequentially................................................................................................. 26 Added Multiplexed Applications Section and Figure 46.................................................................................26 Changes to Power Supplies Section..............................................................................................................28 Changes to Register Access Mode Section...................................................................................................29 Added Figure 52, Figure 53, and Figure 54................................................................................................... 30 Changes to Sample Conversion Timing and Data Transfer Section..............................................................32 analog.com Rev. B | 2 of 55 Data Sheet AD4630-24/AD4632-24 TABLE OF CONTENTS Added Figure 57............................................................................................................................................ 32 Changes to Basic and Averaging Conversion Cycles Section.......................................................................36 Added Figure 63, Figure 64, and Figure 65................................................................................................... 37 7/2022—Rev. 0 to Rev. A Added AD4632-24........................................................................................................................................... 1 Changes to Features Section and General Description Section......................................................................1 Changes to Table 1.......................................................................................................................................... 4 Changes to Table 2.......................................................................................................................................... 6 Changes to Table 7 Title, Figure 9 Title, and Figure 10 Title..........................................................................10 Change to Figure 25 Title...............................................................................................................................17 Added Figure 26; Renumbered Sequentially................................................................................................. 17 Change to Figure 30 Title and Figure 35 Title................................................................................................18 Added Figure 31............................................................................................................................................ 18 Added Figure 36............................................................................................................................................ 19 Changes to Overview Section........................................................................................................................21 Changes to Converter Operation Section...................................................................................................... 21 Changes to Serial Interface Section, SPI Signals Section, and Table 13...................................................... 29 Change to Sample Conversion Timing and Data Transfer Section............................................................... 32 Changes to Host Clock Mode Section, Figure 54 Title, Dual Data Rate Section, 1-Lane Output Data Clocking Mode Section, and 2-Lane Output Data Clocking Mode Section..................................................34 Changes to 4-Lane Output Data Clocking Mode Section, Interleaved Lane Output Data Clocking Mode Section, and Table 14.................................................................................................................................. 35 Change to Basic and Averaging Conversion Cycles Section........................................................................ 36 Changes to Host Clock Mode Timing Section Title, 1-Lane, Host Clock Mode, SDR Section, and 1Lane, Host Clock Mode, DDR Section.........................................................................................................41 Change to Table 43........................................................................................................................................52 Changes to Figure 60 and Figure 60 Title......................................................................................................55 Changes to Ordering Guide........................................................................................................................... 55 11/2021—Revision 0: Initial Version analog.com Rev. B | 3 of 55 Data Sheet AD4630-24/AD4632-24 SPECIFICATIONS VDD_5V = 5.4 V, VDD_1.8V = 1.8 V, VIO = 1.8 V, REFIN = 5 V, input common mode = 2.5 V, sampling frequency (fS) = 2 MSPS and 500 kSPS for the AD4630-24/AD4632-24, and all specifications TMIN to TMAX, unless otherwise noted. Typical values are at TA = 25°C. Table 1. Specifications Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Common-Mode Input Range Common-Mode Rejection Ratio (CMRR) Analog Input Current Analog Input Capacitance (CIN) Test Conditions/Comments Gain Error Temperature Drift Power Supply Sensitivity Low Frequency Noise2 AC ACCURACY Dynamic Range Noise Spectral Density (NSD) Total RMS Noise Signal to Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion (SINAD) Ratio Oversampled Dynamic Range analog.com Typ Max Unit 24 INx+ voltage (VINx+) − INx− voltage (VINx−) −(65/64) × VREF VINx+, VINx− to GND −(1/128) × VREF (VINx+ + VINx−)/2 −(1/128) × VREF Input frequency (fIN) = 10 kHz Acquisition phase, TA = 25°C Converting any dc input at 2 MSPS Acquisition phase Outside acquisition phase (pin capacitance (CPIN)) THROUGHPUT Complete Cycle AD4630-24 AD4632-24 Conversion Time Acquisition Phase1 AD4630-24 AD4632-24 Throughput Rate AD4630-24 AD4632-24 DC ACCURACY No Missing Codes Integral Nonlinearity (INL) Error Differential Nonlinearity (DNL) Error Transition Noise Zero Error Zero Error Drift Gain Error Min Bits +(65/64) × VREF +(129/128) × VREF +(129/128) × VREF 132 0.4 0.6 60 2 V V V dB nA µA pF pF 500 2000 264 282 300 ns ns ns 244 1744 260 1760 275 1775 ns ns 2 500 MSPS kSPS 0 0 24 −0.9 −90 Buffer disabled, REF = 5 V Buffer enabled, REFIN = 5 V Buffer disabled, REF = 5 V Buffer enabled, REFIN = 5 V VDD_5V = 5.4 V ± 0.1 V VDD_1.8V = 1.8 V ± 5% Bandwidth = 0.1 Hz to 10 Hz −0.004 −0.008 ±0.1 ±0.5 29.7 0 ±0.007 ±0.0002 ±0.0006 ±0.025 ±0.07 ±0.1 ±0.2 1.8 +0.9 +90 +0.004 +0.008 106 −166 fIN = 1 kHz, −0.5 dBFS fIN = 1 kHz, −0.5 dBFS fIN = 1 kHz, −0.5 dBFS fIN = 1 kHz, −0.5 dBFS Averaging = 2 103.3 103.3 17.7 105.7 127 −127 105.7 109 −115 Bits ppm LSB LSB rms μV ppm/°C %FS %FS ppm/°C ppm/°C ppm ppm µV p-p dB dBFS/H z µV rms dB dB dB dB dB Rev. B | 4 of 55 Data Sheet AD4630-24/AD4632-24 SPECIFICATIONS Table 1. Specifications (Continued) Parameter SNR SFDR THD SINAD SNR THD SINAD −3 dB Input Bandwidth Aperture Delay Aperture Jitter CHANNEL-TO-CHANNEL CROSSTALK INTERNAL REFERENCE BUFFER REFIN Voltage Range REFIN Bias Current REFIN Input Capacitance Reference Buffer Offset Error Reference Buffer Offset Drift Power-On Settling Time EXTERNALLY OVERDRIVEN REFERENCE REF Voltage Range REF Current AD4630-24 AD4632-24 REF Input Capacitance DIGITAL INPUTS Logic Levels Input Voltage Low (VIL) Input Voltage High (VIH) Input Current Low (IIL) Input Current High (IIH) Input Pin Capacitance DIGITAL OUTPUTS Pipeline Delay Output Voltage Low (VOL) Output Voltage High (VOH) analog.com Test Conditions/Comments Min Averaging = 256 Averaging = 65536 VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V VDD_5V = 5.0 V, fIN = 1 kHz, −0.5 dBFS, REFIN = 4.096 V fIN = 100 kHz, −0.5 dBFS fIN = 100 kHz, −0.5 dBFS fIN = 100 kHz, −0.5 dBFS fIN = 1 kHz, 1.3 kHz External reference drives REFIN 5.3 V ≤ VDD_5V ≤ 5.5 V 4.8 V ≤ VDD_5V ≤ 5.25 V 4.75 V ≤ VDD_5V ≤ 5.25 V REFIN = 5 V, TA = 25°C REFIN = 4.5 V, TA = 25°C REFIN = 4.096 V, TA = 25°C External reference drives REF (REFIN = 0 V) 5.3 V ≤ VDD_5V ≤ 5.5 V 4.8 V ≤ VDD_5V ≤ 5.25 V 4.75 V ≤ VDD_5V ≤ 5.25 V 4.95 4.046 −50 −100 −100 4.95 4.046 fS = 2 MSPS fS = 500 kSPS Typ Max Unit 130 152.7 dB dB 104 dB 130 dB −130 dB 104 105.6 −113 104.9 74 0.7 1.4 −135 dB dB dB dB MHz ns ps rms dB 5 4.5 4.096 5 40 ±25 ±25 ±25 ±0.3 3 5 4.5 4.096 5.05 V V V nA pF µV μV µV µV/°C ms 4.146 +50 +100 +100 5.05 V V V 4.146 1.8 0.5 2 µA µA µF 1.14 V ≤ VIO ≤ 1.89 V −0.3 0.65 × VIO −10 −10 +0.35 × VIO VIO + 0.3 +10 +10 V V µA µA pF 0.25 × VIO V V 2 1.14 V ≤ VIO ≤ 1.89 V Sink current (ISINK) = 2 mA Source current (ISOURCE) = 2 mA Conversion results available immediately after completed conversion 0.75 × VIO Rev. B | 5 of 55 Data Sheet AD4630-24/AD4632-24 SPECIFICATIONS Table 1. Specifications (Continued) Parameter POWER SUPPLIES VDD_5V VDD_1.8V VIO3 Standby Current VDD_5V VDD_1.8V VIO Shutdown Current VDD_5V VDD_1.8V VIO Operating Current, AD4630-24 VDD_5V VDD_1.8V VIO Operating Current, AD4632-24 VDD_5V VDD_1.8V VIO Power Dissipation tRESET_DELAY tRESET_PW TEMPERATURE RANGE Specified Performance Test Conditions/Comments Min Typ Max Unit REF = 5 V REF = 4.5 V REF = 4.096 V 5.3 4.8 4.75 1.71 1.14 5.4 5 5 1.8 5.5 5.25 5.25 1.89 1.89 V V V V V Both channels active, 2 MSPS VDD_5V = 5.4 V VDD_1.8V = 1.8 V VIO = 1.8 V, 1-lane SDO Both channels active, 500 kSPS VDD_5V = 5.4 V VDD_1.8V = 1.8 V VIO = 1.8 V, 1-lane SDO Both channels active, 2 MSPS Both channels active, 500 kSPS After power-on, delay from VDD_5V and VDD_1.8V valid to RST assertion RST pulse width TMIN to TMAX −40 500 90 1.14 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO > 1.71 V VIO > 1.14 V CS Rising Edge to SDO High Impedance SDI Valid Setup Time to SCK Rising Edge SDI Valid Hold Time from SCK Rising Edge CS Falling Edge to First SCK Rising Edge VIO > 1.71 V VIO > 1.14 V Last SCK Edge to CS Rising Edge tCSPW tSCK 10 ns 11.6 12.3 5.2 5.2 2.1 ns ns ns ns ns analog.com tSCKL tSCKH tHSDO tDSDO tCSDIS tSSDI tHSDI tCSSCK tSCKCS Typ Max 9.4 11.8 9 Unit 1.5 1.5 ns ns ns ns ns 11.6 12.3 5.2 ns ns ns Rev. B | 7 of 55 Data Sheet AD4630-24/AD4632-24 SPECIFICATIONS Figure 3. Register Configuration Mode Write Timing Figure 4. Register Configuration Mode Read Timing Figure 5. Register Configuration Mode Command Timing Table 4. SPI Compatible Mode Timing Parameter Symbol SCK Period VIO > 1.71 V VIO > 1.14 V SCK Low Time VIO > 1.71 V VIO > 1.14 V SCK High Time VIO > 1.71 V VIO > 1.14 V SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO > 1.71 V VIO > 1.14 V CS Falling Edge to SDO Valid VIO > 1.71 V tSCK analog.com Min Typ Max Unit 9.8 12.3 ns ns 4.2 5.2 ns ns 4.2 5.2 1.4 ns ns ns tSCKL tSCKH tHSDO tDSDO 5.6 8.1 tCSEN 6.8 ns ns ns ns Rev. B | 8 of 55 Data Sheet AD4630-24/AD4632-24 SPECIFICATIONS Table 4. SPI Compatible Mode Timing (Continued) Parameter VIO > 1.14 V CS Falling Edge to First SCK Rising Edge VIO > 1.71 V VIO > 1.14 V Last SCK Edge to CS Rising Edge CS Rising Edge to SDO High Impedance CS Falling Edge to BUSY Rising Edge Symbol Min Typ Max Unit 9.3 ns tCSSCK tSCKCS tCSDIS tCSBUSY 9.8 12.3 4.2 9 6 ns ns ns ns ns Figure 6. SPI Clocking Mode 1-Lane SDR Timing Table 5. Echo Clock Mode Timing, SDR, 1-Lane Parameter Symbol SCK Period VIO > 1.71 V VIO > 1.14 V SCK Low Time, SCK High Time VIO > 1.71 V VIO > 1.14 V SCK Rising Edge to Data/SCKOUT Remains Valid SCK Rising Edge to Data/SCKOUT Valid Delay VIO > 1.71 V VIO > 1.14 V CS Falling Edge to First SCK Rising Edge VIO > 1.71 V VIO > 1.14 V Skew Between Data and SCKOUT Last SCK Edge to CS Rising Edge CS Rising Edge to SDO High Impedance tSCK analog.com Min Typ Max Unit 9.8 12.3 ns ns 4.2 5.2 1.1 ns ns ns tSCKL, tSCKH tHSDO tDSDO 5.6 8.1 ns ns +0.4 ns ns ns ns ns tCSSCK tSKEW tSCKCS tCSDIS 9.8 12.3 −0.4 4.2 0 9 Rev. B | 9 of 55 Data Sheet AD4630-24/AD4632-24 SPECIFICATIONS Figure 7. Echo Clock Mode Timing, SDR, 1-Lane Table 6. Echo Clock Mode Timing, DDR, 1-Lane Parameter Symbol Min SCK Period SCK Low Time, SCK High Time SCK Edge to Data/SCKOUT Remains Valid SCK Edge to Data/SCKOUT Valid Delay VIO > 1.71 V VIO > 1.14 V CS Falling Edge to First SCK Rising Edge Skew Between Data and SCKOUT Last SCK Edge to CS Rising Edge CS Rising Edge to SDO High Impedance tSCK tSCKL, tSCKH tHSDO tDSDO 12.3 5.2 1.1 Typ Max ns ns ns 6.2 8.7 tCSSCK tSKEW tSCKCS tCSDIS 12.3 −0.4 9 Unit 0 +0.4 9 ns ns ns ns ns ns Figure 8. Echo Clock Mode Timing, DDR, 1-Lane Table 7. Host Clock Mode Timing Parameter Symbol SCK Period OSC_DIV = No Divide OSC_DIV = Divide by 2 OSC_DIV = Divide by 4 SCK Low Time SCK High Time CS Falling Edge to First SCKOUT Rising Edge tSCKOUT analog.com tSCKOUTL tSCKOUTH tDSCKOUT Min Typ Max Unit 11.8 23.6 47.4 0.45 × tSCKOUT 0.45 × tSCKOUT 12.5 25 50 13.3 26.6 53.2 0.55 × tSCKOUT 0.55 × tSCKOUT ns ns ns ns ns Rev. B | 10 of 55 Data Sheet AD4630-24/AD4632-24 SPECIFICATIONS Table 7. Host Clock Mode Timing (Continued) Parameter VIO > 1.71 V VIO > 1.14 V Skew Between Data and SCKOUT Last SCKOUT Edge to CS Rising Edge CS Rising Edge to SDO High Impedance Symbol tSKEW tSCKOUTCS tCSDIS Min Typ Max Unit 10 10 −0.4 5.2 13.6 15 0 19 21 +0.4 ns ns ns ns ns 9 Figure 9. Host Clock Mode Timing, SDR, 1-Lane Figure 10. Host Clock Mode Timing, DDR, 1-Lane analog.com Rev. B | 11 of 55 Data Sheet AD4630-24/AD4632-24 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Absolute Maximum Ratings Parameter Analog Inputs IN1+, IN1−, IN0+, IN0−, REFIN to GND Supply Voltage VDD_5V, REF to GND VDD_1.8V, VIO to GND Digital Inputs to GND CNV to GND Digital Outputs to GND Storage Temperature Range Operating Junction Temperature Range Maximum Reflow (Package Body) Temperature Rating −0.3 V to VDD_5V + 0.3 V −0.3 V to +6.0 V −0.3 V to +2.1 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −55°C to +150°C −40°C to +125°C 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 9. Thermal Resistance Package Type θJA θJC Unit 05-08-1797 35 16 °C/W ELECTROSTATIC DISCHARGE (ESD) RATINGS The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Field induced charged device model (FICDM) per ANSI/ESDA/JEDEC JS-002. ESD Ratings for AD4630-24/AD4632-24 Table 10. AD4630-24/AD4632-24, 64-Ball CSP_BGA ESD Model Withstand Threshold (kV) Class HBM FICDM 4 1.25 3A C3 ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. analog.com Rev. B | 12 of 55 Data Sheet AD4630-24/AD4632-24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 11. Pin Configuration Table 11. Pin Function Descriptions Pin No. Mnemonic Type1 Description A1, D1, E1, H1, B2, C2, F2, G2, H2, C3, F3, A4, B4, C4, D4, E4, F4, G4, H4, A5, B5, C5, D5, E5, F5, G5 A2 GND P Power Supply Ground. REFIN AI A3, B3 VDD_5V P A6 CNV DI A7 A8, B8 RST VIO DI P B1 B6, B7, C6, D6, E6, E7, F6, G6, H8 C1 C7 C8 D2, D3, E2, E3 IN0+ IOGND AI P Buffered Reference Input. When using the internal reference buffer, drive REFIN with 4.096 V to 5 V (referred to GND). To disable the reference buffer, tie REFIN to GND and drive REF with 4.096 V to 5 V. 5 V Power Supply. The range of VDD_5V depends on the reference value: 5.3 V to 5.5 V for a 5 V reference, and 4.75 V to 5.25 V for a 4.096 V reference. This pin has a 1 μF bypass capacitor inside the package. Convert Input. A rising edge on this input powers up the device and initiates a new conversion. This signal must have low jitter to achieve the specified performance of the ADC. The logic levels are determined by VIO. Reset Input (Active Low). Asynchronous device reset. Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 1.5 V, or 1.2 V). This pin has a 0.2 μF bypass capacitor inside the package. For VIO < 1.4 V, Bit IO2X of the output driver register must be set to 1. Channel 0 Positive Analog Input. VIO Ground. Connect to the same ground plane as GND. IN0− SDO3 SDO1 REF AI DO DO AI D7 D8 SDO2 SDO0 DO DO analog.com Channel 0 Negative Analog Input. Channel 0 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. Channel 0 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. Optional Unbuffered Reference Input. Drive REF with 4.096 V to 5 V (referred to GND). This pin has a 2 μF bypass capacitor inside the package. When using the internal reference buffer, do not connect REF. Channel 0 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. Channel 0 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. Rev. B | 13 of 55 Data Sheet AD4630-24/AD4632-24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 11. Pin Function Descriptions (Continued) Pin No. Mnemonic Type1 Description E8 BUSY/SCKOUT DO F1 F7 F8 G1 G3, H3 IN1+ SDO6 SDO4 IN1− VDD_1.8V AI DO DO AI P G7 G8 H5 H6 H7 SDO7 SDO5 CS SDI SCK DO DO DI DI DI BUSY Indicator in SPI Clocking Mode. This pin goes high at the start of a new conversion and returns low when the conversion finishes. The logic levels are determined by VIO. When SCKOUT is enabled, this pin function is either an echo of the incoming SCK from the host controller or a clock sourced by the internal oscillator. Channel 1 Positive Analog Input. Channel 1 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. Channel 1 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. Channel 1 Negative Analog Input. 1.8 V Power Supply. The range of VDD_1.8V is 1.71 V to 1.89 V. This pin has a 1 μF bypass capacitor inside the package. Channel 1 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. Channel 1 Serial Data Output. The conversion result outputs on this pin. It is synchronized to SCK. Chip Select Input (Active Low). Serial Data Input. Serial Data Clock Input. When the device is selected (CS = low), the conversion result is shifted out by this clock. 1 AI is analog input, P is power, DI is digital input, and DO is digital output. analog.com Rev. B | 14 of 55 Data Sheet AD4630-24/AD4632-24 TYPICAL PERFORMANCE CHARACTERISTICS VDD_5V = 5.4 V, VDD_1.8V = 1.8 V, VIO = 1.8 V, REFIN = 5 V, input common mode = 2.5 V, fS = 2 MSPS, and all specifications TMIN to TMAX, unless otherwise noted. Typical values are at TA = 25°C. Figure 12. INL Error vs. Output Code, Differential Input Figure 13. INL Error vs. Output Code, Single-Ended Input Figure 14. Code Histogram for Shorted Inputs analog.com Figure 15. FFT, 2 MSPS, fIN = 1 kHz, VREF = 5 V Figure 16. SNR and SINAD vs. Input Frequency Figure 17. THD vs. Input Frequency and Amplitude Rev. B | 15 of 55 Data Sheet AD4630-24/AD4632-24 TYPICAL PERFORMANCE CHARACTERISTICS Figure 18. SNR and SINAD vs. Input Amplitude, fIN = 1 kHz Figure 21. INL vs. Temperature Figure 19. SNR and SINAD vs. Temperature, fIN = 1 kHz Figure 22. Zero Error and Gain Error vs. Temperature Figure 20. THD vs. Temperature, fIN = 1 kHz Figure 23. Dynamic Range vs. Number of Averages analog.com Rev. B | 16 of 55 Data Sheet AD4630-24/AD4632-24 TYPICAL PERFORMANCE CHARACTERISTICS Figure 24. Low Frequency Noise (Output Data Rate = 19.5 SPS After Averaging Blocks of 2048 Samples) Figure 27. Reference Buffer Offset Voltage vs. Temperature Figure 28. Error During Conversion Burst After Long Idle Time Figure 25. Analog Input Current vs. Differential Input, AD4630-24, 2 MSPS Figure 26. Analog Input Current vs. Differential Input, AD4632-24, 500 kSPS analog.com Figure 29. REFIN Current Normal Operation and REFIN Current Shutdown Mode vs. Temperature Rev. B | 17 of 55 Data Sheet AD4630-24/AD4632-24 TYPICAL PERFORMANCE CHARACTERISTICS Figure 30. REF Current vs. Analog Input, AD4630-24, 2 MSPS Figure 33. REF Current vs. Temperature Figure 31. REF Current vs. Analog Input, AD4632-24, 500 kSPS Figure 34. Supply Current vs. Sample Rate Figure 32. CMRR vs. Input Frequency Figure 35. Supply Current vs. Temperature, AD4630-24, 2 MSPS analog.com Rev. B | 18 of 55 Data Sheet AD4630-24/AD4632-24 TYPICAL PERFORMANCE CHARACTERISTICS Figure 36. Supply Current vs. Temperature, AD4632-24, 500 kSPS Figure 38. Supply Shutdown Current vs. Temperature Figure 37. Supply Standby Current vs. Temperature analog.com Rev. B | 19 of 55 Data Sheet AD4630-24/AD4632-24 TERMINOLOGY Integral Nonlinearity (INL) Error Dynamic Range (DR) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 40). Dynamic range is the rms voltage of a full-scale sine wave to the total rms voltage of the noise measured. The value for dynamic range is expressed in decibels. Dynamic range is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Differential Nonlinearity (DNL) Error Signal-to-Noise Ratio (SNR) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. DNL is often specified in terms of resolution for which no missing codes are guaranteed. SNR is the ratio of the rms voltage of a full-scale sine wave to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Zero Error (ZE) Signal-to-Noise-and-Distortion (SINAD) Ratio Zero error is the difference between the ideal midscale voltage, 0 V, and the actual voltage producing the midscale output code, 0 LSB. SINAD is the ratio of the rms voltage of a full-scale sine wave to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Gain Error (GE) The first transition (from 100 ... 00 to 100 ... 01) occurs at a level ½ LSB above nominal negative full scale. The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of a full-scale input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. ENOB is related to SINAD as follows: ENOB = (SINAD dB − 1.76)/ 6.02. ENOB is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. analog.com Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 4.5 V p-p sine wave applied to the input common-mode voltage of frequency, f. CMRR dB = 10 × log PADC_IN /PADC_OUT where: PADC_IN is the common-mode power at the frequency, f, applied to the inputs. PADC_OUT is the power at the frequency, f, in the ADC output. Rev. B | 20 of 55 Data Sheet AD4630-24/AD4632-24 THEORY OF OPERATION Figure 39 shows the basic functions of the AD4630-24/AD4632-24. Figure 39. Functional Block Diagram and Channel Architecture OVERVIEW The AD4630-24/AD4632-24 are low noise, low power, high speed, dual 24-bit SAR ADCs. The AD4630-24 is capable of converting 2,000,000 samples per second (2 MSPS), and the AD4632-24 is capable of converting 500,000 samples per second (500 kSPS). The AD4630-24/AD4632-24 offer several analog and digital features to ease system design. The analog features include a wide common-mode range, which eases level shifting requirements, as well as an extended fully differential input range of ±(65/64) × VREF, which eases the margin requirements on signal conditioning. The AD4630-24/AD4632-24 have an integrated reference buffer with an integrated decoupling capacitor to minimize the external components on board. The on-chip track-and-hold circuitry does not exhibit any pipeline delay or latency, making this circuitry ideal for control loops and high speed applications. The digital features include offset correction, gain adjustment, and averaging, which offload the host processor. The user can configure the device for one of several output code formats (see the Summary of Selectable Output Data Formats section). The AD4630-24/AD4632-24 uses a Flexi-SPI, allowing the data to be accessed via multiple SPI lanes, which relaxes clocking requirements for the host SPI controller. An echo clock mode is analog.com also available to assist in data clocking, simplifying the use of isolated data interfaces. The AD4630-24/AD4632-24 have a valid first conversion after exiting power-down mode. The architecture achieves ±0.9 ppm INL maximum, with no missing codes at 24 bits and 105.7 dB SNR. The AD4630-24 dissipates only 15 mW per channel at 2 MSPS. CONVERTER OPERATION The AD4630-24/AD4632-24 operate in two phases: acquisition phase and conversion phase. In the acquisition phase, the internal track-and-hold circuitry is connected to each input pin (INx+, INx−) and samples the voltage on each pin independently. Issuing a rising edge pulse on the CNV pin initiates a conversion. The rising edge pulse on the CNV pin also asserts the BUSY signal to indicate a conversion in progress. At the end of conversion, the BUSY signal deasserts. The conversion result is a 24-bit code or a 16-bit code representing the input voltage difference and an 8-bit code representing the input common-mode voltage. Depending on the device configuration, this conversion result can be processed digitally and latched into the output register. The acquisition circuit on each input pin is also precharged to the previous sample voltage, which minimizes the kickback charge to the input driver. The host Rev. B | 21 of 55 Data Sheet AD4630-24/AD4632-24 THEORY OF OPERATION processor retrieves the output code via the SDOx pins that are internally connected to the output register. TRANSFER FUNCTION In the default configuration, the AD4630-24/AD4632-24 digitize the full-scale difference voltage of 2 × VREF into 224 levels, resulting in an LSB size of 0.596 µV with VREF = 5 V. Note that 1 LSB at 24 bits is approximately 0.06 ppm. The ideal transfer function is shown in Figure 40. The differential output data is in twos complement format. Table 12 summarizes the mapping of input voltages to differential output codes. Figure 41. Equivalent Circuit for the AD4630-24/AD4632-24 Differential Analog Input Each input is sampled independently. The conversion results do not saturate, assuming each input is within the specified full-scale input range. Note that digital domain saturation does occur if the digital offset and digital gain parameters are configured to map the conversion result to numeral values that exceed the full-scale digital range (−223 to +223− 1 for the 24-bit word). An input voltage difference up to ±(65/64) × VREF can be captured and converted without saturation by setting the digital gain parameter to a value < 1. Figure 40. ADC Ideal Transfer Function for the Differential Output Codes (FSR Is Full-Scale Range) Table 12. Input Voltage to Output Code Mapping Description Analog Input Voltage Difference Digital Output Code (Twos Complement, Hex) FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR (8388607 × VREF)/(8388608) VREF/(8388608) 0V −VREF/(8388608) −(8388607 × VREF)/(8388608) −VREF 0x7FFFFF 0x000001 0x000000 0xFFFFFF 0x800001 0x800000 ANALOG FEATURES The common-mode voltage is not restricted except by the absolute voltage range for each input (from −1/128 × VREF to 129/128 × VREF). The analog inputs can be modeled by the equivalent circuit shown in Figure 41. In the acquisition phase, each input sees approximately 58 pF (CIN) from the sampling capacitor in series with 37 Ω on resistance (RON) of the sampling switch. During the conversion phase, each input sees CPIN, which is about 2 pF. Any signal that is common to both inputs is reduced by the common-mode rejection of the ADC. During the conversion, the analog inputs draw only a small leakage current. analog.com The slew rate at the analog input pins must be less than 400 V/µs during the acquisition phase and less than 30 V/µs at the sampling moment to ensure good performance. This rate can be ensured by choosing values for the external RC circuit such that the RC time constant is more than 12.5 ns (R × C > 12.5e-9). DIGITAL SAMPLE PROCESSING FEATURES The AD4630-24/AD4632-24 support several digital and data processing features that can be applied to the signal samples. These features are enabled and disabled via the control registers of the AD4630-24/AD4632-24. Figure 39 contains an ADC channel architecture block diagram showing the digital and data processing features available for each input channel. Full-Scale Saturation The conversion results saturate digitally (before any postprocessing) when either or both inputs exceed the specified analog limits. After applying offset and gain scaling, the results are truncated to 24-bit representation (saturating at maximum 0x7FFFFF and minimum 0x800000). Take care to avoid unintentional saturation, especially when applying digital offset and/or gain scaling. See the Digital Offset Adjust and Digital Gain sections for more details on the use of these features. Rev. B | 22 of 55 Data Sheet AD4630-24/AD4632-24 THEORY OF OPERATION Common-Mode Output Digital Offset Adjust When the host controller writes 0x1 or 0x2 to the OUT_DATA_MD bit field of the modes register (see the Modes Register section), an 8-bit code representing the input common-mode voltage is appended to the 16-bit or 24-bit code representing the input voltage difference. The LSB size of the 8-bit code is VREF/256. The 8-bit code saturates at 0 and 255 when the common-mode input voltage is 0 V and VREF, respectively. The 8-bit code is not affected by digital offset and gain scaling, which is applied only to the code representing the input voltage difference. Each ADC channel can be independently programmed to add a 24-bit signed offset value to the sample data (see the Register Details section). When adding an offset to the samples, it is possible to cause the sample data to saturate numerically. Take this into account when using the offset feature. The default value is 0x000000. See the Channel 0 Offset Registers section or Channel 1 Offset Registers section in the AD4630-24/AD4632-24 register map for more details. Block Averaging The AD4630-24/AD4632-24 provides a block averaging filter (SINC1) with programmable block length 2N, where N = 1, 2, 3, …, 16. The filter is reset after processing each block of 2N samples. The filter is enabled by writing 0x3 to the OUT_DATA_MD bit field of the modes register (see the Modes Register section) as well as a value (1 ≤ N ≤ 16) to the AVG_VAL bit field in the averaging mode register (see the Averaging Mode Register section). In this configuration, the output sample word is 32 bits. The 30 MSBs represent the numerical value of the 24-bit codes averaged in blocks of 2N samples. The 24 MSBs of the 30-bit code are equal to the 24-bit codes when averaging blocks of constant values. The 31st bit (OR) is an overrange warning bit, which is high when one or more samples in the block are subject to saturation. The 32nd bit (SYNC) is high once every 2N conversion cycles to indicate when the average values are updated at the end of each block of samples. See the Summary of Selectable Output Data Formats section for the data format when the filter is enabled. The effective data rate in averaging mode is CNV frequency (fCNV)/2N. The reset value of N in the AVG_VAL bit field is 0x00 (no averaging). Figure 62 shows an example timing diagram in averaging mode. Figure 42 shows the frequency response of the filter for N = 1, 2, 3, 4, and 5. Digital Gain Each ADC channel can be programmed independently to apply a 16-bit unsigned digital gain (CHx_USER_GAIN) to the digital samples (see the Register Details section). The gain is applied to each sample based on the following equation: CodeOUT = CodeIN × (CHx_USER_GAIN/0x8000) where 0x0000 ≤ CHx_USER_GAIN ≤ 0xFFFF. The effective gain range is 0 to 1.99997. Note that applying gain to the samples can cause numerical saturation. The default value is 0x8000 (gain = 1). To measure input voltage differences exceeding ±VREF, set the gain below unity to avoid the numerical saturation of the 24-bit/16-bit/30-bit output differential codes. See the Channel 0 Gain Registers section or Channel 1 Gain Registers section in the AD4630-24/AD4632-24 register map for more details. Test Pattern To facilitate functional testing and debugging of the SPI, the host controller can write a 32-bit test pattern to the AD4630-24/ AD4632-24 (see the Test Pattern Registers section). The value written to the test pattern registers applies to both ADC channels, and is output using the normal sample cycle timing on each channel. The 32-bit test pattern output mode is enabled by writing 0x4 to the OUT_DATA_MD bit field of the modes register (see the Modes Register section). The default value stored in the test pattern registers is 0x5A5A0F0F. Figure 42. Frequency Response Examples for the Block Averaging Filter analog.com Rev. B | 23 of 55 Data Sheet AD4630-24/AD4632-24 THEORY OF OPERATION Summary of Selectable Output Data Formats Figure 43 summarizes the output data formats that are available on the AD4630-24/AD4632-24, which are selected in the modes register (see the Modes Register section). Note that the selected mode is applied to both channels. The OR and SYNC flags are each 1 bit. Figure 43. Summary of Selectable Output Sample Formats analog.com Rev. B | 24 of 55 Data Sheet AD4630-24/AD4632-24 APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS Figure 44. Typical Application Circuit Diagrams analog.com Rev. B | 25 of 55 Data Sheet AD4630-24/AD4632-24 APPLICATIONS INFORMATION where: f–3 dB is the input bandwidth, in hertz, of the AD4630-24 (74 MHz) or the cutoff frequency of the input filter, if one is used (see Figure 45). N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the operational amplifier, in V/√Hz. ANALOG FRONT-END DESIGN Easy Drive Features A combination of a long acquisition phase and a precharging circuit of the AD4630-24/AD4632-24 family lessens the design challenges associated with the ADC driver stage and increases the flexibility in ADC driver selection. The AD4630-24/AD4632-24 uniquely combine high performance with ease of use features that enable ease of drive, lower overall system power, simplified signal chain bill of materials (BOM), reduced performance sensitivity to external circuitry, and shorter design cycles. Precharge Buffer The AD4630-24/AD4632-24 have a precharging circuit as a part of the internal track-and-hold circuitry, which charges the internal sampling capacitors to the previously sampled input voltage. This circuit reduces the charge kickback, making it easier to drive than other conventional SAR ADCs. The reduced kickback, combined with a longer acquisition phase, reduces settling requirements on the driving amplifier. This combination also allows the use of larger resistor values, which are beneficial for improving amplifier stability. Furthermore, the bandwidth of the RC filter is reduced, resulting in lower noise and/or power consumption of the signal chain. Long Acquisition Phase The AD4630-24/AD4632-24 also feature a fast conversion time that results in a long acquisition phase. A long acquisition phase reduces the settling requirement on the driving amplifier, and a lower power and lower bandwidth amplifier can be chosen. The longer acquisition phase means that a lower RC input filter cutoff can be used, which means a noisier amplifier can also be tolerated. A larger value of R can be used in the RC filter with a corresponding smaller value of C, reducing amplifier stability concerns without affecting distortion performance significantly. A larger value of R also results in reduced dynamic power dissipation in the amplifier. Driver Amplifier Choice Although the AD4630-24/AD4632-24 use easy to drive technology, which broadens the range of companion circuitry that is capable of driving this ADC, the driver amplifier must meet the following requirements: ► The noise generated by the driver amplifier must be kept low enough to preserve the SNR and transition noise performance of the AD4630-24/AD4632-24. The noise from the driver is filtered by the single-pole, low-pass filter of the analog input circuit made by RON and CIN, or by the external filter, if one is used. Because the typical noise of the AD4630-24/AD4632-24 is 17.7 μVrms, the SNR degradation due to the amplifier is the following: SNRLOSS = 20 × log10 analog.com 17 . 7 × 10‐6V 2 π 2 ‐6 17 . 7 × 10 V + × f−3 dB N × eN 2 (1) Figure 45. External Filter Example For AC applications, the driver must have a THD performance commensurate with the AD4630-24/AD4632-24. ► For multichannel multiplexed applications, the driver amplifier and the analog input circuit of the AD4630-24/AD4632-24 must settle for a full-scale step onto the capacitor array at a 24-bit level. In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. Settling at 0.1% to 0.01% may differ significantly from the settling time at a 24-bit level and must be verified prior to driver selection. ► Figure 44 shows two examples for driving the AD4630-24/ AD4632-24. Either amplifier can be combined with an upstream stage that provides additional signal conditioning. Both amplifiers can accommodate single-ended or differential inputs. To take advantage of the excellent SNR and THD performance of the AD4630-24/AD4632-24, choose a driver amplifier that has low noise and THD sufficient to meet the application requirements. In addition to the amplifiers shown in Figure 44, the LTC6227 is another driver option. Analog Devices, Inc., offers several companion driver amplifiers that can be found on the Differential Amplifiers and ADC Drivers web page. The Precision ADC Driver Tool can be used to model the settling behavior and estimate the ac performance of the AD4630-24 with a selected driver amplifier and RC filter. Once the Precision ADC Driver Tool has modeled a specific circuit, the circuit can be exported for simulation in LTspice. MULTIPLEXED APPLICATIONS The AD4630-24/AD4632-24 significantly reduce system complexity for multiplexed applications that require superior performance in terms of noise, power, and throughput. Figure 46 shows a simplified block diagram of a multiplexed data acquisition system including a multiplexer, an ADC driver, and a precision SAR ADC. Switching multiplexer channels typically results in large voltage steps at the ADC inputs. To ensure an accurate conversion result, the step must be given adequate time to settle before the ADC samples its inputs (on the rising edge of CNV). The settling time Rev. B | 26 of 55 Data Sheet AD4630-24/AD4632-24 APPLICATIONS INFORMATION error is dependent on the drive circuitry (multiplexer and ADC driver), RC filter values, and the time when the multiplexer channels are switched. Switch the multiplexer channels just after the conversion phase has elapsed to maximize settling time and to prevent corruption of the conversion result. To avoid conversion corruption, do not switch the channels during conversion time (BUSY high) and quiet time (tQUIET_CNV_AVD). If the analog inputs are multiplexed during conversion time or quiet time, the current conversion is possibly corrupted. ADCs to share a common reference. An RC circuit between the reference and REFIN can be used to filter reference noise (see Figure 47). The suggested values are 100 Ω < R < 1 kΩ, and C ≥ 10 μF. Figure 47. Reference with Noise Filter Figure 46. Multiplexed Data Acquisition Signal Using the AD4630-24/ AD4632-24 REFERENCE CIRCUITRY DESIGN The AD4630-24/AD4632-24 require an external reference to define the input range. This reference must be 4.096 V to 5 V. An optimal choice for the reference is the ADR4550 or ADR4540. The ADC has several features that reduce the charge pulled from the reference, making the AD4630-24/AD4632-24 easier to use than other ADCs. For most applications, the reference can drive the REFIN pin, which has an internal precision buffer that isolates the reference from the ADC circuitry. The buffer has a high input impedance and small input current (5 nA typical) that allows multiple For the best possible gain error, the internal buffer can be disabled (REFIN = 0 V) and an external reference used to drive the REF pin. The current drawn by the REF pin is small ( 1.71 V, and 81 MHz for 1.14 V ≤ VIO < 1.71 V. ► analog.com The AD4630-24/AD4632-24 offer programmable user registers to configure the device as outlined in the Registers section. By default, at power-up, the device is in conversion mode. Therefore, to access the user registers, a special access command must be sent by the host controller over the SPI, as shown in Figure 52. When this register access command is sent over the SPI, the device enters the register configuration mode. To read back the values from one of the user registers listed in the Registers section, the host controller must send the pattern shown in Figure 53. To write to one of the user registers, the host controller must send the pattern shown in Figure 54. In either case (read/write), the host controller must always issue 24 clock pulses on the SCK line and pull CS low for the entire transaction. After writing to or reading from the appropriate user registers, the host controller must exit the register configuration mode by writing 0x01 to Register Address 0x0014 as detailed in the exit configuration mode register. An algorithm for register read/write access is as follows: 1. Perform a readback from dummy Register Address 0x3FFF to enter the register configuration mode. 2. Readback from or write to the desired user register addresses. 3. Exit the register configuration mode by writing 0x01 to Register Address 0x0014. Exiting register configuration mode causes the register updates to take effect. Rev. B | 29 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE Figure 52. Register Configuration Mode Command Figure 53. Register Configuration Mode Read Figure 54. Register Configuration Mode Write analog.com Rev. B | 30 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE Stream Mode The AD4630-24/AD4632-24 also offer a way to perform bulk register read/write transactions while the AD4630-24/AD4632-24 is in register configuration mode. To perform bulk read/write registers transactions, keep CS low and issue SCK pulses in multiples of 8 because each register is only one byte (8 bits) wide. In stream mode, only address decrementing is allowed, meaning that the user can read back from or write to the initial register address and register addresses that are directly below the initial register address. Apply register accesses in stream mode to register blocks with contiguous addresses. However, it is possible to address registers that are not present in the register map. To do so, write all zeros to these registers, or, when reading back, discard the contents read from these registers because it is random data. See the Registers section to see which register address is valid and continuous. For example, to read back a 24-bit offset value in one shot, the user must issue 24 SCK pulses staring from Register Address 0x0018. Figure 55 shows the timing diagram for a bulk read starting at a given address. Figure 55. Stream Mode Bulk Register Read Back Operation analog.com Rev. B | 31 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE SAMPLE CONVERSION TIMING AND DATA TRANSFER A conversion starts on the rising edge of the CNV signal, as shown in Figure 56. Once the conversion completes, CS can be asserted, which causes the current conversion result to load into the output shift register. Referring to Figure 56, there are two optional data transfer zones for Sample N. Zone 1 represents the use case where CS is asserted immediately following the deassertion of the BUSY signal for the Sample N conversion (in SPI conversion mode), or after 300 ns for echo and host clock modes. For Zone 1, the available time to read out Sample N is given by: Zone 1 Data Read Window = tCYC − tCONV − tQUIET_CNV_ADV For example, if fCNV is 2 MSPS (tCYC = 500 ns) and the typical value of tCONV (282 ns) is used, the available window width is 198.4 ns (500 ns – 282 ns – 19.6 ns). Zone 2 represents the case where an assertion of CS to read Sample N is delayed until after the conversion for Sample N + 1 initiates. To prevent data corruption, a quiet zone must be observed before and after each rising edge of the CNV signal, as shown in Figure 56 and Figure 57. The quiet zone immediately before the rising edge of CNV is labeled as tQUIET_CNV_ADV, and is equal to 19.6 ns. The quiet zone immediately after the rising edge of CNV is labeled tQUIET_CNV_DELAY, and is equal to 9.8 ns. Assuming that the CS asserts immediately after the quiet zone around the rising edge of CNV, the amount of time available to clock out the data is: Zone 2 Data Read Window = tCYC − tQUIET_CNV_DELAY − tQUIET_CNV_ADV For example, if fCNV is 2 MSPS (tCYC = 500 ns) and the typical value of tCONV (282 ns) is used, the available window width is 470.6 ns (500 ns – 9.8 ns – 19.6 ns). The Zone 2 transfer window is longer than the Zone 1 window, which can enable the use of a slower SCK on the SPI and ease the timing requirements for the interface. When using Zone 2 for the data transfer, assert CS immediately after the quiet zone. CS must be asserted at least 25 ns before the falling edge of BUSY for Sample N + 1. If not, Sample N is overwritten with Sample N + 1. Figure 56. Example Timing for Data Transfer Zones Figure 57. Quiet Zones analog.com Rev. B | 32 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE CLOCKING MODES This section covers the various clocking modes supported by the AD4630-24/AD4632-24 SPI. These modes are available for 1-lane, 2-lane, 4-lane, and interleaved configurations. The clocking mode is configured in the modes register (see Table 16 for register descriptions). Note that the selected clocking mode applies to both ADC channels. The channels cannot be configured independently. SPI Clocking Mode SPI clocking mode is the default clocking mode of the AD4630-24/ AD4632-24 and is equivalent to a host sourced bit clock (SCK), in which the host controller uses its own clock to latch the output data. The SPI compatible clocking mode is enabled by writing 0x0 to the CLK_MD bit field of the modes register (see the Modes Register section). The interface connection is as shown in Figure 51. In this mode, the BUSY signal is valid and indicates the completion of a conversion (high to low transition of BUSY). A simplified sample cycle is shown in Figure 58. When not in averaging mode, if the host controller does not use the BUSY signal to detect the completion of a conversion, and instead uses an internal timer to retrieve the data, the host controller must wait at least 300 ns after the rising edge of the CNV pulse before asserting CS low. When operating in block averaging mode, the host controller must assert CS low no sooner than 300 ns after the rising edge of the CNV pulse for the last sample in the block. Figure 58. Typical Sample Cycle for SPI Clocking Mode analog.com Rev. B | 33 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE Echo Clock Mode Figure 59 shows the signal connections for the echo clock mode. Echo clock mode is enabled by writing 0x1 to the CLK_MD bit field of the modes register (see the Modes Register section). In this mode, the BUSY/SCKOUT pin cannot be used to detect a conversion completion. The BUSY/SCKOUT pin becomes a bit clock output and is sourced by looping through the SCK of the host controller to the BUSY/SCKOUT pin (with some fixed delay, 5.4 ns to 7.9 ns, depending on VIO). To begin retrieving the conversion data in nonaveraging mode, the host controller must assert CS low no sooner than 300 ns after the rising edge of the CNV pulse. When the ADC is configured for block averaging mode, the host controller must assert CS low no sooner than 300 ns after the rising edge of the CNV pulse for the last sample in the block. Example timing diagrams are shown in the Data Clocking Requirements and Timing section. When echo clock mode is enabled, SCKOUT is aligned with SDOx transitions, making the data and clock timing insensitive to asymmetric propagation delays in the SDOx and SCK paths. Figure 60. Host Clock Mode Signal Path Example Single Data Rate Single data rate (SDR) clocking in which one bit (per active lane) is clocked out during a single clock cycle, is supported for all output configurations and sample formats (see Table 14). The SDR clocking mode is enabled by default at power-up or can be enabled by writing 0 to the DDR_MD bit of the modes register (see the Modes Register section). Dual Data Rate DDR mode (two data bit transitions per clock cycle per active lane) is available only for host clock mode and echo clock mode. Note that the selected data rate mode is applied to both ADC channels. DDR clocking mode is enabled by writing 1 to the DDR_MD bit of the modes register (see the Modes Register section). DDR mode uses half the number of SCK pulses to clock out conversion data in comparison to SDR mode. Figure 59. Echo Clock Mode Signal Path Diagram Host Clock Mode When enabled, host clock mode uses the internal oscillator as the bit clock source. The host clock mode is enabled by writing 0x2 to the CLK_MD bit field of the modes register. The bit clock frequency can be programmed in the OSC_DIV bit field in the internal oscillator register, with available divisor values of 1, 2, or 4 (see the Internal Oscillator Register section). Figure 60 shows the signal connections for the host clock mode. In this mode, the BUSY/ SCKOUT pin provides the bit clock output and cannot be used to detect a conversion completion. The AD4630-24/AD4632-24 automatically calculate the number of clock pulses required to clock out the conversion data based on word size, number of active lanes, and choice of single data rate or DDR mode. The number of clock pulses can be read from the OSC_LIMIT bit field of the internal oscillator register. The SCK from the host must not be active. When retrieving the conversion data in nonaveraging mode, the host must not assert CS low sooner than 300 ns after the rising edge of the CNV pulse. When the ADC is configured in averaging mode for 2N averages, the host must not assert CS low sooner than 300 ns after the rising edge of CNV pulse for the last sample in the block. analog.com 1-Lane Output Data Clocking Mode 1-lane output data clocking mode is the default output data clocking mode at power-up. 1-lane output data clocking mode is enabled by writing 0x0 to the LANE_MD bit of the modes register (see the Modes Register section). The active lane for ADC Channel 0 is SDO0. The active lane for ADC Channel 1 is SDO4. Example timing diagrams for 1-lane output data clocking mode using SPI clocking mode, echo clock mode, and host clock mode are shown in the Data Clocking Requirements and Timing section. 2-Lane Output Data Clocking Mode When 2-lane output data clocking mode is enabled, the sample word bits are split between two SDO lanes. Figure 66 shows how the bits are allocated between the lanes for 2-lane output data clocking mode. The bit arrangement is the same for SPI clocking mode, echo clock mode, and host clock mode. 2-lane output data clocking mode is enabled by writing 0x1 to the LANE_MD bit of the modes register (see the Modes Register section). The host controller must recombine the data coming from the SDO lanes to reconstruct the original sample word. The number of SCK pulses required to clock out the conversion data is reduced by one half with respect to 1-lane output data clocking mode. Table 14 lists the active SDO lanes for 2-lane output data clocking mode. Example Rev. B | 34 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE timing diagrams for 2-lane output data clocking mode using SPI clocking mode, echo clock mode, and host clock mode are shown in the Data Clocking Requirements and Timing section. 4-Lane Output Data Clocking Mode When 4-lane output data clocking mode is enabled, the sample word bits are split between four SDO lanes. Figure 67 shows how the bits are allocated between the lanes for 4-lane mode. The bit arrangement is the same for SPI clocking mode, echo clock mode, and host clock mode. 4-lane output data clocking mode is enabled by writing 0x2 to the LANE_MD bit of the modes register (see the Modes Register section). The host controller must recombine the data coming from the SDO lanes to reconstruct the original sample word. The number of SCK pulses required to clock out the conversion data is reduced by one fourth with respect to 1-lane output data clocking mode. The active SDO lanes for 4-lane output data clocking mode are shown in Table 14. Example timing diagrams for 4-lane output data clocking mode using SPI clocking mode, echo clock mode, and host clock mode are shown in the Data Clocking Requirements and Timing section. rangement is shown in Figure 68. The bit arrangement is the same for SPI clocking mode, echo clock mode, and host clock mode. Interleaved lane output data clocking mode is enabled by writing 0x3 to the LANE_MD bit of the modes register (see the Modes Register section). The host controller must demultiplex the data on SDO0 to reconstruct the original sample words. The number of SCK pulses required to clock out the conversion data is increased by 2× with respect to 1-lane output data clocking mode. The data transfer can occur in either Zone 1 or Zone 2 (see Figure 56). Using the interleaved lane output data clocking mode allows the host controller to use a single SDO lane to retrieve data from both ADC channels, reducing I/O requirements for the digital interface. Examples of interleaved lane mode timing are shown in the Data Clocking Requirements and Timing section. Data Output Modes Summary Table 14 is a summary of the supported data output modes of the AD4630-24/AD4632-24. Interleaved Lane Output Data Clocking Mode In interleaved lane output data clocking mode, the Channel 0 and Channel 1 conversion data is interleaved on SDO0. The bit arTable 14. Supported Data Output Modes Active SDO Lanes Number of Lanes (per Channel) Channel 0 Channel 1 Clock Mode Supported Data Clocking Mode Output Sample Data-Word Length 1 SDO0 SDO4 2 SDO0, SDO1 SDO4, SDO5 4 SDO0, SDO1, SDO2, SDO3 SDO4, SDO5, SDO6, SDO7 SPI Echo Host SPI Echo Host SPI Echo Host SPI Echo Host SDR only SDR and DDR SDR and DDR SDR only SDR and DDR SDR and DDR SDR only SDR and DDR SDR and DDR SDR only SDR and DDR SDR and DDR 24 or 32 24 or 32 24 or 32 24 or 32 24 or 32 24 or 32 24 or 32 24 or 32 24 or 32 48 or 64 48 or 64 48 or 64 Interleaved analog.com SDO0 Rev. B | 35 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE DATA CLOCKING REQUIREMENTS AND TIMING Basic and Averaging Conversion Cycles Figure 61 shows the basic conversion cycle for a single sample. This cycle applies to SPI clocking mode. When echo clock mode and host clock modes are used, the BUSY function is disabled and the bit clock is sourced on the BUSY pin. The data transfer must meet the requirements described in the Sample Conversion Timing and Data Transfer section. Table 15 contains the minimum and maximum values for the conversion timing parameters, which apply to all clocking modes. Parameter Minimum (ns) Maximum tCNVH tCNVL tCNV 10 20 264 No specific maximum No specific maximum 300 ns The duration of the data transfer period is dependent on the sample resolution, number of active lanes, SCK frequency, and data clocking mode (SDR or DDR). The nominal value of the transfer duration is given by: Data   Transfer   Function = tTRANS = 1 fSCK × 1 K   seconds For a given fSCK, number of data lanes, sample word size, and SDR or DDR mode, the minimum sample period when using Zone 1 for the data transfer is as follows: Minimum Zone 1 Sample Period: tCYC ≥ NBITS MLANES × fSCK × K + tCONV + tQUIET_CNV_ADV The minimum sample period when using Zone 2 for data transfer is as follows: Table 15. Conversion Cycle Timing Parameters × where: tTRANS is the transition time. NBITS = number of bits to clock out. MLANES = number of lanes used to clock out the data (1, 2, or 4). fSCK = SCK clock frequency in Hz. K = 1 (SDR only, DDR not available for SPI clocking mode). NBITS MLANES   tCYC ≥ NBITS MLANES × fSCK × K + tQUIET_CNV_ADV + tQUIET_CNV_DELAY Figure 62 shows a typical conversion cycle when the averaging mode is active and SPI clocking mode is used. The BUSY signal is asserted for a number of CNV clock periods that is equal to the configured number of samples to be averaged. The averaged sample is then available when the BUSY signal is deasserted. Like nonaveraged mode, if the configured clocking mode is either echo clock or host clock, the BUSY signal is replaced by the output bit clock (SCKOUT). The host controller must manage the timing for asserting CS. Figure 61. Basic Single Sample Conversion Cycle Figure 62. Example Conversion Cycle for Averaging Mode analog.com Rev. B | 36 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE The two transfer zones that exist in nonaveraging mode also exist in averaging mode (see Figure 63, Figure 64, and Figure 65). To prevent data corruption, it is necessary to avoid SPI rising and falling edges signals taking place during quiet zones. Figure 63. Example of Different Zones in Averaging Mode (64 Samples Averaged) Figure 64. Example of Zone 2 in Averaging Mode (1 Bit per Sample) Figure 65. Example of Zone 2 in Averaging Mode (N Bits per Cycle) analog.com Rev. B | 37 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE SPI Clocking Mode Timing Diagrams 2-Lane, SDR Mode 1-Lane, SDR Mode Figure 66 shows a conversion cycle for 2-lane data output using SDR clocking mode. Figure 66 shows the timing for Channel 0, but this diagram also applies to Channel 1. See the 2-Lane Output Data Clocking Mode section for a detailed explanation. Figure 6 shows a conversion cycle for 1-lane data output using SDR clocking mode (1-bit transitions per clock cycle). This cycle timing is the same for both ADC channels. Figure 66. 2-Lane Mode, SDR Timing Diagram analog.com Rev. B | 38 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE 4-Lane, SDR Mode Figure 67 shows a conversion cycle for 4-lane data output using SDR clocking mode. Figure 67 shows the timing for Channel 0, but this diagram also applies for Channel 1. See the 4-Lane Output Data Clocking Mode section for a detailed explanation. Figure 67. 4-Lane, SDR Timing Diagram analog.com Rev. B | 39 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE Interleaved Mode Timing, SDR Mode Figure 68 shows a conversion cycle for interleaved data output using SDR clocking mode. See the Interleaved-Lane Output Data Clocking Mode section for a detailed explanation. Figure 68. Interleaved Mode, SDR Timing Diagram analog.com Rev. B | 40 of 55 Data Sheet AD4630-24/AD4632-24 SERIAL INTERFACE Echo Clock Timing Diagrams Host Clock Mode Timing 1-Lane, SDR Mode, Echo Clock Mode 1-Lane, Host Clock Mode, SDR Figure 7 shows the timing relationships for SDR mode (1-bit transitions per SCK period) in 1-lane echo clock mode. The timing relationships between the signals apply to both 24-bit and 32-bit sample word formats. Figure 9 shows the timing relationships for host clock mode when using SDR mode and 1-lane output data clocking mode. Similar to echo clock mode, the clock rising edges are aligned to the data bit transitions. The frequency of the SCKOUT signal is controlled by the OSC_DIV value programmed in the internal oscillator register (see the Internal Oscillator Register section). SCKOUT is a delayed version of the incoming SCK. The delay (tDSDO) has a maximum value of 5.6 ns (at VIO > 1.71 V). Changes the in SDOx logic states are aligned to the rising edges of SCKOUT. The clock and data edge alignments are the same for 1-lane, 2-lane, and 4-lane output data modes. 1-Lane, DDR Mode, Echo Clock Mode Figure 8 shows the timing relationships for DDR mode (2-bit transitions per SCKOUT period) in 1-lane echo clock mode. The timing relationships between the signals apply to both 24-bit and 32-bit sample word formats. 1-Lane, Host Clock Mode, DDR Figure 10 shows the timing relationships for host clock mode when using DDR mode. Similar to echo clock mode, the rising and falling clock edges are aligned to the data bit transitions. The frequency of the SCKOUT signal is controlled by the OSC_DIV value programmed in the internal oscillator register (see the Internal Oscillator Register section). Similar to SDR mode, SCKOUT is a delayed version of the incoming SCK. Changes in the SDOx logic states are aligned to both the rising and falling edges of SCKOUT. analog.com Rev. B | 41 of 55 Data Sheet AD4630-24/AD4632-24 LAYOUT GUIDELINES The following layout guidelines are recommended to achieve maximum performance out of the AD4630-24/AD4632-24: The AD4630-24/AD4632-24 contains internal 1 μF bypass capacitors for VDD_5V and VDD_1.8V, while VIO contains an internal 0.2 μF capacitor. Therefore, no external bypass capacitors are required, saving board space and reducing BOM count and layout sensitivity. ► Have all the analog signals flow in from the left side of the AD4630-24/AD4632-24 and all the digital signals to flow in and out from the right side of AD4630-24/AD4632-24 because this helps isolate analog signals from digital signals. ► Use a solid ground plane under the AD4630-24/AD4632-24 and connect all the analog ground (GND) pins and digital ground ► analog.com (IOGND) pins to the shared ground plane to avoid the formation of ground loops. ► Traces routed to either the REFIN pin or REF pins must be isolated/shielded from other signals. Avoid routing signals beneath the reference trace (REFIN or REF). The REF pins are connected to an internal 2 µF capacitor, eliminating the need to place a decoupling capacitor on the output of the external reference buffer. If a noise reduction filter is placed between the output of the reference (or buffer) and the chosen reference input, the filter must be placed as close as possible to the AD4630-24/ AD4632-24. Rev. B | 42 of 55 Data Sheet AD4630-24/AD4632-24 REGISTERS The AD4630-24/AD4632-24 has programmable user registers that are used to configure the device. These registers can be accessed while the AD4630-24/AD4632-24 are in register configuration mode. Table 16 details the AD4630-24/AD4632-24 user registers and the bit fields in the registers. The Register Details section details the functions of each of the bit fields. The access mode specifies whether the register is comprised only of read-only bits (R) or a mix of read-only and read/write bits (R/W). Read-only bits cannot be overwritten by a SPI write transaction, whereas read/ write bits can be overwritten. Table 16. Register Summary Reg Name Bits Bit 7 Bit 6 Bit 5 0x00 INTERFACE_CONFIG_A [7:0] SW_RESET RESERVED 0x01 INTERFACE_CONFIG_B [7:0] SINGLE_INST STALLING ADDR_ASCE SDO_ENA RESERVED NSION BLE RESERVED SHORT_INST RUCTION RESERVED 0x02 DEVICE_CONFIG [7:0] 0x03 0x04 0x05 0x06 0x0A 0x0B 0x0C 0x0D 0x0E 0x10 0x11 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] CHIP_TYPE PRODUCT_ID_L PRODUCT_ID_H CHIP_GRADE SCRATCH_PAD SPI_REVISION VENDOR_L VENDOR_H STREAM_MODE INTERFACE_CONFIG_C INTERFACE_STATUS_A 0x14 EXIT_CFG_MD [7:0] 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x34 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] AVG OFFSET_CH0_LB OFFSET_CH0_MB OFFSET_CH0_HB OFFSET_CH1_LB OFFSET_CH1_MB OFFSET_CH1_HB GAIN_CH0_LB GAIN_CH0_HB GAIN_CH1_LB GAIN_CH1_HB MODES OSCILLATOR IO TEST_PAT_BYTE0 TEST_PAT_BYTE1 TEST_PAT_BYTE2 TEST_PAT_BYTE3 DIG_DIAG 0x35 DIG_ERR analog.com [7:0] Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W SW_RESE 0x10 TX RESERVED 0x00 R/W OPERATING_MOD 0x00 ES CHIP_TYPE 0x07 0x00 0x20 DEVICE_REVISION 0x01 0x00 VERSION 0x81 0x56 0x04 0x00 0x00 RESERVED 0x00 R/W EXIT_CO 0x00 NFIG_MD AVG_SYNC RESERVED AVG_VAL 0x00 CH0_USER_OFFSET[7:0] 0x00 CH0_USER_OFFSET[15:8] 0x00 CH0_USER_OFFSET[23:16] 0x00 CH1_USER_OFFSET[7:0] 0x00 CH1_USER_OFFSET[15:8] 0x00 CH1_USER_OFFSET[23:16] 0x00 CH0_USER_GAIN[7:0] 0x00 CH0_USER_GAIN[15:8] 0x80 CH1_USER_GAIN[7:0] 0x00 CH1_USER_GAIN[15:8] 0x80 LANE_MD CLK_MD DDR_MD OUT_DATA_MD 0x00 OSC_LIMIT OSC_DIV 0x00 RESERVED IO2X 0x00 TEST_DATA_PAT[7:0] 0x0F TEST_DATA_PAT[15:8] 0x0F TEST_DATA_PAT[23:16] 0x5A TEST_DATA_PAT[31:24] 0x5A POWERUP RESET_OCC RESERVED FUSE_CR 0x40 COMPLETED URRED C_EN RESERVED FUSE_CR 0x00 C_ERR R/W RESERVED [7:4] PRODUCT_ID[7:0] PRODUCT_ID[15:8] GRADE SCRATCH_VALUE SPI_TYPE RESERVED VID[7:0] VID[15:8] LOOP_COUNT RESERVED CLOCK_C OUNT_ER R RESERVED R/W R R R R R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Rev. B | 43 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS INTERFACE CONFIGURATION A REGISTER Address: 0x00, Reset: 0x10, Name: INTERFACE_CONFIG_A Interface configuration settings. Table 17. Bit Descriptions for INTERFACE_CONFIG_A Bits Bit Name Description Reset Access 7 SW_RESET 0x0 R/W 6 5 RESERVED ADDR_ASCENSION 0x0 0x0 R R 4 [3:1] 0 SDO_ENABLE RESERVED SW_RESETX First of Two SW_RESET Bits. This bit appears in two locations in this register. Both locations must be written at the same time to trigger a software reset of the device. All registers except for this register are reset to their default values. Reserved. Determines sequential addressing behavior. 0: address accessed is decremented by one for each data byte when streaming. 1: not a valid option. SDOx Pin Enable. Reserved. Second of Two SW_RESET Bits. This bit appears in two locations in this register. Both locations must be written at the same time to trigger a software reset of the device. All registers except for this register are reset to their default values. 0x1 0x0 0x0 R R R/W INTERFACE CONFIGURATION B REGISTER Address: 0x01, Reset: 0x00, Name: INTERFACE_CONFIG_B Additional interface configuration settings. Table 18. Bit Descriptions for INTERFACE_CONFIG_B Bits Bit Name Description Reset Access 7 SINGLE_INST 0x0 R/W 6 [5:4] 3 STALLING RESERVED SHORT_INSTRUCTION Select streaming or single instruction mode. 0: streaming mode is enabled. The address decrements as successive data bytes are received. 1: single instruction mode is enabled. Reserved for Stalling Feature. Reserved. Set the instruction phase address to 7 or 15 bits. 0: 15-bit addressing. 1: 7-bit addressing. 0x0 0x0 0x0 R/W R R analog.com Rev. B | 44 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS Table 18. Bit Descriptions for INTERFACE_CONFIG_B (Continued) Bits Bit Name Description Reset Access [2:0] RESERVED Reserved. 0x0 R DEVICE CONFIGURATION REGISTER Address: 0x02, Reset: 0x00, Name: DEVICE_CONFIG Table 19. Bit Descriptions for DEVICE_CONFIG Bits Bit Name Description Reset Access [7:2] [1:0] RESERVED OPERATING_MODES Reserved. Power Modes. 00: normal operating mode. 11: shutdown mode. 0x0 0x0 R R/W CHIP TYPE REGISTER Address: 0x03, Reset: 0x07, Name: CHIP_TYPE The chip type is used to identify the family of Analog Devices products a given device belongs to. Use the chip type with the product ID to uniquely identify a given product. Table 20. Bit Descriptions for CHIP_TYPE Bits Bit Name Description Reset Access [7:4] [3:0] RESERVED CHIP_TYPE Reserved. Precision ADC. 0x0 0x7 R R PRODUCT ID LOW REGISTER Address: 0x04, Reset: 0x00, Name: PRODUCT_ID_L Low byte of the product ID. Table 21. Bit Descriptions for PRODUCT_ID_L Bits Bit Name Description Reset Access [7:0] PRODUCT_ID, Bits[7:0] Device Chip Type/Family. Use the product ID with the chip type to identify a product. 0x0 R analog.com Rev. B | 45 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS PRODUCT ID HIGH REGISTER Address: 0x05, Reset: 0x20, Name: PRODUCT_ID_H High byte of the product ID. Table 22. Bit Descriptions for PRODUCT_ID_H Bits Bit Name Description Reset Access [7:0] PRODUCT_ID, Bits[15:8] Device Chip Type/Family. Use the product ID with the chip type to identify a product. 0x20 R CHIP GRADE REGISTER Address: 0x06, Reset: 0x01, Name: CHIP_GRADE Identifies product variations and device revisions. Table 23. Bit Descriptions for CHIP_GRADE Bits Bit Name Description Reset [7:3] GRADE This is the device performance grade. AD4630-24: 0b00000 AD4632-24: 0b00010 This is the device hardware revision. 0x0 0x2 0x1 R [2:0] DEVICE_REVISION Access R SCRATCHPAD REGISTER Address: 0x0A, Reset: 0x00, Name: SCRATCH_PAD This register can be used to test writes and reads. Table 24. Bit Descriptions for SCRATCH_PAD Bits Bit Name Description Reset Access [7:0] SCRATCH_VALUE Software Scratchpad. Software can write to and read from this location without any device side effects. 0x0 R/W SPI REVISION REGISTER Address: 0x0B, Reset: 0x81, Name: SPI_REVISION Indicates the SPI revision. analog.com Rev. B | 46 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS Table 25. Bit Descriptions for SPI_REVISION Bits Bit Name Description Reset Access [7:6] [5:0] SPI_TYPE VERSION Always reads as 0x2. SPI Version. 01: draft 0x2 0x1 R R VENDOR ID LOW REGISTER Address: 0x0C, Reset: 0x56, Name: VENDOR_L Low byte of the vendor ID. Table 26. Bit Descriptions for VENDOR_L Bits Bit Name Description Reset Access [7:0] VID[7:0] Analog Devices Vendor ID. 0x56 R VENDOR ID HIGH REGISTER Address: 0x0D, Reset: 0x04, Name: VENDOR_H High byte of the vendor ID. Table 27. Bit Descriptions for VENDOR_H Bits Bit Name Description Reset Access [7:0] VID[15:8] Analog Devices Vendor ID. 0x4 R STREAM MODE REGISTER Address: 0x0E, Reset: 0x00, Name: STREAM_MODE Defines the length of the loop when streaming data. Table 28. Bit Descriptions for STREAM_MODE Bits Bit Name Description [7:0] LOOP_COUNT Sets the data byte count before looping to start address. When streaming data, a nonzero value sets the number 0x0 of data bytes written before the address loops back to the start address. A maximum of 255 bytes can be written using this approach. A value of 0x00 disables the loop back so that addressing wraps around at the upper and lower limits of the memory. After writing this register, the loop value applies only to the following SPI instruction and auto clears upon the end of that instruction. analog.com Reset Access R/W Rev. B | 47 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS INTERFACE CONFIGURATION C REGISTER Address: 0x10, Reset: 0x00, Name: INTERFACE_CONFIG_C Additional interface configuration settings. Table 29. Bit Descriptions for INTERFACE_CONFIG_C Bits Bit Name Description Reset Access [7:0] RESERVED Reserved. 0x0 R INTERFACE STATUS A REGISTER Address: 0x11, Reset: 0x00, Name: INTERFACE_STATUS_A Status bits are set to 1 to indicate an active condition. The status bits can be cleared by writing a 1 to the corresponding bit location. Table 30. Bit Descriptions for INTERFACE_STATUS_A Bits Bit Name Description Reset Access [7:5] 4 [3:0] RESERVED CLOCK_COUNT_ERR RESERVED Reserved. Incorrect Number of Clocks Detected in a Transaction. Reserved. 0x0 0x0 0x0 R R/W R EXIT CONFIGURATION MODE REGISTER Address: 0x14, Reset: 0x00, Name: EXIT_CFG_MD Table 31. Bit Descriptions for EXIT_CFG_MD Bits Bit Name Description Reset Access [7:1] 0 RESERVED EXIT_CONFIG_MD Reserved. Exit Register Configuration Mode. Write 1 to exit register configuration mode. Self clearing upon CS = 1. 0x0 0x0 R R/W analog.com Rev. B | 48 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS AVERAGING MODE REGISTER Address: 0x15, Reset: 0x00, Name: AVG Table 32. Bit Descriptions for AVG Bits Bit Name Description Reset Access 7 [6:5] [4:0] AVG_SYNC RESERVED AVG_VAL Averaging Filter Reset. 1 = reset, self clearing. Reserved. Averaging Filter Block Length, 2N. 0x00 = no averaging. 0x01 = 21 samples. 0x02 = 22 samples. 0x03 = 23 samples. 0x04 = 24 samples. 0x05 = 25 samples. … 0x0F = 215 samples. 0x10 = 216 samples. 0x11 through 0x1F = invalid. 0x0 0x0 0x0 R/W R R/W CHANNEL 0 OFFSET REGISTERS Address: 0x16, Reset: 0x00, Name: OFFSET_CH0_LB Table 33. Bit Descriptions for OFFSET_CH0_LB Bits Bit Name Description Reset Access [7:0] CH0_USER_OFFSET[7:0] 24-Bit Channel 0 Offset. Twos complement (signed). 1 LSB = (VREF/223)/Gain. See the Channel 0 Gain Registers section for a description of the gain parameter. 0x0 R/W Address: 0x17, Reset: 0x00, Name: OFFSET_CH0_MB Table 34. Bit Descriptions for OFFSET_CH0_MB Bits Bit Name Description Reset Access [7:0] CH0_USER_OFFSET[15:8] 24-Bit Channel 0 Offset. Twos complement (signed). 1 LSB = (VREF/223)/Gain. See the Channel 0 Gain Registers section for a description of the gain parameter. 0x0 R/W analog.com Rev. B | 49 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS Address: 0x18, Reset: 0x00, Name: OFFSET_CH0_HB Table 35. Bit Descriptions for OFFSET_CH0_HB Bits [7:0] Bit Name CH0_USER_OFFSET[23:16] Description /223)/Gain. See the Channel 0 24-Bit Channel 0 Offset. Twos complement (signed). 1 LSB = (VREF Gain Registers section for a description of the gain parameter. Reset Access 0x0 R/W Reset Access 0x0 R/W Reset Access 0x0 R/W Reset Access 0x0 R/W CHANNEL 1 OFFSET REGISTERS Address: 0x19, Reset: 0x00, Name: OFFSET_CH1_LB Table 36. Bit Descriptions for OFFSET_CH1_LB Bits [7:0] Bit Name CH1_USER_OFFSET[7:0] Description /223)/Gain. See the Channel 1 24-Bit Channel 1 Offset. Twos complement (signed). 1 LSB = (VREF Gain Registers section for a description of the gain parameter value. Address: 0x1A, Reset: 0x00, Name: OFFSET_CH1_MB Table 37. Bit Descriptions for OFFSET_CH1_MB Bits [7:0] Bit Name CH1_USER_OFFSET[15:8] Description /223)/Gain. See the Channel 1 24-Bit Channel 1 Offset. Twos complement (signed). 1 LSB = (VREF Gain Registers section for a description of the gain parameter value. Address: 0x1B, Reset: 0x00, Name: OFFSET_CH1_HB Table 38. Bit Descriptions for OFFSET_CH1_HB Bits [7:0] Bit Name CH1_USER_OFFSET[23:16] analog.com Description /223)/Gain. See the Channel 1 24-Bit Channel 1 Offset. Twos complement (signed). 1 LSB = (VREF Gain Registers section for a description of the gain parameter value. Rev. B | 50 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS CHANNEL 0 GAIN REGISTERS Address: 0x1C, Reset: 0x00, Name: GAIN_CH0_LB Table 39. Bit Descriptions for GAIN_CH0_LB Bits Bit Name Description Reset Access [7:0] CH0_USER_GAIN[7:0] Channel 0 Gain Word (Unsigned). Multiplier output = input × gain word/0x8000. Maximum effective gain = 0xFFFF/0x8000 = 1.99997. 0x00 R/W Reset Access Address: 0x1D, Reset: 0x80, Name: GAIN_CH0_HB Table 40. Bit Descriptions for GAIN_CH0_HB Bits Bit Name Description [7:0] CH0_USER_GAIN[15:8] Channel 0 Gain Word (Unsigned). Multiplier output = input × gain word/0x8000. Maximum effective gain 0x80 = 0xFFFF/0x8000 = 1.99997. R/W CHANNEL 1 GAIN REGISTERS Address: 0x1E, Reset: 0x00, Name: GAIN_CH1_LB Table 41. Bit Descriptions for GAIN_CH1_LB Bits Bit Name Description Reset Access [7:0] CH1_USER_GAIN[7:0] Channel 1 Gain Word (Unsigned). Multiplier output = input × gain word/0x8000. Maximum effective gain = 0xFFFF/0x8000 = 1.99997. 0x00 R/W Reset Access Address: 0x1F, Reset: 0x80, Name: GAIN_CH1_HB Table 42. Bit Descriptions for GAIN_CH1_HB Bits Bit Name Description [7:0] CH1_USER_GAIN[15:8] Channel 1 Gain Word (Unsigned). Multiplier output = input × gain word/0x8000. Maximum effective gain 0x80 = 0xFFFF/0x8000 = 1.99997. analog.com R/W Rev. B | 51 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS MODES REGISTER Address: 0x20, Reset: 0x00, Name: MODES Table 43. Bit Descriptions for MODES Bits Bit Name Description Reset Access [7:6] LANE_MD 0x0 R/W [5:4] CLK_MD 0x0 R/W 3 DDR_MD 0x0 R/W [2:0] OUT_DATA_MD Lane Mode Select. 00 = one lane per channel. 01 = two lanes per channel. 10 = four lanes per channel. 11 = Channel 0 and Channel 1 interleaved on SDO0. Clock Mode Select. 00 = SPI clocking mode. 01 = echo clock mode. 10 = host clock mode. 11 = invalid setting. DDR Mode Enable/Disable. 0 = SDR. 1 = DDR (only valid for echo clock and host clock modes). Output Data Mode Select. 000 = 24-bit differential data. 001 = 16-bit differential data + 8-bit common mode data. 010 = 24-bit differential data + 8-bit common mode data. 011 = 30-bit averaged differential data + OR bit + SYNC bit. 100 = 32-bit test data pattern (see the Test Pattern Registers section). 0x0 R/W INTERNAL OSCILLATOR REGISTER Address: 0x21, Reset: 0x00, Name: OSCILLATOR Table 44. Bit Descriptions for OSCILLATOR Bits Bit Name Description [7:2] OSC_LIMIT [1:0] OSC_DIV Oscillator Limit Setting. Oscillator is limited to this number of clock pulses plus one. Automatically calculated by the 0x0 AD4630-24/AD4632-24 based on the data-word size, number of active SDO lanes, and data rate mode (SDR or DDR). Oscillator Frequency Divider Setting. 0x0 00 = no divide (divide by 1). 01 = divide by 2. 10 = divide by 4. 11 = invalid setting. analog.com Reset Access R R/W Rev. B | 52 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS OUTPUT DRIVER REGISTER Address: 0x22, Reset: 0x00, Name: IO Table 45. Bit Descriptions for IO Bits Bit Name Description Reset Access [7:1] 0 RESERVED IO2X Reserved. Double Output Driver Strength. 1 = double output driver strength. 0 = normal output driver strength. 0x0 0x0 R R/W TEST PATTERN REGISTERS Address: 0x23, Reset: 0x0F, Name: TEST_PAT_BYTE0 Table 46. Bit Descriptions for TEST_PAT_BYTE0 Bits Bit Name Description Reset Access [7:0] TEST_DATA_PAT[7:0] 32-Bit Test Pattern. Applied to both channels when OUT_DATA_MD = 4 (see the Modes Register section). 0xF R/W Address: 0x24, Reset: 0x0F, Name: TEST_PAT_BYTE1 Table 47. Bit Descriptions for TEST_PAT_BYTE1 Bits Bit Name Description Reset Access [7:0] TEST_DATA_PAT[15:8] 32-Bit Test Pattern. Applied to both channels when OUT_DATA_MD = 4 (see the Modes Register section). 0xF R/W Address: 0x25, Reset: 0x5A, Name: TEST_PAT_BYTE2 Table 48. Bit Descriptions for TEST_PATBYTE2 Bits Bit Name Description Reset Access [7:0] TEST_DATA_PAT[23:16] 32-Bit Test Pattern. Applied to both channels when OUT_DATA_MD = 4 (see the Modes Register section). 0x5A R/W analog.com Rev. B | 53 of 55 Data Sheet AD4630-24/AD4632-24 REGISTER DETAILS Address: 0x26, Reset: 0x5A, Name: TEST_PAT_BYTE3 Table 49. Bit Descriptions for TEST_PAT_BYTE3 Bits Bit Name Description Reset Access [7:0] TEST_DATA_PAT[31:24] 32-Bit Test Pattern. Applied to both channels when OUT_DATA_MD = 4 (see the Modes Register section). 0x5A R/W DIGITAL DIAGNOSTICS REGISTER Address: 0x34, Reset: 0x40, Name: DIG_DIAG Table 50. Bit Descriptions for DIG_DIAG Bits Bit Name Description Reset Access 7 6 POWERUP_COMPLETED RESET_OCCURRED 0x0 0x1 R R/W1C [5:1] 0 RESERVED FUSE_CRC_EN 1 = Power-Up Completed. Reset Occurred. This bit is set to 1 upon a reset event. Write 1 to clear (useful for detecting brownouts). Reserved. Fuse CRC Enable. Write a 1 to force recheck of CRC. 0x0 0x0 R R/W DIGITAL ERRORS REGISTER Address: 0x35, Reset: 0x00, Name: DIG_ERR Table 51. Bit Descriptions for DIG_ERR Bits Bit Name Description Reset Access [7:1] 0 RESERVED FUSE_CRC_ERR Reserved. Fuse CRC Error. This bit is set to 1 upon a fuse CRC error. Write 1 to clear. 0x0 0x0 R R/W1C analog.com Rev. B | 54 of 55 Data Sheet AD4630-24/AD4632-24 OUTLINE DIMENSIONS Figure 69. 64-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (05-08-1797) Dimensions shown in millimeters Updated: May 11, 2023 ORDERING GUIDE Model1 Temperature Range Package Description AD4630-24BBCZ AD4630-24BBCZ-RL AD4632-24BBCZ AD4632-24BBCZ-RL -40°C to +125°C -40°C to +125°C -40°C to +125°C -40°C to +125°C 64-Lead BGA (7 mm x 7 mm x 1.72 mm) 64-Lead BGA (7 mm x 7 mm x 1.72 mm) 64-Lead BGA (7 mm x 7 mm x 1.72 mm) 64-Lead BGA (7 mm x 7 mm x 1.72 mm) 1 Packing Quantity Reel, 2000 Reel, 2000 Package Option 05-08-1797 05-08-1797 05-08-1797 05-08-1797 Z = RoHS Compliant Part. EVALUATION BOARDS Model1, 2 Description EVAL-AD4630-24-KTZ EVAL-AD4630-24FMCZ Evaluation Kit Evaluation Board 1 Z = RoHS Compliant Part. 2 The EVAL-AD4630-24-KTZ and EVAL-AD4630-24FMCZ can be used to evaluate the AD4632-24. ©2021-2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. B | 55 of 55 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD4632-24BBCZ AD4632-24BBCZ-RL