AD645A

a FEATURES Improved Replacement for Burr-Brown OPA-111 and OPA-121 Op Amp LOW NOISE 2 V p-p max, 0.1 Hz to 10 Hz 10 nV/√Hz max at 10 kHz 11 fA p-p Current Noise 0.1 Hz to 10 Hz Low Noise, Low Drift FET Op Amp AD645 8-Pin Plastic Mini-DIP (N) Package CONNECTION DIAGRAMS TO-99 (H) Package CASE OFFSET NULL –IN +IN –VS OFFSET NULL 8 1 7 HIGH DC ACCURACY 250 V max Offset Voltage 1 V/ C max Drift 1.5 pA max Input Bias Current 114 dB Open-Loop Gain Available in Plastic Mini-DIP, 8-Pin Header Packages, or Chip Form APPLICATIONS Low Noise Photodiode Preamps CT Scanners Precision I-V Converters V OT PR IF M DR I ED 1 2 3 4 TOP VIEW 8 NC +V AD645 7 +VS – IN 6 OUTPUT 5 OFFSET NULL 3 + IN 2 6 OUTPUT AD645 4 –V 5 OFFSET NULL NC = NO CONNECT NOTE: CASE IS CONNECTED TO PIN 8 PRODUCT DESCRIPTION The AD645 is available in six performance grades. The AD645J and AD645K are rated over the commercial temperature range of 0°C to +70°C. The AD645A, AD645B, and the ultraprecision AD645C are rated over the industrial temperature range of –40°C to +85°C. The AD645S is rated over the military temperature range of –55°C to +125°C and is available processed to MIL-STD-883B. The AD645 is available in an 8-pin plastic mini-DIP, 8-pin header, or in die form. PRODUCT HIGHLIGHTS The AD645 is a low noise, precision FET input op amp. It offers the pico amp level input currents of a FET input device coupled with offset drift and input voltage noise comparable to a high performance bipolar input amplifier. The AD645 has been improved to offer the lowest offset drift in a FET op amp, 1 µV/°C. Offset voltage drift is measured and trimmed at wafer level for the lowest cost possible. An inherently low noise architecture and advanced manufacturing techniques result in a device with a guaranteed low input voltage noise of 2 µV p-p, 0.1 Hz to 10 Hz. This level of dc performance along with low input currents make the AD645 an excellent choice for high impedance applications where stability is of prime concern. 1k VOLTAGE NOISE SPECTRAL DENSITY nV/ Hz 1. Guaranteed and tested low frequency noise of 2 µV p-p max and 20 nV/√Hz at 100 Hz makes the AD645C ideal for low noise applications where a FET input op amp is needed. 2. Low VOS drift of 1 µV/°C max makes the AD645C an excellent choice for applications requiring ultimate stability. 3. Low input bias current and current noise (11 fA p-p 0.1 Hz to 10 Hz) allow the AD645 to be used as a high precision preamp for current output sensors such as photodiodes, or as a buffer for high source impedance voltage output sensors. 30 25 NUMBER OF UNITS 100 20 15 10 10 5 1.0 1 10 100 FREQUENCY – Hz 1k 10k 0 –2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 INPUT OFFSET VOLTAGE DRIFT– µV/ °C Figure 1. AD645 Voltage Noise Spectral Density vs. Frequency Figure 2. Typical Distribution of Average Input Offset Voltage Drift (196 Units) R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD645–SPECIFICATIONS(@ +25 C, and Model Conditions1 INPUT OFFSET VOLTAGE 1 Initial Offset Offset Drift (Average) vs. Supply (PSRR) vs. Supply INPUT BIAS CURRENT 2 Either Input Either Input @ TMAX Either Input Offset Current Offset Current @ TMAX INPUT VOLTAGE NOISE Min TMIN –TMAX 90 TMIN –TMAX VCM = 0 V VCM = 0 V VCM = +10 V VCM = 0 V VCM = 0 V 0.1 to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 0.1 to 10 Hz f = 0.1 thru 20 kHz 100 300 3 110 100 0.7/1.8 16/115 0.8/1.9 0.1 2/6 1.0 20 10 9 8 11 0.6 2 VO = 20 V p-p RLOAD = 2 kΩ VOUT = 20 V p-p RLOAD = 2 kΩ 16 1 32 2 6 8 5 3.0 50 30 15 10 20 1.1 15 V dc, unless otherwise noted) Min AD645K/B Typ Max Min AD645C Typ Max Min AD645S Typ Max Units µV µV µV/°C dB dB pA pA pA pA pA 3.3 50 30 15 10 20 1.1 µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA p-p fA/√Hz MHz kHz V/µs µs µs µs AD645J/A Typ Max 500 1000 10/5 94 90 3/5 50 100 1 110 100 250 400 5/2 94 90 50 75 0.5 110 100 1.8 115 1.9 0.1 6 250 300 1 90 86 3 100 500 4 110 95 1.8 1800 1.9 0.1 100 500 1500 10 0.7/1.8 1.5/3 16/115 0.8/1.9 0.1 0.5 2/6 1.0 20 10 9 8 11 0.6 2 16 1 32 2 6 8 5 16 1 2.5 40 20 12 10 15 0.8 5 1.0 0.5 1.0 1 20 10 9 8 11 0.6 2 32 2 6 8 5 2 40 20 12 10 15 0.8 1.0 20 10 9 8 11 0.6 2 16 1 32 2 6 8 5 INPUT CURRENT NOISE FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate, Unity Gain SETTLING TIME 3 To 0.1% To 0.01% Overload Recovery 4 Total Harmonic Distortion INPUT IMPEDANCE Differential Common-Mode INPUT VOLTAGE RANGE Differential5 Common-Mode Voltage Over Max Oper. Range Common-Mode Rejection Ratio OPEN-LOOP GAIN 50% Overdrive f = 1 kHz RLOAD ≥ 2 kΩ VO = 3 V rms VDIFF = ± 1 V 0.0006 1012 1 1014 2.2 ± 20 +11, –10.4 0.0006 1012 1 1014 2.2 ± 20 +11, –10.4 0.0006 1012 1 1014 2.2 ± 20 +11, –10.4 0.0006 1012 1 1014 2.2 ± 20 +11, –10.4 % Ω pF Ω pF V V V dB dB dB dB V V mA mA V V mA ± 10 ± 10 VCM = ± 10 V TMIN–TMAX VO = ± 10 V RLOAD ≥ 2 kΩ TMIN –TMAX 90 ± 10 ± 10 94 90 120 114 ± 10 ± 10 ±5 ± 10 ± 10 94 90 120 114 ± 10 ± 10 ±5 ± 10 ± 10 90 86 114 110 ± 10 ± 10 ±5 110 100 130 110 100 130 110 100 130 110 100 130 114 OUTPUT CHARACTERISTICS Voltage RLOAD ≥ 2 kΩ TMIN –TMAX Current VOUT = ± 10 V Short Circuit POWER SUPPLY Rated Performance Operating Range Quiescent Current Transistor Count ± 10 ± 10 ±5 ± 11 ± 10 ± 15 ± 15 3.0 62 ± 11 ± 10 ± 15 ± 15 3.0 62 ± 11 ± 10 ± 15 ± 15 3.0 62 ± 11 ± 10 ± 15 ± 15 3.0 62 ±5 # of Transistors ± 18 3.5 ±5 ± 18 3.5 ±5 ± 18 3.5 ±5 ± 18 3.5 NOTES 1 Input offset voltage specifications are guaranteed after 5 minutes of operation at T A = +25 °C. 2 Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C. 3 Gain = –1, RLOAD = 2 kΩ. 4 Defined as the time required for the amplifier’s output to return to normal operation after removal of a 50% overload from the amplifier input. 5 Defined as the maximum continuous voltage between the inputs such that neither input exceeds ± 10 V from ground. All min and max specifications are guaranteed. Specifications subject to change without notice. –2– REV. B AD645 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation2 (@ TA = +25°C) 8-Pin Header Package . . . . . . . . . . . . . . . . . . . . . . 500 mW 8-Pin Mini-DIP Package . . . . . . . . . . . . . . . . . . . . 750 mW Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS Storage Temperature Range (H) . . . . . . . . . –65°C to +150°C Storage Temperature Range (N) . . . . . . . . . –65°C to +125°C Operating Temperature Range AD645J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C AD645A/B/C . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C AD645S . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 8-Pin Plastic Mini-DIP Package: θJA = 100°C/Watt 8-Pin Header Package: θJA = 200°C/Watt CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD645 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE WARNING! ESD SENSITIVE DEVICE METALIZATION PHOTOGRAPH Model1 AD645JN AD645KN AD645AH AD645BH AD645CH AD645SH/883B Temperature Range 0°C to +70°C 0°C to +70°C – 40°C to +85°C – 40°C to +85°C – 40°C to +85°C – 55°C to +125°C Package Option2 N-8 N-8 H-08A H-08A H-08A H-08A Dimensions shown in inches and (mm). Contact factory for latest dimensions. NOTES 1 Chips are also available. 2 N = Plastic Mini-DIP; H = Metal Can. +VS 2 7 AD645 3 4 1 10k 6 5 VOS ADJUST –VS Figure 3. AD645 Offset Null Configuration 800 700 100 20 120 110 25 NUMBER OF UNITS NUMBER OF UNITS 80 70 60 50 40 30 20 500 400 300 200 100 NUMBER OF UNITS 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 600 90 15 10 5 10 0 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0 0.2 0.4 0.6 0.8 1.0 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 INPUT OFFSET VOLTAGE – mV INPUT BIAS CURRENT – pA INPUT VOLTAGE NOISE – µV p-p Figure 4. Typical Distribution of Input Offset Voltage (1855 Units) Figure 5. Typical Distribution of Input Bias Current (576 Units) Figure 6. Typical Distribution of 0.1 Hz to 10 Hz Voltage Noise (202 Units) REV. B –3– AD645–Typical Characteristics (@ +25 C, 100 15 V unless otherwise noted) 1000 Hz 1k Hz CURRENT NOISE SPECTRAL DENSITY – fA/√Hz RS = 10MΩ VOLTAGE NOISE SPECTRAL DENSITY – nV/ VOLTAGE NOISE SPECTRAL DENSITY – nV RS = 1MΩ 100 RS = 100kΩ 10 100 1.0 10 10 RS = 100Ω 0.1 1 10 100 1k 10k 100k 1M FREQUENCY – Hz 0 1 10 100 1k 10k 100k FREQUENCY – Hz 1 0.1 1.0 10 100 1k 10k 100k FREQUENCY – Hz Figure 7. Current Noise Spectral Density vs. Frequency Figure 8. Voltage Noise Spectral Density vs. Frequency Figure 9. Voltage Noise Spectral Density vs. Frequency for Various Source Resistances 1k 25 fo = 1kHz 100 nV/ √Hz 100 CURRENT NOISE – fA/√Hz 20 10 VOLTAGE NOISE SPECTRAL DENSITY @ 1kHz – nV/√Hz 1k INPUT VOLTAGE NOISE – µV p-p 100 – VOLTAGE NOISE CURRENT NOISE 15 1 NOISE BANDWIDTH: 0.1 to 10Hz NOISE OF AD645 AND RESISTOR 10 10 SOURCE RESISTANCE RESISTOR NOISE ONLY 1.0 100 1k 10k 100k 1M 10M 100M 10 VOLTAGE NOISE 0.1 1.0 10 3 10 4 10 5 10 6 10 7 SOURCE RESISTANCE – Ω 10 8 10 9 5 – 60 – 40 – 20 0 20 40 60 80 0.01 100 120 140 TEMPERATURE – C SOURCE RESISTANCE – Ω Figure 10. Input Voltage Noise vs. Source Resistance Figure 11. Voltage and Current Noise Spectral Density vs. Temperature Figure 12. Voltage Noise Spectral Density @ 1 kHz vs. Source Resistance 50 CHANGE IN INPUT OFFSET VOLTAGE – µV 150 10 – 9 10 – 9 25 75 TA = 25°C TO TA = 85°C 0 INPUT BIAS CURRENT 10 – 11 10 –11 0 10 – 12 INPUT OFFSET CURRENT 10 – 13 10 –12 – 25 –75 10 – 13 – 50 0 1 2 3 4 5 WARM-UP TIME – Minutes –150 0 1 2 3 4 5 10 – 14 – 60 – 40 – 20 0 20 40 60 10 – 14 80 100 120 140 TIME FROM THERMAL SHOCK – Minutes TEMPERATURE – C Figure 13. Change in Input Offset Voltage vs. Warmup Time Figure 14. Change in Input Offset Voltage vs. Time from Thermal Shock Figure 15. Input Bias and Offset Currents vs. Temperature –4– REV. B INPUT OFFSET CURRENT – Amps VS = ±15V CHANGE IN INPUT OFFSET VOLTAGE – µV TA = +25 C INPUT BIAS CURRENT – Amps 10 – 10 10 – 10 AD645 10 POWER SUPPLY REJECTION – dB 120 120 INPUT BIAS CURRENT – pA + PSRR 80 – PSRR 60 COMMON-MODE REJECTION – dB TA = +25°C VS = ±15V H PACKAGE 100 100 80 1.0 60 40 40 20 20 0.1 –20 0 0 –15 –10 –5 5 10 0 COMMON MODE VOLTAGE – Volts 15 1 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M 1 10 100 10k 100k 1k FREQUENCY – Hz 1M 10M Figure 16. Input Bias Current vs. Common-Mode Voltage Figure 17. Power Supply Rejection vs. Frequency Figure 18. Common-Mode Rejection vs. Frequency 120 110 – 45 3.0 4.0 100 COMMON-MODE REJECTION – dB OPEN-LOOP GAIN – dB 80 – 90 GAIN-BANDWIDTH PRODUCT – MHz PHASE PHASE SHIFT – Degrees 110 2.0 SLEW RATE 100 60 40 GAIN –135 90 1.0 GAIN-BANDWIDTH 2.0 20 80 0 – 180 70 – 15 – 20 – 10 –5 0 5 10 15 10 100 COMMON MODE VOLTAGE – Volts 1k 10k 100k FREQUENCY – Hz 1M 10M 0 – 60 – 40 – 20 0 20 40 60 80 1.0 100 120 140 TEMPERATURE – C Figure 19. Common-Mode Rejection vs. Input Common-Mode Voltage 4.0 Figure 20. Open-Loop Gain and Phase Shift vs. Frequency Figure 21. Gain-Bandwidth Product and Slew Rate vs. Temperature 160 VS = ±15V VO = ±10V RL = 2kΩ 35 GAIN-BANDWIDTH PRODUCT – MHz 4.0 150 OPEN-LOOP GAIN – dB 30 OUTPUT VOLTAGE – Volts p-p SLEW RATE – Volts/µs 3.0 140 25 20 SLEW RATE 3.0 130 15 2.0 GAIN-BANDWIDTH 2.0 120 10 110 5 1.0 0 5 10 15 20 SUPPLY VOLTAGE – ±Volts 100 – 60 – 40 – 20 0 20 40 60 80 TEMPERATURE – C 100 120 140 0 1k 10k 100k FREQUENCY – Hz 1M Figure 22. Gain-Bandwidth and Slew Rate vs. Supply Voltage Figure 23. Open-Loop Gain vs. Temperature Figure 24. Large Signal Frequency Response REV. B –5– SLEW RATE – Volts/µs 3.0 AD645 AD645–Typical Characteristics 10 8 100 90 FOR 10V STEP 80 4 OUTPUT SWING FROM 0V TO ±VOLTS 6 SETTLING TIME – µs 3 4 2 0 –2 0.01% 60 50 0.1% 40 30 20 10 0 ERROR SUPPLY CURRENT – mA 0.1% 0.01% 70 2 0.1% –4 –6 –8 0.01% 1 – 10 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 1 SETTLING TIME – µs 10 100 CLOSED-LOOP VOLTAGE GAIN (V/V) 1k 0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE – C Figure 25. Output Swing and Error vs. Settling Time Figure 26. Settling Time vs. ClosedLoop Voltage Gain Figure 27. Supply Current vs. Temperature + VS 2 VIN 3 7 0.1µF VOUT 6 0.1µF RL 2kΩ CL 10pF AD645 4 – VS Figure 28a. Unity-Gain Follower Figure 28b. Unity-Gain Follower Large Signal Pulse Response Figure 28c. Unity-Gain Follower Small Signal Pulse Response 5kΩ +VS VIN 5kΩ 2 3 7 6 0.1µF RL 2kΩ CL 10pF 4 – VS VOUT 0.1µF AD645 Figure 29a. Unity-Gain Inverter Figure 29b. Unity-Gain Inverter Large Signal Pulse Response Figure 29c. Unity-Gain Inverter Small Signal Pulse Response –6– REV. B AD645 10pF 10 Ω GUARD 2 OUTPUT 6 8 FILTERED OUTPUT V OUT = 9 Sources of noise in a typical preamp are shown in Figure 32. The total noise contribution is defined as: i 2 n + i f 2 + is 2  Rf    1 + s ( Cf ) Rf    2  2 1+ + en      1 + s ( Cd ) Rd   Rd  1 + s ( Cf ) Rf     Rf 2 AD645 PHOTODIODE 3 OPTIONAL 26Hz FILTER Figure 30. The AD645 Used as a Sensitive Preamplifier Preamplifier Applications The low input current and offset voltage levels of the AD645 together with its low voltage noise make this amplifier an excellent choice for preamplifiers used in sensitive photodiode applications. In a typical preamp circuit, shown in Figure 30, the output of the amplifier is equal to: VOUT = ID (Rf) = Rp (P) Rf where: ID = photodiode signal current (Amps) Rp = photodiode sensitivity (Amp/Watt) Rf = the value of the feedback resistor, in ohms. P = light power incident to photodiode surface, in watts. An equivalent model for a photodiode and its dc error sources is shown in Figure 31. The amplifier’s input current, IB, will contribute an output voltage error which will be proportional to the value of the feedback resistor. The offset voltage error, VOS, will cause a “dark” current error due to the photodiode’s finite shunt resistance, Rd. The resulting output voltage error, VE, is equal to: VE = (1 + Rf/Rd) VOS + Rf IB A shunt resistance on the order of 109 ohms is typical for a small photodiode. Resistance Rd is a junction resistance which will typically drop by a factor of two for every 10°C rise in temperature. In the AD645, both the offset voltage and drift are low, this helps minimize these errors. Cf 10pF Rf 9 10 Ω PHOTODIODE VOS Figure 33, a spectral density versus frequency plot of each source’s noise contribution, shows that the bandwidth of the amplifier’s input voltage noise contribution is much greater than its signal bandwidth. In addition, capacitance at the summing junction results in a “peaking” of noise gain in this configuration. This effect can be substantial when large photodiodes with large shunt capacitances are used. Capacitor Cf sets the signal bandwidth and also limits the peak in the noise gain. Each source’s rms or root-sum-square contribution to noise is obtained by integrating the sum of the squares of all the noise sources and then by obtaining the square root of this sum. Minimizing the total area under these curves will optimize the preamplifier’s overall noise performance. Cf 10pF Rf 9 10 Ω PHOTODIODE en in if iS Rd iS Cd 50pF OUTPUT Figure 32. Noise Contributions of Various Sources 10µV is & i f √ OUTPUT VOLTAGE NOISE – Volts/ Hz SIGNAL BANDWIDTH 1µV in WITH FILTER NO FILTER 100nV en en 10nV 1 10 100 1k 10k 100k FREQUENCY – Hz Figure 33. Voltage Noise Spectral Density of the Circuit of Figure 32 With and Without an Output Filter Rd ID Cd 50pF IB OUTPUT An output filter with a passband close to that of the signal can greatly improve the preamplifier’s signal to noise ratio. The photodiode preamplifier shown in Figure 32—without a bandpass filter—has a total output noise of 50 µV rms. Using a 26 Hz single pole output filter, the total output noise drops to 23 µV rms, a factor of 2 improvement with no loss in signal bandwidth. Using a “T” Network Figure 31. A Photodiode Model Showing DC Error Sources Minimizing Noise Contributions The noise level limits the resolution obtainable from any preamplifier. The total output voltage noise divided by the feedback resistance of the op amp defines the minimum detectable signal current. The minimum detectable current divided by the photodiode sensitivity is the minimum detectable light power. REV. B A “T” network, shown in Figure 34, can be used to boost the effective transimpedance of an I to V converter, for a given feedback resistor value. Unfortunately, amplifier noise and offset voltage contributions are also amplified by the “T” network gain. A low noise, low offset voltage amplifier, such as the AD645, is needed for this type of application. –7– AD645 10pF RG 10kΩ Rf 10 8 Ω Ri 1.1kΩ VOUT AD645 PHOTODIODE VOUT = ID R f (1 + RG ) Ri Figure 34. A Photodiode Preamp Employing a “T” Network for Added Gain A pH Probe Buffer Amplifier Guarding the input lines by completely surrounding them with a metal conductor biased near the input lines’ potential has two major benefits. First, parasitic leakage from the signal line is reduced, since the voltage between the input line and the guard is very low. Second, stray capacitance at the input terminal is minimized which in turn increases signal bandwidth. In the header or can package, the case of the AD645 is connected to Pin 8 so that it may be tied to the input potential (when operating as a follower) or tied to ground (when operating as an inverter). The AD645’s positive input (Pin 3) is located next to the negative supply voltage pin (Pin 4). The negative input (Pin 2) is next to the balance adjust pin (Pin 1) which is biased at a potential close to that of the negative supply voltage. Note that any guard traces should be placed on both sides of the board. In addition, the input trace should be guarded along both of its edges, along its entire length. Contaminants such as solder flux, on the board’s surface and on the amplifier’s package, can greatly reduce the insulation resistance and also increase the sensitivity to atmospheric humidity. Both the package and the board must be kept clean and dry. An effective cleaning procedure is to: first, swab the surface with high grade isopropyl alcohol, then rinse it with deionized water, and finally, bake it at 80°C for 1 hour. Note that if either polystyrene or polypropylene capacitors are used on the printed circuit board that a baking temperature of 70°C is safer, since both of these plastic compounds begin to melt at approximately +85°C. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). A typical pH probe requires a buffer amplifier to isolate its 106 to 109 Ω source resistance from external circuitry. Just such an amplifier is shown in Figure 35. The low input current of the AD645 allows the voltage error produced by the bias current and electrode resistance to be minimal. The use of guarding, shielding, high insulation resistance standoffs, and other such standard methods used to minimize leakage are all needed to maintain the accuracy of this circuit. The slope of the pH probe transfer function, 50 mV per pH unit at room temperature, has a +3300 ppm/°C temperature coefficient. The buffer of Figure 35 provides an output voltage equal to 1 volt/pH unit. Temperature compensation is provided by resistor RT which is a special temperature compensation resistor, part number Q81, 1 kΩ, 1%, +3500 ppm/°C, available from Tel Labs Inc. V ADJUST OS 100kΩ +VS +15V 0.1µF COM 0.1µF – VS GUARD 3 2 pH PROBE 8 1 4 5 –VS OUTPUT 1VOLT/pH UNIT 19.6kΩ –15V TO-99 Header (H) Package REFERENCE PLANE 0.185 (4.70) 0.165 (4.19) 0.050 (1.27) MAX 0.750 (19.05) 0.500 (12.70) 0.250 (6.35) MIN 0.100 (2.54) BSC 5 0.160 (4.06) 0.110 (2.79) 6 7 0.045 (1.14) 0.027 (0.69) AD645 7 + VS 6 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 4 0.200 (5.08) BSC 3 2 0.100 (2.54) BSC 1 8 BASE & SEATING PLANE Figure 35. A pH Probe Amplifier Circuit Board Notes 8 PIN 1 1 Plastic Mini-DIP (N) Package 5 0.280 (7.11) 0.240 (6.10) 4 The AD645 is designed for through hole mount into PC boards. Maintaining picoampere level resolution in that environment requires a lot of care. Since both the printed circuit board and the amplifier’s package have a finite resistance, the voltage difference between the amplifier’s input pin and other pins (or traces on the PC board) will cause parasitic currents to flow into (or out of) the signal path. These currents can easily exceed the 1.5 pA input current level of the AD645 unless special precautions are taken. Two successful methods for minimizing leakage are: guarding the AD645’s input lines and maintaining adequate insulation resistance. –8– 0.430 (10.92) 0.348 (8.84) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN SEATING PLANE 0.015 (0.381) 0.008 (0.204) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) REV. B PRINTED IN U.S.A. RT 1kΩ +3500ppm/°C 0.040 (1.02) MAX 0.045 (1.14) 0.010 (0.25) 0.019 (0.48) 0.016 (0.41) 0.021 (0.53) 0.016 (0.41) 0.034 (0.86) 0.027 (0.69) 45 ° BSC C1398a–24–9/91