AD7008

a FEATURES Single +5 V Supply 32-Bit Phase Accumulator On-Chip COSINE and SINE Look-Up Tables On-Chip 10-Bit DAC Frequency, Phase and Amplitude Modulation Parallel and Serial Loading Software and Hardware Power Down Options 20 MHz and 50 MHz Speed Grades 44-Pin PLCC APPLICATIONS Frequency Synthesizers Frequency, Phase or Amplitude Modulators DDS Tuning Digital Modulation CMOS DDS Modulator AD7008 phase modulation, frequency modulation, and both in-phase and quadrature amplitude modulation suitable for QAM and SSB generation. Clock rates up to 20 MHz and 50 MHz are supported. Frequency accuracy can be controlled to one part in 4 billion. Modulation may be effected by loading registers either through the parallel microprocessor interface or the serial interface. A frequency-select pin permits selection between two frequencies on a per cycle basis. The serial and parallel interfaces may be operated independently and asynchronously from the DDS clock; the transfer control signals are internally synchronized to prevent metastability problems. The synchronizer can be bypassed to reduce the transfer latency in the event that the microprocessor clock is synchronous with the DDS clock. A power-down pin allows external control of a power-down mode (also accessible through the microprocessor interface) The AD7008 is available in 44-pin PLCC. PRODUCT HIGHLIGHT PRODUCT DESCRIPTION The AD7008 direct digital synthesis chip is a numerically controlled oscillator employing a 32-bit phase accumulator, sine and cosine look-up tables and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for 1. Low Power 2. DSP/µP Interface 3. Completely Integrated FUNCTIONAL BLOCK DIAGRAM VAA CLOCK FSELECT FREQ0 REG 32 32 MUX 32 FREQ1 REG PHASE ACCUMULATOR 12 COS 10 PHASE REG SCLK SDATA 32-BIT SERIAL REGISTER IQMOD [9:0] 32 SIN 12 12 SIN/COS ROM 10 10 10 GND FS ADJUST VREF IQMOD [19:10] 10 10 10 10-BIT DAC IOUT FULLSCALE ADJUST COMP Σ Σ Σ IOUT AD7008 32-BIT PARALLEL REGISTER COMMAND REG MPU INTERFACE TRANSFER LOGIC D0 D15 WR CS TC0 TC3 LOAD TEST RESET SLEEP R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 (V V V±5 to T AD7008–SPECIFICATIONS1 IOUT=and I= +,5unless%; T = T noted) , R OUT otherwise AA DD A MIN MAX SET = 390 Ω, RLOAD = 1 Ω for Test Conditions/ Comments Parameter SIGNAL DAC SPECIFICATIONS Resolution Update Rate (fMAX) IOUT Full Scale Output Compliance DC Accuracy Integral Nonlinearity Differential Nonlinearity DDS SPECIFICATIONS 2 Update Rate (fMAX) Dynamic Specifications Signal-to-Noise Total Harmonic Distortion Spurious Free Dynamic Range (SFDR)3 Narrow Band (± 50 kHz) Wide Band (± 2 MHz) VOLTAGE REFERENCE Internal Reference @ +25 °C4 Reference TC VREF Overdrive5 LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance POWER SUPPLIES VDD IAA IDD IAA + IDD fCLK = Max Sleep = VDD NOTES 1 2 3 Min 10 AD7008AP20 Typ Max Min 10 AD7008JP50 Typ Max Units Bits MSPS mA Volts LSB LSB 20 20 1 +1 ±1 20 50 –55 50 –53 +1 ±1 20 50 1 50 MSPS dB dB fCLK = fMAX, fOUT = 2 MHz fCLK = fMAX, fOUT = 2 MHz fCLK = 6.25 MHz, fOUT = 2.11 MHz –70 –55 1.2 0 VDD–0.9 0.9 10 10 4.75 5.25 26 22 + 1.5/MHz 80 110 10 1.27 300 2 1.35 –70 –55 1.2 0 VDD–0.9 0.9 10 10 4.75 26 22 + 1.5/MHz 125 160 20 5.25 1.27 300 2 1.35 dBc dBc Volts ppm/°C V Volts Volts µA pF Volts mA mA mA mA RSET = 390 Ω Operating temperature ranges as follows: A Version: –40 °C to +85 °C; J Version: 0°C to +70°C. All dynamic specifications are measured using IOUT. 100% Production tested. fCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz. 4 VREF may be externally driven between 0 and V DD. 5 Do not allow reference current to cause power dissipation beyond the limit of I AA + IDD shown above. Specifications subject to change without notice. –2– REV. B AD7008 TIMING CHARACTERISTICS (V Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 Min 50 20 20 5 3 4t1 2t1 5 5 10 10 20 10 3 3 20 8 8 10 10 AD7008AP20 Typ Max AA = VDD +5 V ± 5%; TA = TMIN to TMAX, unless otherwise noted) Min 20 8 8 5 3 4t1 2t1 5 5 10 10 20 10 3 3 20 8 8 10 10 AD7008JP50 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions/Comments CLOCK Period CLOCK High Duration CLOCK Low Duration CLOCK to Control Setup Time CLOCK to Control Hold Time LOAD Period LOAD High Duration1 LOAD High to TC0–TC3 Setup Time LOAD High to TC0–TC3 Hold Time WR Falling to CS Low Setup Time WR Falling to CS Low Hold Time Minimum WR Low Duration Minimum WR High Duration WR to D0–D15 Setup Time WR to D0–D15 Hold Time SCLK Period SCLK High Duration SCLK Low Duration SCLK Rising to SDATA Setup Time SCLK Rising to SDATA Hold Time NOTE 1 May be reduced to 1t 1 if LOAD is synchronized to CLOCK and Setup (t 4) and Hold (t5) Times for LOAD to CLOCK are observed. t1 t2 CLOCK CS t10 t11 t3 t4 FSEL, LOAD, TC3–TC0 VALID VALID WR t12 t14 D0–D15 t13 t15 t5 VALID DATA Figure 1. Clock Synchronization Timing Figure 3. Parallel Port Timing t16 t6 t7 LOAD SCLK t17 t20 t18 t8 TC0–TC3 VALID t9 SDATA t19 DB31 DB0 Figure 2. Register Transfer Timing Figure 4. Serial Port Timing REV. B –3– AD7008 ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) 32-BIT PARALLEL ASSEMBLY REGISTER MSB A WORD LSB D15–D0 ← A WORD* VAA, VDD to GND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . . . . –0.3 V to VDD + 0.3 V Analog I/O Voltage to AGND . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Commercial (J Version) . . . . . . . . . . . . . . . . . .0°C to +70°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +115°C PLCC θJA Thermal Impedance . . . . . . . . . . . . . . . +53.8°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . +24.1°C/W *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. A WORD B WORD D15–D0 ← B WORD *MOST SIGNIFICANT WORD IS LOADED FIRST Figure 5. 16-Bit Parallel Port Loading Sequence 32-BIT PARALLEL ASSEMBLY REGISTER MSB A BYTE LSB D7–D0 ← A BYTE* A BYTE B BYTE D7–D0 ← B BYTE A BYTE B BYTE C BYTE D7–D0 ← C BYTE ORDERING GUIDE Model Temperature Range Package Description Package Option A BYTE B BYTE C BYTE D BYTE D7–D0 ← D BYTE *MOST SIGNIFICANT BYTE IS LOADED FIRST AD7008AP20 –40°C to +85°C AD7008JP50 0°C to +70°C AD7008/PCB* 44-Pin PLCC P-44A 44-Pin PLCC P-44A 1–3.5" Disk Figure 6. 8-Bit Parallel Port Loading Sequence *AD7008/PCB DDS Evaluation Kit, assembled and tested. Kit includes an AD7008JP50. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7008 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATION PLCC FS ADJUST SDATA WARNING! ESD SENSITIVE DEVICE COMP AGND DGND SCLK 6 DGND D8 D9 D10 D11 D12 D13 D14 D15 WR VDD 17 18 7 PIN NO. 1 IDENTIFIER IOUT IOUT VREF VAA 40 39 VDD RESET SLEEP LOAD TEST AD7008 PLCC TOP VIEW (NOT TO SCALE) TC3 TC2 TC1 TC0 FSELECT CLOCK 29 28 DGND DGND VDD D1 D3 D5 D6 CS D0 D2 D4 D7 –4– REV. B AD7008 PIN DESCRIPTION Mnemonic Function Positive power supply for the analog section. A 0.1 µF decoupling capacitor should be connected between VAA and AGND. This is +5 V ± 5%. Analog Ground. Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between VDD and DGND. This is +5 V ± 5%. Both VAA and VDD should be externally tied together. Digital Ground; both AGND and DGND should be externally tied together. Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND. IOUT should be either tied directly to AGND or through an external load resistor to AGND. Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows: IOUTFULL-SCALE (mA) = POWER SUPPLY VAA AGND VDD DGND IOUT, IOUT FS ADJUST ANALOG SIGNAL AND REFERENCE 6233 × V REF RSET VREF = 1.27 V nominal RSET = 390 Ω typical VREF Voltage Reference Input. A 0.1 µF decoupling ceramic capacitor should be connected between VREF and VAA. There is an internal 1.27 volt reference which can be overdriven by an external reference if required. See specifications for maximum range. Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF decoupling ceramic capacitor should be connected between COMP and VAA. Digital Clock Input for DAC and NCO. DDS output frequencies are expressed as a binary fraction of the frequency of this clock. The output frequency accuracy and phase noise is determined by this clock. Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. Frequency selection can be done on a cycle-per-cycle basis. See Tables I, II and III. Register load, active high digital Input. This pin, in conjunction with TC3–TC0, control loading of internal registers from either the parallel or serial assembly registers. The load pin must be high at least 1t1. See Table II. Transfer Control address bus, digital inputs. This address determines the source and destination registers that are used during a transfer. The source register can either be the parallel assembly register or the serial assembly register. The destination register can be any of the following: COMMAND REG, FREQ0 REG, FREQ1 REG, PHASE REG or IQMOD REG. TC3–TC0 should be valid prior to LOAD rising and should not change until LOAD falls. The Command Register can only be loaded from the parallel assembly register. See Table II. Chip Select, active low digital input. This input in conjunction with WR is used when writing to the parallel assembly register. Write, active low digital input. This input in conjunction with CS is used when writing to the parallel assembly register. Data Bus, digital inputs. These represent the low byte of the 16-bit data input port used to write to the 32-bit parallel assembly register. The databus can configured for either a 8-bit or 16-bit MPU/DSP ports. Data Bus, digital inputs. These represent the high byte of the 16-bit data input port used to write to the 32-bit parallel assembly register. The databus can be configured for either a 8-bit or 16-bit MPU/DSP ports. When the databus is configured for 8-bit operation, D8–D15 should be tied to DGND. Serial Clock, digital input. SCLK is used, in conjunction with SDATA, to clock data into the 32-bit serial assembly register. Serial Data, digital input. Serial data is clocked on the rising edge of SCLK, Most Significant Bit (MSB) first. Low power sleep control, active high digital input. SLEEP puts the AD7008 into a low power sleep mode. Internal clocks are disabled, while also turning off the DAC current sources. A SLEEP bit is also provided in the COMMAND REG to put the AD7008 into a low power sleep mode. Register Reset, active high digital input. RESET clears the COMMAND REG and all the modulation registers to zero. Test Mode. This is used for factory test only and should be left as a No Connect. –5– COMP DIGITAL INTERFACE AND CONTROL CLOCK FSELECT LOAD TC3–TC0 CS WR D7–D0 D15–D8 SCLK SDATA SLEEP RESET TEST REV. B AD7008 14 PIPELINE DELAYS 13 PIPELINE DELAYS 11 PIPELINE DELAYS SIN/ COS SUMMATION PHASE ACCUMULATOR 32 AD7008 REGISTER AND CONTROL LOGIC 32 12 12 COS 12 20 ACCUM RESET SLEEP AM ENABLE IOUT/ IOUT PHASE SUMMATION ROM 10 10 DAC 9:0 19:10 SIN 10 10 10 Figure 7. AD7008 CMOS DDS Modulator (See Table I) SLEEP (37) COMMAND REGISTER SCLK (41) SDATA (42) DQ x 32 32-BIT SERIAL ASSEMBLY REGISTER 32-BIT PARALLEL ASSEMBLY REGISTER 23:0 15:0 23:8 15:8 7:0 7:0 CLK 0 31:8 x 24 1 DQ x 32 REGISTER MUX CLK D0 D3 31:0 31:0 0 x 32 1 3:0 D2 DQ CLK DQ CLK DQ CLK BUS MODE SYNCHRO LOGIC D1 DQ SLEEP AM ENABLE DQ x4 D0-D15 (19-26, 8-15) WR (16) CS (27) D FLIP-FLOPS ARE MASTER SLAVE, LATCHING DATA ON CLK RISING EDGE. PASS FLIP-FLOPS ARE TRANSPARENT WHEN THE CLOCK IS LOW. LOAD (36) FSEL (31) TC0-TC3 (32-35) TRANSFER CONTROL (TC) REGISTER D Q x6 PASS DQ x6 DQ x6 DQ x6 DQ x6 0 x6 1 FSELECT 5 6 TRANSFER DECODE 0 1 2 E3 0 1 2 3 4 CLK 32 FREQUENCY REGISTERS FREQ 0 DQ x 32 E 4 0 1 2 3 FREQ 1 DQ x 32 E 0 x32 1 TO PHASE ACCUMULATOR CLK TC0 TC1 TC3 LOAD TC3 TC2 S x5 DQ x5 32 CLK CLK TC2 RESET SYNCHRONIZATION RESET (38) CLK DQ PHASE REGISTER 12 DQ x 12 CLK E TO PHASE SUMMATION DQ DQ DQ CLK CLOCK (30) IQ MOD REGISTER 10 DQ x 20 CLK E TO SIN/COS SUMMATION ACCUMULATOR CLK RESET Figure 8. AD7008 Register and Control Logic –6– REV. B AD7008 Table I. Latency Table Function FSelect Phase IQ Mod Latency (Synchronizer Enabled CR3 = 01) 14t1 13t1 11t1 NOTE 1 All latencies are reduced by 4t 1 when CR3 = 1 (synchronizer disabled). 1t 1 is equal to one pipeline delay. Table II. Source and Destination Register TC3 X 0 1 1 1 1 1 1 1 1 TC2 X 0 0 0 0 0 1 1 1 1 TC1 X X 0 0 1 1 0 0 1 1 TC0 X X 0 1 0 1 0 1 0 1 LOAD 0 1 1 1 1 1 1 1 1 1 Source Register N/A Parallel Parallel Parallel Parallel Parallel Serial Serial Serial Serial Destination Register N/A COMMAND* FREQ0 FREQ1 PHASE IQMOD FREQ0 FREQ1 PHASE IQMOD *The Command Register can only be loaded from the parallel assembly registers. Table III. AD7008 Control Registers Register Size Reset State Description Command Register. This is written to using the parallel assembly register. Frequency Register 0. This defines the output frequency, when FSELECT = 0, as a fraction of the CLOCK frequency. Frequency Register 1. This defines the output frequency, when FSELECT = 1, as a fraction of the CLOCK frequency. Phase Offset Register. The contents of this register is added to the output of the phase accumulator. I and Q Amplitude Modulation Register. This defines the amplitude of the I and Q signals as 10-bit twos complement binary fractions. DB[19:10] is multiplied by the Quadrature (sine component and multiplied by the In-Phase (cosine) component. COMMAND REG* 4 Bits CR3–CR0 All Zeros FREQ0 REG 32 Bits DB31–DB0 All Zeros FREQ1 REG PHASE REG IQMOD REG 32 Bits DB31–DB0 All Zeros 12 Bits DB11–DB0 All Zeros 20 Bits DB19–DB0 All Zeros *On power up, the Command Register should be configured by the user for the desired mode before operation. Table IV. Command Register Bits* CR0 =0 =1 CR1 CR2 CR3 =0 =1 =0 =1 =0 =1 Eight-Bit Databus. Pins D15–D8 are ignored and the parallel assembly register shifts eight places left on each write. Hence four successive writes are required to load the 32-bit parallel assembly register, Figure 6. Sixteen-Bit Databus. The parallel assembly register shifts 16 places left on each write. Hence two successive writes are required to load the 32-bit parallel assembly register, Figure 5. Normal Operation. Low Power Sleep Mode. Internal Clocks and the DAC current sources are turned off. Amplitude Modulation Bypass. The output of the sine LUT is directly sent to the DAC. Amplitude Modulation Enable. IQ modulation is enabled allowing AM or QAM to be performed. Synchronizer Logic Enabled. The FSELECT, LOAD and TC3–TC0 signals are passed through a 4-stage pipeline to synchronize them with the CLOCK, avoiding metastability problems. Synchronizer Logic Disabled. The FSELECT, LOAD and TC3–TC0 signals bypass the synchronization logic. This allows for faster response to the control signals. *The Command Register can only be loaded from the parallel assembly register. REV. B –7– AD7008 CIRCUIT DESCRIPTION The AD7008 provides an exciting new level of integration for the RF/Communications system designer. The AD7008 combines the numerically controlled oscillator (NCO), SINE/COSINE look-up tables, frequency, phase and IQ modulators, and a digital-to-analog converter on a single integrated circuit. The internal circuitry of the AD7008 consists of four main sections. These are: Numerically Controlled Oscillator (NCO) + Phase Modulator SINE and COSINE Look-Up Tables In Phase and Quadrature Modulators Digital-to-Analog Converter The AD7008 is a fully integrated Direct Digital Synthesis (DDS) chip. The chip requires one reference clock, two lowprecision resistors and six decoupling capacitors to provide digitally created sine waves up to 25 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain allowing accurate and simple realization of complex modulation algorithms using DSP techniques. THEORY OF OPERATION The AD7008 builds the output based on this simple equation. A simple DDS chip will implement this equation with 3 major subcircuits. The AD7008 has an extra section for I and Q modulation. Numerically Controlled Oscillator + Phase Modulator This consists of two frequency select registers, a phase accumulator and a phase offset register. The main component of the NCO is a 32-bit phase accumulator which assembles the phase component of the output signal. Continuous time signals have a phase range 0 to 2 π. Outside this range of numbers, the sinusoidal functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD7008 is implemented with 32 bits. Therefore in the AD7008, 2 π = 232. Likewise, the ∆Phase term is scaled into this range of numbers 0 ≤ ∆Phase ≤ 232 – 1. Making these substitutions into the equation above: f= ∆Phase × f CLOCK 2 32 where 0 ≤ ∆Phase < 2 32 With a clock signal of 50 MHz and a phase word of 051EB852 hex: = 1.000000000931 MHz 32 2 The input to the phase accumulator (i.e., the phase step) can be selected either from the FREQ0 Register or FREQ1 Register, and this is controlled by the FSELECT pin. The phase accumulator in the AD7008 inherently generates a continuous 32bit phase signal, thus avoiding any output discontinuity when switching between frequencies. This facilitates complex frequency modulation schemes, such as GMSK. f= 51EB 852 × 50 MHz Sine waves are typically thought of in terms of their amplitude form: a(t) = sin (ωt) or a(t) = cos (ωt). However, these are nonlinear and not easy to generate except through piece wise construction. On the other hand, the angular information is linear in nature. That is, the phase angle rotates though a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of: ω = 2 πf. +1 MAGNITUDE 0 Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit PHASE Register. The contents of this register are added to the most significant bits of the NCO. Sine and Cosine Look-Up Tables –1 2π PHASE 0 Figure 9. Knowing that the phase of a sine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined. To make the output useful, the signal must be converted from phase information into a sinusoidal value. Since phase information maps directly into amplitude, a ROM look up table converts the phase information into amplitude. To do this the digital phase information is used to address a Sine/Cosine ROM LUT. Only the most significant 12 bits are used for this purpose. The remaining 20 bits provide frequency resolution and minimize the effects of quantization of the phase to amplitude conversion. In Phase and Quadrature Modulators ∆Phase = ωdt Solving for w: ω= ∆Phase = 2 πf dt Solving for f and substituting the reference clock frequency for   1 = dt  : the reference period:  f  CLOCK  f= ∆Phase × fCLOCK 2π Two 10-bit amplitude multipliers are provided allowing the easy implementation of either Quadrature Amplitude Modulation (QAM) or Amplitude Modulation (AM). The 20-bit IQMOD Register is used to control the amplitude of the I (cos) and Q (sin) signals. IQMOD [9:0] controls the I amplitude and IQMOD [19:10] controls the Q amplitude. The user should ensure that when summing the I and Q signals the sum should not exceed the value that a 10-bit accumulator can hold. The AD7008 does not clip the digital output; the output will roll over instead of clip. –8– REV. B AD7008 When amplitude modulation is not required, the IQ multipliers can be bypassed (CR = 2). The sine output is directly sent to the 10-bit DAC. Digital-to-Analog Converter The AD7008 includes a high impedance current source 10-bit DAC, capable of driving a wide range of loads at different speeds. Full-scale output current can be adjusted, for optimum power and external load requirements, through the use of a single external resistor (RSET). The DAC can be configured for single or differential-ended operation. IOUT can be tied directly to AGND for single-ended operation or through a load resistor to develop an output voltage. The load resistor can be any value required as long as the full-scale voltage developed across it does not exceed 1 volt. Since full-scale current is controlled by RSET, adjustments to RSET can balance changes made to the load resistor. DSP and MPU Interfacing TC3–TC0. At some time after the second falling edge of WR, the LOAD signal may go high. As long as the load signal is high 5 ns (see setup time) before the rising edge of the CLOCK signal, data will be transferred to the destination register. The limiting factor of this technique is the WR period which is 30 ns. Thus the CLOCK may run up to 33 MSPS using this technique and the effective update rate would be one half or 16.5 MHz. See timing Figure 10 for timing details. DATA HI WORD LOW WORD WR CLOCK TC The AD7008 contains a 32-bit parallel assembly register and a 32-bit serial assembly register. Each of the modulation registers can be loaded from either assembly register under control of the LOAD pin and the Transfer-Control (TC) pins (See Table II). The Command register can be loaded only from the parallel assembly register. In practical use, both serial and parallel interfaces can be used simultaneously if the application requires. TC3–TC0 should be stable before the LOAD signal rises and should not change until after LOAD falls (Figure 2). The DSP/MPU asserts both WR and CS to load the parallel assembly register (Figure 3). At the end of each write, the parallel assembly register is shifted left by 8 or 16 bits (Depending on CR0), and the new data is loaded into the low bits. Hence, two 16-bit writes or four 8-bit writes are used to load the parallel assembly register. When loading parallel data, it is only necessary to write as much data as will be used by that register. For instance, the Command Register requires only one write to the parallel assembly register. Serial data is input to the chip on the rising edge of SCLK, most significant bit first (Figure 4). The data in the assembly registers can be transferred to the modulation registers by means of the transfer control pins. Maximum Updating of the AD7008 LOAD Figure 10. Accelerated Data Load Sequence APPLICATIONS Serial Configuration Data is written to the AD7008 in serial mode using the two signal lines SDATA and SCLK. Data is accumulated in the serial assembly register with the most significant bit loaded first. The data bits are loaded on the rising edge of the serial clock. Once data is loaded in the serial assembly register, it must be transferred to the appropriate register on chip. This is accomplished by setting the TC bits according to Tables II and III. If you want to load the serial assembly register into FREQ1 register, the TC bits should be 1101. When the LOAD pin is raised, data is transferred directly to the FREQ1 register. When operating in serial mode, some functions must still operate in parallel mode such as loading the TC bits and updating the Command register which is accessed only through the parallel assembly register. See Figure 11 for a typical serial mode configuration. U3 AD7008 CMD0 CMD1 CMD2 CMD3 Updating the AD7008 need not take place in a synchronous fashion. However, in asynchronous systems, most of the external clock pulses (LOAD and SCLK) must be high for greater than one system clock period. This insures that at least one CLOCK rising edge will occur successfully completing the latch function (Figure 1). However, if the AD7008 is run in a synchronous mode with the controlling DSP or microcontroller, the AD7008 may be loaded very rapidly. Optimal speed is attained when operated in the 16-bit load mode; the following discussion will assume that mode is used. Each of the modulation registers require two 16 bit loads. This data is latched into the parallel assembly register on the falling edge of the WR command. This strobe is not qualified by the CLOCK pulse but must be held low for a minimum of 20 ns and only need be high for 10 ns. The two 16-bit words may be loaded in succession. While the second 16-bit word is being latched into the parallel assembly register, the Transfer and Control word may be presented to the TC3–TC0 pins. If the designation register is always the same, an external register can be used to store the information on the inputs of REV. B –9– WR TC0 TC1 TC2 TC3 LOAD SCLK SDATA +5V U2 14 50MHz VCC 8 OUT VEE RESET 7 K1115 19 20 21 22 23 24 25 26 8 9 10 11 12 13 14 15 16 27 32 33 34 35 36 41 42 31 30 38 37 C1 6 +5V D0 VREF D1 0.1µF C2 5 +5V D2 COMP D3 0.1µF D4 2 R4 D5 IOUT 49.9 D6 R3 1 D7 D8 49.9 IOUT D9 D10 D11 R5 4 D12 FSADJUST D13 390 D14 D15 VAA 3 +5V WR VDD 17 +5V CS VDD 28 +5V TC0 VDD 39 +5V TC1 TC2 TC3 44 AGND LOAD 7 DGND SCLK 18 DGND SDATA 29 DGND FSELECT 43 DGND CLK RESET 40 TEST SLEEP Figure 11. General Purpose Serial Interface AD7008 Parallel Configuration The AD7008 functions fully in the parallel mode. There are two parallel modes of operation. Both are similar but are tailored for different bus widths, 8 and 16 bits. All modes of operation can be controlled by the parallel interface. On power up and reset, the chip must be configured by instructing the command register how to operate. The command register may be used to set the device up for 8- or 16-bit mode, 19 20 21 22 23 24 25 26 8 9 10 11 12 13 14 15 16 27 32 33 34 35 36 41 42 31 30 38 37 C1 6 +5V D0 VREF 0.1µF C2 D1 5 +5V D2 COMP D3 0.1µF D4 R4 2 D5 49.9 D6 IOUT 1 D7 R3 D8 IOUT 49.9 D9 D10 D11 R5 4 D12 FSADJUST D13 390 D14 D15 VAA 3 +5V WR VDD 17 +5V CS 28 +5V VDD TC0 VDD 39 +5V TC1 TC2 TC3 44 AGND LOAD 7 DGND SCLK 18 DGND SDATA 29 DGND FSELECT 43 DGND CLK RESET 40 TEST SLEEP U3 AD7008 sleep mode, amplitude control and synchronization logic. At reset, the chip defaults to 8-bit bus, no amplitude control and logic synchronized. The code fragment below indicates how the initialization code for the AD7008 might look using the ADSP-21020. {dds_para is a port define to decode for the parallel assembly register write pulse. dds_cont is a port defined to decode for the TC control Load pin. The Command register must first be loaded with configuration information. In this example, the chip is set up for 16 bits data. See Table III for details.} r4 = 0x00010000; {16 bits, Normal Op., AM disabled, Synchronizer enabled} dm(dds_para) = r4; {write data to parallel assembly register} r4 = 0x00000000; dm(dds_cont) = r5; {No data written, data is just transferred from parallel assembly register to the command register} r4 = 0x051E0000; {1 MHz=051EB852, load high word first} dm(dds_para) = r4; r4 = 0xB8520000; {Now load low word} dm(dds_para)=r4; r4 = 0x80000000; {Transfer data from the parallel assembly register to Freq0} dm(dds_cont)=r4; Local Oscillator DMDXX–DATA BITS DMAXX–ADDRESS BITS U1 74HC138 6 +5V 4 DMS1 5 DMWR G1 G2A G2B Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 7 9 10 11 12 13 14 15 DMD24 DMD25 DMD26 DMD27 DMD28 DMD29 DMD30 DMD31 DMD32 DMD33 DMD34 DMD35 DMD36 DMD37 DMD38 DMD39 GND DMD36 DMD37 DMD38 DMD39 DMA02 DMA01 DMA00 3 2 1 C B A +5V U2 50MHz 14 VCC RESET OUT VEE 7 K1115 8 Figure 12. Parallel Interface to a 16- or 32-Bit DSP or Microprocessor AD7008 10 BITS RSET 390Ω FILTER 5Ω 5Ω 0.1µF –16dBm The AD7008 is well suited for applications such as local oscillators used in super-heterodyne receivers. Although the AD7008 can be used in a variety of receiver designs, one simple local os- 10Ω AM OUTPUT VMID 0° OPTIONAL BPF OR LPF 10Ω PLL INPUT PLL 90° FM OUTPUT RF INPUT (ANTENNA) BANDPASS FILTER 330Ω 330Ω 4.7 µF 100 nF 100 nF MIDPOINT BIAS GENERATOR AGC VOLTAGE AGC DETECTOR AD607 BIAS CIRCUIT PTAT VOLTAGE RECEIVED SIGNAL STRENGTH INDICATOR Figure 13. AD7008 and AD607 Receiver Circuit –10– REV. B AD7008 cillator application is with the AD607 Monoceiver(tm). This unique two chip combination provides a complete receiver subsystem with digital frequency control, RSSI and demodulated outputs for AM, FM and complex I/Q (SSB or QAM). (See Figure 13.) Direct Digital Modulator In addition to the basic DDS function provided by the AD7008, the device also offers several modulation capabilities useful in a wide variety of application. The simplest modulation scheme is frequency shift keying or FSK. In this application, each of the two frequency registers is loaded with a different value, one representing the space frequency and the other the mark frequency. The digital data stream is fed to the FSELECT pin causing the AD7008 to modulate the carrier frequency between the two values. 1 0 0 1 0 FREQ 0 32 REG MUX FREQ 1 REG 32 32 32 PHASE ACCUMULATOR F SELECT CLOCK {This section converts the twos complement audio into offset binary scaled for modulating the AD7008. If twos complement is used, the modulation scheme will instead be double sideband, suppressed carrier.} r5 = 0x80000000; r6 = r6 xor r5; r6 = lshift r6 by -1; r6 = r6 xor r5; r4 = lshift r6 by -6; {Load parallel assembly register with modulation data. Q portion set to midscale, I portion with scaled data} r5 = 0x00000004; dm(dds_para) = r5; dm(dds_para) = r4; {Transfer parallel assembly register to IQMOD register} r4 = 0xb0000000; dm(dds_cont) = r4; rti; Many applications require precise control of the output amplitude, such as in local oscillators, signal generators and modulators. There are several methods to control signal amplitude. The most direct is to program the amplitude using the IQMOD register on the AD7008. Other methods include selecting the load resistor value or changing the value of RSET. Another option is to place a voltage out DAC on the ground side of RSET as in Figure 16. This allows easy control of the output amplitude without affecting other functions of the AD7008. Any combination of these techniques may be used as long as the full-scale voltage developed across the load does not exceed 1 volt. U3 AD7008 DMDXX–DATA BITS DMAXX–ADDRESS BITS DMD24 DMD25 DMD26 DMD27 DMD28 DMD29 DMD30 DMD31 DMD32 DMD33 DMD34 DMD35 DMD36 DMD37 DMD38 DMD39 DMS3 DMD36 DMD37 DMD38 DMD39 19 20 21 22 23 24 25 26 8 9 10 11 12 13 14 15 16 27 32 33 34 35 36 41 42 31 30 38 37 D0 VREF D1 D2 COMP D3 D4 D5 D6 IOUT D7 D8 IOUT D9 D10 D11 D12 FSADJUST D13 D14 D15 VAA WR VDD CS VDD TC0 VDD TC1 TC2 TC3 AGND LOAD DGND SCLK DGND SDATA DGND FSELECT DGND CLK RESET TEST SLEEP 6 5 2 1 AD7008 Figure 14. FSK Modulator The AD7008 has three registers that can be used for modulation. Besides the example of frequency modulation shown above, the frequency registers can be updated dynamically as can the phase register and the IQMOD register. These can be modulated at rates up to 16.5 MHz. The example shown below along with code fragment shows how to implement the AD7008 in an amplitude modulation scheme. Other modulation schemes can be implemented in a similar fashion. DSP: SCALE ANALOG ADC INPUT TO FULL SCALE SIN SIN/COS ROM COS 10 0 10 10 Q MOD 10 C1 +5V 0.1µF C2 +5V 0.1µF R4 49.9 R3 49.9 I MOD 10 10 10 IOUT 10 10-BIT DAC IOUT 6 +5V 4 DMS1 5 DMWR U1 74HC138 G1 G2A G2B Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 7 9 10 11 12 13 14 15 4 R5 390 AD7008 DMA02 DMA01 DMA00 3 2 1 C B A 3 17 28 39 44 7 18 29 43 40 +5V +5V +5V +5V Figure 15. Amplitude Modulation {__________IRQ3 Interrupt Vector__________} {in_audio is a port used to sample the audio signal. This signal is assumed to be twos complement. This interrupt should be serviced at an audio sample rate. This routine assumes that the AD7008 has been set up with the Amplitude Modulation Enabled.} irq3_asserted: {Get audio sample} r6=dm(in_audio); REV. B –11– +5V U2 50MHz 14 VCC OUT VEE 7 K1115 8 RESET VOLTAGE OUT DAC, i.e., AD7245A 0 TO +1 VOLTS Ifs = 6233 x (VREF –VDAC) RSET Figure 16. External Gain Adjustment AD7008–Typical Performance Characteristics REF 5.0 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 4 640 000.0 Hz –54.8 dB +5V VREF 6 115Ω TYP 5 COMP VREF TO DAC AD7008 4 RSET START 0 Hz RBW 3 kHz VBW 10 kHz STOP 10 000 000.0 Hz ST 2.4 SEC Figure 17. Equivalent Reference Circuit Figure 20. fCLK = 20 MHz, fOUT = 5.1 MHz REF 4.3 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 3 330 000.0 Hz –63.6 dB REF 4.3 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 6 320 000.0 Hz –61.3 dB START 0 Hz RBW 3 kHz VBW 10 kHz STOP 10 000 000.0 Hz ST 2.4 SEC START 0 Hz RBW 3 kHz VBW 10 kHz STOP 10 000 000.0 Hz ST 2.4 SEC Figure 18. fCLK = 20 MHz, fOUT = 1.1 MHz Figure 21. fCLK = 20 MHz, fOUT = 2.1 MHz REF 4.3 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 4 500 000.0 Hz –61.1 dB REF 5.0 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET –490 000.0 Hz –63.4 dB START 0 Hz RBW 3 kHz VBW 10 kHz STOP 10 000 000.0 Hz ST 2.4 SEC START 0 Hz RBW 3 kHz VBW 10 kHz STOP 10 000 000.0 Hz ST 2.4 SEC Figure 19. fCLK = 20 MHz, fOUT = 3.1 MHz Figure 22. fCLK = 20 MHz, fOUT = 4.1 MHz –12– REV. B Typical Performance Characteristics–AD7008 REF 5.0 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 1 680 000.0 Hz –52.8 dB REF 4.3 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 14 500 000.0 Hz –52.4 dB START 0 Hz RBW 3 kHz VBW 10 kHz STOP 10 000 000.0 Hz ST 2.4 SEC CENTER 16 000 000.0 Hz RBW 3 kHz VBW 10 kHz SPAN 25 000 000.0 Hz ST 5.6 SEC Figure 23. fCLK = 20 MHz, fOUT = 6.1 MHz REF 4.3 dBm 10 dB/DIV OFFSET 500 000.0 Hz –51.7 dB Figure 26. fCLK = 50 MHz, fOUT = 7.1 MHz REF 5.0 dBm 10 dB/DIV OFFSET –1 280 000.0 Hz –51.8 dB RANGE 5.0 dBm RANGE 5.0 dBm CENTER 6 500 000.0 Hz RBW 3 kHz VBW 10 kHz SPAN 10 000 000.0 Hz ST 2.4 SEC START 0 Hz RBW 3 kHz VBW 10 kHz STOP 10 000 000.0 Hz ST 2.4 SEC Figure 24. fCLK = 20 MHz, fOUT = 6.5 MHz REF 4.3 dBm 10 dB/DIV OFFSET 6 304 000.0 Hz–56.3 dB Figure 27. fCLK = 20 MHz, fOUT = 7.1 MHz REF 4.3 dBm 10 dB/DIV OFFSET 15 300 000.0 Hz –51.8 dB RANGE 5.0 dBm RANGE 5.0 dBm START 0 Hz RBW 3 kHz VBW 10 kHz STOP 16 000 000.0 Hz ST 3.6 SEC START 0 Hz RBW 3 kHz VBW 10 kHz STOP 25 000 000.0 Hz ST 5.6 SEC Figure 25. fCLK = 50 MHz, fOUT = 2.1 MHz Figure 28. fCLK = 50 MHz, fOUT = 5.1 MHz REV. B –13– AD7008–Typical Performance Characteristics REF 5.0 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 4 500 000.0 Hz –54.7 dB REF 5.0 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 500 000.0 Hz –44.8 dB START 0 Hz RBW 3 kHz VBW 10 kHz STOP 25 000 000.0 Hz ST 5.6 SEC CENTER 16 500 000.0 Hz RBW 3 kHz VBW 10 kHz SPAN 25 000 000.0 Hz ST 5.6 SEC Figure 29. fCLK = 50 MHz, fOUT = 9.1 MHz Figure 32. fCLK = 50 MHz, fOUT = 16.5 MHz REF 5.0 dBm 10 dB/DIV RANGE 5.0 dBm OFFSET 11 100 000.0 Hz –54.1 dB 130 120 TOTAL CURRENT IAA + I DD – mA START 0 Hz RBW 3 kHz STOP 25 000 000.0 Hz ST 5.6 SEC 110 100 90 80 70 60 50 0 10 20 30 40 50 MASTER CLOCK – MHz VBW 10 kHz Figure 30. fCLK = 50 MHz, fOUT = 11.1 MHz REF 5.0 dBm 10 dB/DIV OFFSET 10 675 000.0 Hz –47.0 dB Figure 33. Typical Current Consumption vs. Frequency RANGE 5.0 dBm –40 –45 WIDEBAND SFDR – dB CENTER 13 100 000.0 Hz RBW 3 kHz SPAN 25 000 000.0 Hz ST 5.6 SEC –50 –55 –60 –65 –70 –75 0 10 20 30 40 50 MASTER CLOCK – MHz VBW 10 kHz Figure 31. fCLK = 50 MHz, fOUT = 13.1 MHz Figure 34. Typical Plot of SFDR vs. Master Clock Frequency When fOUT = 1/3fCLK, Frequency Word = 5671C71C Hex –14– REV. B AD7008 AD7008/PCB DDS EVALUATION BOARD The AD7008/PCB DDS Evaluation Board allows designers to evaluate the high performance AD7008 DDS Modulator with a minimum amount of effort. To prove this DDS will meet the user’s waveform synthesis requirements, the only things needed are the AD7008/PCB DDS Evaluation Board, +5 V power supply, an IBM-compatible PC, and a spectrum analyzer. The evaluation setup is shown below. The DDS evaluation kit includes a populated, tested AD7008/ PCB board; software which controls the AD7008 through the parallel printer port in a DOS or Windows environment and an AD7008P. The AD7008 direct digital synthesis chip is a numerically controlled oscillator employing a 32-bit phase accumulator, sine and cosine look-up tables, and a l0-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation, frequency modulation, and both in-phase and quadrature amplitude modulation suitable for SSB generation. Clock rates up to 20 MHz and 50 MHz are supported. Frequency accuracy can be controlled to one part in four billion. necessary software. This data sheet provides information on operating the evaluation board; additional details are available from the ADI technical assistance line 1-800-ANALOGD. Prototyping Area An area near one edge of the board is intentionally left void of components to allow the user to add additional circuits to the evaluation test set. Users may want to build custom analog filters for the outputs, or add buffers and operational amplifiers used in the final applications. XO vs. External Clock The reference clock of the AD7008/PCB is normally provided by a 50 MHz CMOS oscillator. This oscillator can be removed and an external CMOS clock connected to CLOCK. If an external clock is used, a 50 Ω resistor R6 should be installed. Power Supply Power for the AD7008/PCB must be provided externally through the pin connections, as described in the Inputs/Outputs. The power leads should be twisted to reduce ground loops. AD7008/PCB BILL OF MATERIAL Quantity EXTERNAL POWER SUPPLY Reference C1 C2–C9 Description Tag – Tant Cap, 10 µF, 35 V, 20% 1 8 OPTIONAL TTL CLOCK REFERENCE GENERATOR CLOCK OSCILLATOR POWER SUPPLY INTERFACE AD7008 50MHz CMOS DDS +5V 6 INTERFACE LOGIC STANDARD PRINTER CABLE 1 1 1 1 1 Cer Chip Cap, 0.1 µF, Murata Grm42 CLOCK, FSEL SMB – Submin Snap-on (Male) IOUT, IOUTN PCB MT Plug SCLK, SDATA FSADJ RN55 – Res Met Film, 392 LK1 P1 P2 R1–R3 R4, R5 RZ1 RZ2 U1 U2 VREF XTAL HDR SIP 3-Pin Male Shunt 530153-2 36-Pin D Conn Rt Ang Pcmt Fem AMP PC Voltage Ter Blk w/Screws Augat RDI RN55 – Res Met Film, 10k RN55 – Res Met Film, 49.9 10P Bussed Res Ntwk, 10k CSC10A01103G 6P Bussed Res Ntwk, 4.7k CSC06A01472G AD7008 JP50 CMOS DDS Modulator 74HC74 – Dual D-type Pos-EdTrigd Flip-Flop Pin Terminal, Testpoint OSC XTAL, Fox F1100H 50 MHz Socket, Methode 213-044-501 Support, Nylon PCB, 48295(-) Pin Sockets, Closed End AD7008 DDS EVALUATION BOARD 50Ω CABLE SOFTWARE PROVIDED IBM-COMPATIBLE PC SPECTRUM ANALYZER 3 2 1 1 1 Figure 35. AD7008 DDS Evaluation Board Setup Table IV. AD7008/PCB Typical Electrical Characteristics (Nominal power supplies, CLK = 50 MHz) Characteristics +5.0 V Supply Current AD7008 Output Voltage (Terminated into 50 Ω Externally) CMOS clock input HIGH CMOS clock input LOW Typical Value 125 0 to +1.0 4.1 to 5 0.0 to 0.5 Units mA V V V 1 1 1 1 4 1 26 USING THE AD7008/PCB DDS EVALUATION BOARD The AD7008/PCB evaluation kit is a test system designed to simplify the evaluation of the AD7008 50 MHz Direct Digital Synthesizer. Provisions to control the AD7008 from the printer port of an IBM-compatible PC are included, along with the REV. B –15– AD7008 Controlling the AD7008/PCB The AD7008/PCB is designed to allow control (frequency specification, reset, etc.) through the parallel printer port of a standard IBM-compatible PC. The user simply disconnects the printer cable from the printer and inserts it into edge connector P1 of the evaluation board. The printer port provides information to the AD7008/PCB through eight data lines and four control lines. Control signals are latched on the AD7008/PCB to prevent problems with long printer cables. A 3.5" floppy disk containing software to control the AD7008 is provided with the AD7008/PCB. This software was developed using C. The C source code is provided in a file named A:\AD7008.C, which the user may view, run, or modify. An executable version of this software is also provided, and can be executed from DOS by typing “A:\AD7008.” The software prompts the user to provide the necessary information needed by the program. Additional information is included in a test file named A:\readme.txt. A windows 3.1 executable called WIN7008 is also included. U1 DUT7008P C36DRPF P1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LATCH D0 D1 D2 D3 D4 D5 D6 D7 10k 10PB+5 RZ1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 10 SMB SDATA D0 D1 D2 D3 D4 D5 D6 SMB SCLK D7 R1 10k RESET R2 10k SMB FSELECT LWR D0 D1 D2 D3 LLOAD R3 10k SMB CLK R6 50 OPTIONAL 4.7k 6PB+5 RZ2 LATCH RESET LOAD WR 2 3 4 5 6 XTAL1 14 VCC OUT VEE 7 8 H3M LK1 1 2 3 19 20 21 22 23 24 25 26 8 9 10 11 12 13 14 15 16 27 32 33 34 35 36 41 42 31 30 38 37 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 WR CS TC0 TC1 TC2 TC3 LOAD VREF COMP 6 5 C6 0.1µF VREF C7 0.1µF +5V SMB IOUT R4 50 IOUT IOUT 2 1 R5 50 4 FSADJ FSADJUST 390 +5VD VAA VDD VDD VDD 3 17 28 39 +5V +5V +5V +5V SMB IOUT C2 0.1µF P2 PCTB2 1 2 C3 0.1µF C4 0.1µF C5 0.1µF +5V C1 10µF C8 0.1µF SCLK SDATA FSELECT CLK RESET SLEEP AGND DGND DGND DGND DGND TEST 44 7 18 29 43 40 LOAD +5V 2 3 D >C 4 PR Q 5 U2 74HC74 LLOAD RESET +5V GND LOAD +5V C9 0.1µF +5V +5V WR LATCH 12 11 D CLQ 6 1 10 PR Q 9 U2 74HC74 LWR WR +5V >C Q CL 8 13 Figure 36. INPUTS/OUTPUTS OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Name P1 CLOCK FSEL SDATA SCLK IOUT IOUTN VREF P2 LK1 Description 36-pin edge connector to connect to parallel port of PC. CMOS input for clock R6 provides termination. CMOS input to select between Freq 0 and Freq 1. Low selects Freq 0. CMOS input for serial input pin. CMOS input for clocking in SDATA. Analog output. Complementary analog output. Test point for VREF pin. +5 V and ground power connection. External sleep command input. 44-Pin PLCC (P-44A) 0.180 (4.57) 0.165 (4.19) 0.025 (0.63) 0.015 (0.38) 0.048 (1.21) 0.042 (1.07) 6 7 PIN 1 IDENTIFIER 40 39 0.050 (1.27) BSC 0.63 (16.00) 0.59 (14.99) TOP VIEW (PINS DOWN) 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) 17 18 29 28 0.020 (0.50) R 0.656 (16.66) SQ 0.650 (16.51) 0.695 (17.65) SQ 0.685 (17.40) –16– REV. B PRINTED IN U.S.A. 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) C1791a–10–2/95