AD8042

Dual 160 MHz Rail-to-Rail Amplifier AD8042 FEATURES Single AD8041 and quad AD8044 also available Fully specified at +3 V, +5 V, and ±5 V supplies Output swings to within 30 mV of either rail Input voltage range extends 200 mV below ground No phase reversal with inputs 0.5 V beyond supplies Low power of 5.2 mA per amplifier High speed and fast settling on 5 V 160 MHz, −3 dB bandwidth (G = +1) 200 V/μs slew rate 39 ns settling time to 0.1% Good video specifications (RL = 150 Ω, G = +2) Gain flatness of 0.1 dB to 14 MHz 0.02% differential gain error 0.04° differential phase error Low distortion: −64 dBc worst harmonic @ 10 MHz Drives 50 mA 0.5 V from supply rails CONNECTION DIAGRAM OUT1 –IN1 +IN1 –VS 1 2 3 4 8 7 6 5 +VS OUT2 –IN2 +IN2 01059-001 AD8042 Figure 2. 8-Lead PDIP and 8-Lead SOIC_N The output voltage swing extends to within 30 mV of each rail, providing the maximum output dynamic range. Additionally, it features gain flatness of 0.1 dB to 14 MHz while offering differential gain and phase error of 0.04% and 0.06° on a single 5 V supply. This makes the AD8042 useful for professional video electronics, such as cameras, video switchers, or any high speed portable equipment. The AD8042’s low distortion and fast settling make it ideal for buffering single-supply, high speed analog-to-digital converters (ADCs). The AD8042 offers a low power supply current of 12 mA maximum and can run on a single 3.3 V power supply. These features are ideally suited for portable and battery-powered applications where size and power are critical. The wide bandwidth of 160 MHz along with 200 V/μs of slew rate on a single 5 V supply make the AD8042 useful in many general-purpose, high speed applications where single supplies from +3.3 V to +12 V and dual power supplies of up to ±6 V are needed. The AD8042 is available in 8-lead PDIP and SOIC_N packages. 15 12 9 VS = 5V G = +1 CL = 5pF RL = 2kΩ TO 2.5V APPLICATIONS Video switchers Distribution amplifiers A/D drivers Professional cameras CCD Imaging systems Ultrasound equipment (multichannel) GENERAL DESCRIPTION The AD8042 is a low power voltage feedback, high speed amplifier designed to operate on +3 V, +5 V, or ±5 V supplies. It has true single-supply capability with an input voltage range extending 200 mV below the negative rail and within 1 V of the positive rail. G = +1 RL = 2kΩ TO 2.5V 5.0V CLOSED-LOOP GAIN (dB) 6 3 0 –3 –6 –9 –12 01059-003 2.5V 0V –15 01059-002 1 10 FREQUENCY (MHz) 100 500 1V 1µs Figure 3. Frequency Response Figure 1. Output Swing: Gain = −1, VS = +5 V Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD8042 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Connection Diagram ....................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Maximum Power Dissipation ..................................................... 6 ESD Caution.................................................................................. 6 Typical Performance Characteristics ..............................................7 Overdrive Recovery ................................................................... 12 Circuit Description .................................................................... 12 Driving Capacitive Loads.......................................................... 12 Layout Considerations............................................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16 REVISION HISTORY 3/06—Rev. C to Rev. D Changes to Text Prior to Table 2..................................................... 4 8/04—Rev. B to Rev. C Changes to Ordering Guide ............................................................ 5 Changes to Outline Dimensions................................................... 15 7/02—Rev. A to Rev. B Changes to Specifications ................................................................ 2 Rev. D | Page 2 of 16 AD8042 SPECIFICATIONS TA = 25°C, VS = 5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 1% Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC, 100 IRE) Differential Phase Error (NTSC, 100 IRE) Worst-Case Crosstalk DC PERFORMANCE Input Offset Voltage Offset Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing R L = 1 kΩ TMIN to TMAX 90 0.2 100 90 300 1.5 −0.2 to +4 74 0.03 to 4.97 0.05 to 4.95 0.36 to 4.45 50 90 100 20 12 6.4 +85 Conditions G = +1 G = +2, RL = 150 Ω, RF = 200 Ω G = –1, VO = 2 V step VO = 2 V p-p G = –1, VO = 2 V step Min 125 130 Typ 160 14 200 30 26 39 –73 15 700 0.04 0.04 0.06 0.24 –63 3 TMIN to TMAX 12 1.2 Max Unit MHz MHz V/μs MHz ns ns dB nV/√Hz fA/√Hz % % Degrees Degrees dB mV mV mV/°C μA μA μA dB dB kΩ pF V dB V V V mA mA mA pF V mA dB °C fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kΩ f = 10 kHz f = 10 kHz G = +2, RL = 150 Ω to 2.5 V G = +2, RL = 75 Ω to 2.5 V G = +2, RL = 150 Ω to 2.5 V G = +2, RL = 75 Ω to 2.5 V f = 5 MHz, RL = 150 Ω to 2.5 V 0.06 0.12 9 12 3.2 4.8 0.5 VCM = 0 V to 3.5 V RL = 10 kΩ to 2.5 V RL = 1 kΩ to 2.5 V RL = 50 Ω to 2.5 V TMIN to TMAX, VOUT = 0.5 V to 4.5 V Sourcing Sinking G = +1 68 0.10 to 4.9 0.4 to 4.4 Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE 3 VS– = 0 V to −1 V, or VS+ = +5 V to +6 V 72 −40 5.5 80 Rev. D | Page 3 of 16 AD8042 TA = 25°C, VS = 3 V, RL = 2 kΩ to 1.5 V, unless otherwise noted Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 1% Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC, 100 IRE) Differential Phase Error (NTSC, 100 IRE) Worst-Case Crosstalk DC PERFORMANCE Input Offset Voltage Offset Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing RL = 1 kΩ TMIN to TMAX 90 0.2 100 90 300 1.5 –0.2 to +2 74 0.03 to 2.97 0.05 to 2.95 0.25 to 2.65 50 50 70 17 12 6.4 70 Conditions G = +1 G = +2, RL = 150 Ω, RF = 200 Ω G = −1, VO = 2 V step VO = 2 V p-p G = −1, VO = 1 V step Min 120 120 Typ 140 11 170 25 30 45 –56 16 500 0.10 0.10 0.12 0.27 –68 3 TMIN to TMAX 12 1.2 9 12 3.2 4.8 0.6 Max Unit MHz MHz V/μs MHz ns ns dB nV/√Hz fA/√Hz % % Degrees Degrees dB mV mV μV/°C μA μA μA dB dB kΩ pF V dB V V V mA mA mA pF V mA dB °C fC = 5 MHz, VO = 2 V p-p, G = −1, RL = 100 Ω f = 10 kHz f = 10 kHz G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V RL = 75 Ω to 1.5 V, Input VCM = 1 V G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V RL = 75 Ω to 1.5 V, Input VCM = 1 V f = 5 MHz, RL = 1 kΩ to 1.5 V VCM = 0 V to 1.5 V RL = 10 kΩ to 1.5 V RL = 1 kΩ to 1.5 V RL = 50 Ω to 1.5 V TMIN to TMAX, VOUT = 0.5 V to 2.5 V Sourcing Sinking G = +1 66 0.1 to 2.9 0.3 to 2.6 Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE 3 VS– = 0 V to –1 V, or VS+ = +3 V to +4 V 68 0 5.5 80 Rev. D | Page 4 of 16 AD8042 TA = 25°C, VS = ±5 V, RL = 2 kΩ to 0 V, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth, VO < 0.5 V p-p Bandwidth for 0.1 dB Flatness Slew Rate Full Power Response Settling Time to 1% Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Input Voltage Noise Input Current Noise Differential Gain Error (NTSC, 100 IRE) Differential Phase Error (NTSC, 100 IRE) Worst-Case Crosstalk DC PERFORMANCE Input Offset Voltage Offset Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing R L = 1 kΩ TMIN to TMAX 90 0.2 94 86 300 1.5 −5.2 to +4 74 −4.97 to +4.97 −4.9 to +4.9 −4.2 to +3.5 50 100 100 25 12 7 +85 Conditions G = +1 G = +2, RL = 150 Ω, RF = 200 Ω G = −1, VO = 2 V step VO = 2 V p-p G = −1, VO = 2 V step Min 125 145 Typ 170 18 225 35 22 32 –78 15 700 0.02 0.02 0.04 0.12 –63 3 TMIN to TMAX 12 1.2 Max Unit MHz MHz V/μs MHz ns ns dB nV/√Hz fA/√Hz % % Degrees Degrees dB mV mV μV/°C μA μA μA dB dB kΩ pF V dB V V V mA mA mA pF V mA dB °C fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kΩ f = 10 kHz f = 10 kHz G = +2, RL = 150 Ω G = +2, RL = 75 Ω G = +2, RL = 150 Ω G = +2, RL = 75 Ω f = 5 MHz, RL = 150 Ω 0.05 0.10 9.8 14 3.2 4.8 0.6 VCM = –5 V to +3.5 V RL = 10 kΩ RL = 1 kΩ RL = 50 Ω TMIN to TMAX, VOUT = −4.5 V to +4.5 V Sourcing Sinking G = +1 66 −4.8 to +4.8 −4 to +3.2 Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current (Per Amplifier) Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE 3 VS– = −5 V to −6 V, or VS+ = +5 V to +6 V 68 −40 6 80 Rev. D | Page 5 of 16 AD8042 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Internal Power Dissipation 1 8-Lead PDIP (N) 8-Lead SOIC_N (R) Input Voltage (Common Mode) Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range (N, R) Lead Temperature (Soldering 10 sec) Rating 12.6 V 1.3 W 0.9 W ±VS ± 0.5 V ±3.4 V Observe Power Derating Curves −65°C to +125°C 300°C MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8042 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic—approximately 150°C. Exceeding this limit temporarily can cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. While the AD8042 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. 2.0 8-LEAD PLASTIC-DIP PACKAGE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Specification is for the device in free air: 8-Lead PDIP: θJA = 90°C/W 8-Lead SOIC_N: θJA = 155°C/W. MAXIMUM POWER DISSIPATION (W) 1.5 TJ = 150°C 1.0 8-LEAD SOIC PACKAGE 0.5 01059-004 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE (°C) Figure 4. Maximum Power Dissipation vs. Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 6 of 16 AD8042 TYPICAL PERFORMANCE CHARACTERISTICS 100 90 80 70 FREQUENCY 100 VS = 5V T = 25°C 140 PARTS, SIDE A & B MEAN = –1.52mV STD DEVIATION = 1.15 SAMPLE SIZE = 280 (140 AD8042S) VS = 5V T = 25°C 95 OPEN-LOOP GAIN (dB) 01059-005 90 60 50 40 30 20 10 0 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 85 80 75 01059-008 70 0 250 500 750 1000 1250 1500 1750 2000 VOS (mV) LOAD RESISTANCE (Ω) Figure 5. Typical Distribution of VOS 30 VS = 5V MEAN = –12.6µV/°C STD DEVIATION = 2.02µV/°C SAMPLE SIZE = 60 100 98 96 94 92 90 88 86 –40 Figure 8. Open-Loop Gain vs. RL to 2.5 V 25 VS = 5V RL = 1kΩ 15 10 5 01059-006 01059-009 0 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 OPEN-LOOP GAIN (dB) 20 FREQUENCY VOS DRIFT (µV/°C) –20 0 20 40 60 80 Figure 6. VOS Drift Over −40°C to +85°C 0 –0.2 –0.4 INPUT BIAS CURRENT (µA) TEMPERATURE (°C) Figure 9. Open-Loop Gain vs. Temperature VS = 5V VCM = 0V 100 VS = 5V 90 OPEN-LOOP GAIN (dB) –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 01059-007 RL = 500Ω TO 2.5V 80 70 RL = 50Ω TO 2.5V 60 50 01059-010 40 TEMPERATURE (°C) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 7. IB vs. Temperature OUTPUT VOLTAGE (V) Figure 10. Open-Loop Gain vs. Output Voltage Rev. D | Page 7 of 16 AD8042 0.04 300 100 30 10 3 1 DIFFERENTIAL GAIN ERROR (%) NTSC SUBCARRIER (3.579MHz) 0.03 0.02 0.01 0 –0.01 0.05 INPUT VOLTAGE NOISE (nV/ Hz) VS = +5V G = +2 RL = 150Ω TO 2.5V VS = ±5V G = +2 RL = 150Ω DIFFERENTIAL PHASE ERROR (Degrees) 0.04 0.03 0.02 0.01 0 –0.01 0 VS = +5V G = +2 RL = 150Ω TO 2.5V 01059-011 10 100 1k 10k 100k 1M 10M 100M 1G 10 20 30 40 50 60 70 80 90 100 FREQUENCY (Hz) MODULATING RAMP LEVEL (IRE) Figure 11. Input Voltage Noise vs. Frequency –30 Figure 14. Differential Gain and Phase Errors 0.6 TOTAL HARMONIC DISTORTION (dBc) –40 –50 –60 –70 –80 –90 –100 VS = 5V, AV = +2, RL = 100Ω TO 2.5V VS = 5V, AV = +1, RL = 100Ω TO 2.5V VS = 3V, AV = –1, RL = 100Ω TO 1.5V 0.5 0.4 NORMALIZED GAIN (dB) VS = 5V G = +2 RF = 200Ω RL = 150Ω TO 2.5V 0.3 0.2 0.1 0 –0.1 –0.2 14MHz 01059-012 –0.3 –0.4 1 10 FREQUENCY (MHz) 100 500 1 2 3 4 5 6 7 8 9 10 FUNDAMENTAL FREQUENCY (MHz) Figure 12. Total Harmonic Distortion –30 –40 120 100 80 Figure 15. 0.1 dB Gain Flatness VS = 5V, G = +2, RL = 1kΩ TO 2.5V VS = 5V G = +2 RF = 200Ω RL = 150Ω TO 2.5V GAIN 45 0 –45 PHASE –90 –135 –180 –225 0.1 1 10 100 –270 500 01059-016 WORST HARMONIC (dBc) 10MHz OPEN-LOOP GAIN (dB) –50 –60 60 40 20 0 –20 –40 5MHz –70 –80 –90 –100 –110 1MHz 01059-013 –60 –80 0.01 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE (V p-p) FREQUENCY (MHz) Figure 13. Worst Harmonic vs. Output Voltage Figure 16. Open-Loop Gain and Phase vs. Frequency Rev. D | Page 8 of 16 PHASE (Degrees) 01059-015 VS = 5V, AV = +1, RL = 1kΩ TO 2.5V VS = 5V, AV = +2, RL = 1kΩ TO 2.5V 01059-014 VS = ±5V G = +2 RL = 150Ω AD8042 10 8 6 CLOSED-LOOP GAIN (dB) VS = 5V G = +1 CL = 5pF RL = 2kΩ TO 2.5V 60 55 50 SETTLING TIME (ns) T = +85°C G = –1 RL = 2kΩ TO MIDPOINT CL = 5pF VS = +3V, 0.1% 4 2 0 –2 –4 –6 01059-017 T = +25°C T = –40°C 45 40 35 30 VS = +3V, 1% VS = +5V, 0.1% VS = ±5V, 0.1% –8 –10 1 10 FREQUENCY (MHz) 100 VS = ±5V, 1% 20 0.5 1.0 1.5 2.0 500 BIPOLAR INPUT STEP (V) Figure 17. Closed-Loop Frequency Response vs. Temperature 12 10 8 CLOSED-LOOP GAIN (dB) Figure 20. Settling Time VS = +5V RL AND CL TO 2.5V COMMON-MODE REJECTION (dB) G = +1 CL = 5pF RL = 2kΩ VS = +3V RL AND CL TO 1.5V TEST CIRCUIT: 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 10k 100k 1.02kΩ INCM 1.02kΩ 1.02kΩ VS = 5V OUT 6 4 2 0 –2 –4 –6 –8 1 10 FREQUENCY (MHz) 100 VS = ±5V 1.02kΩ 01059-018 500 1M 10M 100M 500M FREQUENCY (Hz) Figure 18. Closed-Loop Frequency Response vs. Supply Figure 21. Common-Mode Rejection (CMR) vs. Frequency 0.8 OUTPUT SATURATION VOLTAGE (V) 100 VS = 5V G = +1 RBT = 50Ω VS = 5V 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 5V – VOH (+125°C) 5V – VOH (+25°C) 5V – VOH (–55°C) OUTPUT RESISTANCE (Ω) 10 RBT 1 VOUT RBT = 0Ω 0.1 +VOL (+125°C) 01059-022 01059-019 0.01 0.01 0.1 1 10 100 +VOL (+25°C) +VOL (–55°C) 0 5 10 15 20 25 30 35 40 45 50 500 FREQUENCY (MHz) LOAD CURRENT (mA) Figure 19. Output Resistance vs. Frequency Figure 22. Output Saturation Voltage vs. Load Current Rev. D | Page 9 of 16 01059-021 01059-020 25 VS = +5V, 1% AD8042 12.0 VS = ±5V 11.5 40 SUPPLY CURRENT (mA) 50 VS = 5V VOUT = 100mV STEP 11.0 10.5 10.0 9.5 9.0 10 01059-023 OVERSHOOT (%) VS = +5V G = +2 30 VS = +3V 20 G = +3 8.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 0 0 20 40 60 80 100 120 140 160 180 200 TEMPERATURE (°C) LOAD CAPACITANCE (pF) Figure 23. Supply Current vs. Temperature 10 0 –10 –20 PSRR (dB) –30 –40 –50 –60 –70 01059-024 Figure 26. % Overshoot vs. Load Capacitance 6 5 4 NORMALIZED GAIN (dB) VS = 5V VS = 5V RF = 2kΩ RL = 2kΩ to 2.5V 3 2 1 0 –1 G = +10 –2 –3 –4 1 10 G = +2 –PSRR +PSRR G = +2 RF = 200Ω G = +5 –80 –90 10k 100k 1M 10M 100M 500M 100 500 FREQUENCY (Hz) FREQUENCY (MHz) Figure 24. PSRR vs. Frequency 10 9 8 OUTPUT VOLTAGE (V p-p) CROSSTALK (dB) Figure 27. Frequency Response vs. Closed-Loop Gain –10 VS = ±5V RL = 2kΩ G = –1 –20 –30 –40 –50 –60 –70 –80 –90 01059-025 VS = 5V VIN = 0.6V p-p G = +2 RF = 1kΩ 7 6 5 4 3 2 1 0 0.1 1 10 FREQUENCY (MHz) VOUT1 , RL = 1kΩ TO 2.5V VOUT2 VOUT1 , RL = 150Ω TO 2.5V VOUT2 VOUT2 , RL = 150Ω TO 2.5V VOUT1 01059-028 –100 –110 0.1 VOUT2 , RL = 1kΩ TO 2.5V VOUT1 1 10 FREQUENCY (MHz) 100 100 200 Figure 25. Output Voltage Swing vs. Frequency Figure 28. Crosstalk (Output-to-Output) vs. Frequency Rev. D | Page 10 of 16 01059-027 01059-026 8.5 AD8042 5V 4.770V 4V VS = 5V G = –1 RL = 150Ω TO 2.5V 2.6V AV = 1 VS = 5V VIN = 100mV p-p CL = 5pF RL = 1kΩ TO 2.5V 3V 2.5V 2V 1V 01059-029 0V 0.5V 200µs 25mV 10ns Figure 29. Output Swing with Load Reference to Supply Midpoint 5V Figure 32. 100 mV Pulse Response, VS = +5 V VS = 5V G = –1 RL = 150Ω TO GND 4.59V G = –1 RL = 2kΩ TO 1.5V 3.0V 4V 3V 1.5V 2V 1V 0.035V 01059-030 0V 01059-033 01059-034 0V 0.5V 200µs 0.5V 1µs Figure 30. Output Swing with Load Reference to Negative to Supply 4.5V Figure 33. Rail-to-Rail Output Swing, VS = +3 V 3.5V AV = 2 VS = 5V CL = 5pF RL = 1kΩ TO 2.5V VIN = 1V p-p 1.6V AV = 1 VS = 3V VIN = 100mV p-p CL = 5pF RL = 1kΩ TO 1.5V 2.5V 1.5V 1.5V 01059-031 1.4V 25mV 10ns 0.5V 0.5V 10ns Figure 31. 1 V Pulse Response, VS = +5 V Figure 34. 100 mV Pulse Response, VS = +3 V Rev. D | Page 11 of 16 01059-032 0.160V 2.4V AD8042 OVERDRIVE RECOVERY Overdrive of an amplifier occurs when the output and/or input range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 35, the AD8042 recovers within 30 ns from negative overdrive and within 25 ns from positive overdrive. The AD8042’s rail-to-rail output range is provided by a complementary common-emitter output stage. High output drive capability is provided by injecting all output stage predriver currents directly into the bases of the output devices Q8 and Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5, along with a common-mode feedback loop (not shown). This circuit topology allows the AD8042 to drive 40 mA of output current with the outputs within 0.5 V of the supply rails. On the input side, the device can handle voltages from 0.2 V below the negative rail to within 1.2 V of the positive rail. Exceeding these values does not cause phase reversal; however, the input ESD devices do begin to conduct if the input voltages exceed the rails by greater than 0.5 V. 5.0V 2.5V DRIVING CAPACITIVE LOADS 0V 01059-035 1V G = +2 VS = 5V VIN = 5V p-p RL = 1kΩ TO 2.5V 50ns Figure 35. Overdrive Recovery CIRCUIT DESCRIPTION The AD8042 is fabricated on Analog Devices proprietary eXtraFast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fTs in the 2 GHz to 4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features allow the construction of high frequency, low distortion amplifiers with low supply currents. This design uses a differential output input stage to maximize bandwidth and headroom (see Figure 36). The smaller signal swings required on the first stage outputs (nodes S1P, S1N) reduce the effect of nonlinear currents due to junction capacitances and improve the distortion performance. With this design, harmonic distortion of better than −77 dB @ 1 MHz into 100 Ω with VOUT = 2 V p-p (gain = +2) on a single 5 V supply is achieved. VCC I1 R26 Q4 R15 R2 VINP VINN SIP Q2 Q3 C7 VEE R5 R21 R3 SIN Q11 Q24 I7 Q47 I8 01059-036 The capacitive load drive of the AD8042 can be increased by adding a low valued resistor in series with the load. Figure 37 shows the effects of a series resistor on capacitive drive for varying voltage gains. As the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less overshoot. Adding a series resistor with lower closed-loop gains accomplishes the same effect. For large capacitive loads, the frequency response of the amplifier is dominated by the roll-off of the series resistor and capacitive load. 1000 VS = 5V 200mV STEP WITH 90% OVERSHOOT RS RS = 5Ω CAPACITIVE LOAD (pF) CL RS = 0Ω 100 RS = 20Ω 01059-037 10 1 2 3 CLOSED-LOOP GAIN (V/V) 4 5 I10 R39 Q5 I2 I3 Q25 Q51 Q50 Q39 Q23 I9 Q36 I5 VEE C3 VOUT C9 Q8 VCC Figure 37. Capacitive Load Drive vs. Closed-Loop Gain Q40 VEE Q22 Q7 Q21 Q27 R23 R27 Q13 Q17 Q31 Figure 36. Simplified Schematic Rev. D | Page 12 of 16 AD8042 Single-Supply Composite Video Line Driver The two op amps of an AD8042 can be configured as a singlesupply dual line driver for composite video. The wide signal swing of the AD8042 enables this function to be performed without using any type of clamping or dc restore circuit, which can cause signal distortion. Figure 38 shows a schematic for a circuit that is driven by a single composite video source that is ac-coupled, level-shifted and applied to both + inputs of the two amplifiers. Each op amp provides a separate 75 Ω composite video output. To obtain single-supply operation, ac coupling is used throughout. The large capacitor values are required to ensure that there is minimal tilting of the video signals due to their low frequency (30 Hz) signal content. The circuit shown was measured to have a differential gain of 0.06% and a differential phase of 0.06°. The input is terminated in 75 Ω and ac-coupled via CIN to a voltage divider that provides the dc bias point to the input. Setting the optimal bias point requires some understanding of the nature of composite video signals and the video performance of the AD8042. +5V 4.99kΩ 4.99kΩ 10µF 3 2 COMPOSITE VIDEO IN 75Ω 100kΩ RG 1kΩ 220µF 5 6 4 0.1µF RG 1kΩ 220µF RF 1kΩ 01059-038 The other extreme is for a video signal that is full white everywhere. The blanking intervals and sync tips of such a signal have negative going excursions in compliance with composite video specifications. The combination of horizontal and vertical blanking intervals limit such a signal to being at its highest level (white) for only about 75% of the time. As a result of the duty cycle variations between the two extremes presented above, a 1 V p-p composite video signal that is multiplied by a gain of 2 requires about 3.2 V p-p of dynamic voltage swing at the output for an op amp to pass a composite video signal of arbitrary duty cycle without distortion. Some circuits use a sync tip clamp along with ac coupling to hold the sync tips at a relatively constant level to lower the amount of dynamic signal swing required. However, these circuits can have artifacts, such as sync tip compression, unless they are driven by sources with very low output impedance. The AD8042 not only has ample signal swing capability to handle the dynamic range required without using a sync tip clamp but also has good video specifications such as differential gain and differential phase when buffering these signals in an ac-coupled configuration. To test this, the differential gain and differential phase were measured for the AD8042 while the supplies were varied. As the lower supply is raised to approach the video signal, the first effect observed is that the sync tips become compressed before the differential gain and differential phase are adversely affected. Therefore, there must be adequate swing in the negative direction to pass the sync tips without compression. As the upper supply is lowered to approach the video, the differential gain and differential phase was not significantly affected until the difference between the peak video output and the supply reached 0.6 V. Therefore, the highest video level should be kept at least 0.6 V below the positive supply rail. Therefore, it was found that the optimal point to bias the noninverting input is at 2.2 V dc. Operating at this point, the worst-case differential gain is measured at 0.06% and the worstcase differential phase is 0.06°. The ac-coupling capacitors used in the circuit at first glance appear quite large. A composite video signal has a lower frequency band edge of 30 Hz. The resistances at the various ac coupling points, especially at the output, are quite small. To minimize phase shifts and baseline tilt, the large value capacitors are required. For video system performance that is not to be of the highest quality, the value of these capacitors can be reduced by a factor of up to five with only a slightly observable change in the picture quality. 0.1µF 8 1 RF 1kΩ 1000µF 10µF 75Ω COAX RT 75Ω VOUT RL 75Ω 0.1µF 7 1000µF RT 75Ω VOUT RL 75Ω Figure 38. Single-Supply Composite Video Line Driver Using AD8042 Signals of bounded peak-to-peak amplitude that vary in duty cycle require larger dynamic swing capability than their peakto-peak amplitude after ac coupling. As a worst case, the dynamic signal swing required approaches twice the peak-topeak value. The two bounding cases are for a duty cycle that is mostly low, but occasionally goes high at a fraction of a percent duty cycle and vice versa. Composite video is not quite this demanding. One bounding extreme is for a signal that is mostly black for an entire frame but has a white (full intensity), minimum width spike at least once per frame. Rev. D | Page 13 of 16 AD8042 Single-Ended-to-Differential Driver Using a cross-coupled, single-ended-to-differential converter, the AD8042 makes a good general-purpose differential line driver. This can be used for applications such as driving Category-5 (CAT-5) twisted pair wire. Figure 39 shows a configuration for a circuit that performs this function that can be used for video transmission over a differential pair or various data communication purposes. +5V 0.1µF RIN 1kΩ 49.9Ω 10µF 100 The cable has a characteristic impedance of about 120 Ω. Each driver output is back terminated with a pair of 60.4 Ω resistors to make the source look like 120 Ω. The receive end is terminated with 121 Ω, and the signal is measured differentially with a pair of scope probes. One channel on the oscilloscope is inverted and then the signals are added. The scope photo in Figure 40 shows a 10 MHz, 2 V p-p input signal driving the circuit with 50 m of CAT-5 twisted pair wire. 1V 200mV 50ns VIN 3 8 1 RF 1kΩ 2 AMP1 RA 1kΩ 60.4Ω VIN 90 50m RB 1kΩ 121Ω VOUT VOUT 10 0% AD8042 RB 1kΩ RA 1kΩ 6 5 AMP2 4 100Ω –5V 200mV 01059-039 0.1µF 10µF Figure 40. Differential Driver Frequency Response Figure 39. Single-Ended-to-Differential Twisted Pair Line Driver Single-Supply Differential A/D Driver The single-ended-to-differential converter circuit is also useful as a differential driver for video speed, single-ended, differential input ADCs. Figure 41 is a schematic that shows such a circuit differentially driving an AD9220, a 12-bit, 10-MSPS ADC. +5V Each of the AD8042’s op amps is configured as a unity gain follower by the feedback resistors (RA). Each op amp output also drives the other as a unity gain inverter via the two RBS, creating a totally symmetrical circuit. If the + input to Amp2 is grounded and a small positive signal is applied to the + input of Amp1, the output of Amp1 is driven to saturation in the positive direction and the input of Amp2 is driven to saturation in the negative direction. This is similar to the way a conventional op amp behaves without any feedback. If a resistor (RF) is connected from the output of Amp2 to the + input of Amp1, negative feedback is provided which closes the loop. An input resistor (RI) makes the circuit look like a conventional inverting op amp configuration with differential outputs. The gain of this circuit from input to either output is ±RF/RI, or the single-ended-to-differential gain is 2 × RF/RI. This gives the circuit the advantage of being able to adjust its gain by changing a single resistor. +5V 0.1µF 0.1µF VIN 1kΩ 3 2 8 1kΩ 1 +5V +5V 0.1µF 1kΩ 28 DVDD VINA 7 VINB CAPT 15 AVDD 0.1µF 26 AVDD OTR BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT9 BIT10 BIT11 CLK 19 27 25 BIT12 REFCOM DVSS AVSS AVSS 16 14 13 12 11 10 9 8 7 6 5 4 3 2 +5V 0.1µF 1kΩ AD8042 +5V 1kΩ 6 2.49kΩ 2.49kΩ 5 1kΩ 4 0.1µF 0.1µF 0.1µF 10/16 0.1µF 18 17 22 0.1µF CLOCK 1 AD9220 CAPB VREF SENSE CML 01059-040 7 60.4Ω Figure 41. AD8042 Differential Driver for the AD9220 12-Bit, 10-MSPS ADC Rev. D | Page 14 of 16 01059-041 AD8042 The circuit was tested with a 1 MHz input signal and clocked at 10 MHz. An FFT response of the digital output is shown in Figure 42. Pin 5 is biased at 2.5 V by the voltage divider and bypassed. This biases each output at 2.5 V. VIN is ac-coupled such that VIN going positive makes VINA go positive and VINB go in the negative direction. The opposite happens for a negative going VIN. 1 2kΩ 6 VIN 232Ω 5 3kΩ 7 ATT 2718AF 93DJ39 1 4 VOUT 1/2 AD8042 2kΩ 2 3 3kΩ 1 10 5 0.001µF 1/2 AD8042 912Ω 0.0027µF 2 7 9 34Ω 6 2kΩ 2 2kΩ 1 249Ω VERTICAL SCALE (15dB/DIV) 2kΩ 2kΩ 0.001µF 9 2 8 3 7 6 4 5 3 2kΩ VREC 1/4 AD8044 01059-043 Figure 43. HDSL Line Driver LAYOUT CONSIDERATIONS The specified high speed performance of the AD8042 requires careful attention to board layout and component selection. Proper RF design techniques and low-pass parasitic component selection are necessary. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the area near the input pins to reduce the stray capacitance. Chip capacitors should be used for the supply bypassing. One end should be connected to the ground plane and the other within ⅛-inch of each power pin. An additional large (0.47 μF to 10 μF) tantalum electrolytic capacitor should be connected in parallel but not necessarily so close to supply current for fast, large signal changes at the output. The feedback resistor should be located close to the inverting input pin to keep the stray capacitance at this node to a minimum. Capacitance variations of less than 1 pF at the inverting input significantly affect high speed performance. Stripline design techniques should be used for long signal traces (greater than approximately one inch). These should be designed with a characteristic impedance of 50 Ω or 75 Ω and be properly terminated at each end. 01059-042 HARMONICS (dBc) FUND FRQ 1000977 SMPL FRQ 10000000 THD SNR SINAD SFDR –82.00 71.13 70.79 –86.74 2ND 3RD 4TH 5TH –88.34 –86.74 –99.26 –90.67 6TH 7TH 8TH 9TH –99.47 –91.16 –97.25 –91.61 Figure 42. FFT of the AD9220 Output When Driven by the AD8042 HDSL Line Driver High-bit-rate digital subscriber line (HDSL) is a popular means of providing data communication at DS1 rates (1.544 Mbps) over moderate distances via conventional telephone twisted pair wires. In these systems, the transceiver at the customer’s end is powered sometimes via the twisted pair from a power source at the central office. Sometimes, it is required to raise the dc voltage of the power source to compensate for IR drops in long lines or lines with narrow gauge wires. Because of this, it is highly desirable to keep the power consumption of the customer’s transceiver as low as possible. One means to realize significant power savings is to run the transceiver from a ±5 V supply instead of the more conventional ±12 V. The high output swing and current drive capability of the AD8042 make it ideally suited to this application. Figure 43 shows a circuit for the analog portion of an HDSL transceiver using the AD8042 as the line driver. Rev. D | Page 15 of 16 AD8042 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 1 5 4 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 0.060 (1.52) MAX 0.015 (0.38) MIN 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 5.00 (0.1968) 4.80 (0.1890) 8 5 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 4 5.80 (0.2284) 0.005 (0.13) MIN 0.430 (10.92) MAX 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) × 45° 0.25 (0.0099) 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) COMPLIANT TO JEDEC STANDARDS MS-001-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 44. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) Figure 45. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model AD8042AN AD8042AR AD8042AR-REEL AD8042AR-REEL7 AD8042ARZ 1 AD8042ARZ-REEL1 AD8042ARZ-REEL71 AD8042ACHIPS 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N, 13" Reel 8-Lead SOIC_N, 7" Reel 8-Lead SOIC_N 8-Lead SOIC_N, 13" Reel 8-Lead SOIC_N, 7" Reel DIE Package Option N-8 R-8 R-8 R-8 R-8 R-8 R-8 Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01059-0-3/06(D) Rev. D | Page 16 of 16