AD8067

High Gain Bandwidth Product, Precision Fast FET™ Op Amp AD8067 FEATURES FET input amplifier: 0.6 pA input bias current Stable for gains ≥8 High speed 54 MHz, −3 dB bandwidth (G = +10) 640 V/μs slew rate Low noise 6.6 nV/√Hz 0.6 fA/√Hz Low offset voltage (1.0 mV max) Wide supply voltage range: 5 V to 24 V No phase reversal Low input capacitance Single-supply and rail-to-rail output Excellent distortion specs: SFDR 95 dBc @ 1 MHz High common-mode rejection ratio: −106 dB Low power: 6.5 mA typical supply current Low cost Small packaging: SOT-23-5 CONNECTION DIAGRAM (TOP VIEW) SOT-23-5 (RT-5) VOUT 1 5 +VS –VS 2 +IN 3 4 –IN Figure 1. APPLICATIONS Photodiode preamplifiers Precision high gain amplifiers High gain, high bandwidth composite amplifiers GENERAL DESCRIPTION The AD8067 FastFET amp is a voltage feedback amplifier with FET inputs offering wide bandwidth (54 MHz @ G = +10) and high slew rate (640 V/μs). The AD8067 is fabricated in a proprietary, dielectrically isolated eXtra Fast Complementary Bipolar process (XFCB) that enables high speed, low power, and high performance FET input amplifiers. The AD8067 is designed to work in applications that require high speed and low input bias current, such as fast photodiode preamplifiers. As required by photodiode applications, the laser trimmed AD8067 has excellent dc voltage offset (1.0 mV max) and drift (15 μV/°C max). The FET input bias current (5 pA max) and low voltage noise (6.6 nV/√Hz) also contribute to making it appropriate for precision applications. With a wide supply voltage range (5 V to 24 V) and rail-to-rail output, the AD8067 is well suited for a variety of applications that require wide dynamic range and low distortion. The AD8067 amplifier is available in a SOT-23-5 package and is rated to operate over the industrial temperature range of –40°C to +85°C. 28 G = +20 26 24 22 G = +10 GAIN – dB 20 18 16 14 12 10 8 0.1 G = +8 1 10 FREQUENCY – MHz 100 Figure 2. Small Signal Frequency Response Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD8067 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Connection Diagram (Top View)................................................... 1 Revision History ............................................................................... 2 Specifications for ±5 V..................................................................... 3 Specifications for +5 V..................................................................... 4 Specifications for ±12 V................................................................... 5 Absolute Maximum Ratings............................................................ 6 Maximum Power Dissipation ..................................................... 6 ESD Caution.................................................................................. 6 Typical Performance Characteristics ............................................. 7 Test Circuits..................................................................................... 12 Theory of Operation ...................................................................... 13 Basic Frequency Response ........................................................ 13 Resistor Selection for Wideband Operation............................... 14 DC Error Calculations............................................................... 15 Input and Output Overload Behavior ..................................... 15 Input Protection ......................................................................... 16 Capacitive Load Drive ............................................................... 16 Layout, Grounding, and Bypassing Considerations .............. 16 Applications..................................................................................... 18 Wideband Photodiode Preamp ................................................ 18 Using the AD8067 at Gains of Less Than 8 ............................ 19 Single-Supply Operation ........................................................... 20 High Gain, High Bandwidth Composite Amplifier .............. 20 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22 REVISION HISTORY 5/06—Rev. 0 to Rev. A Changes to Figure 51...................................................................... 18 Changes to Figure 54...................................................................... 19 Changes to Figure 57...................................................................... 21 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 11/02—Revision 0: Initial Version Rev. A | Page 2 of 24 AD8067 SPECIFICATIONS FOR ±5 V VS = ±5 V (@ TA = +25°C, G = +10, RF = RL =1 kΩ, unless otherwise noted.) Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Output Overdrive Recovery Time (Pos/Neg) Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious-Free Dynamic Range (SFDR) Conditions VO = 0.2 V p-p VO = 2 V p-p VO = 0.2 V p-p VI = ±0.6 V VO = 5 V step VO = 5 V step fC = 1 MHz, 2 V p-p fC = 1 MHz, 8 V p-p fC = 5 MHz, 2 V p-p fC = 1 MHz, 2 V p-p, RL = 150 Ω f = 10 kHz f = 10 kHz Min 39 Typ 54 54 8 115/190 640 27 95 84 82 72 6.6 0.6 0.2 1 0.6 25 0.2 1 119 1000||1.5 1000||2.5 VCM = –1 V to +1 V RL = 1 kΩ RL = 150 Ω SFDR > 60 dBc, f = 1 MHz 30% overshoot 5 −90 6.5 −109 −5.0 −85 −4.86 to +4.83 2.0 −106 −4.92 to +4.92 −4.67 to +4.72 30 105 120 24 6.8 1.0 15 5 1 Max Unit MHz MHz MHz ns V/μs ns dBc dBc dBc dBc nV/√Hz fA/√Hz mV μV/°C pA pA pA pA dB GΩ||pF GΩ||pF V dB V V mA mA pF V mA dB 500 Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range Common-Mode Rejection Ratio (CMRR) OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio (PSRR) TMIN to TMAX TMIN to TMAX VO = ±3 V 103 Rev. A | Page 3 of 24 AD8067 SPECIFICATIONS FOR +5 V VS = +5 V (@ TA = +25°C, G = +10, RL = RF = 1 kΩ, unless otherwise noted.) Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Output Overdrive Recovery Time (Pos/Neg) Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious-Free Dynamic Range (SFDR) Conditions VO = 0.2 V p-p VO = 2 V p-p VO = 0.2 V p-p VI = +0.6 V VO = 3 V step VO = 2 V step fC = 1 MHz, 2 V p-p fC = 1 MHz, 4 V p-p fC = 5 MHz, 2 V p-p fC = 1 MHz, 2 V p-p, RL = 150 Ω f = 10 kHz f = 10 kHz Min 36 Typ 54 54 8 150/200 490 25 86 74 60 72 6.6 0.6 0.2 1 0.5 25 0.1 117 1000||2.3 1000||2.5 VCM = 0.5 V to 1.5 V RL = 1 kΩ RL =150 Ω SFDR > 60 dBc, f = 1 MHz 30% overshoot 5 −87 6.4 −103 0 −81 0.07 to 4.89 2.0 −98 0.03 to 4.94 0.08 to 4.83 22 95 120 24 6.7 1.0 15 5 1 Max Unit MHz MHz MHz ns V/μs ns dBc dBc dBc dBc nV/√Hz fA/√Hz mV μV/°C pA pA pA dB GΩ||pF GΩ||pF V dB V V mA mA pF V mA dB 390 Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range Common-Mode Rejection Ratio (CMRR) OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio (PSRR) TMIN to TMAX VO = 0.5 V to 4.5 V 100 Rev. A | Page 4 of 24 AD8067 SPECIFICATIONS FOR ±12 V VS = ±12 V (@ TA = +25°C, G = +10, RL = RF = 1 kΩ, unless otherwise noted.) Table 3. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Bandwidth for 0.1 dB Flatness Output Overdrive Recovery Time (Pos/Neg) Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious-Free Dynamic Range (SFDR) Conditions VO = 0.2 V p-p VO = 2 V p-p VO = 0.2 V p-p VI = ±1.5 V VO = 5 V step VO = 5 V step fC = 1 MHz, 2 V p-p fC = 1 MHz, 20 V p-p fC = 5 MHz, 2 V p-p fC = 1 MHz, 2 V p-p, RL = 150 Ω f = 10 kHz f = 10 kHz Min 39 Typ 54 53 8 75/180 640 27 92 84 74 72 6.6 0.6 0.2 1 1.0 25 0.2 119 1000||1.5 1000||2.5 VCM = –1 V to +1 V RL = 1 kΩ RL = 500 Ω SFDR > 60 dBc, f = 1 MHz 30% overshoot 5 −86 6.6 −97 −12.0 −89 −11.70 to +11.70 +9.0 −108 −11.85 to +11.84 −11.31 to +11.73 26 125 120 24 7.0 1.0 15 5 1 Max Unit MHz MHz MHz ns V/μs ns dBc dBc dBc dBc nV/√Hz fA/√Hz mV μV/°C pA pA pA dB GΩ||pF GΩ||pF V dB V V mA mA pF V mA dB 500 Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Common-Mode Input Impedance Differential Input Impedance Input Common-Mode Voltage Range Common-Mode Rejection Ratio (CMRR) OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Short Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio (PSRR) TMIN to TMAX VO = ±10 V 107 Rev. A | Page 5 of 24 AD8067 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 26.4 V See Figure 3 VEE – 0.5 V to VCC + 0.5 V 1.8 V –65°C to +125°C –40°C to +85°C 300°C 150°C PD = Quiescent Power + (Total Drive Power − Load Power) ⎛V V PD = (VS × I S )+ ⎜ S × OUT ⎜2 RL ⎝ ⎞ VOUT 2 ⎟– ⎟R L ⎠ If RL is referenced to VS− as in single-supply operation, then the total drive power is VS × IOUT. If the rms signal levels are indeterminate, then consider the worst case, when VOUT = VS/4 for RL to midsupply: PD = (VS × I S ) + (VS /4 )2 RL Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. In single-supply operation with RL referenced to VS−, worst case is VOUT = VS/2. Airflow increases heat dissipation effectively, reducing θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the SOT-23-5 (180°C/W) package on a JEDEC standard 4-layer board. θJA values are approximations. It should be noted that for every 10°C rise in temperature, IB approximately doubles (see Figure 22). B MAXIMUM POWER DISSIPATION The associated raise in junction temperature (TJ) on the die limits the maximum safe power dissipation in the AD8067 package. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8067. Exceeding a junction temperature of 175°C for an extended period can result in changes in the silicon devices, potentially causing failure. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. RMS output voltages should be considered. 2.0 MAXIMUM POWER DISSIPATION – W 1.5 1.0 SOT-23-5 0.5 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 AMBIENT TEMPERATURE – °C Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 24 AD8067 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: VS = ±5 V (@ TA = +25°C, G = +10, RL = RF = 1 kΩ, unless otherwise noted.) 28 G = +20 26 24 22 GAIN – dB 20.7 VOUT = 200mV p-p 20.6 20.5 VOUT = 0.2V p-p VOUT = 0.7V p-p VOUT = 1.4V p-p 20.4 20 18 16 14 G = +8 G = +6 GAIN – dB G = +10 20.3 20.2 20.1 20.0 12 19.9 10 8 1 10 FREQUENCY – MHz 100 19.8 1 10 FREQUENCY – MHz 100 Figure 4. Small Signal Frequency Response for Various Gains 22 VOUT = 200mV p-p 21 20 19 18 17 16 15 14 1 10 FREQUENCY – MHz 100 GAIN – dB 24 Figure 7. 0.1 dB Flatness Frequency Response VOUT = 200mV p-p 23 CL = 100pF VS = +5V VS = ±5V 22 21 CL = 25pF VS = ±12V 20 19 18 17 16 15 14 1 10 FREQUENCY – MHz 100 CL = 5pF CL = 100pF RSNUB = 24.9Ω GAIN – dB Figure 5. Small Signal Frequency Response for Various Supplies 22 VOUT = 2V p-p 21 20 19 18 17 16 15 14 1 10 FREQUENCY – MHz 100 VS = ±12V GAIN – dB Figure 8. Small Signal Frequency Response for Various CLOAD 22 VS = +5V VS = ±5V 21 20 VOUT = 4V p-p 19 18 17 16 15 14 1 10 FREQUENCY – MHz 100 VOUT = 0.2V p-p, 2V p-p GAIN – dB Figure 6. Large Signal Frequency Response for Various Supplies Figure 9. Frequency Response for Various Output Amplitudes Rev. A | Page 7 of 24 AD8067 22 VOUT = 200mV p-p 21 20 RF = 499Ω GAIN – dB 90 120 90 60 PHASE RF = 2kΩ RF = 1kΩ 80 70 60 GAIN – dB 19 18 17 16 50 40 GAIN 30 20 10 0 –30 –60 –90 –120 –150 –180 1000 15 14 1 10 FREQUENCY – MHz 100 0 –10 0.01 0.1 1 10 FREQUENCY – MHz 100 Figure 10. Small Signal Frequency Response for Various RF –40 –50 –60 DISTORTION – dBc DISTORTION – dBc Figure 13. Open-Loop Gain and Phase –40 HD2 RLOAD = 150Ω –50 –60 HD3 RLOAD = 150Ω G = +10 VOUT = 2V p-p –70 –80 –90 –100 –110 HD3 RLOAD = 1kΩ –120 –130 –140 0.1 HD2 RLOAD = 1kΩ –70 –80 –90 –100 –110 HD2 VS = ±12V HD2 VS = ±5V VOUT = 2V p-p –120 G = +10 VS = ±5V 1 10 FREQUENCY – MHz 100 HD3 VS = ±12V HD3 VS = ±5V –130 –140 0.1 1 10 FREQUENCY – MHz 100 Figure 11. Distortion vs. Frequency for Various Loads –20 –30 –40 –50 DISTORTION – dBc Figure 14. Distortion vs. Frequency for Various Supplies VS = ±12V G = +10 –40 VS = ±12V f = 1MHz G = +10 HD2 RLOAD = 150Ω DISTORTION – dBc –60 –60 –70 –80 –90 –100 –110 –120 HD2 RLOAD = 1kΩ HD3 RLOAD = 150Ω –80 HD2 VOUT = 20V p-p HD3 VOUT = 2V p-p –100 HD2 VOUT = 2V p-p –120 HD3 VOUT = 20V p-p HD3 RLOAD = 1kΩ –140 0.1 1 10 FREQUENCY – MHz 100 –130 0 2 4 6 8 10 12 14 16 18 OUTPUT AMPLITUDE – V p-p 20 22 24 Figure 12. Distortion vs. Frequency for Various Amplitudes Figure 15. Distortion vs. Output Amplitude for Various Loads Rev. A | Page 8 of 24 PHASE – Degrees 30 AD8067 G = +10 VIN = 20mV p-p CL = 100pF CL = 0pF G = +10 VIN = 20mV p-p 1.5V 50mV/DIV 25ns/DIV 50mV/DIV 25ns/DIV Figure 16. Small Signal Transient Response 5 V Supply Figure 19. Small Signal Transient Response ± 5 V Supply 10VIN VOUT G = +10 VS = ±12V VIN = 2V p-p G = +10 2V/DIV 200ns/DIV 5V/DIV 50ns/DIV Figure 17. Output Overdrive Recovery Figure 20. Large Signal Transient Response VOUT (1V/DIV) VIN (100mV/DIV) G = +10 +0.1% VOUT – 10VIN (5mV/DIV) VIN (100mV/DIV) +0.1% VOUT – 10VIN (5mV/DIV) –0.1% –0.1% 5μs/DIV t=0 5ns/DIV Figure 18. Long-Term Settling Time Figure 21. 0.1% Short-Term Settling Time Rev. A | Page 9 of 24 AD8067 14 12 INPUT BIAS CURRENT – pA 10 8 INPUT BIAS CURRENT – pA VS = ±12V VS = ±5V VS = +5V 6 4 2 0 –2 –4 –6 10 8 6 VS = ±12V 4 2 VS = ±5V 0 25 35 45 55 65 TEMPERATURE – °C 75 85 –8 –10 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 COMMON-MODE VOLTAGE – V 10 12 14 Figure 22. Input Bias Current vs. Temperature 1800 1600 1400 1200 COUNT Figure 25. Input Bias Current vs. Common-Mode Voltage 5 4 INPUT OFFSET VOLTAGE – mV N = 12255 SD = 0.203 MEAN = –0.033 VS = ±12V VS = ±5V 3 2 1 1000 800 600 400 200 0 –1 0 INPUT OFFSET VOLTAGE – mV 1 VS = +5V 0 –1 –2 –6 –4 –5 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 COMMON-MODE VOLTAGE – V 10 12 14 Figure 23. Input Offset Voltage Histogram 1000 Figure 26. Input Offset Voltage vs. Common-Mode Voltage –40 –50 –60 NOISE – nV/ Hz 100 CMRR – dB –70 –80 –90 –100 –110 10 1 1 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M 100M –120 0.1 1 10 FREQUENCY – MHz 100 Figure 24. Voltage Noise Figure 27. CMRR vs. Frequency Rev. A | Page 10 of 24 AD8067 100 G = +10 6.6 QUIESCENT CURRENT – mA 6.7 VS = ±12V VS = ±5V VS = +5V OUTPUT IMPEDANCE – Ω 10 6.5 6.4 6.3 6.2 6.1 6.0 –40 1 0.1 0.01 0.001 0.01 –20 0 0.1 1 10 FREQUENCY – MHz 100 1000 20 40 TEMPERATURE – °C 60 80 Figure 28. Output Impedance vs. Frequency 0.30 Figure 31. Quiescent Current vs. Temperature for Various Supply Voltages 200 OUTPUT SATURATION VOLTAGE – mV RL = 1kΩ (VCC – VOH), (VOL – VEE), VS = ±12V OUTPUT SATURATION VOLTAGE – V 0.25 VCC – VOH 0.20 VOL – VEE 0.15 180 160 140 120 100 80 60 40 20 0 –40 –20 (VCC – VOH), (VOL – VEE), VS = ±5V VCC – VOH, VS = +5V 0.10 0.05 VOL – VEE, VS = +5V 0 0 5 10 15 20 25 ILOAD – mA 30 35 40 0 20 40 TEMPERATURE – °C 60 80 Figure 29. Output Saturation Voltage vs. Output Load Current 0 Figure 32. Output Saturation Voltage vs. Temperature 140 –10 130 –20 –30 120 OPEN-LOOP GAIN – dB –PSRR VS = ±12V 110 100 90 VS = ±5V 80 70 60 VS = +5V PSRR – dB –40 –50 –60 –70 –80 –90 +PSRR –100 0.01 0.1 1 FREQUENCY – MHz 10 100 50 0 5 10 15 20 25 ILOAD – mA 30 35 40 Figure 30. PSRR vs. Frequency Figure 33. Open-Loop Gain vs. Load Current for Various Supplies Rev. A | Page 11 of 24 AD8067 TEST CIRCUITS +VCC 10μF + 0.1μF 110Ω 1kΩ +VCC 10μF + 0.1μF 110Ω 1kΩ 4 5 VIN 1 4 5 VIN 49.9Ω 3 AD8067 2 VOUT RL = 1kΩ 110Ω 1kΩ AD8067 3 2 VOUT 1 1kΩ 0.1μF 10μF + 0.1μF 10μF + AV = 10 –VEE –VEE Figure 34. Standard Test Circuit +VCC Figure 37. CMRR Test Circuit VIN 10μF + 0.1μF 110Ω V– 1kΩ 110Ω 1kΩ +VCC 4 5 AD8067 4 5 1 VOUT 1kΩ 3 1 100Ω 3 AD8067 2 VOUT 2 100Ω 1kΩ 0.1μF 10μF + 0.1μF 10μF VOUT AOL = V– –VEE + –VEE Figure 35. Open-Loop Gain Test Circuit +VCC 10μF + 0.1μF 110Ω 1kΩ Figure 38. Positive PSRR Test Circuit +VCC 10μF + 0.1μF 110Ω 1kΩ 4 5 4 5 VIN 49.9Ω 3 AD8067 2 RSNUB 1 VOUT CLOAD 1kΩ 100Ω 3 AD8067 2 VOUT 1 NETWORK ANALYZER 0.1μF 10μF + –VEE 0.1μF 10μF + AV = 10 –VEE Figure 36. Test Circuit for Capacitive Load Figure 39. Output Impedance Test Circuit Rev. A | Page 12 of 24 AD8067 THEORY OF OPERATION The AD8067 is a low noise, wideband, voltage feedback operational amplifier that combines a precision JFET input stage with Analog Devices’ dielectrically isolated eXtra Fast Complementary Bipolar (XFCB) process BJTs. Operating supply voltages range from 5 V to 24 V. The amplifier features a patented rail-to-rail output stage capable of driving within 0.25 V of either power supply while sourcing or sinking 30 mA. The JFET input, composed of N-channel devices, has a common-mode input range that includes the negative supply rail and extends to 3 V below the positive supply. In addition, the potential for phase reversal behavior was eliminated for all input voltages within the power supplies. The combination of low noise, dc precision, and high bandwidth makes the AD8067 uniquely suited for wideband, very high input impedance, high gain buffer applications. It is also useful in wideband transimpedance applications, such as a photodiode interface, that require very low input currents and dc precision. 90 80 70 PHASE PHASE – Degrees 120 90 60 30 0 –30 GAIN –60 –90 –120 –150 0.1 1 10 FREQUENCY – MHz 100 –180 1000 60 GAIN – dB 50 40 30 20 10 0 –10 0.01 Figure 41. Open-Loop Frequency Response BASIC FREQUENCY RESPONSE The AD8067’s typical open-loop response (see Figure 41) shows a phase margin of 60° at a gain of +10. Typical configurations for noninverting and inverting voltage gain applications are shown in Figure 40 and Figure 42. The closed-loop frequency response of a basic noninverting gain configuration can be approximated by: Closed Loop–3 dB Frequency = (GBP ) × RG (RF + RG ) The bandwidth formula only holds true when the phase margin of the application approaches 90°, which it will in high gain configurations. The bandwidth of the AD8067 used in a G = +10 buffer is 54 MHz, considerably faster than the 30 MHz predicted by the closed loop –3 dB frequency equation. This extended bandwidth is due to the phase margin being at 60° instead of 90°. Gains lower than +10 show an increased amount of peaking, as shown in Figure 4. For gains lower than +7, use the AD8065, a unity gain stable JFET input op amp with a unity gain bandwidth of 145 MHz, or refer to the Applications section for using the AD8067 in a gain of 2 configuration. Table 5. Recommended Values of RG and RF Gain 10 20 50 100 RG (Ω) 110 49.9 20 10 RF (kΩ) 1 1 1 1 BW (MHz) 54 15 6 3 DC Gain = RF/RG + 1 GBP is the gain bandwidth product of the amplifier. Typical GBP for the AD8067 is 300 MHz. See Table 5 for the recommended values for RG and RF. Noninverting Configuration Noise Gain = +VS RS VI RX + RF +1 RG +VS 0.1μF + 10μF RX + 0.1μF + 10μF AD8067 – 0.1μF 10μF + RLOAD + VOUT – AD8067 – RLOAD 0.1μF –VS RF RG SIGNAL SOURCE 10μF + + VOUT – RS VI RG –VS RF FOR BEST PERFORMANCE, SET RS + RX = RG || RF SIGNAL SOURCE FOR BEST PERFORMANCE, SET RX = (RS + RG) || RF Figure 40. Noninverting Gain Configuration Figure 42. Inverting Gain Configuration Rev. A | Page 13 of 24 AD8067 For inverting voltage gain applications, the source impedance of the input signal must be considered because it sets the application’s noise gain as well as the apparent closed-loop gain. The basic frequency equation for inverting applications is RS + VI – – SIGNAL SOURCE CPAR RG RF CPAR + CM CD CM + VOUT – RG + RS Closed-Loop –3 dB Frequency = (GBP ) × R F + R G + RS RF DC Gain = – RG + RS where GBP is the gain bandwidth product of the amplifier, and RS is the signal source resistance. Inverting Configuration Noise Gain = RF + RG + RS RG + RS Figure 43. Input and Board Capacitances It is important that the noise gain for inverting applications be kept above 6 for stability reasons. If the signal source driving the inverter is another amplifier, take care that the driving amplifier shows low output impedance through the frequency span of the expected closed-loop bandwidth of the AD8067. RESISTOR SELECTION FOR WIDEBAND OPERATION Voltage feedback amplifiers can use a wide range of resistor values to set their gain. Proper design of the application’s feedback network requires consideration of the following issues: • • • • There is a pole in the feedback loop response formed by the source impedance seen by the amplifier’s negative input (RG ⎢⎢RF) and the sum of the amplifier’s differential input capacitance, common-mode input capacitance, and any board parasitic capacitance. This decreases the loop phase margin and can cause stability problems, that is, unacceptable peaking and ringing in the response. To avoid this problem, it is recommended that the resistance at the AD8067’s negative input be kept below 200 Ω for all wideband voltage gain applications. Matching the impedances at the inputs of the AD8067 is also recommended for wideband voltage gain applications. This minimizes nonlinear common-mode capacitive effects that can significantly degrade settling time and distortion performance. The AD8067 has a low input voltage noise of 6.6 nV/√Hz. Source resistances greater than 500 Ω at either input terminal notably increases the apparent referred-to-input (RTI) voltage noise of the application. The amplifier must supply output current to its feedback network, as well as to the identified load. For instance, the load resistance presented to the amplifier in Figure 40 is RLOAD ⎪⎪ (RF + RG). For an RLOAD of 100 Ω, RF of 1 kΩ, and RG of 100 Ω, the amplifier is driving a total load resistance of about 92 Ω. This becomes more of an issue as RF decreases. The AD8067 is rated to provide 30 mA of low distortion output current. Heavy output drive requirements also increase the part’s power dissipation and should be taken into account. Poles formed by the amplifier’s input capacitances with the resistances seen at the amplifier’s input terminals Effects of mismatched source impedances Resistor value impact on the application’s output voltage noise Amplifier loading effects The AD8067 has common-mode input capacitances (CM) of 1.5 pF and a differential input capacitance (CD) of 2.5 pF. This is illustrated in Figure 43. The source impedance driving the positive input of a noninverting buffer forms a pole primarily with the amplifier’s common-mode input capacitance as well as any parasitic capacitance due to the board layout (CPAR). This limits the obtainable bandwidth. For G = +10 buffers, this bandwidth limit becomes apparent for source impedances >1 kΩ. Rev. A | Page 14 of 24 AD8067 DC ERROR CALCULATIONS Figure 44 illustrates the primary dc errors associated with a voltage feedback amplifier. For both inverting and noninverting configurations: INPUT AND OUTPUT OVERLOAD BEHAVIOR A simplified schematic of the AD8067 input stage is shown in Figure 45. This shows the cascoded N-channel JFET input pair, the ESD and other protection diodes, and the auxiliary NPN input stage that eliminates phase inversion behavior. When the common-mode input voltage to the amplifier is driven to within approximately 3 V of the positive power supply, the input JFET’s bias current turns off, and the bias of the NPN pair turns on, taking over control of the amplifier. The NPN differential pair now sets the amplifier’s offset, and the input bias current is now in the range of several tens of microamps. This behavior is illustrated in Figure 25 and Figure 26. Normal operation resumes when the common-mode voltage goes below the 3 V from the positive supply threshold. The output transistors have circuitry included to limit the extent of their saturation when the output is overdriven. This improves output recovery time. A plot of the output recovery time for the AD8067 used as a G = +10 buffer is shown in Figure 17. VCC VTHRESHOLD ⎛ R + RF Output Voltage Error due to VOS = VOS ⎜ G ⎜R G ⎝ ⎞ ⎟ ⎟ ⎠ ⎞ ⎟ – I B– × RF ⎟ ⎠ ⎛ R + RG Output Voltage Error due to I B = I B + × RS ⎜ F ⎜R G ⎝ Total error is the sum of the two. DC common-mode and power supply effects can be added by modeling the total VOS with the expression: VOS (tot ) = VOS (nom) + ΔVS ΔVCM + PSR CMR where: VOS (nom) is the offset voltage specified at nominal conditions (1 mV max). ΔVS is the change in power supply voltage from nominal conditions. TO REST OF AMP PSR is power supply rejection (90 dB minimum). ΔVCM is the change in common-mode voltage from nominal test conditions. SWITCH CONTROL VCC VCC VN VP VBIAS CMR is the common-mode rejection (85 dB minimum for the AD8067). RF VEE VEE RG +VOS– – IB– + VOUT – VEE – VI + RS + IB+ Figure 45. Simplified Input Schematic Figure 44. Op Amp DC Error Sources Rev. A | Page 15 of 24 AD8067 INPUT PROTECTION The inputs of the AD8067 are protected with back-to-back diodes between the input terminals as well as ESD diodes to either power supply. The result is an input stage with picoamp level input currents that can withstand 2 kV ESD events (human body model) with no degradation. Excessive power dissipation through the protection devices destroys or degrades the performance of the amplifier. Differential voltages greater than 0.7 V result in an input current of approximately (| V+ – V− | − 0.7 V)/(RI + RG)), where RI and RG are the resistors (see Figure 46). For input voltages beyond the positive supply, the input current is about (VI – VCC – 0.7 V)/RI. For input voltages beyond the negative supply, the input current is about (VI – VEE + 0.7 V)/RI. For any of these conditions, RI should be sized to limit the resulting input current to 50 mA or less. – VI + RI RI > (VI – VEE + 0.7V)/50mA RI > (VI – VCC – 0.7V)/50mA FOR VI BEYOND + SUPPLY VOLTAGES VOUT – LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS Layout In extremely low input bias current amplifier applications, stray leakage current paths must be kept to a minimum. Any voltage differential between the amplifier inputs and nearby traces sets up a leakage path through the PCB. Consider a 1 V signal and 100 GΩ to ground present at the input of the amplifier. The resultant leakage current is 10 pA; this is 10× the input bias current of the amplifier. Poor PCB layout, contamination, and the board material can create large leakage currents. Common contaminants on boards are skin oils, moisture, solder flux, and cleaning agents. Therefore, it is imperative that the board be thoroughly cleaned and the board surface be free of contaminants to fully take advantage of the AD8067’s low input bias currents. To significantly reduce leakage paths, a guard-ring/shield around the inputs should be used. The guard-ring circles the input pins and is driven to the same potential as the input signal, thereby reducing the potential difference between pins. For the guard ring to be completely effective, it must be driven by a relatively low impedance source and should completely surround the input leads on all sides, above, and below, using a multilayer board (see Figure 47). The SOT-23-5 package presents a challenge in keeping the leakage paths to a minimum. The pin spacing is very tight, so extra care must be used when constructing the guard ring (see Figure 48 for recommended guard-ring construction). GUARD RING AD8067 RI > ( |V+ – V– | –0.7V)/50mA FOR LARGE |V+ – V– | RG RF Figure 46. Current Limiting Resistor CAPACITIVE LOAD DRIVE Capacitive load introduces a pole in the amplifier loop response due to the finite output impedance of the amplifier. This can cause excessive peaking and ringing in the response. The AD8067 with a gain of +10 handles up to a 30 pF capacitive load without an excessive amount of peaking (see Figure 8). If greater capacitive load drive is required, consider inserting a small resistor in series with the load (24.9 Ω is a good value to start with). Capacitive load drive capability also increases as the gain of the amplifier increases. GUARD RING INVERTING NONINVERTING Figure 47. Guard-Ring Configurations VOUT +V VOUT AD8067 –V –V AD8067 +V +IN –IN +IN –IN INVERTING NONINVERTING Figure 48. Guard-Ring Layout SOT-23-5 Rev. A | Page 16 of 24 AD8067 Grounding To minimize parasitic inductances and ground loops in high speed, densely populated boards, a ground plane layer is critical. Understanding where the current flows in a circuit is critical in the implementation of high speed circuit design. The length of the current path is directly proportional to the magnitude of the parasitic inductances and thus the high frequency impedance of the path. Fast current changes in an inductive ground return creates unwanted noise and ringing. The length of the high frequency bypass capacitor leads is critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Because load currents flow from supplies as well as ground, the load should be placed at the same physical location as the bypass capacitor ground. For large values of capacitors, which are intended to be effective at lower frequencies, the current return path length is less critical. Power Supply Bypassing Power supply pins are actually inputs and care must be taken to provide a clean, low noise dc voltage source to these inputs. The bypass capacitors have two functions: • Provide a low impedance path for unwanted frequencies from the supply inputs to ground, thereby reducing the effect of noise on the supply lines • Provide localized charge storage—this is usually accomplished with larger electrolytic capacitors Decoupling methods are designed to minimize the bypassing impedance at all frequencies. This can be accomplished with a combination of capacitors in parallel to ground. Good quality ceramic chip capacitors (X7R or NPO) should be used and always kept as close to the amplifier package as possible. A parallel combination of a 0.1 μF ceramic and a 10 μF electrolytic, covers a wide range of rejection for unwanted noise. The 10 μF capacitor is less critical for high frequency bypassing, and in most cases, one per supply line is sufficient. Rev. A | Page 17 of 24 AD8067 APPLICATIONS WIDEBAND PHOTODIODE PREAMP CF RF The preamp’s output noise over frequency is shown in Figure 50. Table 6. RMS Noise Contributions of Photodiode Preamp RMS Noise (μV)1 152 4.3 96 f 2 – f1 – CM IPHOTO VB CF + CS CS RSH = 1011Ω + CD CM VOUT Contributor RF × 2 Amp to f1 Amp (f2 − f1) Amp (Past f2) Expression 2 × 4kT × R F × f 2 × 1.57 VNOISE × f 1 AD8067 RF VNOISE × (C S + C M + C F + 2C D ) × CF VNOISE × (C S + C M + C F + 2C D ) × CF f 3 × 1.57 684 708 Figure 49. Wideband Photodiode Preamp 1 RSS Total Figure 49 shows an I/V converter with an electrical model of a photodiode. The basic transfer function is RMS noise with RF = 50 kΩ, CS = 0.67 pF, CF = 0.33 pF, CM = 1.5 pF, and CD = 2.5 pF. f1 = 2 πR (C + C + C + 2C ) FF S M D f2 = VOLTAGE NOISE – nV/ Hz 1 VOUT = I PHOTO × RF 1 + sC F RF 1 2 πR F C F GBP f3 = (C + C + 2C + C )/C S M D F F where IPHOTO is the output current of the photodiode, and the parallel combination of RF and CF sets the signal bandwidth. The stable bandwidth attainable with this preamp is a function of RF, the gain bandwidth product of the amplifier, and the total capacitance at the amplifier’s summing junction, including CS and the amplifier input capacitance. RF and the total capacitance produce a pole in the amplifier’s loop transmission that can result in peaking and instability. Adding CF creates a zero in the loop transmission that compensates for the pole’s effect and reduces the signal bandwidth. It can be shown that the signal bandwidth resulting in a 45° phase margin (f(45)) is defined by f ( 45 ) = GBP 2π × RF × C S RF NOISE f2 f1 VEN VEN (C F + C S + C M + 2C D )/C F f3 NOISE DUE TO AMPLIFIER FREQUENCY – Hz Figure 50. Photodiode Voltage Noise Contributions GBP is the unit gain bandwidth product, RF is the feedback resistance, and CS is the total capacitance at the amplifier summing junction (amplifier + photodiode + board parasitics). The value of CF that produces f(45) can be shown to be CF = CS 2π × R F × GBP Figure 51 shows the AD8067 configured as a transimpedance photodiode amplifier. The amplifier is used in conjunction with a JDS uniphase photodiode detector. This amplifier has a bandwidth of 9.6 MHz, as shown in Figure 52, and is verified by the design equations shown in Figure 50. 0.33pF 49.9kΩ +5V 10μF –5V 0.1μF EPM 605 LL The frequency response in this case shows about 2 dB of peaking and 15% overshoot. Doubling CF and cutting the bandwidth in half results in a flat frequency response, with about 5% transient overshoot. AD8067 0.1μF 50Ω VOUT 0.33pF NOTES ID @ –5V = 0.074nA CD @ –5V = 0.690pF RB @ 1550nm = –49dB 49.9kΩ 10μF –5V Figure 51. Photodiode Preamplifier Rev. A | Page 18 of 24 AD8067 Test data for the preamp is shown in Figure 52 and Figure 53. 100 95 TRANSIMPEDANCE GAIN – dB USING THE AD8067 AT GAINS OF LESS THAN 8 A common technique used to stabilize de-compensated amplifiers is to increase the noise gain, independent of the signal gain. The AD8067 can be used in applications where the signal gain is less than 8, if proper care is taken to ensure that the noise gain of the amplifier is set to at least the recommended minimum signal gain of 8 (see Figure 54). The signal and noise gain equations for a noninverting amplifier are: Signal Gain = 1 + Noise Gain = 1 + R3 R1 90 85 80 75 70 65 60 0.01 R3 R1 0.1 1 FREQUENCY – MHz 10 100 Figure 52. Photodiode Preamplifier Frequency Response The addition of resistor R2 modifies the noise gain equation. Note the signal gain equation has not changed. Noise Gain = 1 + R3 R1 || R2 R3 600Ω +5V C1 10μF C1 RISE 31.2ns T R1 301Ω 4 R2 50Ω 5 C2 0.1μF 1 C4 0.1μF C1 FALL 31.6ns AD8067 3 2 R4 51Ω VOUT VIN RL CH1 500mV M 50ns CH1 830mV –5V C3 10μF Figure 53. Photodiode Preamplifier Pulse Response Figure 54. Gain of Less than 2 Schematic This technique allows the designer to use the AD8067 in gain configurations of less than 8. The drawback to this type of compensation is that the input noise and offset voltages are also amplified by the value of the noise gain. In addition, the distortion performance is degraded. To avoid excessive overshoot and ringing when driving a capacitive load, the AD8067 should be buffered by a small series resistor; in this case, a 51 Ω resistor was used. Rev. A | Page 19 of 24 AD8067 Reference network: VOUT V+REF − 3 dB Bandwidth = 1 2π(R2 || R3)C2 T VIN Resistors R4 and R1 set the gain, in this case, an inverting gain of 10 was selected. In this application, the input and output bandwidths were set for approximately 10 Hz. The reference network was set for a tenth of the input and output bandwidth, at approximately 1 Hz. R4 2.7kΩ +5V C3 10μF CH1 200mV CH2 200mV M 50ns CH1 288mV Figure 55. Gain of 2 Pulse Response C1 47μF VIN R1 300Ω 4 5 C4 0.1μF 1 C5 15μF SINGLE-SUPPLY OPERATION The AD8067 is well suited for low voltage single-supply applications, given its N-channel JFET input stage and rail-torail output stage. It is fully specified for 5 V supplies. Successful single-supply applications require attention to keep signal voltages within the input and output headroom limits of the amplifier. The input stage headroom extends to 1.7 V (minimum) on a 5 V supply. The center of the input range is 0.85 V. The output saturation limit defines the hard limit of the output headroom. This limit depends on the amount of current the amplifier is sourcing or sinking, as shown in Figure 29. Traditionally, an offset voltage is introduced in the input network replacing ground as a reference. This allows the output to swing about a dc reference point, typically midsupply. Attention to the required headroom of the amplifier is important, in this case, the required headroom from the positive supply is 3 V; therefore, 1.5 V was selected as a reference, which allows for a 100 mV signal at the input. Figure 56 shows the AD8067 configured for 5 V supply operation with a reference voltage of 1.5 V. Capacitors C1 and C5 ac couple the signal into and out of the amplifier and partially determine the bandwidth of the input and output structures. VINPUT – 3 dB Bandwidth = 1 2πR1C1 R2 70kΩ +5V C2 6.8μF R3 30kΩ AD8067 3 2 VOUT RL 1kΩ Figure 56. Single-Supply Operation Schematic HIGH GAIN, HIGH BANDWIDTH COMPOSITE AMPLIFIER The composite amplifier takes advantage of combining key parameters that can otherwise be mutually exclusive of a conventional single amplifier. For example, most precision amplifiers have good dc characteristics but lack high speed ac characteristics. Composite amplifiers combine the best of both amplifiers to achieve superior performance over their single op amp counterparts. The AD8067 and the AD8009 are well suited for a composite amplifier circuit, combining dc precision with high gain and bandwidth. The circuit runs off a ±5 V power supply at approximately 20 mA of bias current. With a gain of approximately 40 dB, the composite amplifier offers