High Common-Mode Voltage, Single-Supply Difference Amplifier AD8202
FEATURES
High common-mode voltage range −8 V to +28 V at a 5 V supply voltage Operating temperature range: −40°C to +125°C Supply voltage range: 3.5 V to 12 V Low-pass filter (1-pole or 2-pole) Excellent ac and dc performance ±1 mV voltage offset ±1 ppm/°C typical gain drift 80 dB CMRR min dc to 10 kHz
FUNCTIONAL BLOCK DIAGRAMS
NC
7
A1
3
A2
4
+VS
6
100kΩ G = ×10 +IN 8 –IN 1 200kΩ +IN A1 –IN 200kΩ G = ×2 +IN A2 –IN
AD8202
5
OUT
10kΩ
10kΩ
04981-001
APPLICATIONS
Transmission control Diesel injection control Engine management Adaptive suspension control Vehicle dynamics control
NC = NO CONNECT
2
GND
Figure 1. SOIC (R) Package Die Form
INDUCTIVE LOAD
CLAMP DIODE
5V OUTPUT
+IN
NC
+VS OUT
GENERAL DESCRIPTION
The AD8202 is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage (CMV). The input CMV range extends from −8 V to +28 V at a typical supply voltage of 5 V. The AD8202 is available in die and packaged form. The MSOP and SOIC packages are specified over a wide temperature range, from −40°C to +125°C, making the AD8202 well-suited for use in many automotive platforms. Automotive platforms demand precision components for better system control. The AD8202 provides excellent ac and dc performance keeping errors to a minimum in the user’s system. Typical offset and gain drift in the SOIC package are 0.3 μV/°C and 1 ppm/°C, respectively. Typical offset and gain drift in the MSOP package are 2 μV/°C and 1 ppm/°C, respectively. The device also delivers a minimum CMRR of 80 dB from dc to 10 kHz. The AD8202 features an externally accessible 100 kΩ resistor at the output of the Preamp A1 that can be used for low-pass filter applications and for establishing gains other than 20.
BATTERY
14V 4-TERM SHUNT
AD8202
–IN GND A1 A2
POWER DEVICE
COMMON
NC = NO CONNECT
Figure 2. High Line Current Sensor
POWER DEVICE 5V OUTPUT
+IN NC +VS OUT
BATTERY
14V 4-TERM SHUNT
AD8202
–IN GND A1 A2
CLAMP DIODE
INDUCTIVE LOAD
04981-003
COMMON
NC = NO CONNECT
Figure 3. Low Line Current Sensor
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
04981-002
AD8202 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams............................................................. 1 Specifications..................................................................................... 3 Single Supply ................................................................................. 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ...................................................................... 12 Applications..................................................................................... 14 Current Sensing .......................................................................... 14 Gain Adjustment ........................................................................ 14 Gain Trim .................................................................................... 15 Low-Pass Filtering...................................................................... 15 High Line Current Sensing with LPF and Gain Adjustment 16 Driving Charge Redistribution ADCs..................................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17
REVISION HISTORY
11/05—Rev. C to Rev. D Updated Format..................................................................Universal Changes to Typical Performance Characteristics ........................ 6 Added Figure 18................................................................................ 8 Added Figure 25 to Figure 27.......................................................... 9 Added Figure 32.............................................................................. 10 Added Figure 37 to Figure 39........................................................ 11 Changes to Theory of Operation.................................................. 12 Added Figure 41.............................................................................. 13 2/05—Rev. B to Rev. C Changes to Table 1............................................................................ 3 Changes to Figure 14........................................................................ 8 Changes to Figure 22........................................................................ 9 1/05—Rev. A to Rev. B Changes to the General Description.............................................. 1 Changes to Specifications ................................................................ 3 Added Figure 14 to Figure 33.......................................................... 8 Changes to Figure 38...................................................................... 14 Changes to Figure 40 and Figure 41............................................. 15 Changes to Ordering Guide .......................................................... 16 11/04—Rev. 0 to Rev. A Changes to the Features....................................................................1 Changes to the General Description...............................................1 Changes to Specifications (Table 1) ................................................3 Changes to Absolute Maximum Ratings (Table 2) .......................4 Changes to Pin Function Descriptions (Table 3) ..........................5 Changes to Figure 5...........................................................................5 Changes to Figure 9 and Figure 10..................................................6 Updated Outline Dimensions....................................................... 12 Changes to the Ordering Guide ................................................... 12 7/04—Revision 0: Initial Version
Rev. D | Page 2 of 20
AD8202 SPECIFICATIONS
SINGLE SUPPLY
TA = operating temperature range, VS = 5 V, unless otherwise noted. Table 1.
Parameter SYSTEM GAIN Initial Error vs. Temperature VOLTAGE OFFSET Input Offset (RTI) vs. Temperature INPUT Input Impedance Differential Common Mode CMV CMRR1 Conditions AD8202 SOIC Min Typ Max 20 0.02 ≤ VOUT ≤ 4.8 V dc @ 25°C −0.3 1 VCM = 0.15 V; 25°C −40°C to +125°C −40°C to +150°C −1 −10 +0.3 20 +1 +10 −2 −20 AD8202 MSOP Min Typ Max 20 −0.3 1 25 +2 +20 −1 −10 −15 1 AD8202 Die Min Typ Max 20 +0.3 30 +1 +10 +15 Unit V/V % ppm/°C mV μV/°C μV/°C
+0.3
+2
+0.3 +5
Continuous VCM = −8 V to +28 V f = dc f = 1 kHz f = 10 kHz 2
260 135 −8 82 82 80
325 170
390 205 +28
260 135 −8 82 82 80
325 170
390 205 +28
260 135 −8 82 82 80
325 170
390 205 +28
kΩ kΩ V dB dB dB
PREAMPLIFIER Gain Gain Error Output Voltage Range Output Resistance OUTPUT BUFFER Gain Gain Error Output Voltage Range Input Bias Current Output Resistance DYNAMIC RESPONSE System Bandwidth Slew Rate NOISE 0.1 Hz to 10 Hz Spectral Density, 1 kHz (RTI) POWER SUPPLY Operating Range Quiescent Current vs. Temperature PSRR TEMPERATURE RANGE For Specified Performance
1 2
10 −0.3 0.02 97 +0.3 4.8 103 −0.3 0.02 97
10 +0.3 4.8 103 −0.3 0.02 97
10 +0.3 4.8 103
100 2
100 2
100 2
V/V % V kΩ V/V % V nA Ω kHz V/μs μV p-p nV/√Hz
0.02 ≤ VOUT ≤ 4.8 V dc
−0.3 0.02 40 2
+0.3 4.8
−0.3 0.02 40 2 30 50 0.28 10 275
+0.3 4.8
−0.3 0.02 40 2 30 50 0.28 10 275
+0.3 4.8
VIN = 0.1 V p-p; VOUT = 2.0 V p-p VIN = 0.2 V dc; VOUT = 4 V step
30
50 0.28 10 275
3.5 VO = 0.1 V dc VS = 3.5 V to 12 V 75 −40 0.25 83
12 1.0
3.5 0.25 75 83
12 1.0
3.5 0.25 75 83
12 1.0
V mA dB
+125
−40
+125
−40
+150
°C
Source imbalance 20
Rev. D | Page 14 of 20
04981-017
AD8202
GAIN TRIM
Figure 45 shows a method for incremental gain trimming by using a trim potentiometer and external resistor, REXT. The following approximation is useful for small gain ranges: ΔG ≈ (10 MΩ/REXT)% Thus, the adjustment range is ±2% for REXT = 5 MΩ; ±10% for REXT = 1 MΩ, and so on.
5V OUT
+IN NC +VS OUT +IN NC +VS OUT
Low-pass filters can be implemented in several ways by using the AD8202. In the simplest case, a single-pole filter (20 dB/decade) is formed when the output of A1 is connected to the input of A2 via the internal 100 kΩ resistor by tying Pin 3 and Pin 4 and adding a capacitor from this node to ground, as shown in Figure 46. If a resistor is added across the capacitor to lower the gain, the corner frequency increases; it should be calculated using the parallel sum of the resistor and 100 kΩ.
5V OUTPUT VDIFF 2
VDIFF 2
AD8202 AD8202
VCM VDIFF 2
–IN –IN GND A1 A2 GND A1 A2
fC =
1 2πC105
C IN FARADS
VCM
VDIFF 2 GAIN TRIM 20kΩ MIN
REXT
C
04981-018
NC = NO CONNECT
NC = NO CONNECT
Figure 46. Single-Pole, Low-Pass Filter Using the Internal 100 kΩ Resistor
Figure 45. Incremental Gain Trim
Internal Signal Overload Considerations
When configuring gain for values other than 20, the maximum input voltage with respect to the supply voltage and ground must be considered because either the preamplifier or the output buffer reaches its full-scale output (approximately VS − 0.2 V) with large differential input voltages. The input of the AD8202 is limited to (VS − 0.2)/10 for overall gains ≤ 10 because the preamplifier, with its fixed gain of ×10, reaches its fullscale output before the output buffer. For gains greater than 10, the swing at the buffer output reaches its full scale first and limits the AD8202 input to (VS − 0.2)/G, where G is the overall gain.
If the gain is raised using a resistor, as shown in Figure 44, the corner frequency is lowered by the same factor as the gain is raised. Thus, using a resistor of 200 kΩ (for which the gain would be doubled), the corner frequency is now 0.796 Hz/μF (0.039 μF for a 20 Hz corner frequency).
5V OUT
+IN NC +VS OUT
VDIFF 2
AD8202
VCM VDIFF 2
–IN GND A1 A2
C
LOW-PASS FILTERING
In many transducer applications, it is necessary to filter the signal to remove spurious high frequency components including noise, or to extract the mean value of a fluctuating signal with a peak-to-average ratio (PAR) greater than unity. For example, a full-wave rectified sinusoid has a PAR of 1.57, a raised cosine has a PAR of 2, and a half-wave sinusoid has a PAR of 3.14. Signals having large spikes can have PARs of 10 or more. When implementing a filter, the PAR should be considered so that the output of the AD8202 preamplifier (A1) does not clip before A2 because this nonlinearity would be averaged and appear as an error at the output. To avoid this error, both amplifiers should clip at the same time. This condition is achieved when the PAR is no greater than the gain of the second amplifier (2 for the default configuration). For example, if a PAR of 5 is expected, the gain of A2 should be increased to 5.
C NC = NO CONNECT
255kΩ fC(Hz) = 1/C(μF)
04981-020
Figure 47. 2-Pole, Low-Pass Filter
A 2-pole filter (with a roll-off of 40 dB/decade) can be implemented using the connections shown in Figure 47. This is a Sallen-Key form based on a ×2 amplifier. It is useful to remember that a 2-pole filter with a corner frequency f2 and a 1-pole filter with a corner at f1 have the same attenuation at the frequency (f22/f1). The attenuation at that frequency is 40 log (f2/f1), which is illustrated in Figure 48. Using the standard resistor value shown and equal capacitors (see Figure 47), the corner frequency is conveniently scaled at 1 Hz/μF (0.05 μF for a 20 Hz corner). A maximally flat response occurs when the resistor is lowered to 196 kΩ and the scaling is then 1.145 Hz/μF. The output offset is raised by approximately 5 mV (equivalent to 250 μV at the input pins).
Rev. D | Page 15 of 20
04981-019
AD8202
FREQUENCY
ATTENUATION
40dB/DECADE 20dB/DECADE
by a 1-pole low-pass filter, set with a corner frequency of 3.6 Hz, providing about 30 dB of attenuation at 100 Hz. A higher rate of attenuation can be obtained using a 2-pole filter with fC = 20 Hz, as shown in Figure 50. Although this circuit uses two separate capacitors, the total capacitance is less than half that needed for the 1-pole filter.
INDUCTIVE LOAD 5V OUTPUT
+IN NC +VS OUT
40LOG (f2/f1)
CLAMP DIODE
04981-021
A 1-POLE FILTER, CORNER f1, AND A 2-POLE FILTER, CORNER f2, HAVE THE SAME ATTENUATION –40LOG (f2/f1) AT FREQUENCY f22/f1 f1 f2 f22/f1
BATTERY
14V 4-TERM SHUNT
432kΩ
AD8202
–IN GND A1 A2
C 50kΩ
Figure 48. Comparative Responses of 1-Pole and 2-Pole Low-Pass Filters
POWER DEVICE
127kΩ C
NC = NO CONNECT
COMMON
fC(Hz) = 1/C(μF) (0.05μF FOR fC = 20Hz)
Figure 49 is another refinement of Figure 2, including gain adjustment and low-pass filtering.
CLAMP DIODE INDUCTIVE LOAD 5V OUT 4V/AMP
Figure 50. 2-Pole Low-Pass Filter
DRIVING CHARGE REDISTRIBUTION ADCS
+VS OUT
+IN
NC
BATTERY
14V 4-TERM SHUNT
191kΩ
AD8202
20kΩ
–IN GND A1 A2
POWER DEVICE
VOS/IB NULL C
NC = NO CONNECT
COMMON
5% CALIBRATION RANGE fC(Hz) = 0.796Hz/C(μF) (0.22μF FOR fC = 3.6Hz)
Figure 49. High Line Current Sensor Interface; Gain = ×40, Single-Pole, Low-Pass Filter
When driving CMOS ADCs, such as those embedded in popular microcontrollers, the charge injection (ΔQ) can cause a significant deflection in the output voltage of the AD8202. Though generally of short duration, this deflection can persist until after the sample period of the ADC expires due to the relatively high open-loop output impedance (typically 21 kΩ) of the AD8202. Including an R-C network in the output can significantly reduce the effect. The capacitor helps to absorb the transient charge, effectively lowering the high frequency output impedance of the AD8202. For these applications, the output signal should be taken from the midpoint of the RLAG − CLAG combination, as shown in Figure 51. Because the perturbations from the analog-to-digital converter are small, the output impedance of the AD8202 appears to be low. The transient response, therefore, has a time constant governed by the product of the two LAG components, CLAG × RLAG. For the values shown in Figure 51, this time constant is programmed at approximately 10 μs. Therefore, if samples are taken at several tenths of microseconds or more, there is negligible charge stack-up.
5V
4 6
A power device that is either on or off controls the current in the load. The average current is proportional to the duty cycle of the input pulse and is sensed by a small value resistor. The average differential voltage across the shunt is typically 100 mV, although its peak value is higher by an amount that depends on the inductance of the load and the control frequency. The common-mode voltage, conversely, extends from roughly 1 V above ground for the on condition to about 1.5 V above the battery voltage in the off condition. The conduction of the clamping diode regulates the common-mode potential applied to the device. For example, a battery spike of 20 V can result in an applied common-mode potential of 21.5 V to the input of the devices. To produce a full-scale output of 4 V, a gain ×40 is used, adjustable by ±5% to absorb the tolerance in the shunt. Sufficient headroom allows 10% overrange (to 4.4 V). The roughly triangular voltage across the sense resistor is averaged
04981-022
+IN
AD8202
A2
5
RLAG 1kΩ CLAG 0.01μF
MICROPROCESSOR A/D
–IN
10kΩ
10kΩ
2
04981-024
Figure 51. Recommended Circuit for Driving CMOS A/D
Rev. D | Page 16 of 20
04981-023
HIGH LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT
AD8202 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5 4
8
3.20 3.00 2.80
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440) 5.80 (0.2284)
3.20 3.00 2.80
5
1
5.15 4.90 4.65
4
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) × 45° 0.25 (0.0099)
0.95 0.85 0.75
PIN 1 0.65 BSC 1.10 MAX 8° 0° 0.80 0.60 0.40
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8° 0.25 (0.0098) 0° 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
0.15 0.00
0.38 0.22 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.23 0.08
COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
Figure 53. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8202YR AD8202YR-REEL AD8202YR-REEL7 AD8202YRZ 1 AD8202YRZ-RL1 AD8202YRZ-R71 AD8202YRMZ1 AD8202YRMZ-RL1 AD8202YRMZ-R71 AD8202YCSURF
1
Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C
Package Description 8 Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8 Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] Die
Package Option R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8
Branding
JWY JWY JWY
Z = Pb-free part.
Rev. D | Page 17 of 20
AD8202 NOTES
Rev. D | Page 18 of 20
AD8202 NOTES
Rev. D | Page 19 of 20
AD8202 NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04981-0-11/05(D)
Rev. D | Page 20 of 20