AD8273

Dual-Channel, Audio Difference Amplifier AD8273 FEATURES Two gain settings Gain of ½ (−6 dB) Gain of 2 (+6 dB) 0.05% maximum gain error 10 ppm maximum gain drift Excellent ac specifications 20 V/μs minimum slew rate 800 ns to 0.01% settling time Low distortion: 0.004%, 20 Hz to 20 kHz High accuracy dc performance 77 dB minimum CMRR 700 μV maximum offset voltage 14-lead SOIC package Supply current: 2.5 mA maximum per channel Supply range: ±2.5 V to ±18 V FUNCTIONAL BLOCK DIAGRAM +VS 11 2 12kΩ 6kΩ 12 13 3 6 12kΩ 12kΩ 6kΩ 6kΩ 14 10 9 4 –VS Figure 1. APPLICATIONS High performance audio Instrumentation amplifier building blocks Level translators Automatic test equipment Sin/Cos encoders GENERAL DESCRIPTION The AD8273 is a low distortion, dual-channel amplifier with internal gain setting resistors. With no external components, it can be configured as a high performance difference amplifier (G = ½ or 2), inverting amplifier (G = ½ or 2), or noninverting amplifier (G = 1½ or 3). The AD8273 operates on both single and dual supplies and only requires 2.5 mA maximum supply current for each amplifier. It is specified over the industrial temperature range of −40°C to +85°C and is fully RoHS compliant. Table 1. Difference Amplifiers by Category Low Distortion AD8270 AD8273 AMP03 High Voltage AD628 AD629 Single-Supply Unidirectional AD8202 AD8203 Single-Supply Bidirectional AD8205 AD8206 AD8216 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. 06981-001 5 12kΩ 6kΩ 8 AD8273 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Maximum Power Dissipation ..................................................... 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions..............................5 Typical Performance Characteristics ..............................................6 Theory of Operation ...................................................................... 11 Configurations............................................................................ 11 Power Supplies ............................................................................ 11 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13 REVISION HISTORY 1/08—Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD8273 SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = ½, RL = 2 kΩ, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Bandwidth Slew Rate Settling Time to 0.1% Settling Time to 0.01% Channel Separation NOISE/DISTORTION 1 THD + Noise Noise Floor, RTO 2 Output Voltage Noise (Referred to Output) GAIN Gain Error Gain Drift Gain Nonlinearity INPUT CHARACTERISTICS Offset 3 vs. Temperature vs. Power Supply Common-Mode Rejection Ratio Input Voltage Range 4 Impedance 5 Differential Common Mode 6 OUTPUT CHARACTERISTICS Output Swing Short-Circuit Current Limit Capacitive Load Drive POWER SUPPLY Supply Current (per Amplifier) TEMPERATURE RANGE Specified Performance 1 2 Conditions Min Typ 20 Max Unit MHz V/μs ns ns dB % dBu μV rms nV/√Hz 20 10 V step on output, CL = 100 pF 10 V step on output, CL = 100 pF f = 1 kHz f = 1 kHz, VOUT = 10 V p-p, 600 Ω load 20 kHz BW f = 20 Hz to 20 kHz f = 1 kHz 670 750 130 0.004 −106 3.5 26 0.05 10 750 800 −40°C to +85°C VOUT = 10 V p-p, 600 Ω load VOUT = 5 V p-p, 600 Ω load Referred to output −40°C to +85°C VS = ±2.5 V to ±18 V VCM = ±40 V, RS = 0 Ω, referred to input 2 200 50 100 3 2 86 % ppm/°C ppm ppm μV μV/°C μV/V dB V kΩ kΩ 700 10 +3VS − 4.5 77 −3VS + 4.5 VCM = 0 V 36 9 −VS + 1.5 +VS − 1.5 100 60 200 1200 2.5 −40 +85 Sourcing Sinking G=½ G=2 V mA mA pF pF mA °C Includes amplifier voltage and current noise, as well as noise of internal resistors. dBu = 20 log (V rms /0.7746). 3 Includes input bias and offset current errors. 4 May also be limited by absolute maximum input voltage or by the output swing. See the Absolute Maximum Ratings section and Figure 9 through Figure 12 for details. 5 Internal resistors are trimmed to be ratio matched but have ±20% absolute accuracy. 6 Common mode is calculated looking into both inputs. Common-mode impedance looking into only one input is 18 kΩ. Rev. 0 | Page 3 of 16 AD8273 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Output Short-Circuit Current Voltage at Any Input Pin Differential Input Voltage Current into Any Input Pin Storage Temperature Range Specified Temperature Range Thermal Resistance θJA θJC Package Glass Transition Temperature (TG) Rating ±18 V Observe derating curve 40 V 40 V 3 mA −65°C to +130°C −40°C to +85°C 105°C/W 36°C/W 150°C MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the AD8273 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a temperature of 150°C for an extended period can result in a loss of functionality. The AD8273 has built-in, short-circuit protection that limits the output current to approximately 100 mA (see Figure 2 for more information). While the short-circuit condition itself does not damage the part, the heat generated by the condition can cause the part to exceed its maximum junction temperature, with corresponding negative effects on reliability. 2.0 TJ MAX = 150°C θJA = 105°C/W MAXIMUM POWER DISSIPATION (W) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1.6 1.2 0.8 0.4 –25 0 25 50 75 100 125 AMBIENT TEMPERATURE (°C) Figure 2. Maximum Power Dissipation vs. Ambient Temperature ESD CAUTION Rev. 0 | Page 4 of 16 06981-043 0 –50 AD8273 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 1 –12A 2 +12A 3 –VS 4 14 13 +6A OUTA –6A AD8273 12 TOP VIEW 11 +VS (Not to Scale) +12B 5 10 –6B –12B 6 NC 7 9 8 OUTB 06981-020 +6B NC = NO CONNECT Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 7 2 3 4 5 6 8 9 10 11 12 13 14 Mnemonic NC −12A +12A −VS +12B −12B +6B OUTB −6B +VS −6A OUTA +6A Description No Connect. The 12 kΩ resistor connects to the negative terminal of Op Amp A. The 12 kΩ resistor connects to the positive terminal of Op Amp A. Negative Supply. The 12 kΩ resistor connects to the positive terminal of Op Amp B. The 12 kΩ resistor connects to the negative terminal of Op Amp B. The 6 kΩ resistor connects to the positive terminal of Op Amp B. Op Amp B Output. The 6 kΩ resistor connects to the negative terminal of Op Amp B. Positive Supply. The 6 kΩ resistor connects to the negative terminal of Op Amp A. Op Amp A Output. The 6 kΩ resistor connects to the positive terminal of Op Amp A. Rev. 0 | Page 5 of 16 AD8273 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±15 V, TA = 25°C, G = ½, difference amplifier configuration, unless otherwise noted. 100 N: 1641 MEAN: –9.5 SD: 228.4 500 400 300 SYSTEM OFFSET (µV) 80 200 100 0 –100 –200 –300 –400 60 75 90 105 120 06981-030 06981-041 HITS 60 40 20 06981-036 0 –500 –250 0 VOSO ±15V (µV/V) 250 500 REPRESENTATIVE SAMPLES –500 –45 –30 –15 0 15 30 45 TEMPERATURE (°C) Figure 4. Typical Distribution of System Offset Voltage, G = ½, Referred to Output N: 1649 MEAN: –0.59 SD: 37.3 Figure 7. System Offset vs. Temperature, Normalized at 25°C, Referred to Output 150 100 50 0 –50 –100 –150 REPRESENTATIVE SAMPLES –200 –45 –30 –15 0 15 30 45 120 100 80 60 40 20 0 –150 GAIN ERROR (µV/V) HITS –100 –50 0 50 100 150 60 75 90 105 120 CMRR ±15V (µV/V) TEMPERATURE (°C) Figure 5. Typical Distribution of CMRR, G = ½, Referred to Input 70 60 INPUT COMMON-MODE VOLTAGE (V) Figure 8. Gain Error vs. Temperature, Normalized at 25°C 50 0, +40 40 30 –13.5, +26.5 20 10 0 –10 –20 –30 –40 0, –40 –13.5, –26.5 +13.5, –26.5 G=½ 50 40 30 20 +13.5, +26.5 CMRR (µV/V) 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –45 –30 –15 REPRESENTATIVE SAMPLES 0 15 30 45 60 75 90 105 120 06981-029 –50 –15 –10 TEMPERATURE (°C) –5 0 5 OUTPUT VOLTAGE (V) 10 15 Figure 6. CMRR vs. Temperature, Normalized at 25°C Figure 9. Input Common-Mode Voltage vs. Output Voltage, Gain = ½, ±15 V Supplies Rev. 0 | Page 6 of 16 06981-031 06981-028 AD8273 18 15 INPUT COMMON-MODE VOLTAGE (V) –3.5, +14 ±5V SUPPLIES G=½ POWER SUPPLY REJECTION (dB) 140 POSITIVE PSRR 120 100 80 60 40 20 0 NEGATIVE PSRR 12 9 6 3 0 –3 –6 –9 –12 –15 –18 –4 –3 –2 –3.5,–7 –1, –2 +3.5, +7 –1, +4 +1, +2 ±2.5V SUPPLIES +1, –4 +3.5, –14 –1 0 1 2 3 4 06981-003 OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 10. Input Common-Mode Voltage vs. Output Voltage, Gain = ½, ±5 V and ±2.5 V Supplies 50 0, +40 INPUT COMMON-MODE VOLTAGE (V) Figure 13. Power Supply Rejection vs. Frequency, G = ½, Referred to Output 32 G=2 +13.5, +36.25 MAXIMUM OUTPUT VOLTAGE (V p-p) 40 30 20 10 0 –10 –20 –30 –40 0, –40 –10 –5 0 5 OUTPUT VOLTAGE (V) 10 15 06981-042 ±15V SUPPLY 28 24 20 16 12 8 4 0 100 ±5V SUPPLY –13.5, +36.25 –13.5, –36.25 +13.5, –36.25 –50 –15 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 11. Input Common-Mode Voltage vs. Output Voltage, Gain = 2, ±15 V Supplies 8 INPUT COMMON-MODE VOLTAGE (V) 10 Figure 14. Maximum Output Voltage vs. Frequency 6 4 2 0 –2 –4 –6 –8 –4 –3.5, +6.125 ±5V SUPPLIES G=2 5 G=2 +3.5, +4.375 –1, +1.175 +1, +1.25 0 ±2.5V SUPPLIES –1, –1.25 –3.5, –4.375 +1, –1.175 GAIN (dB) –5 G=½ –10 –15 +3.5, –6.125 –3 –2 –1 0 1 2 3 4 06981-005 –20 100 1k 10k 100k 1M 10M 100M OUTPUT VOLTAGE (V) FREQUENCY(Hz) Figure 12. Input Common-Mode Voltage vs. Output Voltage, Gain = 2, ±5 V and ±2.5 V Supplies Figure 15. Gain vs. Frequency Rev. 0 | Page 7 of 16 06981-007 06981-006 06981-021 1 10 100 1k 10k 100k 1M AD8273 120 +VS –40°C +25°C COMMON-MODE REJECTION (dB) GAIN = ½ OUTPUT VOLTAGE (V) 100 GAIN = 2 +VS – 3 +VS – 6 +125°C +85°C 80 –VS + 6 +125°C +85°C +25°C 60 –VS + 3 1k 10k FREQUENCY (Hz) 100k 1M 06981-022 CURRENT (mA) Figure 16. Common-Mode Rejection vs. Frequency, Referred to Input 120 100 80 60 CURRENT (mA) Figure 19. Output Voltage vs. IOUT ISHORT+ CLOAD = 100pF 40 50mV/DIV 20 0 –20 –40 –60 –80 ISHORT– NO LOAD 600Ω 2kΩ –120 –40 –20 0 20 40 60 80 100 120 1µs/DIV TEMPERATURE (°C) Figure 17. Short-Circuit Current vs. Temperature +VS Figure 20. Small Signal Step Response, Gain = 2 +125°C +85°C +25°C CLOAD = 100pF OUTPUT VOLTAGE SWING (V) +VS – 2 –40°C +VS – 4 50mV/DIV 0 –VS + 2 +125°C NO LOAD 600Ω 2kΩ –VS + 4 06981-025 –VS –40°C +25°C +85°C 200 1k RLOAD (Ω) 10k 06981-009 1µs/DIV Figure 18. Output Voltage Swing vs. RLOAD, VS = ±15 V Figure 21. Small Signal Step Response, Gain = ½ Rev. 0 | Page 8 of 16 06981-024 –100 06981-008 06981-023 40 100 –VS –40°C 0 20 40 60 80 100 AD8273 100 90 80 70 2.5V 5V 15V 18V OVERSHOOT (%) 06981-026 50mV/DIV 60 50 40 30 20 10 0 20 40 60 80 100 1µs/DIV 120 140 160 180 200 CAPACITANCE (pF) Figure 22. Small Signal Pulse Response with 500 pF Capacitor Load, Gain = 2 100 90 80 70 Figure 25. Small Signal Overshoot vs. Capacitive Load, G = ½, 600 Ω in Parallel with Capacitive Load OVERSHOOT (%) 50mV/DIV 60 50 2.5V 5V 18V 15V 40 30 20 10 06981-027 1µs/DIV 0 200 400 600 800 1000 1200 CAPACITANCE (pF) Figure 23. Small Signal Pulse Response for 100 pF Capacitive Load, Gain = ½ 100 90 80 70 2.5V 5V Figure 26. Small Signal Overshoot vs. Capacitive Load, G = 2, No Resistive Load 100 90 80 70 OVERSHOOT (%) OVERSHOOT (%) 15V 18V 60 50 40 30 20 10 60 50 40 30 20 10 18V 2.5V 5V 15V 06981-037 0 20 40 60 80 100 120 140 160 180 200 0 200 400 600 800 1000 1200 CAPACITANCE (pF) CAPACITANCE (pF) Figure 24. Small Signal Overshoot vs. Capacitive Load, G = ½, No Resistive Load Figure 27. Small Signal Overshoot vs. Capacitive Load, G = 2, 600 Ω in Parallel with Capacitive Load Rev. 0 | Page 9 of 16 06981-040 0 0 06981-039 0 06981-038 0 AD8273 0.1 0.01 THD + N (%) 2V/DIV GAIN = ½ GAIN = 2 0.001 06981-032 1µs/DIV 20 200 FREQUENCY (Hz) 2k 20k Figure 28. Large Signal Pulse Response Gain = ½ 10000 Figure 31. THD+N vs. Frequency, VOUT = 10 V p-p VOLTAGE NOISE DENSITY (nV/√Hz) 1000 2V/DIV 100 GAIN = 2 GAIN = ½ 10 FREQUENCY (Hz) 06981-034 06981-033 1µs/DIV 1 10 100 1k 10k 100k Figure 29. Large Signal Pulse Response, Gain = 2 40 35 30 Figure 32. Voltage Noise Density vs. Frequency, Referred to Output G=2 SLEW RATE (V/µS) 25 20 –SR 15 10 06981-010 1µV/DIV +SR G=½ 5 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 1s/DIV Figure 30.Slew Rate vs. Temperature Figure 33. 0.1 Hz to 10 Hz Voltage Noise, RTO Rev. 0 | Page 10 of 16 06981–035 06981-011 0.0001 AD8273 THEORY OF OPERATION The AD8273 has two channels, each consisting of a high precision, low distortion op amp and four trimmed resistors. Although such a circuit can be built discretely, placing the resistors on the chip offers advantages to board designers that include better dc specifications, better ac specification, and lower production costs. The resistors on the AD8273 are laser trimmed and tightly matched. Specifications that depend on the resistor matching, such as gain drift, common-mode rejection, and gain accuracy, are better than can be achieved with standard discrete resistors. The positive and negative input terminals of the AD8273 op amp are not pinned out intentionally. Keeping these nodes internal means their capacitance is considerably lower than it would be in discrete designs. Lower capacitance at these nodes means better loop stability and improved common-mode rejection vs. frequency. The internal resistors of the AD8273 lower production cost. One part rather than several is placed on the board, which improves both board build time and reliability. –IN1 12 6kΩ 12kΩ 2 13 OUT1 +IN1 14 6kΩ 12kΩ 3 –IN2 10 6kΩ 12kΩ 6 9 OUT2 +IN2 8 6kΩ 12kΩ 5 06981-016 VOUT = 2 (VIN+ − VIN−) Figure 35. Difference Amplifier, G = 2 2 12kΩ 6kΩ 12 13 OUT1 IN1 14 6kΩ 3 12kΩ CONFIGURATIONS The AD8273 can be configured in several different ways; see Figure 34 to Figure 41. Because these configurations rely on the internal, matched resistors, these configurations have excellent gain accuracy and gain drift. IN2 6 12kΩ 6kΩ 10 9 OUT2 8 6kΩ 5 12kΩ 06981-013 POWER SUPPLIES A stable dc voltage should be used to power the AD8273. Noise on the supply pins can adversely affect performance. A bypass capacitor of 0.1 μF should be placed between each supply pin and ground, as close to each pin as possible. A tantalum capacitor of 10 μF should also be used between each supply and ground. It can be farther away from the AD8273 and typically can be shared by other precision integrated circuits. The AD8273 is specified at ±15 V, but it can be used with unbalanced supplies as well, for example, −VS = 0 V, +VS = 20 V. The difference between the two supplies must be kept below 36 V. –IN1 2 12kΩ 6kΩ 12 13 OUT1 VOUT = −½ VIN Figure 36. Inverting Amplifier, G = ½ 12 6kΩ 12kΩ 2 13 OUT1 IN1 3 12kΩ 14 6kΩ IN2 10 6kΩ 12kΩ 6 9 OUT2 5 12kΩ 8 6kΩ VOUT = −2 VIN +IN1 3 12kΩ 6kΩ 14 Figure 37. Inverting Amplifier, G = 2 –IN2 6 12kΩ 6kΩ 10 9 OUT2 +IN2 5 12kΩ 6kΩ 8 06981-012 VOUT = ½ (VIN+ − VIN−) Figure 34. Difference Amplifier, G = ½ Rev. 0 | Page 11 of 16 06981-017 AD8273 2 12kΩ 6kΩ 12 13 OUT1 2 12kΩ 6kΩ 12 13 OUT1 14 IN1 3 12kΩ 6kΩ 14 6kΩ IN1 3 12kΩ 6 12kΩ 6kΩ 10 9 OUT2 6 12kΩ 6kΩ 10 9 OUT2 8 IN2 5 12kΩ 6kΩ 8 06981-015 6kΩ IN2 5 12kΩ 06981-014 VOUT = ½ VIN VOUT = 1½ VIN Figure 38. Noninverting Amplifier, G = ½ 12 6kΩ 12kΩ 2 13 OUT1 Figure 40. Noninverting Amplifier, G = 1.5 12 6kΩ 12kΩ 2 13 3 12kΩ IN1 OUT1 IN1 14 6kΩ 12kΩ 3 14 6kΩ 10 6kΩ 12kΩ 6 9 OUT2 10 6kΩ 12kΩ 6 9 OUT2 5 12kΩ IN2 8 6kΩ 12kΩ 5 06981-019 IN2 8 6kΩ 06981-018 VOUT = 2 VIN VOUT = 3 VIN Figure 39. Noninverting Amplifier, G = 2 Figure 41. Noninverting Amplifier, G = 3 Rev. 0 | Page 12 of 16 AD8273 OUTLINE DIMENSIONS 8.75 (0.3445) 8.55 (0.3366) 14 1 8 7 4.00 (0.1575) 3.80 (0.1496) 6.20 (0.2441) 5.80 (0.2283) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45° COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 42. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model AD8273ARZ 1 AD8273ARZ-R71 AD8273ARZ-RL1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 14-Lead SOIC_N 14-Lead SOIC_N, 7" Tape and Reel 14-Lead SOIC_N, 13" Tape and Reel 060606-A Package Option R-14 R-14 R-14 Z = RoHS Compliant Part. Rev. 0 | Page 13 of 16 AD8273 NOTES Rev. 0 | Page 14 of 16 AD8273 NOTES Rev. 0 | Page 15 of 16 AD8273 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06981-0-1/08(0) Rev. 0 | Page 16 of 16