AD8426

Data Sheet FEATURES Fixed gain of 2000 Access to internal nodes provides flexibility Low noise: 1.5 nV/√Hz input voltage noise High accuracy dc performance Gain drift: 10 ppm/°C Offset drift: 1 μV/°C Gain accuracy: 0.2% CMRR: 130 dB min Excellent ac specifications Bandwidth: 3.5 MHz Slew rate: 40 V/μs Power supply range: ±4 V to ±18 V 8-pin SOIC package ESD protection >5000 V (HBM) Temperature range for specified performance: −40°C to +85°C Operational up to 125°C Low Noise, Low Gain Drift, G = 2000 Instrumentation Amplifier AD8428 FUNCTIONAL BLOCK DIAGRAM +VS –FIL –IN 3kΩ 30.15Ω 3kΩ +IN 09731-001 6kΩ 6kΩ 120kΩ OUT 6kΩ 6kΩ 120kΩ REF AD8428 –VS +FIL Figure 1. Table 1. Instrumentation Amplifiers by Category1 GeneralPurpose AD8220 AD8221 AD8222 AD8224 AD8228 AD8295 Zero Drift AD8231 AD8290 AD8293 AD8553 AD8556 AD8557 Military Grade AD620 AD621 AD524 AD526 AD624 Low Power AD627 AD623 AD8235 AD8236 AD8426 AD8226 AD8227 Low Noise AD8428 AD8429 APPLICATIONS Sensor interface Medical instrumentation Patient monitoring 1 See www.analog.com for the latest instrumentation amplifiers. GENERAL DESCRIPTION The AD8428 is an ultralow noise instrumentation amplifier designed to accurately measure tiny, high speed signals. It delivers industry-leading gain accuracy, noise, and bandwidth. All gain setting resistors for the AD8428 are internal to the part and are precisely matched. Care is taken in both the chip pinout and layout. This results in excellent gain drift and quick settling to the final gain value after the part is powered on. The high CMRR of the AD8428 prevents unwanted signals from corrupting the signal of interest. The pinout of the AD8428 is designed to avoid parasitic capacitance mismatches that can degrade CMRR at high frequencies. The AD8428 is one of the fastest instrumentation amplifiers available. The circuit architecture is designed for high bandwidth at high gain. The AD8428 uses a current feedback topology for the initial preamplifier gain stage of 200, followed by a difference amplifier stage of 10. This architecture results in a 3.5 MHz bandwidth at a gain of 2000 for an equivalent gain bandwidth product of 7 GHz. The AD8428 pinout allows access to internal nodes between the first and second stages. This feature can be useful for modifying the frequency response between the two amplification stages, thereby preventing unwanted signals from contaminating the output results. The performance of the AD8428 is specified over the industrial temperature range of −40°C to +85°C. It is available in an 8-lead plastic SOIC package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD8428 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Absolute Maximum Ratings............................................................ 5  Thermal Resistance ...................................................................... 5  ESD Caution .................................................................................. 5  Pin Configuration and Function Descriptions ............................. 6  Typical Performance Characteristics ............................................. 7  Data Sheet Theory of Operation ...................................................................... 13  Architecture ................................................................................ 13  Filter Terminals........................................................................... 13  Reference Terminal .................................................................... 13  Input Voltage Range ................................................................... 14  Layout .......................................................................................... 14  Input Bias Current Return Path ............................................... 15  Input Protection ......................................................................... 15  Radio Frequency Interference (RFI) ........................................ 16  Calculating the Noise of the Input Stage ................................. 16  Outline Dimensions ....................................................................... 18  Ordering Guide .......................................................................... 18  REVISION HISTORY 10/11—Revision 0: Initial Version Rev. 0 | Page 2 of 20 Data Sheet SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 2000, RL = 10 kΩ, unless otherwise noted. Table 2. Parameter COMMON-MODE REJECTION RATIO (RTI) CMRR, DC to 60 Hz CMRR at 50 kHz NOISE (RTI) Voltage Noise Current Noise VOLTAGE OFFSET Input Offset, VOSI Average TC Offset RTI vs. Supply (PSRR) INPUT CURRENT Input Bias Current Over Temperature Input Offset Current Over Temperature DYNAMIC RESPONSE −3 dB Small Signal Bandwidth Settling Time to 0.01% Settling Time to 0.001% Slew Rate GAIN First Stage Gain Subtractor Stage Gain Total Gain Error Total Gain Nonlinearity Total Gain vs. Temperature INPUT Impedance (Pin to Ground) 1 Input Operating Voltage Range Over Temperature OUTPUT Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current REFERENCE INPUT RIN IIN Voltage Range Reference Gain to Output Reference Gain Error Test Conditions/Comments VCM = ±10 V Min 130 110 VIN+, VIN− = 0 V f = 1 kHz f = 0.1 Hz to 10 Hz f = 1 kHz f = 0.1 Hz to 10 Hz 1.3 40 1.5 150 1.5 50 Typ Max AD8428 Unit dB dB nV/√Hz nV p-p pA/√Hz pA p-p μV μV/°C dB nA pA/°C nA pA/°C MHz μs μs V/μs V/V V/V % ppm ppm/°C GΩ||pF V V V V V V V V mA kΩ μA V V/V % TA = −40°C to +85°C 120 100 1 200 TA = −40°C to +85°C TA = −40°C to +85°C 250 50 20 3.5 0.75 1.4 50 200 10 VOUT = −10 V to +10 V VOUT = −10 V to +10 V 0.2 5 10 1||2 VS = ±4 V to ±18 V TA = −40°C to +85°C RL = 2 kΩ TA = −40°C TA = +85°C RL = 10 kΩ TA = −40°C TA = +85°C −VS + 2.5 −VS + 2.5 −VS + 1.7 −VS + 2.0 −VS + 1.6 −VS + 1.7 −VS + 1.8 −VS + 1.4 30 132 6.5 −VS 1 0.01 +VS +VS − 2.5 +VS − 2.5 +VS − 1.2 +VS − 1.3 +VS − 1.1 +VS − 1.0 +VS − 1.2 +VS − 0.9 10 V step 10 V step 40 VIN+, VIN− = 0 V Rev. 0 | Page 3 of 20 AD8428 Parameter FILTER TERMINALS RIN 2 Voltage Range POWER SUPPLY Operating Range Quiescent Current Over Temperature 1 2 Data Sheet Test Conditions/Comments Min Typ 6 −VS ±4 6.5 TA = −40°C to +85°C +VS ±18 6.8 8 Max Unit kΩ V V mA mA The differential and common-mode input impedances can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2. To calculate the actual impedance, see Figure 1. Rev. 0 | Page 4 of 20 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Output Short-Circuit Current Duration Maximum Voltage at −IN, +IN1 Maximum Voltage at −FIL, +FIL Differential Input Voltage1 Maximum Voltage at REF Storage Temperature Range Specified Temperature Range Maximum Junction Temperature ESD Human Body Model Charged Device Model Machine Model 1 AD8428 THERMAL RESISTANCE Rating ±18 V Indefinite ±VS ±VS ±1 V ±VS −65°C to +150°C −40°C to +85°C 140°C 5000 V 1250 V 400 V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package 8-Lead SOIC_N θJA 121 Unit °C/W ESD CAUTION For voltages beyond these limits, use input protection resistors. See the Input Protection section for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 5 of 20 AD8428 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD8428 –IN 1 –FIL 2 +FIL 3 +IN 4 TOP VIEW (Not to Scale) 8 7 6 5 Data Sheet +VS OUT REF –VS 09731-002 Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic −IN −FIL +FIL +IN −VS REF OUT +VS Description Negative Input Terminal. Negative Filter Terminal. Positive Filter Terminal. Positive Input Terminal. Negative Power Supply Terminal. Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output. Output Terminal. Positive Power Supply Terminal. Rev. 0 | Page 6 of 20 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±15 V, VREF = 0 V, RL = 10 kΩ, unless otherwise noted. 1200 N = 5170 MEAN = 2.12 SD = 7.332 AD8428 1600 1400 1200 NONINVERTING IBIAS INVERTING IBIAS 1000 800 1000 N = +5171 MEAN = –10.8 SD = +6.67496 N = +5171 MEAN = –10.2 SD = +6.52901 HITS HITS 09731-003 600 800 600 400 400 200 200 09731-006 09731-008 09731-007 0 –40 –20 0 VOSI (µV) 20 40 0 –60 –40 –20 0 20 40 IBIAS (nA) Figure 3. Typical Distribution of Input Offset Voltage, VS = ±5 V Figure 6. Typical Distribution of Input Bias Current 1400 1200 1000 800 600 N = +5169 MEAN = –2.57 SD = +7.31066 1000 N = +5171 MEAN = –0.53 SD = +1.41655 800 HITS HITS 09731-004 600 400 400 200 0 200 –40 –20 0 VOSI (µV) 20 40 0 –8 –6 –4 –2 0 2 4 6 IBIAS OFFSET (nA) Figure 4. Typical Distribution of Input Offset Voltage, VS = ±15 V Figure 7. Typical Distribution of Input Bias Current Offset 1400 1200 1000 N = 5166 MEAN = 0.398 SD = 0.42707 1200 N = +3487 MEAN = –53.9 SD = +86.7774 1000 800 HITS HITS 09731-005 800 600 600 400 400 200 0 200 0 –3 –2 –1 0 1 2 3 –600 –400 –200 0 200 400 VOSI DRIFT (µV) GAIN ERROR (µV/V) Figure 5. Typical Distribution of Input Offset Voltage Drift Figure 8. Typical Distribution of Gain Error, Gain = 2000, VS = ±15 V, RL = 10 kΩ Rev. 0 | Page 7 of 20 AD8428 15 INPUT COMMON-MODE VOLTAGE (V) Data Sheet 72 66 60 54 48 42 GAIN (dB) 10 VS = ±15V VS = ±12V 5 VS = ±5V 36 30 24 18 12 6 0 –6 –12 100 0 –5 –10 –10 –5 0 5 10 15 09731-009 1k 10k 100k 1M 10M 100M OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 9. Input Common-Mode Voltage vs. Output Voltage, VS = ±5 V, VS = ±12 V, VS = ±15 V Figure 12. Gain vs. Frequency 18 16 INPUT BIAS CURRENT (nA) –11.8V 170 160 150 140 CMRR (dB) GAIN = 2000 14 12 10 8 6 4 2 0 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 +12V 09731-010 130 120 110 100 90 09731-015 09731-016 8 10 12 14 80 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M COMMON-MODE VOLTAGE (V) Figure 10. Input Bias Current vs. Common-Mode Voltage, VS = ±15 V Figure 13. CMRR vs. Frequency 140 120 100 PSRR (dB) 120 110 100 +PSRR –PSRR CMRR (dB) GAIN = 2000 90 80 70 60 50 40 80 60 40 20 0 0.1 30 20 10 1 10 100 1k 10k 100k 1M 09731-011 0 1 10 100 1k FREQUENCY (Hz) 10k 100k 1M FREQUENCY (Hz) Figure 11. PSRR vs. Frequency Figure 14. CMRR vs. Frequency, 1 kΩ Source Imbalance Rev. 0 | Page 8 of 20 09731-014 –15 –15 Data Sheet 5 CHANGE IN INPUT OFFSET VOLTAGE (µV) AD8428 70 60 50 REPRESENTATIVE DATA NORMALIZED AT 25°C 4 3 CMRR (nV/V) 40 30 20 10 0 –10 2 1 0 –1 –2 –20 09731-017 0 10 20 30 40 50 60 70 80 90 100 110 120 –25 –10 5 20 35 50 65 80 95 110 125 WARM-UP TIME (Seconds) TEMPERATURE (°C) Figure 15. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time Figure 18. CMRR vs. Temperature, Normalized at 25°C 15 IOS 10 INPUT BIAS CURRENT (nA) 1.2 IB+ 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 NORMALIZED AT 25°C 09731-018 9.0 8.5 INPUT OFFSET CURRENT (nA) 5 0 –5 –10 –15 –20 –25 –30 –40 SUPPLY CURRENT (mA) IB– 8.0 7.5 7.0 6.5 6.0 5.5 09731-021 09731-022 –25 –10 5 20 35 50 65 80 95 110 –2.4 125 5.0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Input Bias Current and Input Offset Current vs. Temperature Figure 19. Supply Current vs. Temperature 250 200 150 GAIN ERROR (µV/V) SHORT-CIRCUIT CURRENT (mA) 50 40 30 20 10 0 –10 –20 –30 –40 REPRESENTATIVE DATA NORMALIZED AT 25°C 09731-019 ISHORT+ 100 50 0 –50 –100 –150 –200 –40 ISHORT– –25 –10 5 20 35 50 65 80 95 110 125 –50 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 17. Gain Error vs. Temperature, Normalized at 25°C Figure 20. Short-Circuit Current vs. Temperature Rev. 0 | Page 9 of 20 09731-020 –30 –40 AD8428 100 90 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES Data Sheet +VS –0.4 –0.8 –1.2 –40°C +25°C +85°C +125°C 80 SLEW RATE (V/µs) 70 60 50 40 30 20 10 –SR +SR +2.0 +1.6 +1.2 +0.8 +0.4 09731-023 –25 –10 5 20 35 50 65 80 95 110 125 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TEMPERATURE (°C) SUPPLY VOLTAGE (±VS) Figure 21. Slew Rate vs. Temperature, VS = ±15 V Figure 24. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ 100 90 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +VS –0.4 –0.8 –1.2 –40°C +25°C +85°C +125°C 80 SLEW RATE (V/µs) 70 60 50 40 30 20 10 09731-024 –SR +2.0 +1.6 +1.2 +0.8 +0.4 +SR –25 –10 5 20 35 50 65 80 95 110 125 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TEMPERATURE (°C) SUPPLY VOLTAGE (±VS) Figure 22. Slew Rate vs. Temperature, VS = ±5 V Figure 25. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ +VS –0.5 INPUT VOLTAGE (V) REFERRED TO SUPPLY VOLTAGES 15 –40°C +25°C +85°C +125°C –40°C +25°C +85°C +125°C –1.0 –1.5 –2.0 –2.5 10 OUTPUT VOLTAGE SWING (V) 5 0 +2.5 +2.0 +1.5 +1.0 +0.5 09731-025 –5 –10 4 6 8 10 12 14 16 18 1k LOAD (Ω) 10k 100k SUPPLY VOLTAGE (±VS) Figure 23. Input Voltage Limit vs. Supply Voltage Figure 26. Output Voltage Swing vs. Load Resistance, VS = ±15 V Rev. 0 | Page 10 of 20 09731-028 –VS –15 100 09731-027 0 –40 –VS 09731-026 0 –40 –VS Data Sheet +VS –40°C OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES AD8428 +25°C +85°C +125°C –0.5 –1.0 –1.5 +1.5 +1.0 +0.5 20nV/DIV 1s/DIV 09731-032 0.1 1 10 OUTPUT CURRENT (mA) Figure 27. Output Voltage Swing vs. Output Current, VS = ±15 V 09731-029 –VS 0.01 Figure 30. 0.1 Hz to 10 Hz RTI Voltage Noise 20 15 GAIN NONLINEARITY (5 ppm/DIV) GAIN = 2000 16 15 14 13 12 NOISE (pA/√Hz) 10 5 0 –5 –10 –15 09731-030 11 10 9 8 7 6 5 4 3 2 09731-033 –20 –10 –8 –6 –4 –2 0 2 4 6 8 10 1 1 10 100 1k 10k 100k OUTPUT VOLTAGE (V) FREQUENCY (Hz) Figure 28. Gain Nonlinearity, RL = 10 kΩ Figure 31. Current Noise Spectral Density vs. Frequency 100 GAIN = 2000 NOISE (nV/√Hz) 10 1 50pA/DIV 1s/DIV 1 10 100 FREQUENCY (Hz) 1k 10k 100k 09731-031 0.1 0.1 Figure 29. RTI Voltage Noise Spectral Density vs. Frequency Figure 32. 0.1 Hz to 10 Hz Current Noise Rev. 0 | Page 11 of 20 09731-034 AD8428 Data Sheet 5V/DIV 752ns TO 0.01% 1408ns TO 0.001% 0.002%/DIV NO LOAD CL = 500pF 09731-035 09731-037 CL = 770pF 50mV/DIV 1µs/DIV 1µs/DIV TIME (µs) Figure 33. Large Signal Pulse Response and Settling Time, 10 V Step, VS = ±15 V Figure 35. Small Signal Pulse Response with Various Capacitive Loads, No Resistive Load GAIN = 2000 1800 1600 1400 SETTLING TIME (ns) 1200 1000 800 600 400 SETTLED TO 0.001% SETTLED TO 0.01% 20mV/DIV 1µs/DIV 09731-036 200 09731-038 0 2 4 6 8 10 12 14 16 18 20 STEP SIZE (V) Figure 34. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF Figure 36. Settling Time vs. Step Size Rev. 0 | Page 12 of 20 Data Sheet THEORY OF OPERATION I IB COMPENSATION C1 NODE 1 NODE 2 +VS 1 –IN Q1 30.15Ω –VS –RG RG +RG –VS R1 3kΩ R2 3kΩ Q2 +VS 4 +IN R5 6kΩ +VS 3 +FIL R6 6kΩ –VS VB I IB COMPENSATION C2 +VS R3 6kΩ –FIL 2 –VS R4 6kΩ A3 +VS 120kΩ R8 –VS 6 REF 120kΩ R7 +VS 7 OUT A1 A2 AD8428 –VS Figure 37. Simplified Schematic ARCHITECTURE The AD8428 is based on the classic 3-op-amp topology. This topology has two stages: a gain stage (preamplifier) to provide differential amplification by a factor of 200, followed by a difference amplifier stage to remove the common-mode voltage and provide additional amplification by a factor of 10. Figure 37 shows a simplified schematic of the AD8428. The first stage works as follows. To keep its two inputs matched, Amplifier A1 must keep the collector of Q1 at a constant voltage. It does this by forcing −RG to be a precise diode drop from −IN. Similarly, A2 forces +RG to be a constant diode drop from +IN. Therefore, a replica of the differential input voltage is placed across the gain setting resistor, RG. The current that flows across this resistance must also flow through the R1 and R2 resistors, creating a gained differential signal between the A2 and A1 outputs. The second stage is a G = 10 difference amplifier, composed of Amplifier A3 and Resistors R3 through R8. This stage removes the common-mode signal from the amplified differential signal. The transfer function of the AD8428 is VOUT = 2000 × (VIN+ − VIN−) + VREF REFERENCE TERMINAL The output voltage of the AD8428 is developed with respect to the potential on the reference terminal. This is useful when the output signal must be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8428 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or −VS. For best performance, the source impedance to the REF terminal should be kept well below 1 Ω. As shown in Figure 37, the reference terminal, REF, is at one end of a 120 kΩ resistor. Additional impedance at the REF terminal adds to this 120 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be calculated as follows: 2 × (120 kΩ + RREF)/(240 kΩ + RREF) Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades the CMRR of the amplifier. INCORRECT CORRECT FILTER TERMINALS The −FIL and +FIL terminals allow access between R3 and R4, and between R5 and R6, respectively. Adding a filter between these two terminals modifies the signal gain vs. frequency before it reaches the second amplifier stage. AD8428 REF V + V AD8428 REF OP1177 – 09731-043 Figure 38. Driving the Reference Pin Rev. 0 | Page 13 of 20 09731-042 AD8428 INPUT VOLTAGE RANGE The 3-op-amp architecture of the AD8428 applies gain in the first stage before removing the common-mode voltage in the difference amplifier stage. Internal nodes between the first and second stages (Node 1 and Node 2 in Figure 37) experience a combination of an amplified differential signal, a common-mode signal, and a diode drop. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited. Figure 9 shows the allowable input common-mode voltage ranges for various output voltages and supply voltages. Data Sheet Power Supplies and Grounding Use a stable dc voltage to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. See the PSRR performance curves in Figure 11 for more information. Place a 0.1 μF capacitor as close as possible to each supply pin. Because the length of the bypass capacitor leads is critical at high frequency, surface-mount capacitors are recommended. A parasitic inductance in the bypass ground trace works against the low impedance created by the bypass capacitor. As shown in Figure 40, a 10 μF capacitor can be used farther away from the device. For larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. In most cases, the 10 μF capacitor can be shared by other precision integrated circuits. +VS LAYOUT To ensure optimum performance of the AD8428 at the PCB level, care must be taken in the design of the board layout. The pins of the AD8428 are especially arranged to simplify board layout and to help minimize parasitic imbalance between the inputs. AD8428 –IN 1 –FIL 2 +FIL 3 +IN 4 TOP VIEW (Not to Scale) 8 7 6 5 0.1µF +IN 10µF +VS OUT REF –VS 09731-044 AD8428 –IN REF VOUT LOAD Figure 39. Pinout Diagram Common-Mode Rejection Ratio over Frequency Poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. Such conversions occur when one input path has a frequency response that is different from the other. To maintain high CMRR over frequency, the input source impedance and capacitance of each path should be closely matched. Additional source resistance in the input paths (for example, for input protection) should be placed close to the in-amp inputs to minimize the interaction of the inputs with parasitic capacitance from the PCB traces. Parasitic capacitance at the filter pins can also affect CMRR over frequency. If the board design has a component at the filter pins, the component should be chosen so that the parasitic capacitance is as small as possible. –VS Figure 40. Supply Decoupling, REF, and Output Referred to Local Ground A ground plane layer is helpful to reduce undesired parasitic inductances and to minimize voltage drops with changes in current. The area of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the impedance of the path at high frequency. Large changes in currents in an inductive decoupling path or ground return create unwanted effects due to the coupling of such changes into the amplifier inputs. Because load currents flow from the supplies, the load should be connected at the same physical location as the bypass capacitor grounds. Reference Pin The output voltage of the AD8428 is developed with respect to the potential on the reference terminal. Ensure that REF is tied to the appropriate local ground. Rev. 0 | Page 14 of 20 09731-045 0.1µF 10µF Data Sheet INPUT BIAS CURRENT RETURN PATH The input bias current of the AD8428 must have a return path to ground. When the source, such as a thermocouple, cannot provide a current return path, one should be created, as shown in Figure 41. INCORRECT +VS AD8428 Input Voltages Beyond the Rails If voltages beyond the rails are expected, use an external resistor in series with each input to limit current during overload conditions. The limiting resistor at each input can be computed using the following equation: CORRECT +VS R PROTECT ≥ V IN − VSUPPLY I MAX AD8428 REF AD8428 REF –VS TRANSFORMER +VS –VS TRANSFORMER +VS Noise sensitive applications may require a lower protection resistance. Low leakage diode clamps, such as the BAV199, can be used at the inputs to shunt current away from the AD8428 inputs and, therefore, allow smaller protection resistor values. To ensure that current flows primarily through the external protection diodes, place a small value resistor, such as a 33 Ω resistor, between the diodes and the AD8428. RPROTECT + VIN+ – I +VS +VS RPROTECT + VIN+ – I –VS +VS RPROTECT –VS VIN– – + –VS 33Ω –VS 09731-047 33Ω +VS AD8428 RPROTECT AD8428 AD8428 REF 10MΩ –VS THERMOCOUPLE +VS C C AD8428 REF VIN– – + –VS THERMOCOUPLE +VS SIMPLE METHOD LOW NOISE METHOD Figure 42. Protection for Voltages Beyond the Rails Large Differential Input Voltage at High Gain If large differential voltages at high gain are expected, use an external resistor in series with each input to limit current during overload conditions. The limiting resistor at each input can be computed using the following equation: REF R –VS CAPACITIVELY COUPLED –VS CAPACITIVELY COUPLED 09731-046 AD8428 C REF fHIGH-PASS = 2π1 RC C R AD8428 R PROTECT ≥ ⎞ 1 ⎛ VDIFF − 1 V ×⎜ − RG ⎟ ⎟ 2⎜ I MAX ⎝ ⎠ Figure 41. Creating an Input Bias Current Return Path INPUT PROTECTION Do not allow the inputs of the AD8428 to exceed the ratings stated in the Absolute Maximum Ratings section. If these ratings cannot be adhered to, add protection circuitry in front of the AD8428 to limit the maximum current into the inputs (see the IMAX section). Noise sensitive applications may require a lower protection resistance. Low leakage diode clamps, such as the BAV199, can be used across the AD8428 inputs to shunt current away from the inputs and, therefore, allow smaller protection resistor values. RPROTECT +I VDIFF – RPROTECT AD8428 09731-048 IMAX The maximum current into the AD8428 inputs, IMAX, depends on time and temperature. At room temperature, the device can withstand a current of 10 mA for at least one day. This time is cumulative over the life of the device. Figure 43. Protection for Large Differential Voltages Rev. 0 | Page 15 of 20 AD8428 RADIO FREQUENCY INTERFERENCE (RFI) Because of its high gain and low noise properties, the AD8428 is a highly sensitive amplifier. Therefore, RF rectification can be a problem if the AD8428 is used in applications that have strong RF signal sources present. The problem is intensified if long leads or PCB traces are required to connect the amplifier to the signal source. The disturbance can appear as a dc offset voltage or a train of pulses. High frequency signals can be filtered with a low-pass filter network at the input of the instrumentation amplifier, as shown in Figure 44. +VS 0.1µF CC 1nF R 33Ω L* CD 10nF R 33Ω CC 1nF 0.1µF –VS *CHIP FERRITE BEAD. 10µF 09731-049 Data Sheet For best results, place the RFI filter network as close as possible to the amplifier. Layout is critical to ensure that RF signals are not picked up on the traces after the filter. If RF interference is too strong to be filtered, shielding is recommended. Note that the resistors used for the RFI filter can be the same as those used for input protection (see the Input Protection section). CALCULATING THE NOISE OF THE INPUT STAGE The total noise of the amplifier front end depends on much more than the specifications in this data sheet. The three main contributors to noise are as follows: the source resistance, the voltage noise of the instrumentation amplifier, and the current noise of the instrumentation amplifier. In the following calculations, noise is referred to the input (RTI); that is, all sources of noise are calculated as if the source appeared at the amplifier input. To calculate the noise referred to the amplifier output (RTO), simply multiply the RTI noise by the gain of the instrumentation amplifier. 10µF L* +IN AD8428 REF –IN VOUT Source Resistance Noise Any sensor connected to the AD8428 has some output resistance. There may also be resistance placed in series with the inputs for protection from either overvoltage or radio frequency interference. This combined resistance is labeled R1 and R2 in Figure 45. Any resistor, no matter how well made, has an intrinsic level of noise. This noise is proportional to the square root of the resistor value. At room temperature, the value is approximately equal to 4 nV/√Hz × √(resistor value in kΩ). SENSOR Figure 44. RFI Suppression The filter limits both the differential and common-mode bandwidth, as shown in the following equations: FilterFreq uency DIFF = FilterFreq uency CM = 1 2πR(2C D + C C ) 1 2πRC C R1 AD8428 09731-050 where CD ≥ 10 CC. CD affects the differential signal, and CC affects the commonmode signal. Choose values of R and CC that minimize RFI. A mismatch between R × CC at the positive input and R × CC at the negative input degrades the CMRR of the AD8428. By using a value of CD one order of magnitude larger than CC, the effect of the mismatch is reduced, and performance is improved. Resistors add noise; therefore, the choice of resistor and capacitor values depends on the desired trade-off between noise, input impedance at high frequencies, and RFI immunity. To achieve low noise and sufficient RFI filtering, the use of inductive ferrite beads is recommended (see Figure 44). Using inductive ferrite beads allows the value of the resistors to be reduced, which helps to minimize the noise at the input. R2 Figure 45. Source Resistance from Sensor and Protection Resistors For example, assuming that the combined sensor and protection resistance is 4 kΩ on the positive input and 1 kΩ on the negative input, the total noise from the input resistance is (4 × 4 ) + (4 × 1 ) 2 2 = 64 + 16 = 8.9 nV/ Hz Rev. 0 | Page 16 of 20 Data Sheet Voltage Noise of the Instrumentation Amplifier Unlike other instrumentation amplifiers in which an external resistor is used to set the gain, the voltage noise specification of the AD8428 already includes the input noise, output noise, and the RG resistor noise. AD8428 Total Noise Density Calculation To determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current noise contribution by the sum of squares method. For example, if the R1 source resistance in Figure 45 is 4 kΩ and the R2 source resistance is 1 kΩ, the total noise, referred to input, is 8.9 2 + 1.5 2 + 6.2 2 = 11.0 nV/ Hz Current Noise of the Instrumentation Amplifier The contribution of current noise to the input stage in nV/√Hz is calculated by multiplying the source resistance in kΩ by the specified current noise of the instrumentation amplifier in pA/√Hz. For example, if the R1 source resistance in Figure 45 is 4 kΩ and the R2 source resistance is 1 kΩ, the total effect from the current noise is calculated as follows: (4 × 1.5)2 + (1 × 1.5)2 = 6.2 nV/ Hz Rev. 0 | Page 17 of 20 AD8428 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) Data Sheet 4.00 (0.1574) 3.80 (0.1497) 8 1 5 4 6.20 (0.2441) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) 0.25 (0.0099) 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 45° 0.51 (0.0201) 0.31 (0.0122) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 46. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 AD8428ARZ AD8428ARZ-RL 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N, 13” Tape and Reel 012407-A Package Option R-8 R-8 Z = RoHS Compliant Part. Rev. 0 | Page 18 of 20 Data Sheet NOTES AD8428 Rev. 0 | Page 19 of 20 AD8428 NOTES Data Sheet ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09731-0-10/11(0) Rev. 0 | Page 20 of 20