AD9252BCPZ-50

Octal, 14-Bit, 50 MSPS Serial LVDS 1.8 V A/D Converter AD9252 FEATURES 8 ADCs integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) Excellent linearity DNL = ±0.4 LSB (typical) INL = ±1.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power reduced signal option, IEEE 1596.3 similar Data and frame clock outputs 325 MHz, full power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND AD9252 VIN+A VIN–A VIN+B VIN–B VIN+C VIN–C VIN+D VIN–D VIN+E VIN–E VIN+F VIN–F VIN+G VIN–G VIN+H VIN–H VREF SENSE 0.5V REFT REFB REF SELECT SERIAL PORT INTERFACE ADC 14 SERIAL LVDS 14 ADC 14 ADC 14 ADC 14 ADC 14 ADC 14 ADC 14 ADC SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS D+A D–A D+B D–B D+C D–C D+D D–D D+E D–E D+F D–F D+G D–G D+H D–H APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment FCO+ DATA RATE MULTIPLIER FCO– DCO+ DCO– 06296-001 RBIAS AGND CSB SDIO/ ODM SCLK/ DTP CLK+ CLK– Figure 1. GENERAL DESCRIPTION The AD9252 is an octal, 14-bit, 50 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 50 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI®). The AD9252 is available in a Pb-free, 64-lead LFCSP package. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. 2. 3. 4. Small Footprint. Eight ADCs are contained in a small, spacesaving package; low power of 93.5 mW/channel at 50 MSPS. Ease of Use. A data clock output (DCO) operates up to 300 MHz and supports double data rate operation (DDR). User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9212 (10-bit), and AD9222 (12-bit). One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD9252 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams .............................................................................. 7 Absolute Maximum Ratings............................................................ 9 Thermal Impedance ..................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 14 Theory of Operation ...................................................................... 17 Analog Input Considerations ................................................... 17 Clock Input Considerations ...................................................... 19 Serial Port Interface (SPI) .............................................................. 27 Hardware Interface..................................................................... 27 Memory Map .................................................................................. 29 Reading the Memory Map Table .............................................. 29 Reserved Locations .................................................................... 29 Default Values ............................................................................. 29 Logic Levels ................................................................................. 29 Evaluation Board ............................................................................ 33 Power Supplies ............................................................................ 33 Input Signals................................................................................ 33 Output Signals ............................................................................ 33 Default Operation and Jumper Selection Settings ................. 34 Alternative Analog Input Drive Configuration...................... 35 Outline Dimensions ....................................................................... 52 Ordering Guide .......................................................................... 52 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 52 AD9252 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Input Resistance ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation 2 CROSSTALK CROSSTALK (Overrange Condition) 3 1 2 Temperature Min 14 AD9252-50 Typ Max Unit Bits Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 1.7 1.7 Guaranteed ±1 ±3 ±1.5 ±0.3 ±0.4 ±1.5 ±2 ±17 ±21 ±2 3 6 2 AVDD/2 7 325 1.8 1.8 360 55.5 748 2 89 −90 −90 ±8 ±8 ±2.5 ±0.7 ±1 ±4 mV mV % FS % FS LSB LSB ppm/°C ppm/°C ppm/°C ±30 mV mV kΩ V p-p V pF MHz 1.9 1.9 373.4 58 773 11 V V mA mA mW mW mW dB dB See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Can be controlled via SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. Rev. 0 | Page 3 of 52 AD9252 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C Min AD9252-50 Typ Max 73.2 71 73 72.7 71 72.5 70.2 72.2 72 70.5 11.87 11.5 11.84 11.79 11.5 85 73 84 83 79 −85 −84 −73 −83 −79 −90 −90 −80 −90 −89 80.0 80.0 Unit dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) EFFECTIVE NUMBER OF BITS (ENOB) SPURIOUS-FREE DYNAMIC RANGE (SFDR) WORST HARMONIC (Second or Third) WORST OTHER (Excluding Second or Third) TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 52 AD9252 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM)3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D+, D−), (ANSI-644) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D+, D−), (Low Power, Reduced Signal Option) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 3 Temperature Min AD9252-50 Typ Max CMOS/LVDS/LVPECL Unit Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full 250 1.2 20 1.5 1.2 30 0.5 1.2 70 0.5 1.2 0 30 2 1.79 0.05 LVDS DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3 mV p-p V kΩ pF V V kΩ pF V V kΩ pF V V kΩ pF V V Full Full 247 1.125 454 1.375 Offset binary mV V LVDS Full Full 150 1.10 250 1.30 Offset binary mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. This is specified for LVDS and LVPECL only. This is specified for 13 SDIO pins sharing the same connection. Rev. 0 | Page 5 of 52 AD9252 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. AD9252-50 Parameter 1 CLOCK 2 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) 4 DCO to Data Delay (tDATA)4 DCO to FCO Delay (tFRAME)4 Data to Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time Temp Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C Full Min 50 10 10.0 10.0 1.5 2.3 300 300 2.3 tFCO + (tSAMPLE/28) (tSAMPLE/28) (tSAMPLE/28) ±50 600 375 8 3.1 Typ Max Unit MSPS MSPS ns ns ns ps ps ns ns ps ps ps ns μs CLK cycles ps ps rms CLK cycles 1.5 3.1 (tSAMPLE/28) − 300 (tSAMPLE/28) − 300 (tSAMPLE/28) + 300 (tSAMPLE/28) + 300 ±200 25°C 25°C 25°C 750