AD9626BCPZ-210

12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter AD9626 FEATURES SNR = 64.8 dBFS @ fIN up to 70 MHz @ 250 MSPS ENOB of 10.5 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) SFDR = 80 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS) Excellent linearity DNL = ±0.3 LSB typical INL = ±0.7 LSB typical CMOS outputs Single data port at up to 250 MHz Interleaved dual port @ ½ sample rate up to 125 MHz 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation 272 mW @ 170 MSPS 364 mW @ 250 MSPS Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, Gray code) Clock duty cycle stabilizer Integrated data capture clock APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization FUNCTIONAL BLOCK DIAGRAM RBIAS PWDN AGND AVDD (1.8V) REFERENCE CML VIN+ VIN– TRACK-AND-HOLD ADC 12-BIT CORE CLK+ CLK– CLOCK MANAGEMENT 12 AD9626 DRVDD DRGND OUTPUT 12 STAGING LVDS Dx11 TO Dx0 OVRA OVRB SERIAL PORT DCO+ 07099-001 DCO– RESET SCLK SDIO CSB Figure 1. GENERAL DESCRIPTION The AD9626 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are CMOS compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9626 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. 2. 3. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS with a 70 MHz input. Low Power—Consumes only 364 mW @ 250 MSPS. Ease of Use—CMOS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control—Standard serial port interface supports various product functions, such as data formatting, clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family—10-bit pin-compatible family offered as the AD9601. 4. 5. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD9626 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams.......................................................................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Equivalent Circuits ......................................................................... 11 Typical Performance Characteristics ........................................... 12 Theory of Operation ...................................................................... 18 Analog Input and Voltage Reference ....................................... 18 Clock Input Considerations...................................................... 19 Power Dissipation and Power-Down Mode ........................... 20 Digital Outputs ........................................................................... 20 Timing—Single Port Mode ....................................................... 21 Timing—Interleaved Mode....................................................... 21 Layout Considerations................................................................... 22 Power and Ground Recommendations ................................... 22 CML ............................................................................................. 22 RBIAS........................................................................................... 22 AD9626 Configuration Using the SPI ..................................... 22 Hardware Interface..................................................................... 23 Configuration Without the SPI ................................................ 23 Memory Map .................................................................................. 25 Reading the Memory Map Table.............................................. 25 Reserved Locations .................................................................... 25 Default Values ............................................................................. 25 Logic Levels................................................................................. 25 Evaluation Board ............................................................................ 27 Outline Dimensions ....................................................................... 33 Ordering Guide .......................................................................... 33 REVISION HISTORY 11/07—Revision 0: Initial Version Rev. 0 | Page 2 of 36 AD9626 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance POWER SUPPLY AVDD DRVDD Supply Currents IAVDD 3 IDRVDD3/Single Port Mode 4 IDRVDD3/Interleaved Mode 5 Power Dissipation3 Single Port Mode4 Interleaved Mode5 Power-Down Mode Supply Currents IAVDD IDRVDD Standby Mode Supply Currents IAVDD IDRVDD 1 2 Temp Min AD9626-170 Typ Max 12 Guaranteed 4.0 Min AD9626-210 Typ Max 12 Guaranteed 4.0 Min AD9626-250 Typ Max 12 Guaranteed 4.0 Unit Bits Full 25°C Full 25°C Full 25°C Full 25°C Full Full Full Full Full Full 25°C Full Full Full Full Full Full Full Full −12 1.4 −2.1 0.3 −0.6 0.7 −1.4 ±8 0.021 0.98 1.25 1.4 4.3 2 1.8 1.8 134 17 15 272 268 +12 +4.5 +0.6 +1.4 −12 1.4 −2.1 0.3 −0.6 0.6 −1.1 ±8 0.021 +12 +4.5 +0.6 +1.1 −12 1.4 −2.1 0.3 −0.6 0.7 −1.7 ±8 0.021 +12 +4.5 +0.6 +1.7 mV mV % FS % FS LSB LSB LSB LSB μV/°C %/°C 1.5 0.98 1.25 1.4 4.3 2 1.8 1.8 151 21 18 310 304 1.5 0.98 1.25 1.4 4.3 2 1.8 1.8 178 24 20 364 357 1.5 V p-p V kΩ pF V V mA mA mA mW mW mW 1.7 1.58 1.9 1.9 143 18.5 1.7 1.7 1.9 1.9 161 22 1.7 1.7 1.9 1.9 191 25.5 291 330 390 Full Full Full Full 40 170 19 170 40 170 19 170 22 40 170 19 170 μA μA mA μA 22 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9626. 5 Interleaved mode; user-programmable feature. See the Memory Map section. Rev. 0 | Page 3 of 36 AD9626 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, , Single Port Output mode, DCS enabled, unless otherwise noted. 1 Table 2. Parameter 2 SNR fIN = 10 MHz fIN = 70 MHz SINAD fIN = 10 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 70 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 10 MHz fIN = 70 MHz WORST OTHER (SFDR EXCLUDING SECOND AND THIRD) fIN = 10 MHz fIN = 70 MHz T WO-TONE IMD 140.2 MHz/141.3 MHz @ −7 dBFS 170.2 MHz/171.3 MHz @ −7 dBFS ANALOG INPUT BANDWIDTH 1 2 Temp 25°C Full 25°C Full 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full Min AD9626-170 Typ Max 64.5 63.6 64.4 63.0 64.5 63.5 64.2 62.6 10.6 10.5 84 75 79 71 Min AD9626-210 Typ Max 64.4 63.0 64.2 62.3 64.4 62.8 64.0 62.0 10.6 10.5 86 77 79 73 Min AD9626-250 Typ Max 64.0 63.8 Unit dB dB dB dB dB dB dB dB Bits Bits dBc dBc dBc dBc 64.0 63.4 10.5 10.5 83 73 80 71 25°C Full 25°C Full 25°C 25°C 25°C 92 85 92 81 80 700 90 79 87 77 84 76 84 73 dBc dBc dBc dBc dBFS dBc MHz 83 700 83 700 All ac specifications tested by driving CLK+ and CLK− differentially. See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 36 AD9626 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Input Resistance (Differential) Input Capacitance LOGIC INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current (SDIO) Logic 0 Input Current (SDIO) Logic 1 Input Current (SCLK, PDWN, CSB, RESET) Logic 0 Input Current (SCLK, PDWN, CSB, RESET) Input Capacitance LOGIC OUTPUTS 2 High Level Output Voltage Low Level Output Voltage Output Coding 1 2 Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C Full Full Min AD9626-170 Typ Max Min AD9626-210 Typ Max Min AD9626-250 Typ Max Unit CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − AVDD + 0.3 1.6 1.1 AVDD 1.2 3.6 0 0.8 16 20 24 4 0.8 × AVDD 0.2 × AVDD 0 −60 55 0 4 CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − AVDD + 0.3 1.6 1.1 AVDD 1.2 3.6 0 0.8 16 20 24 4 0.8 × AVDD 0.2 × AVDD 0 −60 55 0 4 CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − AVDD + 0.3 1.6 1.1 AVDD 1.2 3.6 0 0.8 16 20 24 4 0.8 × AVDD 0.2 × AVDD 0 −60 50 0 4 V V p-p V V V V kΩ pF V V μA μA μA μA pF V V DRVDD − 0.05 DRVDD − 0.05 DRVDD − 0.05 GND + 0.05 GND + 0.05 GND + 0.05 Twos complement, Gray code, or offset binary (default) See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. LVDS RTERMINATION = 100 Ω. Rev. 0 | Page 5 of 36 AD9626 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 4. Parameter (Conditions) Maximum Conversion Rate Minimum Conversion Rate CLK+ Pulse Width High (tCH) CLK+ Pulse Width Low (tCL) Output, Single Data Port Mode 1 Data Propagation Delay (tPD) DCO Propagation Delay (tCPD) Data to DCO Skew (tSKEW) Latency Output, Interleaved Mode 2 Data Propagation Delay (tPDA, tPDB) DCO Propagation Delay (tCPDA, tCPDB) Data to DCO Skew (tSKEWA, tSKEWB ) Latency Standby Recovery Power-Down Recovery Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) 1 2 Temp Full Full Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C 25°C Min 170 2.65 2.65 AD9626-170 Typ Max 40 2.9 2.9 3.7 3.4 0.3 6 3.5 3.0 0.5 6 250 50 0.1 0.2 Min 210 2.15 2.15 AD9626-210 Typ Max 40 2.4 2.4 3.7 3.4 0.3 6 3.5 3.0 0.5 6 250 50 0.1 0.2 Min 250 1.8 1.8 AD9626-250 Typ Max 40 2.0 2.0 3.7 3.4 0.3 6 3.5 3.0 0.5 6 250 50 0.1 0.2 Unit MSPS MSPS ns ns ns ns ns Cycles ns ns ns Cycles ns μs ns ps rms 0 0.55 0 0.55 0 0.55 0 1.1 0 1.1 0 1.1 See Figure 2. See Figure 3. Rev. 0 | Page 6 of 36 AD9626 TIMING DIAGRAMS N+1 N N+2 N+3 N+4 tA tCLK = 1/fCLK CLK+ CLK– DCO– DCO+ N+8 N+5 N+6 N+7 tCPD tSKEW N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 07099-051 tPD DAX Figure 2. Single Port Mode N+1 N N+2 N+3 N+4 tA tCLK = 1/fCLK CLK+ CLK– DCO+ DCO– N+8 N+5 N+6 N+7 tCPDA tCPDB tSKEWA tPDA DAX N–6 N–4 N–2 N N+2 tSKEWB tPDB DBX N–7 N–5 N–3 N–1 N+1 07099-050 Figure 3. Interleaved Mode Rev. 0 | Page 7 of 36 AD9626 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD Dx0 Through Dx11 to DRGND DCO+/DCO− to DRGND OVRA/OVRB to DGND CLK+ to AGND CLK− to AGND VIN+ to AGND VIN− to AGND SDIO/DCS to DGND PDWN to AGND CSB to AGND SCLK/DFS to AGND ENVIRONMENTAL Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +2.0 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +3.6 V −65°C to +125°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 6. Package Type 56-Lead LFCSP (CP-56-2) θJA 30.4 θJC 2.9 Unit °C/W Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes reduces the θJA. ESD CAUTION Rev. 0 | Page 8 of 36 AD9626 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DA5 DA4 DA3 DA2 DA1 DA0 (LSB) DCO+ DCO– DRGND DRVDD AVDD CLK– CLK+ AVDD DA6 DA7 DA8 DA9 DA10 (MSB) DA11 DRVDD DRGND OVRA (LSB) DB0 DB1 DB2 DB3 DB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PIN 1 INDICATOR AD9626 TOP VIEW (Not to Scale) PIN 0 (EXPOSED PADDLE) = AGND AVDD AVDD CML AVDD AVDD AVDD VIN– VIN+ AVDD AVDD AVDD RBIAS AVDD PWDN DB5 DB6 DB7 DB8 DB9 DB10 (MSB) DB11 OVRB DRGND DRVDD SDIO/DCS SCLK/DFS CSB RESET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Figure 4. Pin Configuration Table 7. Single Data Rate Mode Pin Function Descriptions Pin No. 30, 32, 33, 34, 37, 38, 39, 41, 42, 43, 46 7, 24, 47 0 8, 23, 48 35 36 40 44 45 31 28 25 26 27 29 49 50 51 52 53 54 55 56 1 2 Mnemonic AVDD DRVDD AGND 1 DRGND1 VIN+ VIN− CML CLK+ CLK− RBIAS RESET SDIO/DCS SCLK/DFS CSB PWDN DCO− DCO+ DA0 (LSB) DA1 DA2 DA3 DA4 DA5 DA6 DA7 Description 1.8 V Analog Supply. 1.8 V Digital Output Supply. Analog Ground. Digital Output Ground. Analog Input—True. Analog Input—Complement. Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN−. Clock Input—True. Clock Input—Complement. Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V. CMOS-Compatible Chip Reset (Active Low). Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). Serial Port Chip Select (Active Low). Chip Power-Down. Data Clock Output—Complement. Data Clock Output—True. Output Port A Output Bit 0 (LSB). Output Port A Output Bit 1. Output Port A Output Bit 2. Output Port A Output Bit 3. Output Port A Output Bit 4. Output Port A Output Bit 5. Output Port A Output Bit 6. Output Port A Output Bit 7. Rev. 0 | Page 9 of 36 07099-002 AD9626 Pin No. 3 4 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 Mnemonic DA8 DA9 DA10 DA11 (MSB) OVRA DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 (MSB) OVRB Description Output Port A Output Bit 8. Output Port A Output Bit 9. Output Port A Output Bit 10. Output Port A Output Bit 11 (MSB). Output Port A Overrange Output Bit. Output Port B Output Bit 0 (LSB). Output Port B Output Bit 1. Output Port B Output Bit 2. Output Port B Output Bit 3. Output Port B Output Bit 4. Output Port B Output Bit 5. Output Port B Output Bit 6. Output Port B Output Bit 7. Output Port B Output Bit 8. Output Port B Output Bit 9. Output Port B Output Bit 10. Output Port B Output Bit 11 (MSB). Output Port B Overrange Output Bit. AGND and DRGND should be tied to a common quiet ground plane. Rev. 0 | Page 10 of 36 AD9626 EQUIVALENT CIRCUITS AVDD AVDD 26k Ω CSB 1kΩ 1.2V CLK+ 10kΩ 10kΩ CLK– Figure 5. Clock Inputs 07099-003 Figure 8. Equivalent CSB Input Circuit AVDD DRVDD VIN+ 2kΩ AVDD BUF AVDD BUF 2kΩ BUF VCML ~1.4V VIN– 07099-006 07099-004 DRGND Figure 6. Analog Inputs (VCML = ~1.4 V) Figure 9. CMOS Outputs (Dx, OVRA, OVRB, DCO+, DCO−) SCLK/DFS RESET PDWN 1kΩ 30kΩ DRVDD 1kΩ SDIO/DCS 07099-005 Figure 7. Equivalent SCLK/DFS, RESET, PDWN Input Circuit Figure 10. Equivalent SDIO/DCS Input Circuit Rev. 0 | Page 11 of 36 07099-007 07099-052 AD9626 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, TA = 25°C, 1.25 V p-p differential input, AIN = −1 dBFS, unless otherwise noted. 0 –20 –40 –60 –80 –100 –120 –140 170MSPS 10.3MHz @ –1.0dBFS SNR: 64.5dB ENOB: 10.6 BITS SFDR: 84dBFS NUMBER OF HITS 35k 30k 25k 20k 15k 10k 5k 0 AMPLITUDE (dBFS) 0 10 20 30 40 50 60 70 80 N–4 N–3 N–2 N–1 N BIN N+1 N+2 N+3 N+4 FREQUENCY (MHz) Figure 11. AD9626-170 64k Point Single-Tone FFT; 170 MSPS, 10.3 MHz Figure 14. AD9626-170 Grounded Input Histogram; 170 MSPS 0 –20 –40 –60 –80 –100 –120 –140 170MSPS 70.3MHz @ –1.0dBFS SNR: 64.4dB ENOB: 10.5 BITS SFDR: 79dBFS SNR/SFDR (dB) 90 SFDR (+85°C) 85 80 75 SFDR (–40°C) 70 65 60 SNR (+85°C) 55 50 SNR (–40°C) 07099-024 07099-025 SFDR (+25°C) AMPLITUDE (dBFS) SNR (+25°C) 07099-021 0 10 20 30 40 50 60 70 80 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Figure 12. AD9626-170 64k Point Single-Tone FFT; 170 MSPS, 70.3 MHz Figure 15. AD9626-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 1.25 V p-p Full Scale; 170 MSPS 100 0 –20 –40 –60 –80 –100 –120 –140 170MSPS 140.3MHz @ –1.0dBFS SNR: 63.7dB ENOB: 10.4 BITS SFDR: 80dBc SNR/SFDR (dB) 90 SFDR (dBFS) 80 70 SNR (dBFS) 60 50 40 30 SFDR (dBc) 20 10 SNR (dB) AMPLITUDE (dBFS) 0 07099-022 10 20 30 40 50 60 70 80 0 90 80 70 60 50 40 30 20 10 0 FREQUENCY (MHz) AMPLITUDE (–dBFS) Figure 13. AD9626-170 64k Point Single-Tone FFT; 170 MSPS, 140.3 MHz Figure 16. AD9626-170 SNR/SFDR vs. Input Amplitude; 140.3 MHz Rev. 0 | Page 12 of 36 07099-023 07099-020 AD9626 1.0 0.8 0.6 80 0.4 SNR/SFDR (dB) INL (LSB) 90 85 SFDR (+25°C) 0.2 0 –0.2 –0.4 75 70 SNR (–40°C) 65 60 SNR (+85°C) SFDR (+85°C) SFDR (–40°C) –0.6 –0.8 07099-026 SNR (+25°C) 55 50 0 512 1024 1536 2048 2560 3072 3584 4096 0 50 100 150 200 250 300 350 400 450 500 OUTPUT CODE ANALOG INPUT FREQUENCY (MHz) Figure 17. AD9626-170 INL; 170 MSPS Figure 20. SNR/SFDR vs. Analog Input Frequency, Interleaved Mode vs. Temperature 0 –20 –40 –60 –80 –100 –120 –140 210MSPS 10.3MHz @ –1.0dBFS SNR: 64.5dB ENOB: 10.6 BITS SFDR: 86dBc 400 350 300 250 200 150 100 50 0 IDVDD (mA) IAVDD (mA) AMPLITUDE (dBFS) TOTAL POWER (mW) CURRENT (mA) 07099-027 5 25 45 65 85 105 125 145 165 185 205 225 245 0 20 40 60 80 100 SAMPLE RATE (MSPS) FREQUENCY (MHz) Figure 18. AD9626-170 Power Supply Current vs. Sample Rate Figure 21. AD9626-210 64k Point Single-Tone FFT; 210 MSPS, 10.3 MHz 1.0 0.8 0.6 AMPLITUDE (dBFS) 0 –20 –40 –60 –80 –100 –120 –140 210MSPS 70.3MHz @ –1.0dBFS SNR: 64.2dB ENOB: 10.5 BITS SFDR: 79dBc 0.4 DNL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 07099-028 0 512 1024 1536 2048 2560 3072 3584 4096 0 20 40 60 80 100 OUTPUT CODE FREQUENCY (MHz) Figure 19. AD9626-170 DNL; 170 MSPS Figure 22. AD9626-210 64k Point Single-Tone FFT; 210 MSPS, 70.3 MHz Rev. 0 | Page 13 of 36 07099-031 –1.0 07099-030 07099-029 –1.0 AD9626 0 –20 –40 –60 –80 –100 –120 –140 210MSPS 170.3MHz @ –1.0dBFS SNR: 63.23dB ENOB: 10.4 BITS SFDR: 78dBc SNR/SFDR (dB) 100 90 80 70 60 50 40 30 SNR (dB) 20 10 07099-032 SFDR (dBFS) AMPLITUDE (dBFS) SNR (dBFS) SFDR (dBc) 0 20 40 60 80 100 80 70 60 50 40 30 20 10 0 FREQUENCY (MHz) AMPLITUDE (–dBFS) Figure 23. AD9626-210 64k Point Single-Tone FFT; 210 MSPS, 170.3 MHz Figure 26. AD9626-210 SNR/SFDR vs. Input Amplitude; 210 MSPS, 170.3 MHz 35k 30k 25k NUMBER OF HITS 1.0 0.8 0.6 0.4 INL (LSB) 20k 15k 10k 5k 0 0.2 0 –0.2 –0.4 –0.6 –0.8 07099-033 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 BIN 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE Figure 24. AD9626-210 Grounded Input Histogram; 210 MSPS Figure 27. AD9626-210 INL; 210 MSPS 90 85 80 SNR/SFDR (dB) 400 350 SFDR (+85°C) 300 CURRENT (mA) TOTAL POWER (mW) 75 70 SNR (–40°C) 65 60 55 50 SNR (+85°C) SNR (+25°C) SFDR (+25°C) SFDR (–40°C) 250 200 150 100 50 0 IDVDD (mA) IAVDD (mA) 07099-034 0 50 100 150 200 250 300 350 400 450 500 5 25 45 65 85 105 125 145 165 185 205 225 245 ANALOG INPUT FREQUENCY (MHz) SAMPLE RATE (MSPS) Figure 25. AD9626-210 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 1.25 V p-p Full Scale; 210 MSPS Figure 28. AD9626-210 Power Supply Current vs. Sample Rate Rev. 0 | Page 14 of 36 07099-037 07099-036 –1.0 07099-035 0 90 AD9626 1.0 0.8 0.6 AMPLITUDE (dBFS) 0 –20 –40 –60 –80 –100 –120 –140 250MSPS 170MHz @ –1.0dBFS SNR: 62.9dB ENOB: 10.2 BITS SFDR: 72dBc 0.4 DNL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 07099-038 0 512 1024 1536 2048 2560 3072 3584 4096 0 20 40 60 80 100 120 OUTPUT CODE FREQUENCY (MHz) Figure 29. AD9626-210 DNL; 210 MSPS Figure 32. AD9626-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz 0 –20 –40 –60 –80 –100 –120 –140 250MSPS 10.3MHz @ –1.0dBFS SNR: 64.0dB ENOB: 10.5 BITS SFDR: 83dBc NUMBER OF HITS 35k 30k 25k 20k 15k 10k 5k 0 AMPLITUDE (dBFS) 07099-039 0 20 40 60 80 100 120 N–4 N–3 N–2 N–1 N BIN N+1 N+2 N+3 N+4 FREQUENCY (MHz) Figure 30. AD9626-250 64k Point Single-Tone FFT; 250 MSPS, 10.3 MHz Figure 33. AD9626-250 Grounded Input Histogram; 250 MSPS 0 –20 –40 –60 –80 –100 –120 –140 250MSPS 70.3MHz @ –1.0dBFS SNR: 63.8dB ENOB: 10.6 BITS SFDR: 80dBc SNR/SFDR (dB) 90 85 SFDR (+25°C) 80 75 70 SNR (–40°C) 65 60 55 50 SNR (+85°C) SFDR (–40°C) SFDR (+85°C) AMPLITUDE (dBFS) SNR (+25°C) 07099-057 0 20 40 60 80 100 120 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Figure 31. AD9626-250 64k Point Single-Tone FFT; 250 MSPS, 70.3 MHz Figure 34. AD9626-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 1.25 V p-p Full Scale; 250 MSPS Rev. 0 | Page 15 of 36 07099-042 07099-041 07099-040 –1.0 AD9626 100 90 80 70 SNR/SFDR (dB) DNL (LSB) 1.0 SFDR (dBFS) 0.8 0.6 0.4 SNR (dBFS) 0.2 0 –0.2 –0.4 SNR (dB) –0.6 –0.8 07099-043 60 50 40 30 20 10 0 90 SFDR (dBc) 80 70 60 50 40 30 20 10 0 0 512 1024 1536 2048 2560 3072 3584 4096 AMPLITUDE (–dBFS) OUTPUT CODE Figure 35. AD9626-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz Figure 38. AD9626-250 DNL; 250 MSPS 1.0 0.8 0.6 0.4 INL (LSB) 90 SFDR 80 70 SNR/SFDR (dB) 60 50 40 30 20 10 0.2 0 –0.2 –0.4 –0.6 –0.8 07099-044 SNR 0 512 1024 1536 2048 2560 3072 3584 4096 95 115 135 155 175 195 215 235 255 275 OUTPUT CODE SAMPLE RATE (MSPS) Figure 36. AD9626-250 INL; 250 MSPS Figure 39. SNR/SFDR vs. Sample Rate; 250 MSPS, 170.3 MHz @ −1 dBFS 2.5 450 400 2.0 350 CURRENT (mA) TOTAL POWER (mW) 1.5 AD9626-250 300 GAIN (%FS) 250 200 150 100 50 0 IDVDD (mA) IAVDD (mA) AD9626-210 1.0 AD9626-170 0.5 0 5 25 45 65 85 105 125 145 165 185 205 225 245 07099-045 –40 –20 0 20 40 60 80 100 120 SAMPLE RATE (MSPS) TEMPERATURE (°C) Figure 37. AD9626 Power Supply Current vs. Sample Rate Figure 40. Gain vs. Temperature Rev. 0 | Page 16 of 36 07099-048 –0.5 –60 07099-047 –1.0 0 75 07099-046 –1.0 AD9626 6.0 5.5 AD9626-250 5.0 OFFSET (mV) 4.5 4.0 AD9626-210 AD9626-170 3.5 3.0 2.5 2.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) Figure 41. Offset vs. Temperature 07099-049 Rev. 0 | Page 17 of 36 AD9626 THEORY OF OPERATION The AD9626 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be ac- or dc-coupled. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During powerdown, the output buffers go into a high impedance state. 1V p-p 49.9Ω 499Ω 499Ω 523Ω 0.1µF 33Ω 499Ω 33Ω AVDD VIN+ AD8138 20pF AD9626 VIN– 07099-008 CML Figure 42. Differential Input Configuration Using the AD8138 At input frequencies in the second Nyquist zone and above, the performance of most amplifiers may not be adequate to achieve the true performance of the AD9626. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few millihertz, and excessive signal power can also cause core saturation, which leads to distortion. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. 15Ω 1.25V p-p 50Ω 2pF VIN+ ANALOG INPUT AND VOLTAGE REFERENCE The analog input to the AD9626 is a differential buffer. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. A wideband transformer, such as Mini-Circuits® ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are self-biased by an on-chip resistor divider to a nominal 1.4 V. An internal differential voltage reference creates positive and negative reference voltages that define the 1.25 V p-p fixed span of the ADC core. This internal voltage reference can be adjusted by means of SPI control. See the AD9626 Configuration Using the SPI section for more details. AD9626 VIN– 07099-009 15Ω 0.1µF Figure 43. Differential Transformer-Coupled Configuration As an alternative to using a transformer-coupled input at frequencies in the second Nyquist zone, the AD8352 differential driver can be used (see Figure 44). VCC 0.1µF 0.1µF ANALOG INPUT 0Ω 16 1 2 200 Ω CD RD RG 3 ANALOG INPUT 0.1µF 0Ω 4 5 14 0.1µF 07099-010 8, 13 11 0.1µF R VIN+ C R Differential Input Configurations Optimum performance is achieved while driving the AD9626 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. AD8352 10 0.1µF 200 Ω AD9626 VIN– CML 0.1µF Figure 44. Differential Input Configuration Using the AD8352 Rev. 0 | Page 18 of 36 AD9626 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9626 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ pin and the CLK− pin via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 45 shows one preferred method for clocking the AD9626. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9626 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9626 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. MINI-CIRCUITS ADT1–1WT, 1:1Z 0.1µF XFMR 100Ω 0.1µF 0.1µF SCHOTTKY DIODES: HSM2812 In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 48). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the selection of the drive logic voltage very flexible. 0.1µF CLK AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 OPTIONAL 0.1µF 100Ω CLOCK INPUT 50Ω* CMOS DRIVER CLK CLK+ AD9626 CLK– ADC 0.1µF 0.1µF *50Ω RESISTOR IS OPTIONAL. 39kΩ 07099-014 0.1µF CLOCK INPUT 50Ω Figure 48. Single-Ended 1.8 V CMOS Sample Clock CLK+ AD9626 CLK– 07099-011 ADC CLOCK INPUT 0.1µF CLK 50Ω* AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 OPTIONAL 0.1µF 100Ω Figure 45. Transformer-Coupled Differential Clock CMOS DRIVER CLK CLK+ If a low jitter clock is available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 46. The AD9510/AD9511/AD9512/AD9513/ AD9514/AD9515 family of clock drivers offers excellent jitter performance. AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 CLOCK INPUT 0.1µF CLK PECL DRIVER CLK 50Ω* 50Ω* 240Ω 240Ω 07099-012 0.1µF 0.1µF AD9626 CLK– 07099-015 ADC *50Ω RESISTOR IS OPTIONAL. Figure 49. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations 0.1µF CLK+ 100Ω 0.1µF CLOCK INPUT 0.1µF AD9626 CLK– ADC *50Ω RESISTORS ARE OPTIONAL. Figure 46. Differential PECL Sample Clock CLOCK INPUT 0.1µF CLK AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1µF CLK+ 100Ω 0.1µF CLOCK INPUT 50Ω* 0.1µF 50Ω* LVDS DRIVER CLK ADC AD9626 CLK– 07099-013 Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9626 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9626. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the AD9626 Configuration Using the SPI section for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. *50Ω RESISTORS ARE OPTIONAL. Figure 47. Differential LVDS Sample Clock Rev. 0 | Page 19 of 36 AD9626 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR for a full-scale input signal at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR Degradation = 20 × log10[1/2 × π × fA × tJ] In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 50). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9626. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs (visit www.analog.com). 130 120 110 100 SNR (dB) and internal reference remain on, but digital circuitry is powered down. Upon reactivating the clock, the AD9626 resumes normal operation after allowing for the pipeline latency. DIGITAL OUTPUTS Digital Outputs and Timing The off-chip drivers on the AD9626 are CMOS-compatible output levels. The outputs are biased from a separate supply (DRVDD), allowing isolation from the analog supply and easy interface to external logic. The outputs are CMOS devices that swing from ground to DRVDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short ( 0.62 + 0.5 LSB OR 1 0 0 0 1 Rev. 0 | Page 24 of 36 AD9626 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), transfer register map (Address 0xFF), and program register map (Address 0x08 to Address 0x2A). The Addr (Hex) column of the memory map indicates the register address in hexadecimal, and the Default Value (Hex) column shows the default hexadecimal value that is already written into the register, The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x09, clock, has a hexadecimal default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The default value enables the duty cycle stabilizer. Overwriting this default so that Bit 0 = 0 disables the duty cycle stabilizer. For more information on this and other functions, consult the Interfacing to High Speed ADCs via SPI user manual at www.analog.com. Table 12. Memory Map Register Addr Bit 7 (Hex) Parameter Name (MSB) Chip Configuration Registers 00 chip_port_config 0 Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first Bit 0 (LSB) 0 Default Value (Hex) 0x18 Default Notes/ Comments The nibbles should be mirrored by the user so that LSB or MSB first mode registers correctly, regardless of shift mode. Default is unique chip ID, different for each device. This is a read-only register. Child ID used to differentiate graded devices. RESERVED LOCATIONS Undefined memory locations should not be written to other than their default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES Coming out of reset, critical registers are preloaded with default values. These values are indicated in Table 12. Other registers do not have default values and retain the previous value when exiting reset. LOGIC LEVELS An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” 01 chip_id 8-bit chip ID, Bits[7:0] AD9626 = 0x3c Readonly 02 chip_grade 0 0 0 Speed grade: 00 = 170 MSPS 01 = 210 MSPS 10 = 250 MSPS 0 0 X X X Readonly Transfer Register FF device_update 0 0 0 0 0 SW transfer 0x00 Synchronously transfers data from the master shift register to the slave. Determines various generic modes of chip operation. ADC Functions 08 modes 0 0 PDWN: 0 = full (default) 1= standby 0 0 Internal power-down mode: 000 = normal (power-up, default) 001 = full power-down 010 = standby 011 = normal (power-up) Note: external PDWN pin overrides this setting 0x00 Rev. 0 | Page 25 of 36 AD9626 Addr (Hex) 09 Parameter Name clock Bit 7 (MSB) 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 (LSB) Duty cycle stabilizer: 0= disabled 1= enabled (default) Default Value (Hex) 0x01 Default Notes/ Comments OD test_io Reset PN23 gen: 1 = on 0 = off (default) Reset PN9 gen: 1 = on 0 = off (default) OF ain_config 0 0 0 0 14 output_mode 0 0 16 output_phase 17 flex_output_delay Output clock polarity 1= inverted 0= normal (default) Output delay enable: 0= enable 1= disable 0 Interleave output mode: 1= enabled 0= disabled (default) 0 Output enable: 0= enable (default) 1= disable 0 Output test mode: 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checker board output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = unused 1001 = unused 1010 = unused 1011 = unused 1100 = unused (Format determined by output_mode) CML 0 0 Analog enable: input disable: 1 = on 1 = on 0 = off 0 = off (default) (default) Data format select: 0 Output 00 = offset binary invert: (default) 1 = on 01 = twos 0 = off complement (default) 10 = Gray code 0x00 When set, the test data is placed on the output pins in place of normal data. 0x00 0x00 0x03 18 flex_vref Output clock delay: 00000 = 0.1 ns 00001 = 0.2 ns 00010 = 0.3 ns … 11101 = 3.0 ns 11110 = 3.1 ns 11111 = 3.2 ns Input voltage range setting: 10000 = 0.98 V 10001 =1.00 V 10010 = 1.02 V 10011 =1.04 V … 11111 = 1.23 V 00000 = 1.25 V 00001 = 1.27 V … 01110 = 1.48 V 01111 = 1.50 V 0x00 0x00 Rev. 0 | Page 26 of 36 GND P7 CONNECTS TO J2 GNDCD10 VSPI E32 E31 RN1 50_OHMS D10 C9 GNDCD8 GNDCD7 GNDCD6 GNDCD5 C5 C4 C3 C2 C1 A10 GNDCD4 GNDCD3 GNDCD2 GNDCD1 GNDAB10 GNDAB9 C8 C7 C6 D9 D8 D7 D6 D5 D4 D3 D2 D1 B10 E33 CSB DOR C10 GNDCD9 D10 50 49 48 47 46 45 44 43 42 41 20 GND GND GND GND GND CSB_DUT D8 D6 1 16 DOR D4 D2 D0 DORB D11 D11B D10 D10B D9 D9B D11 D9 50_OHMS P17 P16 P10 P9 SCLK_DTP SDIO_ODM DORB D10B D8B D6B D4B D2B D0B GND GND P1 GND GND P5 P4 P3 P2 EVALUATION BOARD 2 15 14 13 12 11 10 9 3 R13 1K 4 5 6 7 8 CSB DRVDD GND R10 1K E1 E3 E2 GND VSPI VSPI AVDD GND E4 E5 E10 IN GND RN2 R12 10K SW3 1 EVQ-Q2 20 19 18 17 28 27 26 25 24 23 22 21 16 15 ANALOG 2 1 D8 14 3 4 5 6 7 GND DRVDD 50_OHMS RN3 1 2 3 4 D1 D2 D2B OUT R11 1K A9 A8 GNDAB8 GNDAB7 B9 B8 19 18 D11B D9B D7 A7 GNDAB6 B7 17 Alternate Options D7B 16 15 14 13 12 11 10 D8 D8B D7 D7B D6 DCO D5 D3 D1 A6 A5 A4 A3 A2 A1 GNDAB5 GNDAB4 GNDAB3 GNDAB2 GNDAB1 B6 B5 B4 B3 B2 B1 16 15 14 13 12 11 D5B D3B D1B Input D11 D10 D9B DOR 6 2 4 T3 ADT1-1WT GND D9 1 VSPI E9 E8 AVDD 30 31 12 11 10 9 8 7 6 AVDD 32 33 34 35 36 AVDD 37 38 39 40 AVDD 41 D0 DCOB CLKB DCO CLK D0B D1B DGND2 DVDD2 E7 29 AVDD_REF 13 RBIAS D7 D7B D6 D6B AVDD_PIPE5 AVDD_PIPE4 AVDD_PIPE3 AIN DGND DVDD D5 D5B AINB AVDD_PIPE2 AVDD_PIPE1 AVDD_PIPE CML AVDD_FL1 AVDD_FL 43 44 45 46 51 52 47 48 49 50 D11B D10B DORB SPCSB DVDD1 DGND1 5 RESETB PDN 2 D8B SPSDIO/DCS SPSCLK/DFS GND 5 2 4 CML GND CML nc TINB GND TOUT R7 33 3 PRI SEC C19 AMPOUT+ AVDD AVDD DNP L8 0 TOUT CML TOUTB R4 DNP GND 0.1UF 0.1UF C21 C16 T5 GND 1 60 40 59 39 58 38 57 37 56 36 55 35 54 34 53 33 52 32 51 31 30 10 29 9 28 8 27 7 26 6 25 5 24 4 23 3 22 2 21 1 DCOB HEADERM1469169_1 8 9 D6B GND 0.1UF C22 0.1UF GND 3 1 J2 R5 36 CML R6 36 GND R16 33 optional C17 3 PRI SEC L1 10NH TINB ETC1-1-13 T6 R9 DNP U4 AD9626_CSP 0.1UF C18 AVDD 42 AVDD_CLK CMLX L9 PRI SEC ETC1-1-13 GND 5 2 4 E6 TOUTB GND AVDD AVDD P11 CONNECTS TO J1 GNDCD10 16 15 14 13 5 12 D5 D5B D4 D4B D3 C10 GNDCD9 D10 C9 GNDCD8 D9 C8 C7 GNDCD7 GNDCD6 D8 50 49 48 D7 47 C6 GNDCD5 D6 46 0 C75 GND GND R1 R8 00 CLK 50 1 2 3 0.1UF ENCODE CLKCT nc GND 3 4 C15 0.1UF CR3 CR2 2 1 PRI SEC 3 07099-053 C74 0.1UF GND Figure 54. AD9601 Evaluation Board Schematic Page 1 AVDD_CLK1 Rev. 0 | Page 27 of 36 AMPOUT5 D4 4 D4B 3 D3 2 D3B 1 PAD 53 54 55 56 57 R17 0 DNP CML 6 7 GND 11 10 8 9 D3B C5 C4 C3 C2 GNDCD4 GNDCD3 GNDCD2 GNDCD1 D5 D4 D3 D2 C1 GNDAB10 D1 45 44 43 42 41 GND AVDD AVDD DRVDD CR2 TO MAKE LAYOUT AND PARASITIC LOADING SYMMETRICAL GND CLK 1 2 3 4 VCLK 5 6 R85 10K 7 RN4 50_OHMS A10 A9 A8 GNDAB9 B10 GNDAB8 B9 GNDAB7 B8 20 19 J3 T2 CLKCT DNP GND 0.1UF C23 R90 00 R14 DNP C20 DNP R89 00 16 15 14 13 12 11 10 18 D2 D2B D1 D1B D0 D0B CSB1_CHA A7 A6 A5 A4 A3 A2 GNDAB6 B7 GNDAB5 B6 GNDAB4 B5 GNDAB3 B4 GNDAB2 B3 GNDAB1 B2 17 16 15 14 13 12 ADT1-1WT 1 6 5 2 SCLK_CH A SDI_CHA SDO_CHA J4 GND GND XTALINPUT 4 OUTPUT NC VCLK 5 6 XTALINPUT CVHD_956 Crystek Crystal U6 VOLT_CONTROL TRI_STATE GND 1 R87 R3 50 R15 DNP 0 OPTIONAL ENCODE CIRCUITS VOLT_CONTROL E18 2 3 E19 VCLK E20 GND GND DCO 8 GND R86 10K C61 0.1UF 9 DCOB 60 40 59 39 58 38 57 37 56 36 55 35 54 34 53 33 52 32 51 31 30 10 29 9 28 8 27 7 26 6 25 5 24 4 23 3 22 2 21 1 A1 B1 11 HEADERM1469169_1 VCLK AD9626 AD9626 AVDD C27 C65 C32 0.1UF C30 0.1UF C29 0.1UF C33 0.1UF C31 0.1UF 0.1UF C28 0.1UF C62 0.1UF C63 0.1UF C64 0.1UF 0.1UF 0.1UF C70 POWER OPTIONS GND P8 GND DRVDD C26 0.1UF C24 C13 0.1UF C67 C60 0.1UF 0.1UF C69 0.1UF C73 C68 0.1UF C72 C58 0.1UF 0.1UF C56 C14 10UF + 2 EGND 4 10UF VIN T1 GND GND 3 C9 C54 + 3 1 + U7 C11 499 R2 C36 EGND 0.1UF GND GND GND H4 MTHOLE6 H3 MTHOLE6 AVDDX DRVDDX1 VSPIEXTX GND H2 MTHOLE6 H1 MTHOLE6 0.1UF C35 C39 0.1UF C12 + 10UF C34 0.1UF C57 GND VAMPX GND GND C7 1UF GND GND 4 4 OUT OUT +5V 1.8V OUT1 GND IN OUT1 VSPIEXTX GND 1.8V 3.3V IN OUT OUT IN OUT1 GND 8 3 2 1 3 2 1 IN OUT1 GND 3 2 1 7 3 2 1 6 GND 5 4 DRVDDX1 3 2 R88 1 L7 FERRITE FERRITE L4 L2 FERRITE L5 FERRITE VAMP1 AVDD1 FERRITE L3 FERRITE DRVDD1 VSPI VSPIEXT1 VCLK L6 07099-054 Figure 55. AD9601 Evaluation Board Schematic Page 2 C3 C1 1UF 4 4 1UF P6 GND VSPIEXT1 GND DRVDD1 FERRITE L14 DRVDD 1.8V FERRITE L15 VSPIEXT 3.3V ADP3338 U10 ADP3338 U12 GND GND ADP3338 U11 ADP3338 U9 GND GND GND GND VSPIEXTX 1UF GND VIN AVDD1 FERRITE L13 GND VAMP1 FERRITE L12 VIN AVDD 1.8V VAMP +5.0V DRVDDX 0.1UF EGND 0.1UF 10UF VSPI VSPIEXT 0.1UF 0.1UF 1 2 0.1UF C59 C66 U8 C25 10UF VAMP 100PF EGND + 0.1UF PJ-102A VCLK C71 0.1UF C8 10UF + C5 1UF Rev. 0 | Page 28 of 36 C4 AVDDX C10 1UF 1UF C2 VIN 0 C6 VAMPX GND 1UF VIN 10K 10K GND VAMP R43 R42 GND E14 R91 00 CML .1UF GND VAMP 25 R37 1 2 RGP VOP 11 R41 00 VIP VCC ENB VCM 16 GND 12 GND 15 14 13 C46 E13 E12 Operational Amplifier C47 .1UF GND R94 00 T4 ADT1-1WT 1 6 .1UF GND GND R45 5 C37 00 R36 C40 DNP P13 SMBMST TINB1 R35 DNP L11 DNP C44 DNP TOUT2 RDP GND GND R40 DNP C43 DNP AMPOUT+ C76 R34 3 4 3 RGN VON 10 R46 00 DNP AMPOUT- nc PRI SEC 5 2 49.9 R33 R44 00 Z1 C41 00 R47 DNP P12 SMBMST DNP AD8352 L10 DNP C45 DNP 4 RDN GND GND 6 GND 7 8 VCC 5 9 25 R38 VIN C42 .1UF R39 5 VAMP TINB2 TOUTB2 AD9515 Logic Setup VCLK GND S0 TINB1 5 2 4 GND GND TOUT2 T7 1 3 R64 00 TINB2 TOUTB2 PRI SEC ETC1-1-13 VCLK S1 R63 00 GND R66 00 R65 00 VCLK S2 GND R68 00 VCLK R67 00 GND S3 R70 00 C53 CLK VCLK 0.1UF 100 R59 C50 CLK 0.1UF 240 R61 240 R60 VCLK S5 R69 00 R72 00 R71 00 R49 DNP C49 DNP R74 00 GND RSET P15 5 SYNCB CLK CLKB OUT0 OUT0B R73 00 C48 0.1UF R76 00 P14 VREF S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 GND C51 E17 0.1UF VCLK S7 R75 00 50 R48 00 R56 E15 00 R55 R50 DNP 6 7 8 9 10 11 12 13 14 15 16 25 R78 00 100 R58 C52 VCLK E16 0.1UF S8 GND GND DNC; 27, 28 VCLK; 1, 4, 17, 20, 21, 24, 26, 29, 30 GND R77 00 R80 00 R79 00 R82 00 R81 00 00 R83 00 R84 07099-055 S10 Figure 56. AD9601 Evaluation Board Schematic Page 3 Rev. 0 | Page 29 of 36 AD9515(Opt_Clk Circuit) VCLK R62 4.12K GND S4 GND GND SMBMST 2 3 00 R51 00 R53 GND 23 22 19 OUT1 OUT1B 18 00 R52 10K R54 GND 32 31 33 U1 GND_PAD VCLK S6 GND SMBMST R57 00 AD9515 GND S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 GND VCLK S9 GND AD9626 GND VCLK AD9626 CSB_DUT R24 1K SCLK_DTP VSPIEXT 07099-056 R25 1K VSPI VSPI 5 VCC GND 2 GND VSPI 3 A2 R19 10K Y2 4 5 6 4 VCC Y1 Y2 U5 NC7WZ07 GND U3 NC7WZ16 A1 A2 1 2 R26 10K GND 3 SPI CIRCUITRY GND SDIO_ODM GND R18 10K 1 A1 Y1 6 Figure 57. AD9601 Evaluation Board Schematic Page 4 Table 13. Bill of Materials Qty 1 7 6 1 7 Reference Designator C1, C3, C4, C5, C6, C7, C10 C8, C9, C11, C12, C14, C55 C17 C27, C32, C33, C62, C63, C64, C71 C28, C29, C30, C31, C65, C70 C21, C22, C23, C24, C25, C26, C34, C35, C36, C39 CR4 CR2 F1 E1, E2, E3, E4, E5, E7, E8, E9, E10, E12, E13, E14, E31, E32, E33 J2, J3 L2, L3, L4, L5, L7, L12, L13, L14, L15, R88 P8 R1 R2 Package PCB 603 6032-28 402 402 Description PCB, AD9230 customer evaluation board, Rev. G Capacitor, 1 μF, 0603, X5R, ceramic, 6.3 V, 10% Capacitor, 10 μF, tantalum, 16 V, 10% Capacitor, 2.0 pF, 50 V, ceramic, 0402, SMD Capacitor, 0.33 μF, ceramic, X5R, 10 V, 10% Vendor Moog Panasonic Kemet Murata Murata Part Number AD9230revG ECJ-1VB0J105K T491C106K016AS GRM1555C1H2R0GZ01D GRM155R61A334KE15D 6 10 402 402 Capacitor, 120 pF, ceramic, C0G, 25 V, 5% Capacitor, 0.1 μF, ceramic, X5R, 10 V, 10% Murata Murata VSPIEXT 1 1 1 15 603 Mini 3P 1210 LED green, SMT, 0603, SS-TYPE Diode, 30 V, 20 mA Fuse, 6.0 V, 2.2 A trip current resettable fuse Connector, header, 0.1" 2 10 SMA end launch 1206 Connector, SMA PCB coax end launch, Johnson 142 Ferrite bead, BLM, 3 A, 50 Ω @ 100 MHz 1 1 1 201 603 Power jack, male, 2.1 mm power jack dc Resistor, 100 Ω, 0201, 1/20 W, 1% Resistor, 499 Ω, 0603, 1/10 W, 1% Rev. 0 | Page 30 of 36 R27 1K CSB1_CHA SCLK_CHA SDO_CHA SDI_CHA GRM1555C1H121JA01J GRM155R71C104KA88D Panasonic Agilent Tyco/Raychem Samtec LNJ314G8TRA HSMS2812 NANOSMDC110F-2 TSW-150-08-G-S Johnson Murata 142-0701-851 BLM31PG500SN1L CUI Inc NIC Components NIC Components CP-102A-ND NRC02F1000TRF NRC06F4990TRF AD9626 Qty 2 2 6 4 7 Reference Designator R5, R6 R7, R16 R10, R11, R13, R24, R25, R27 R12, R18, R19, R26, R15, C16, C18, C19, C20, R89, R90 RN1, RN2, RN3, RN4 L1, L8, L9 P9, P10 SW3 T1 T2,T3 U3 U5 U7 U8 U11 U9, U12 U4 P7, P11 Package 402 402 402 402 402 Description Resistor, 36 Ω, 0402, 1/16 W, 1% Resistor, 15 Ω, 0402, 1/16 W, 5% Resistor, 1 kΩ, 0402, 1/16 W, 1% Resistor, 10 kΩ, 0402, 1/16 W, 5% Resistor, 0 Ω, 0402, 1/16 W, 5% Vendor Panasonic Panasonic NIC Components NIC Components NIC Components Part Number ERJ-2GEJ360X ERJ-2RKF15R0X NRC04F1001TRF NRC04J103TRF NRC04ZOTRF 4 3 1 1 1 2 1 1 1 1 1 2 1 2 0402x8 603 805 EVQQ2F03W 2020 CD542 6-SC70 6-SC70 DO-214AA DO-214AB SOT-223 SOT-223 LFCSP56 HM-Zd PCB Resistor array, SMT 0402; 0 Ω, ¼ W, 5%, RESNEXB-2HV Resistor, 0 Ω, 0603, 1/10 W, 5% Resistor, 0 Ω, 0805, 1/8 W, 1% Switch, light touch SMD Ferrite bead, 5 A, 50 V, 190 Ω @ 100 MHz Transformer, 0.5 W, 30 mA IC, buffer, inverter, UHS dual SC70-6 IC, buffer, inverter, UHS dual OD out SC70-6 Diode, 50 V, 2 A Diode, 30 V, 3 A (SMC) Voltage regulator, 3.3 V, 1.5 A Voltage regulator, 1.8 V, 1.5 A AD9230 12-bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V ADC, LFCSP-56 Connector, 2-Pr, 10-column, high speed, HM-Zd, PCB-mounted Capacitor, tantalum, SMT 6032, 10 μF, 16 V, 10% Capacitor, 0.1 μF, ceramic, 10% Panasonic NIC Components NIC Components Panasonic Murata Mini-Circuits Fairchild Fairchild Micro Commercial Micro Commercial Analog Devices Analog Devices Analog Devices Tyco EXB2HV050JV NRC06ZOTRF NRC10ZOTRF P12937SCT-ND DLW5BSN191SQ2L ADT1-1WT+ NC7WZ16P6X NC7WZ07P6X S2A-TPMSTR-ND SK33-TPMSCT-ND ADP3339AKCZ-3.3 ADP3339AKCZ-1.8 AD9230BCPZ-xxx 6469169-1 Do not install the following: 0 C2, C54 TAJD 0 402 C15, C37, C38, C40, C41, C61, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53, C39, C56, C57, C58, C59, C74, C75, C60, C66, C67, C68, C69, C72 0 CR1 Led_ss 0 CR3 Diode 0 805 0 E6, E15, E16, E17, E18, E19, E20 0 J1 10-pin header 0 J4 SMA 0 0 L6 P12, P13, P14, P15 1206 Kemet Murata T491C106K016AS GRM155R71C104KA88D LED green, USS type 0603 Schottky diode Connector, header, 0.1" Panasonic Agilent Tyco/Raychem Samtec LNJ314G8TRA HSMS2812 NANOSMDC110F-2 TSW-150-08-G-S TSW-110-08-G-D Connector, PCB coax SMA end launch, Johnson 142 Inductor, 10 nH SMA Samtec Johnson Murata Amphenol RF TSW-110-08-G-D 142-0701-851 BLM31P500S ARFX1231-ND Rev. 0 | Page 31 of 36 AD9626 Qty 0 Reference Designator R3, R14, R33, R34, R35, R48, R49 R42, R43, R54, R85, R86 R28, R29, R30, R31, R32 R37, R38 R39, R45 R58, R59 R60, R61 R8, R9, R17, R36, R40, R41, R44, R46, R47, R87, R50, R51, R52, R53, R55, R56, R57, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84 P1, P2, P16, P17 SW1 T4 T5, T6 U2 U6 U10 Z1 U1 P6 P6 sm-22 SOIC-8 Crystal SOT-223 16CSP4X4 16CSP8X8 Package 402 Description Resistor, 49.9 Ω Vendor Susumu Part Number RR0510R-49R9-D 0 0 0 0 0 0 0 402 402 402 402 402 402 402 Resistor, 10 kΩ Resistor, 5 kΩ Resistor, 25 Ω Resistor, 5 Ω Resistor, 100 Ω Resistor, 240 Ω Resistor, 0 Ω NIC Components NIC Components NIC Components NIC Components NIC Components NIC Components NIC Components NRC04J103TRF NRC04F4991TRF NRC04F24R9TRF NRC04J5R1TRF NRC04F1000TRF NRC04J241TRF NRC04ZOTRF 0 0 0 0 0 0 0 0 0 0 0 805 EVQQ2F03W Resistor, 0 Ω Switch, light touch SMD Transformer, RF, 0.4 MHz to 800 MHz, SMD case style CD542 Balun PIC12F629 Cvhd_956 crystal Regulator AD8352 AD9515 8-pin power connector post 8-pin power connector top NIC Components Panasonic Mini-Circuits M/A-Com Microchip Tech NRC10ZOTRF P12937SCT-ND ADT1-1WT+ MABA007159-0000 PIC12F629-I/SN CVHD_956 ADP3339AKCZ-5.0 Wieland Wieland Z5.530.0825.0 25.602.2853.0 Rev. 0 | Page 32 of 36 AD9626 OUTLINE DIMENSIONS 8.00 BSC SQ 0.60 MAX 0.60 MAX 43 42 0.30 0.23 0.18 56 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 7.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 4.45 4.30 SQ 4.15 0.50 0.40 0.30 29 28 14 15 0.30 MIN 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 112805-0 6.50 REF SEATING PLANE 0.50 BSC COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 Figure 58. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-2) Dimensions shown in millimeters ORDERING GUIDE Model AD9626BCPZ-1701 AD9626BCPZ-2101 AD9626BCPZ-2501 AD9626-250EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CMOS Evaluation Board with AD9626BCPZ-250 Package Option CP-56-2 CP-56-2 CP-56-2 Z = RoHS Compliant Part. Rev. 0 | Page 33 of 36 AD9626 NOTES Rev. 0 | Page 34 of 36 AD9626 NOTES Rev. 0 | Page 35 of 36 AD9626 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07099-0-11/07(0) Rev. 0 | Page 36 of 36