8-Bit, 125 MSPS, Dual TxDAC+
Digital-to-Analog Converter
AD9709
FEATURES
FUNCTIONAL BLOCK DIAGRAM
8-bit dual transmit digital-to-analog converter (DAC)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single-resistor gain control
Dual port or interleaved data
On-chip 1.2 V reference
Single 5 V or 3.3 V supply operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
DVDD1/ DCOM1/
DVDD2 DCOM2 AVDD
WRT2/IQSEL
DIGITAL
INTERFACE
1
DAC
MODE
IOUTA1
IOUTB1
REFERENCE
REFIO
FSADJ1
FSADJ2
GAINCTRL
BIAS
GENERATOR
SLEEP
AD9709
2
LATCH
PORT2
CLK1
2
DAC
IOUTA2
IOUTB2
CLK2/IQ RESET
00606-001
1
LATCH
PORT1
WRT1/IQWRT
ACOM
Figure 1.
APPLICATIONS
Communications
Base stations
Digital synthesis
Quadrature modulation
3D ultrasound
GENERAL DESCRIPTION
1
The AD9709 is a dual-port, high speed, 2-channel, 8-bit CMOS
DAC. It integrates two high quality 8-bit TxDAC+® cores, a voltage
reference, and digital interface circuitry into a small 48-lead LQFP
package. The AD9709 offers exceptional ac and dc performance
while supporting update rates of up to 125 MSPS.
The AD9709 has been optimized for processing I and Q data in
communications applications. The digital interface consists of two
double-buffered latches as well as control logic. Separate write
inputs allow data to be written to the two DAC ports independent
of one another. Separate clocks control the update rate of the DACs.
A mode control pin allows the AD9709 to interface to two separate
data ports, or to a single interleaved high speed data port. In interleaving mode, the input data stream is demuxed into its original
I and Q data and then latched. The I and Q data is then converted
by the two DACs and updated at half the input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set
independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor. See the Gain
Control Mode section for important date code information on
this feature.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
1
glitch energy and to maximize dynamic accuracy. Each DAC
provides differential current output, thus supporting singleended or differential applications. Both DACs can be
simultaneously updated and provide a nominal full-scale
current of 20 mA. The full-scale currents between each DAC
are matched to within 0.1%.
The AD9709 is manufactured on an advanced low-cost CMOS
process. It operates from a single supply of 3.3 V or 5 V and
consumes 380 mW of power.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
The AD9709 is a member of a pin-compatible family of
dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.
Dual 8-Bit, 125 MSPS DACs. A pair of high performance
DACs optimized for low distortion performance provide
for flexible transmission of I and Q information.
Matching. Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
Low Power. Complete CMOS dual DAC function operates
at 380 mW from a 3.3 V or 5 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
On-Chip Voltage Reference. The AD9709 includes a 1.20 V
temperature-compensated band gap voltage reference.
Dual 8-Bit Inputs. The AD9709 features a flexible dualport interface, allowing dual or interleaved input data.
Patent pending.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.
AD9709
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Outputs .......................................................................... 14
Applications ....................................................................................... 1
Digital Inputs .............................................................................. 15
Functional Block Diagram .............................................................. 1
DAC Timing................................................................................ 15
General Description ......................................................................... 1
Sleep Mode Operation ............................................................... 18
Product Highlights ........................................................................... 1
Power Dissipation....................................................................... 18
Revision History ............................................................................... 2
Applying the AD9709 .................................................................... 19
Specifications..................................................................................... 3
Output Configurations .............................................................. 19
DC Specifications ......................................................................... 3
Differential Coupling Using a Transformer............................ 19
Dynamic Specifications ............................................................... 4
Differential Coupling Using an Op Amp ................................ 19
Digital Specifications ................................................................... 5
Single-Ended, Unbuffered Voltage Output ............................. 20
Absolute Maximum Ratings............................................................ 6
Single-Ended, Buffered Voltage Output Configuration ........ 20
Thermal Resistance ...................................................................... 6
Power and Grounding Considerations .................................... 20
ESD Caution .................................................................................. 6
Applications Information .............................................................. 22
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Quadrature Amplitude Modulation (QAM) Using the
AD9709 ........................................................................................ 22
Terminology .................................................................................... 11
CDMA ......................................................................................... 23
Theory of Operation ...................................................................... 12
Evaluation Board ............................................................................ 24
Functional Description .............................................................. 12
General Description ................................................................... 24
Reference Operation .................................................................. 13
Schematics ................................................................................... 24
Gain Control Mode .................................................................... 13
Evaluation Board Layout ........................................................... 30
Setting the Full-Scale Current................................................... 13
Outline Dimensions ....................................................................... 32
DAC Transfer Function ............................................................. 14
Ordering Guide .......................................................................... 32
REVISION HISTORY
9/09—Rev. A to Rev. B
Changes to Power and Grounding Considerations Section ..... 20
Changes to Schematics Section..................................................... 24
Changes to Evaluation Board Layout Section............................. 30
1/08—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changed Single Supply Operation to 5 V or 3.3 V ........ Universal
Changes to Figure 1 .......................................................................... 1
Added Timing Diagram Section .................................................... 5
Changes to Figure 3 and Table 6 ..................................................... 7
Change to Figure 12 ......................................................................... 9
Changes to Figure 18 to Figure 20 ................................................ 10
Changes to Functional Description Section ............................... 13
Changes to Reference Operation Section .................................... 13
Changes to Figure 23 and Figure 24 ............................................. 13
Changes to Gain Control Mode Section...................................... 13
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section ...................................................... 13
Changes to DAC Transfer Function Section............................... 14
Changes to Interleaved Mode Timing Section ........................... 16
Added Figure 28 ............................................................................. 16
Changes to Power and Grounding Considerations Section ..... 20
Changes to Figure 44...................................................................... 22
Deleted Figure 43............................................................................ 17
Changes to CDMA Section ........................................................... 23
Changes to Figure 45 Caption ...................................................... 23
Changes to Figure 46...................................................................... 24
Changes to Figure 48...................................................................... 26
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 30
5/00—Revision 0: Initial Version
Rev. B | Page 2 of 32
AD9709
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY 1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error Without Internal Reference
Gain Error with Internal Reference
Gain Match
TA = 25°C
TMIN to TMAX
TMIN to TMAX
Full-Scale Output Current 2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current 3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small-Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift Without Internal Reference
Gain Drift with Internal Reference
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD1, DVDD2
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD) 4
Digital Supply Current (IDVDD) 5
Supply Current Sleep Mode (IAVDD)
Power Dissipation4 (5 V, IOUTFS = 20 mA)
Power Dissipation5 (5 V, IOUTFS = 20 mA)
Power Dissipation 6 (5 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio 7 —AVDD
Power Supply Rejection Ratio7—DVDD1, DVDD2
OPERATING RANGE
Min
8
Typ
Max
Unit
Bits
−0.5
−0.5
±0.1
±0.1
+0.5
+0.5
LSB
LSB
−0.02
−2
−5
±0.25
+1
+0.02
+2
+5
% of FSR
% of FSR
% of FSR
+0.3
+1.6
+0.14
20.0
+1.25
% of FSR
% of FSR
dB
mA
V
kΩ
pF
1.26
V
nA
1.25
1
0.5
V
MΩ
MHz
0
±50
±100
±50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
−0.3
−1.6
−0.14
2.0
−1.0
±0.1
100
5
1.14
1.20
100
0.1
3
2.7
5
5
71
5
8
380
420
450
−0.4
−0.025
−40
1
5.5
5.5
75
7
15
12
410
450
+0.4
+0.025
+85
Measured at IOUTA, driving a virtual ground.
Nominal full-scale current, IOUTFS, is 32 times the IREF current.
An external buffer amplifier with input bias current 100 kΩ).
All of these current sources are switched to one of the two
output nodes (that is, IOUTA or IOUTB) via the PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching of complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9709 have separate
power supply inputs (that is, AVDD and DVDD1/DVDD2) that
can operate independently over a 3.3 V to 5 V range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.
Rev. B | Page 12 of 32
AD9709
The full-scale output current of each DAC is regulated by
separate reference control amplifiers and can be set from 2 mA
to 20 mA via an external network connected to the full-scale
adjust (FSADJ) pin. The external network in combination with
both the reference control amplifier and voltage reference
(VREFIO) sets the reference current (IREF), which is replicated to
the segmented current sources with the proper scaling factor.
The full-scale current (IOUTFS) is 32 × IREF.
GAIN CONTROL MODE
The AD9709 allows the gain of each channel to be set
independently by connecting one RSET resistor to FSADJ1 and
another RSET resistor to FSADJ2. To add flexibility and reduce
system cost, a single RSET resistor can be used to set the gain of
both channels simultaneously.
REFERENCE OPERATION
The AD9709 contains an internal 1.20 V band gap reference.
This can easily be overridden by a low noise external reference
with no effect on performance. REFIO serves as either an input
or output depending on whether the internal or an external
reference is used. To use the internal reference, simply decouple
the REFIO pin to ACOM with a 0.1 μF capacitor. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used elsewhere in the circuit, an external buffer
amplifier with an input bias current of less than 100 nA should
be used. An example of the use of the internal reference is
shown in Figure 23.
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
GAINCTRL
REFERENCE
SECTION
REFIO
ADDITIONAL
EXTERNAL
LOAD
CURRENT
SOURCE
ARRAY
0.1µF
256Ω
RSET
FSADJ1/
FSADJ2
I REF =
22nF
Figure 23. Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 24. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 μF
compensation capacitor is not required because the internal
reference is overridden and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
GAINCTRL
1.2V
REF
REFIO
EXTERNAL
REFERENCE
256Ω
IREF
RSET
FSADJ1/
FSADJ2
AVDD
AD9709
REFERENCE
SECTION
CURRENT
SOURCE
ARRAY
22nF
Figure 24. External Reference Configuration
ACOM
00606-024
AVDD
SETTING THE FULL-SCALE CURRENT
ACOM
00606-023
IREF
Note that only parts with a date code of 9930 or later have the
master/slave gain control function. For parts with a date code
before 9930, Pin 42 must be connected to AGND, and the part
operates in the two-resistor, independent gain control mode.
Both of the DACs in the AD9709 contain a control amplifier
that is used to regulate the full-scale output current (IOUTFS). The
control amplifier is configured as a V-I converter, as shown in
Figure 23, so that its current output (IREF) is determined by the ratio
of the VREFIO and an external resistor, RSET.
AVDD
AD9709
1.2V
REF
When GAINCTRL is low (that is, connected to analog ground),
the independent channel gain control mode using two resistors
is enabled. In this mode, individual RSET resistors should be
connected to FSADJ1 and FSADJ2. When GAINCTRL is high
(that is, connected to AVDD), the master/slave channel gain
control mode using one network is enabled. In this mode, a
single network is connected to FSADJ1, and the FSADJ2 pin
must be left unconnected.
VREFIO
RSET
The DAC full-scale current, IOUTFS, is an output current 32 times
larger than the reference current, IREF.
I OUTFS = 32 × I REF
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS from 2 mA to 20 mA by setting IREF between 62.5 μA and
625 μA. The wide adjustment range of IOUTFS provides several
benefits. The first relates directly to the power dissipation of
the AD9709, which is proportional to IOUTFS (refer to the Power
Dissipation section). The second relates to the 20 dB adjustment,
which is useful for system gain control purposes.
It should be noted that when the RSET resistors are 2 kΩ or less,
the 22 nF capacitor and 256 Ω resistor shown in Figure 23 and
Figure 24 are not required and the reference current can be set
by the RSET resistors alone. For RSET values greater than 2 kΩ, the
22 nF capacitor and 256 Ω resistor networks are required to
ensure the stability of the reference control amplifier(s).
Regardless of the value of RSET, however, if the RSET resistor is
located more than ~10 cm away from the pin, use of the 22 nF
capacitor and 256 Ω resistor is recommended.
Rev. B | Page 13 of 32
AD9709
DAC TRANSFER FUNCTION
Both DACs in the AD9709 provide complementary current outputs, IOUTA and IOUTB. IOUTA provides a near full-scale current
output, IOUTFS, when all bits are high (that is, DAC CODE = 256)
while IOUTB, the complementary output, provides no current.
The current output appearing at IOUTA and IOUTB is a function of
both the input code and IOUTFS and can be expressed as
IOUTA = (DAC CODE/256) × IOUTFS
(1)
IOUTB = (255 − DAC CODE)/256 × IOUTFS
(2)
where DAC CODE = 0 to 255 (that is, decimal representation).
IOUTFS is a function of the reference current (IREF), which is
nominally set by a reference voltage (VREFIO) and an external
resistor (RSET). It can be expressed as
IOUTFS = 32 × IREF
(3)
where
IREF = VREFIO/RSET
(4)
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTA and IOUTB
should be connected directly to matching resistive loads, RLOAD,
that are tied to the analog common, ACOM. Note that RLOAD
can represent the equivalent load resistance seen by IOUTA or
IOUTB, as would be the case in a doubly terminated 50 Ω or 75 Ω
cable. The single-ended voltage output appearing at the IOUTA
and IOUTB nodes is
VOUTA = IOUTA × RLOAD
(5)
VOUTB = IOUTB × RLOAD
(6)
Note the full-scale value of VOUTA and VOUTB must not exceed the
specified output compliance range to maintain the specified
distortion and linearity performance.
VDIFF = (IOUTA − IOUTB) × RLOAD
(7)
differential amplifier configuration. The ac performance of the
AD9709 is optimum and specified using a differential
transformer-coupled output in which the voltage swing at IOUTA
and IOUTB is limited to ±0.5 V. If a single-ended unipolar output
is desirable, IOUTA should be selected.
The distortion and noise performance of the AD9709 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can be
significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed
waveform increases. This is due to the first-order cancellation of
various dynamic common-mode distortion mechanisms, digital
feedthrough, and noise.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (that is, assuming no
source termination). Because the output currents of IOUTA and
IOUTB are complementary, they become additive when processed
differentially. A properly selected transformer allows the AD9709
to provide the required power and voltage levels to different loads.
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (that is, VOUTA and VOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a virtual
ground via an I-V op amp configuration results in the optimum
dc linearity. Note that the INL/DNL specifications for the
AD9709 are measured with IOUTA maintained at a virtual ground
via an op amp.
Equation 7 highlights some of the advantages of operating the
AD9709 differentially. First, the differential operation helps cancel
common-mode error sources associated with IOUTA and IOUTB,
such as noise, distortion, and dc offsets. Second, the differential
code-dependent current and subsequent voltage, VDIFF, is twice
the value of the single-ended voltage output (that is, VOUTA or
VOUTB), thus providing twice the signal power to the load.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a
breakdown of the output stage and affect the reliability of the
AD9709.
Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the
AD9709 can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relationship.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. When IOUTFS is decreased
from 20 mA to 2 mA, the positive output compliance range
degrades slightly from its nominal 1.25 V to 1.00 V. The optimum
distortion performance for a single-ended or differential output
is achieved when the maximum full-scale signal at IOUTA and IOUTB
does not exceed 0.5 V. Applications requiring the AD9709 output
(that is, VOUTA and/or VOUTB) to extend its output compliance range
should size RLOAD accordingly. Operation beyond this compliance
range adversely affects the linearity performance of the AD9709
and subsequently degrade its distortion performance.
ANALOG OUTPUTS
The complementary current outputs, IOUTA and IOUTB, in each
DAC can be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load
resistor, RLOAD, as described in Equation 5 through Equation 7.
The differential voltage, VDIFF, existing between VOUTA and VOUTB
can be converted to a single-ended voltage via a transformer or
Rev. B | Page 14 of 32
AD9709
The digital interface is implemented using an edge-triggered
master slave latch. The DAC outputs are updated following
either the rising edge or every other rising edge of the clock,
depending on whether dual or interleaved mode is used. The
DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
Timing specifications for dual port mode are given in Figure 26
and Figure 27.
tS
DATA IN
WRT1/WRT2
tCPW
IOUTA
OR
IOUTB
tPD
Figure 26. Dual Port Mode Timing
DATA IN
D1
D2
D3
D4
D5
WRT1/WRT2
CLK1/CLK2
IOUTA
OR
IOUTB
XX
D1
D2
D3
D4
Figure 27. Dual Mode Timing
Interleaved Mode Timing
The AD9709 can operate in two timing modes, dual and
interleaved, which are described in the following sections. The
block diagram in Figure 25 represents the latch architecture in
the interleaved timing mode.
PORT 1
INPUT
LATCH
When the MODE pin is at Logic 0, the AD9709 operates in
interleaved mode (refer to Figure 25). In addition, WRT1
functions as IQWRT, CLK1 functions as IQCLK, WRT2
functions as IQSEL, and CLK2 functions as IQRESET.
DAC1
LATCH
DAC1
IQCLK
IQRESET
÷2
DEINTERLEAVED
DATA OUT
DAC2
LATCH
00606-027
PORT 2
INPUT
LATCH
IQWRT
IQSEL
tLPW
CLK1/CLK2
DAC TIMING
INTERLEAVED
DATA IN, PORT 1
tH
00606-025
The digital inputs of the AD9709 consist of two independent
channels. For the dual port mode, each DAC has its own
dedicated 8-bit data port: WRT line and CLK line. In the
interleaved timing mode, the function of the digital control pins
changes as described in the Interleaved Mode Timing section.
The 8-bit parallel data inputs follow straight binary coding
where DB7P1 and DB7P2 are the most significant bits (MSBs)
and DB0P1 and DB0P2 are the least significant bits (LSBs).
IOUTA produces a full-scale output current when all data bits are
at Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
The rising edge of CLK should occur before or simultaneously
with the rising edge of WRT. If the rising edge of CLK occurs
after the rising edge of WRT, a minimum delay of 2 ns should
be maintained from rising edge of WRT to rising edge of CLK.
00606-026
DIGITAL INPUTS
DAC2
Figure 25. Latch Structure in Interleaved Mode
Dual Port Mode Timing
When the MODE pin is at Logic 1, the AD9709 operates in dual
port mode (refer to Figure 21). The AD9709 functions as two
distinct DACs. Each DAC has its own completely independent
digital input and control lines.
The AD9709 features a double-buffered data path. Data enters the
device through the channel input latches. This data is then transferred to the DAC latch in each signal path. After the data is loaded
into the DAC latch, the analog output settles to its new value.
Data enters the device on the rising edge of IQWRT. The
logic level of IQSEL steers the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). For proper
operation, IQSEL should only change state when IQWRT and
IQCLK are low.
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the next rising edge on IQCLK updates both DAC
latches with the data present at their inputs. In the interleaved
mode, IQCLK is divided by 2 internally. Following this first
rising edge, the DAC latches are only updated on every other
rising edge of IQCLK. In this way, IQRESET can be used to
synchronize the routing of the data to the DACs.
Similar to the order of CLK and WRT in dual port mode,
IQCLK should occur before or simultaneously with IQWRT.
For general consideration, the WRT lines control the channel
input latches, and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
Rev. B | Page 15 of 32
AD9709
Timing specifications for interleaved mode are shown in Figure 28
and Figure 30.
INTERLEAVED
DATA
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDDx) or
IQSEL
xx
D1
D2
D3
D4
D5
IQWRT
VTHRESHOLD = DVDDx/2 (±20%)
IQCLK
tS
tH
IQRESET
DATA IN
xx
D3
D1
xx
DAC OUTPUT
PORT 2
D4
D2
IQSEL
00606-029
DAC OUTPUT
PORT 1
500 ps
Figure 30. Interleaved Mode Timing
IQWRT
tH*
tLPW
IQCLK
500 ps
IOUTA
OR
IOUTB
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
00606-056
tPD
The internal digital circuitry of the AD9709 is capable of operating
at a digital supply of 3.3 V or 5 V. As a result, the digital inputs
can also accommodate TTL levels when DVDD1/DVDD2 is set to
accommodate the maximum high level voltage (VOH(MAX)) of the
TTL drivers. A DVDD1/DVDD2 of 3.3 V typically ensures proper
compatibility with most TTL logic families. Figure 31 shows the
equivalent digital input circuit for the data and clock inputs.
The sleep mode input is similar with the exception that it
contains an active pull-down circuit, thus ensuring that the
AD9709 remains enabled if this input is left disconnected.
DVDD1
Figure 28. 5 V or 3.3 V Interleaved Mode Timing
At 5 V it is permissible to drive IQWRT and IQCLK together as
shown in Figure 29, but at 3.3 V the interleaved data transfer is
not reliable.
00606-030
tS
DIGITAL
INPUT
tH
Figure 31. Equivalent Digital Input
DATA IN
Because the AD9709 is capable of being clocked up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9709
with reduced logic swings and a corresponding digital supply
(DVDD1/DVDD2) results in the lowest data feedthrough and
on-chip digital noise. The drivers of the digital data interface
circuitry should be specified to meet the minimum setup and
hold times of the AD9709 as well as its required minimum and
maximum input logic level thresholds.
IQSEL
IQWRT
tH*
tLPW
IQCLK
tPD
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
00606-028
IOUTA
OR
IOUTB
Figure 29. 5 V Only Interleaved Mode Timing
Rev. B | Page 16 of 32
AD9709
Note that the clock input can also be driven via a sine wave, which
is centered around the digital threshold (that is, DVDDx/2) and
meets the minimum and maximum logic threshold. This typically
results in a slight degradation in the phase noise, which becomes
more noticeable at higher sampling rates and output frequencies.
In addition, at higher sampling rates, the 20% tolerance of the
digital logic threshold should be considered because it affects
the effective clock duty cycle and, subsequently, cut into the
required data setup and hold times.
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9709 is rising-edge triggered and
therefore exhibits SNR sensitivity when the data transition is
close to this edge. In general, the goal when applying the AD9709 is
to make the data transition close to the falling clock edge. This
becomes more important as the sample rate increases. Figure 32
shows the relationship of SNR to clock/data placement.
60
50
40
30
20
10
0
–4
–3
–2
–1
0
1
2
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE (ns)
3
4
00606-031
The external clock driver circuitry provides the AD9709 with a
low-jitter clock input meeting the minimum and maximum logic
levels while providing fast edges. Fast clock edges help minimize
jitter manifesting itself as phase noise on a reconstructed waveform.
Therefore, the clock input should be driven by the fastest logic
family suitable for the application.
Input Clock and Data Timing Relationship
SNR (dBc)
Digital signal paths should be kept short, and run lengths should be
matched to avoid propagation delay mismatch. The insertion of
a low value (that is, 20 Ω to 100 Ω) resistor network between
the AD9709 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to digital feedthrough. For longer board traces and
high data update rates, stripline techniques with proper
impedance and termination resistors should be considered to
maintain “clean” digital inputs.
Figure 32. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS
Rev. B | Page 17 of 32
AD9709
80
SLEEP MODE OPERATION
70
60
IAVDD (mA)
The AD9709 has a power-down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 3.3 V to 5 V and
temperature range. This mode can be activated by applying a
Logic Level 1 to the SLEEP pin. The SLEEP pin logic threshold
is equal to 0.5 × AVDD. This digital input also contains an active
pull-down circuit that ensures the AD9709 remains enabled if
this input is left disconnected. The AD9709 requires less than
50 ns to power down and approximately 5 μs to power back up.
50
40
30
20
5
10
15
20
25
0.4
0.5
00606-033
•
•
•
•
0
0.5
00606-034
10
The power dissipation, PD, of the AD9709 is dependent on several
factors, including
00606-032
POWER DISSIPATION
IOUTFS (mA)
Figure 33. IAVDD vs. IOUTFS
the power supply voltages (AVDD and DVDD1/DVDD2)
the full-scale current output (IOUTFS)
the update rate (fCLK)
the reconstructed digital input waveform
35
30
125MSPS
25
100MSPS
IDVDD (mA)
The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD. IAVDD
is directly proportional to IOUTFS, as shown in Figure 33, and is
insensitive to fCLK.
Conversely, IDVDD is dependent on the digital input waveform,
fCLK, and digital supply (DVDD1/DVDD2). Figure 34 and
Figure 35 show IDVDD as a function of full-scale sine wave output
ratios (fOUT/fCLK) for various update rates with DVDD1 =
DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively.
Note how IDVDD is reduced by more than a factor of 2 when
DVDD1/DVDD2 is reduced from 5 V to 3.3 V.
20
65MSPS
15
10
25MSPS
5
5MSPS
0
0
0.1
0.2
0.3
RATIO (fOUT/fCLK)
Figure 34. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 5 V
18
125MSPS
16
14
100MSPS
IDVDD (mA)
12
10
65MSPS
8
6
25MSPS
4
5MSPS
2
0
0
0.1
0.2
0.3
0.4
RATIO (fOUT/fCLK)
Figure 35. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 3.3 V
Rev. B | Page 18 of 32
AD9709
APPLYING THE AD9709
The following sections illustrate some typical output configurations for the AD9709. Unless otherwise noted, it is assumed that
IOUTFS is set to a nominal 20 mA. For applications requiring the
optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
can consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the
optimum high frequency performance and is recommended for
any application allowing for ac coupling. The differential op
amp configuration is suitable for applications requiring dc
coupling, bipolar output, signal gain, and/or level shifting,
within the bandwidth of the chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage results
if IOUTA and/or IOUTB is connected to an appropriately sized load
resistor, RLOAD, referred to ACOM. This configuration may be
more suitable for a single-supply system requiring a dc-coupled,
ground-referred output voltage. Alternatively, an amplifier can be
configured as an I-V converter, thus converting IOUTA or IOUTB into a
negative unipolar voltage. This configuration provides the best dc
linearity because IOUTA or IOUTB is maintained at a virtual ground.
Note that IOUTA provides slightly better performance than IOUTB.
DIFFERENTIAL COUPLING USING A
TRANSFORMER
An op amp can also be used as shown in Figure 37 to perform a
differential-to-single-ended conversion. The AD9709 is configured
with two equal load resistors, RLOAD, of 25 Ω each. The differential
voltage developed across IOUTA and IOUTB is converted to a singleended signal via the differential op amp configuration. An optional
capacitor can be installed across IOUTA and IOUTB, forming a real pole
in a low-pass filter. The addition of this capacitor also enhances the
op amp’s distortion performance by preventing the DAC’s highslewing output from overloading the op amp’s input.
500Ω
AD9709
225Ω
IOUTA
AD8047
225Ω
IOUTB
COPT
500Ω
25Ω
25Ω
Mini-Circuits
T1-1T
RLOAD
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential
op amp circuit using the AD8047 is configured to provide some
additional signal gain. The op amp must operate from a dual
supply because its output is approximately ±1.0 V. A high speed
amplifier capable of preserving the differential performance of
the AD9709 while meeting other system level objectives (that is,
cost and power) should be selected. The op amp’s differential
gain, gain setting resistor values, and full-scale output swing
capabilities should be considered when optimizing this circuit.
The differential circuit shown in Figure 38 provides the
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9709 and the op amp, is used to level shift the differential
output of the AD9709 to midsupply (that is, AVDD/2). The
AD8041 is a suitable op amp for this application.
500Ω
OPTIONAL
RDIFF
AD9709
00606-035
IOUTB
225Ω
IOUTA
Figure 36. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically
around ACOM and should be maintained with the specified
output compliance range of the AD9709. A differential resistor,
Rev. B | Page 19 of 32
225Ω
IOUTB
AD8041
COPT
1kΩ
AVDD
25Ω
25Ω
500Ω
Figure 38. Single-Supply DC Differential Coupled Circuit
00606-037
IOUTA
DIFFERENTIAL COUPLING USING AN OP AMP
Figure 37. DC Differential Coupling Using an Op Amp
An RF transformer can be used as shown in Figure 36 to perform
a differential-to-single-ended signal conversion. A differentially
coupled transformer output provides the optimum distortion
performance for output signals whose spectral content lies within
the pass band of the transformer. An RF transformer such as the
Mini-Circuits® T1-1T provides excellent rejection of commonmode distortion (that is, even-order harmonics) and noise over
a wide frequency range. It also provides electrical isolation and
the ability to deliver twice the power to the load. Transformers
with different impedance ratios can also be used for impedance
matching purposes. Note that the transformer provides ac
coupling only.
AD9709
RDIFF, can be inserted in applications where the output of the
transformer is connected to the load, RLOAD, via a passive
reconstruction filter or cable. RDIFF is determined by the
transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately
half the signal power will be dissipated across RDIFF.
00606-036
OUTPUT CONFIGURATIONS
AD9709
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
POWER AND GROUNDING CONSIDERATIONS
Figure 39 shows the AD9709 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated
50 Ω cable, because the nominal full-scale current, IOUTFS, of 20 mA
flows through the equivalent RLOAD of 25 Ω. In this case, RLOAD
represents the equivalent load resistance seen by IOUTA or IOUTB.
The unused output (IOUTA or IOUTB) can be connected directly to
ACOM or via a matching RLOAD. Different values of IOUTFS and
RLOAD can be selected as long as the positive compliance range is
adhered to. One additional consideration in this mode is the
INL (see the Analog Outputs section). For optimum INL
performance, the single-ended, buffered voltage output
configuration is suggested.
Power Supply Rejection
VOUTA = 0V TO 0.5V
50Ω
50Ω
00606-038
IOUTB
25Ω
Figure 39. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 40 shows a buffered single-ended output configuration
in which the U1 op amp performs an I-V conversion on the
AD9709 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, thus minimizing the nonlinear output
impedance effect on the INL performance of the DAC, as
discussed in the Analog Outputs section. Although this singleended configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC
update rates may be limited by the slewing capabilities of U1.
U1 provides a negative unipolar output voltage, and its fullscale output voltage is simply the product of RFB and IOUTFS. The
full-scale output should be set within U1’s voltage output swing
capabilities by scaling IOUTFS and/or RFB. An improvement in ac
distortion performance may result with a reduced IOUTFS because
the signal current U1 has to sink will be subsequently reduced.
90
85
75
70
0.2
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Figure 41. AVDD Power Supply Rejection Ratio vs. Frequency
RFB
200Ω
IOUTFS = 10mA
IOUTA
U1
200Ω
Figure 40. Unipolar Buffered Voltage Output
00606-039
VOUT = IOUTFS × RFB
IOUTB
0.3
FREQUENCY (MHz)
COPT
AD9709
80
00606-040
IOUTFS = 20mA
IOUTA
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum from tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9709 AVDD supply over this frequency range is shown in
Figure 41.
PSRR (dB)
AD9709
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figure 52 and Figure 53 illustrate the recommended
circuit board layout, including ground, power, and signal
input/output.
Note that the data in Figure 41 is given in terms of current out
vs. voltage in. Noise on the analog power supply has the effect
of modulating the internal current sources and therefore the
output current. The voltage noise on AVDD, therefore, is added
in a nonlinear manner to the desired IOUT. PSRR is very code
dependent, thus producing mixing effects that can modulate
low frequency power supply noise to higher frequencies. Worstcase PSRR for either one of the differential DAC outputs occurs
when the full-scale current is directed toward that output. As a
result, the PSRR measurement in Figure 41 represents a worstcase condition in which the digital inputs remain static and the
full-scale output current of 20 mA is directed to the DAC
output being measured.
Rev. B | Page 20 of 32
AD9709
(AVDD) to the analog common (ACOM) as close to the chip as
physically possible. Similarly, decouple DVDD1/DVDD2, the
digital supply (DVDD1/DVDD2) to the digital common
(DCOM1/DCOM2) as close to the chip as possible.
For applications that require a single 5 V or 3.3 V supply for
both the analog and digital supplies, a clean analog supply can
be generated using the circuit shown in Figure 42. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low-ESR
type electrolytic and tantalum capacitors.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
Proper grounding and decoupling should be a primary
objective in any high speed, high resolution system. The
AD9709 features separate analog and digital supply and ground
pins to optimize the management of analog and digital ground
currents in a system. In general, decouple the analog supply
Rev. B | Page 21 of 32
ELECTROLYTIC
CERAMIC
AVDD
100µF
10µF
TO
22µF
0.1µF
ACOM
TANTALUM
5V
POWER SUPPLY
Figure 42. Differential LC Filter for Single 5 V and 3.3 V Applications
00606-041
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s
sake, all of this noise is concentrated at 250 kHz (that is, ignore
harmonics). To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC full-scale
current, IOUTFS, one must determine the PSRR in decibels using
Figure 41 at 250 kHz. To calculate the PSRR for a given RLOAD,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 41 by the scaling factor 20 × log(RLOAD).
For instance, if RLOAD is 50 Ω, the PSRR is reduced by 34 dB
(that is, the PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 41, becomes 51 dB VOUT/VIN).
AD9709
APPLICATIONS INFORMATION
QUADRATURE AMPLITUDE MODULATION (QAM)
USING THE AD9709
8
DAC
DSP
OR
ASIC
QAM is one of the most widely used digital modulation
schemes in digital communications systems. This modulation
technique can be found in FDM as well as spread spectrum
(that is, CDMA) based systems. A QAM signal is a carrier
frequency that is modulated in both amplitude (that is, AM
modulation) and phase (that is, PM modulation). It can be
generated by independently modulating two carriers of identical
frequency but with a 90° phase difference. This results in an
in-phase (I) carrier component and a quadrature (Q) carrier
component at a 90° phase shift with respect to the I component.
The I and Q components are then summed to provide a QAM
signal at the specified carrier frequency.
0°
CARRIER
FREQUENCY
90°
Σ
TO
MIXER
8
NYQUIST
FILTERS
00606-044
DAC
QUADRATURE
MODULATOR
Figure 43. Typical Analog QAM Architecture
In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 44 helps improve
the matching between the I and Q channels, and it shows a path
for upconversion using the AD8346 quadrature modulator. The
AD9709 provides both I and Q DACs with a common reference
that will improve the gain matching and stability. RCAL can be
used to compensate for any mismatch in gain between the two
channels. The mismatch may be attributed to the mismatch
between RSET1 and RSET2, the effective load resistance of each
channel, and/or the voltage offset of the control amplifier in each
DAC. The differential voltage outputs of both DACs in the
AD9709 are fed into the respective differential inputs of the
AD8346 via matching networks.
A common and traditional implementation of a QAM
modulator is shown in Figure 43. The modulation is performed
in the analog domain in which two DACs are used to generate
the baseband I and Q components. Each component is then
typically applied to a Nyquist filter before being applied to a
quadrature mixer. The matching Nyquist filters shape and limit
each component’s spectral envelope while minimizing intersymbol
interference. The DAC is typically updated at the QAM symbol
rate, or at a multiple of the QAM symbol rate if an interpolating
filter precedes the DAC. The use of an interpolating filter typically
eases the implementation and complexity of the analog filter,
which can be a significant contributor to mismatches in gain
and phase between the two baseband channels. A quadrature
mixer modulates the I and Q components with the in-phase and
quadrature carrier frequencies and then sums the two outputs
to provide the QAM signal.
AVDD
ROHDE & SCHWARZ
FSEA30B
OR EQUIVALENT
SPECTRUM ANALYZER
0.1µF
ACOM AVDD
PORT Q
CLK1/IQCLK
RL
LA
IOUTA
I DAC
LATCH
I
DAC
RL
CB
CA
RA
RB
RA
BBIP
VOUT
RB
RL LA
IOUTA
RL LA RL
RL
AD9709
Q DAC
LATCH
Q
DAC
CA
WRT2/IQSEL
CB
RL
LA
RA
RB
256Ω
22nF
FSADJ1
256Ω
2kΩ
20kΩ
22nF
FSADJ2
2kΩ
20kΩ
NOTES
1. DAC FULL-SCALE OUTPUT CURRENT = IOUTFS.
2. RA, RB, AND RL ARE THIN FILM RESISTOR NETWORKS
WITH 0.1% MATCHING, 1% ACCURACY AVAILABLE
FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT.
LOIP
RA
BBQP
RB
PHASE
SPLITTER
LOIN
CFILTER
BBQN
RL
VDIFF = 1.82V p-p
MODE
+
BBIN
IOUTB
IOUTB
SLEEP
VPBF
DIFFERENTIAL
RLC FILTER
RL = 200Ω
0.1µF
RA = 2500Ω
RB = 500Ω
RP = 200Ω
CA = 280pF
CB = 45pF
LA = 10µH
IOUTFS = 11mA
AVDD = 5.0V
VCM = 1.2V
AD8346
REFIO
ROHDE & SCHWARZ
SIGNAL GENERATOR
AVDD
AD976x
RL
RB
0 TO IOUTFS
Figure 44. Baseband QAM Implementation Using an AD9709 and AD8346
Rev. B | Page 22 of 32
VDAC
RA
AD8346
VMOD
00606-045
WRT1/IQWRT
DIGITAL INTERFACE
TEKTRONIX
AWG2021
WITH
OPTION 4
PORT I
DCOM1/ DVDD1/
DCOM2 DVDD2
AD9709
Code division multiple access (CDMA) is an air transmit/receive
scheme where the signal in the transmit path is modulated with a
pseudorandom digital code (sometimes referred to as the spreading
code). The effect of this is to spread the transmitted signal across
a wide spectrum. Similar to a discrete multitone (DMT) waveform, a CDMA waveform containing multiple subscribers can
be characterized as having a high peak to average ratio (that is,
crest factor), thus demanding highly linear components in the
transmit signal path. The bandwidth of the spectrum is defined
by the CDMA standard being used, and in operation it is
implemented by using a spreading code with particular
characteristics.
Figure 45 displays the results of using the application circuit shown
in Figure 44 to reconstruct a wideband CDMA (W-CDMA) test
vector using a bandwidth of 8 MHz that is centered at 2.4 GHz
and sampled at 65 MHz. The IF frequency at the DAC output is
15.625 MHz. The adjacent channel power ratio (ACPR) for the
given test vector is measured at greater than 54 dB.
–30
–40
–50
–60
==
–70
–80
–90
–100
–110
c11
c11
cu1
–120
cu1
C0
C0
–130
CENTER 2.4GHz
3MHz
FREQUENCY
SPAN 30MHz
Figure 45. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS,
Recreated at 2.4 GHz, Adjacent Channel Power > 54 dB
Rev. B | Page 23 of 32
00606-046
CDMA
Distortion in the transmit path can lead to power being transmitted
out of the defined band. The ratio of power transmitted in-band to
out-of-band is often referred to as adjacent channel power (ACP).
This is a regulatory issue due to the possibility of interference
with other signals being transmitted by air. Regulatory bodies
define a spectral mask outside of the transmit band, and the ACP
must fall under this mask. If distortion in the transmit path causes
the ACP to be above the spectral mask, filtering or different
component selection is needed to meet the mask requirements.
(dB)
I and Q digital data can be fed into the AD9709 in two ways. In
dual port mode, the digital I information drives one input port,
and the digital Q information drives the other input port. If no
interpolation filter precedes the DAC, the symbol rate is the rate
at which the system clock drives the CLK and WRT pins on the
AD9709. In interleaved mode, the digital input stream at Port 1
contains the I and the Q information in alternating digital words.
Using IQSEL and IQRESET, the AD9709 can be synchronized
to the I and Q data streams. The internal timing of the AD9709
routes the selected I and Q data to the correct DAC output. In
interleaved mode, if no interpolation filter precedes the AD9709,
the symbol rate is half that of the system clock driving the digital
data stream and the IQWRT and IQCLK pins on the AD9709.
AD9709
EVALUATION BOARD
This board allows the user flexibility to operate the AD9709 in
various configurations. Possible output configurations include
transformer coupled, resistor terminated, and single-ended and
differential outputs. The digital inputs can be used in dual port
or interleaved mode and are designed to be driven from various
word generators, with the on-board option to add a resistor
network for proper load termination. When operating the
AD9709, best performance is obtained when running the digital
supply (DVDD1/DVDD2) at 3.3 V and the analog supply
(AVDD) at 5 V.
GENERAL DESCRIPTION
The AD9709-EB is an evaluation board for the AD9709 8-bit
dual DAC. Careful attention to layout and circuit design,
combined with a prototyping area, allow the user to easily and
effectively evaluate the AD9709 in any application where high
resolution, high speed conversion is required.
SCHEMATICS
RED
RED
L2
L1
TB1 1
DVDD
AVDDIN
BEAD
TB1 3
AVDD
BEAD
C9
DCASE
C10
VAL
VOLT
VAL
VOLT
DCASE
BLK
BLK
BLK
BLK
TB1 2
BLK
BLK
TB1 4
BLK
BLK
DGND
1
2 22
R1
INP32
3
R2
R3
INP33
4
INP34
5
R4
INP35
6
R5
INP36
7
R6
8
R7
9
R8
10
R9
INCK2
1
RCO M
INP31
R1
3
R2
R3
INP25
4
INP26
5
R4
6
R5
7
R6
8
R7
9
R8
10
R9
INP24
INP27
INP28
INP29
1
RCO M
2 22
INP23
INP30
RP15
AGND
INP9
INP10
INP11
INP12
INP13
INP14
INCK1
RP10
1
RCO M
2 22
R1
3
R2
4
R3
5
R4
6
R5
7
R6
8
R7
9
R8
10
R9
R1
3
R2
4
R3
INP4
5
R4
6
R5
INP5
7
R6
8
R7
9
R8
10
R9
INP2
INP3
INP6
INP7
INP8
RP9
Figure 46. Power Decoupling and Clocks on AD9709 Evaluation Board (1)
Rev. B | Page 24 of 32
RCO M
2 22
INP1
RP16
00606-146
DVDDIN
Rev. B | Page 25 of 32
Figure 47. Power Decoupling and Clocks on AD9709 Evaluation Board (2)
DGND;3,4,5
SMA200UP
DGND;3,4,5
SMA200UP
DGND;3,4,5
SMA200UP
DGND;3,4,5
SLEEP
WRT2IN S4
IQSEL
CLK2IN S3
RESET
CLK1IN S2
1QCLK
WRT1IN S1
IQWRT
SMA200UP
WHT
JP13
WHT
WHT
WHT
WHT
R6 3
R17
1K
50
3
4
JP14
RC0603
2
5
T3
1
6
T1-1TCUP
RC0603
RC0805
DVDD
R1
50
C18
C19
R1 8
.1
R13
50
R2
50
.1
RC0603
1K
1K
RC0603
R19
1K
CC0805
RC0603
CC0805
RC0805
R3
50
2
1
-IN
SO16
OUT
15
JP3
JP4
JP17
DS90LV048B
R4
50
U2
+IN
DCLKIN1
JP5
JP16
JP9
4
3
6
5
8
7
9
11
14
SO16
U2
GND
VCC
.1UF
C33
DS90LV048B
EN
EN
DVDD
DS90LV048B
SO16
OUT
DS90LV048B
SO16
OUT
R30
VAL
16
-IN
U2
+IN
-IN
10
SO16
OUT
DS90LV048B
U2
U2
+IN
-IN
+IN
CC0805
DVDD
DCLKIN2
12
13
DVDD
.01UF
C34
CC0805
4
DVDD
SW2
K
CLK
J
U6
PRE
WRT1
SLEEP
WRT2
CLK2
CLK1
Q
5
DVDD
6
Q_
CLR
15
SN74F112
DGND;8
DVDD;16
2
1
3
SW1
/2 CLOCK DIVIDER
DVDD
JP1
JP2
1
A
R16
B
1
RC0805
C
2
RC0805
A
RC0603
3
2 C
B
3
DVDD
CC0805
DVDD
13
11
C8
10
CLK
J
U6
PRE
.01UF
CC0805
Q
7
9
DGND;8
DVDD;16
12
K
Q_
CLR
SN74F112 14
.1UF
C7
AD9709
00606-147
RC0805
AD9709
R23
DNP
51
DNP
DNP
CC0805
C24
C31
RC0603
LC0805
DNP
CC0603
L6
O2N
JP19
CC0805
L5
O2P
C23
DNP
R21
51
R22
DNP
RC0603
LC0805
RC0603
MODULATED OUTPUT
AGND2;3,4,5
10
9
G2
RC0603
AD834 9
AVDD2
R28
1K
ENBL
VPS1
7
2
TP6
RED
AGND2
TP5
BLK
8
11
12
J1
AVDD2
2
JP18
.1UF
LOCAL OSC INPUT
2
CC0603
C30
3
CC0603
ETC1-1-13
AGND2;3,4,5
R29
0
SMAEDGE
4
J2
RC0603
C26
100PF
C25
100PF
S
P
1
5
R20
50
2
CC0603
T4
RC0603
2
SMAEDGE
RC0603
100PF
G3
VOUT
LOIP
LOIN
5
G1B
4
3
IBBP
1
2
G1A
AGND2;17
2
6
14
13
U3
VPS2
G4A
100PF
G4B
16
CC0603
C27
QBBN
CC0603
QBBP
C20
10UF
10V
IBBN
BCASE
.1UF
C29
15
AVDD2
0
CC0603
C28
R27
JP21
2
JP22
O1N
DNP
C32
DNP
JP20
CC0805
L3
DNP
LC0805
C 21
R25
51
R24
RC0603
DNP
RC0603
Figure 48. Modulator on AD9709 Evaluation Board
Rev. B | Page 26 of 32
00606-148
CC0805
C22
51
RC0603
LC0805
DNP
O1P
R26
DNP
CC0603
2
L4
Rev. B | Page 27 of 32
Figure 49. Digital Input Signaling (1)
P1
35
37
39
36
38
40
HDR040RA
33
29
27
25
23
21
19
34
HDR040RA
SPARES
10
10
RP6
7
INP8
15
INCK1
INP14
INP13
INP12
INP11
INP10
INP9
INP7
13
17
INP6
INP4
7
INP5
INP3
5
9
INP2
3
11
INP1
1
31
RIBBON RA
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
8
5
3
1
7
RC0603
RP5
RP5
RP5
RP6
RP6
RP6
RP6
RP5
5
3
1
10
10
10
10
10
9
12
14
16
10
10
10
10
12
14
16
6
4
2
8
RP5
RP5
RP5
RP6
RP6
RP6
RP5
6
4
2
RC0603
R62
470
RC0603
10
10
10
10
11
13
15
9
10
10
10
11
13
15
R61
470
RC0603
R60
470
RC0603
R59
470
RC0603
R58
470
RC0603
R57
470
RC0603
R56
470
RC0603
R55
470
RC0603
R54
470
RC0603
R53
470
RC0603
R52
470
RC0603
R51
470
RC0603
R50
470
RC0603
R33
470
DCLKIN1
DUTP14
DUTP13
DUTP12
DUTP11
DUTP10
DUTP9
DUTP8
DUTP7
DUTP6
DUTP5
DUTP4
DUTP3
DUTP2
DUTP1
R49
470
AD9709
00606-149
Rev. B | Page 28 of 32
Figure 50. Digital Input Signaling (2)
P2
37
39
38
40
HDR040RA
35
36
HDR040RA
33
34
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
31
RIBBON RA
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
1010
RP87
SPARES
INCK2
8 RP8 10 9
INP36
INP35
6 RP7 1011
4 RP8 1013
6 RP8 1011
INP33
RC0603
7 RP7 1010
5 RP7 1012
1 RP7 1016
2 RP7 1015
3 RP7 1014
4 RP7 1013
5 RP8 1012
8 RP7 10 9
1 RP8 1016
2 RP8 1015
3 RP8 1014
INP30
INP29
INP32
INP34
INP27
INP26
INP25
INP28
INP31
INP23
INP24
RC0603
R34
470
RC0603
R35
470
RC0603
R48
470
RC0603
R36
470
RC0603
R37
470
RC0603
R47
470
RC0603
R38
470
RC0603
R39
470
RC0603
R46
470
RC0603
R45
470
RC0603
R44
470
RC0603
R43
470
RC0603
R40
470
RC0603
R42
470
DCLKIN2
DUTP36
DUTP35
DUTP34
DUTP33
DUTP32
DUTP31
DUTP30
DUTP29
DUTP28
DUTP27
DUTP26
DUTP25
DUTP24
DUTP23
R41
470
AD9709
00606-150
Rev. B | Page 29 of 32
DUTP23
DUTP24
WRT1
CLK1
CLK2
WRT2
DUTP1
DUTP2
DUTP3
DUTP4
DUTP5
DUTP6
DUTP7
DUTP8
DUTP9
DUTP10
DUTP11
DUTP12
DUTP13
DUTP14
C1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VAL
CC0805
C2
C3
.1UF
CC0805
DVDD
DB13P1MSB
MODE
DB12P1
AVDD
DB11P1
IA1
DB10P1
IB1
DB9P1
FSADJ1
DB8P1
REFIO
DB7P1
ACOM1
DB6P1
FSADJ2
DB5P1
IB2
DB4P1
IA2
DB3P1
ACOM
DB2P1
SLEEP
U1
DB1P1AD9763/65/67 DB0P2
DB1P2
DB0P1
DB2P2
DCOM1
DB3P2
DVDD1
DB4P2
WRT1
DB5P2
CLK1
DB6P2
CLK2
DB7P2
WRT2
DB8P2
DCOM2
DB9P2
DVDD2
DB13P2MSB
DB10P2
DB12P2
DB11P2
.01UF
CC0805
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Figure 51. Device Under Test/Analog Output Signal Conditioning
C11
VAL
CC0805
SLEEP
DUTP36
DUTP35
DUTP34
DUTP33
DUTP32
DUTP31
DUTP30
DUTP29
DUTP28
DUTP27
DUTP26
DUTP25
MODEJP8
1 A B 3
2
CC0805
R32
O2P
C12
.01UF
CC0805
10PF
CC0805
C15
10PF
C4
CC0805
C13
.1UF
RC0805
10
O2N
JP11
JP7
JP24
JP12
JP6
O1N
O1P
JP23
RC0805
RC0805
RC0805
10
AVDD
R7
50
R5
50
10PF
CC0805
C6
10PF
CC0805
C5
RC0805
RC0805
R31
R8
50
R6
50
C16
C17
R12
VAL
WHT
R10
RC0805
1.92K
22NF
22NF
RC0805
R9 1.92K
R11
VAL
WHT
RC07CUP
CC0805
CC0805
ACOM JP15
1 A B 3
2
AVDD
3
2
1
6
5
4
T6
RC0805
256
RC0805
256
4
6
5
BL4
BL3
BL2
T1-1TCUP
T5
T1-1TCUP
JP10
R14
R15
3
2
1
BL1
WHT
WHT
OUT1
S11
SMA200UP
OUT2
AGND;3,4,5
.1UF
CC0805
C14
WHT
REFIO
S6
SMA200UP
AGND;3,4,5
00606-151
DVDD
AD9709
RC07CUP
AD9709
00606-152
EVALUATION BOARD LAYOUT
Figure 52. Assembly, Top Side
Rev. B | Page 30 of 32
00606-153
AD9709
Figure 53. Assembly, Bottom Side
Rev. B | Page 31 of 32
AD9709
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
Figure 54. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9709ASTZ 1
AD9709ASTZRL1
AD9709-EBZ1
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
Z = RoHS Compliant Part.
©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00606-0-9/09(B)
Rev. B | Page 32 of 32
Package Option
ST-48
ST-48
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