AD9778A

Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters AD9776A/AD9778A/AD9779A FEATURES Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP GENERAL DESCRIPTION The AD9776A/AD9778A/AD9779A are dual, 12-/14-/16-bit, high dynamic range digital-to-analog converters (DACs) that provide a sample rate of 1 GSPS, permitting a multicarrier generation up to the Nyquist frequency. They include features optimized for direct conversion transmission applications, including complex digital modulation and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators such as the ADL537x FMOD series from Analog Devices, Inc. A 3-wire interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 10 mA to 30 mA. The devices are manufactured on an advanced 0.18 μm CMOS process and operate on 1.8 V and 3.3 V supplies for a total power consumption of 1.0 W. They are enclosed in a 100-lead thin quad flat package (TQFP). APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMax, GSM, LTE Digital high or low IF synthesis Internal digital upconversion capability Transmit diversity Wideband communications: LMDS/MMDS, point-to-point PRODUCT HIGHLIGHTS 1. Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. CMOS data input interface with adjustable setup and hold. Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth. QUADRATURE MODULATOR/ MIXER/ AMPLIFIER 2. 3. 4. 5. TYPICAL SIGNAL CHAIN COMPLEX I AND Q DC DC DIGITAL INTERPOLATION FILTERS I DAC FPGA/ASIC/DSP Q DAC POST DAC ANALOG FILTER A 06452-114 LO AD9776A/AD9778A/AD9779A Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved. AD9776A/AD9778A/AD9779A TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Product Highlights ........................................................................... 1  Typical Signal Chain......................................................................... 1  Revision History ............................................................................... 3  Functional Block Diagram .............................................................. 4  Specifications..................................................................................... 5  DC Specifications ......................................................................... 5  Digital Specifications ................................................................... 6  Digital Input Data Timing Specifications ................................. 7  AC Specifications.......................................................................... 8  Absolute Maximum Ratings............................................................ 9  Thermal Resistance ...................................................................... 9  ESD Caution .................................................................................. 9  Pin Configurations and Function Descriptions ......................... 10  Typical Performance Characteristics ........................................... 16  Terminology .................................................................................... 24  Theory of Operation ...................................................................... 25  Differences Between AD9776/AD9778/ AD9779 and AD9776A/AD9778A/AD9779A............................................... 25  3-Wire Interface .............................................................................. 26  General Operation of the Serial Interface ............................... 26  Instruction Byte .......................................................................... 26  Serial Interface Port Pin Descriptions ..................................... 27  MSB/LSB Transfers..................................................................... 27  3-Wire Interface Register Map ...................................................... 28  Interpolation Filter Architecture .................................................. 33  Interpolation Filter Bandwidth Limits .................................... 37  Inverse Sinc Filter ....................................................................... 38  Sourcing the DAC Sample Clock ................................................. 39  Direct Clocking .......................................................................... 39  Clock Multiplication .................................................................. 39  Driving the REFCLK Input ....................................................... 42  Full-Scale Current Generation ..................................................... 43  Internal Reference ...................................................................... 43  Gain and Offset Correction .......................................................... 44  I/Q Channel Gain Matching ..................................................... 44  Auxiliary DAC Operation ......................................................... 44  LO Feedthrough Compensation .............................................. 45  Results of Gain and Offset Correction .................................... 45  Input Data Ports ............................................................................. 46  Single Port Mode ........................................................................ 46  Dual Port Mode .......................................................................... 46  Input Data Referenced to DATACLK ...................................... 46  Input Data Referenced to REFCLK ......................................... 47  Optimizing the Data Input Timing.......................................... 48  Device Synchronization ................................................................. 49  Synchronization Logic Overview ............................................. 49  Synchronizing Devices to a System Clock .............................. 50  Interrupt Request Operation .................................................... 50  Power Dissipation ........................................................................... 51  Power-Down and Sleep Modes................................................. 52  Evaluation Board Overview .......................................................... 53  Evaluation Board Operation ..................................................... 53  Outline Dimensions ....................................................................... 55  Ordering Guide .......................................................................... 55  Rev. B | Page 2 of 56 AD9776A/AD9778A/AD9779A REVISION HISTORY 9/08—Rev. A to Rev. B Changed Serial Peripheral Interface (SPI) to 3-Wire Interface Throughout ................................................................................... 1 Change to Features Section .............................................................. 1 Change to Applications Section ...................................................... 1 Changes to Integral Nonlinearity (INL) Parameter, Table 1 ....... 5 Changes to DAC Clock Input (REFCLK+, REFCLK−) Parameter, Table 2 ........................................................................ 6 Changes to Input Data Parameter, Table 3..................................... 7 Changes to Hold Time Parameters, Table 3................................... 7 Added 3-Wire Interface Parameter, Table 3................................... 7 Added Reset Parameter, Table 3 ...................................................... 7 Changes to Endnotes, Table 3 .......................................................... 7 Added Exposed Pad Notation to Figure 3, Changes to Table 7 ...... 10 Added Exposed Pad Notation to Figure 4, Changes to Table 8 ...... 12 Added Exposed Pad Notation to Figure 5, Changes to Table 9 ...... 14 Changes to DATACLK Delay Range Section ..............................25 Changes to Version Register Section ............................................25 Changes to Table 10 ........................................................................25 Changes to Table 12 ........................................................................26 Changes to Table 13 ........................................................................28 Changes to Table 14 ........................................................................29 Changes to Interpolation Filter Architecture Section ................33 Changes to Figure 60 ......................................................................34 Changes to Table 19 ........................................................................36 Changes to Interpolation Filter Bandwidth Limits Section.......37 Changes to Figure 70 ......................................................................37 Added Digital Modulation Section ...............................................37 Added Table 20 and Table 21; Renumbered Sequentially ..........38 Added Inverse Sinc Filter Section .................................................38 Added Figure 71; Renumbered Sequentially ...............................38 Changes to Clock Multiplication Section ....................................39 Changes to Figure 72 ......................................................................39 Changes to Configuring the PLL Band Select Value Section ....39 Changes to Configuring the PLL Band Select with Temperature Sensing Section ...........................................................................41 Changes to Known Temperature Calibration with Memory Section .........................................................................................41 Changes to Set-and-Forget Device Option Section ....................41 Added Table 26 ................................................................................41 Changes to Internal Reference Section.........................................43 Changed Transmit Path Gain and Offset Correction Heading to Gain and Offset Correction ......................................................44 Changes to I/Q Channel Gain Matching Section .......................44 Changes to Auxiliary DAC Operation Section ........................... 44 Replaced Figure 79 .......................................................................... 45 Deleted Figure 79; Renumbered Sequentially ............................. 41 Changes to LO Feedthrough Compensation Section................. 45 Changes to Table 28 ........................................................................ 47 Changes to Optimizing the Data Input Timing Section ............ 48 Change to Synchronization Logic Overview Section ................. 49 Changes to Figure 88 ...................................................................... 49 Changes to Figure 101 .................................................................... 53 Deleted Using the ADL5372 Quadrature Modulator Section and Figure 104 .................................................................................... 51 Deleted Evaluation Board Schematics Section and Figure 105; Renumbered Sequentially ......................................................... 52 Deleted Figure 106 .......................................................................... 53 Deleted Figure 107 .......................................................................... 54 Deleted Figure 108 .......................................................................... 55 Deleted Figure 109 .......................................................................... 56 Deleted Figure 110 .......................................................................... 57 Deleted Figure 111 .......................................................................... 58 Deleted Figure 112 .......................................................................... 59 Updated Outline Dimensions........................................................ 60 3/08—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Added Note 2 ..................................................................................... 4 Changes to Table 2 ............................................................................ 5 Changes to Table 3 ............................................................................ 6 Changes to Thermal Resistance Section ........................................ 7 Inserted Table 6 ................................................................................. 8 Changes to Pin 39 Description, Table 7 ......................................... 9 Changes to Pin 39 Description, Table 8 ....................................... 10 Changes to Pin 39 Description, Table 9 ....................................... 12 Changes to Theory of Operation Section .................................... 23 Changes to Table 10 ........................................................................ 23 Changes to Table 13 ........................................................................ 26 Changes to Table 14 ........................................................................ 27 Changes to Interpolation Filter Architecture Section ................ 33 Replaced Sourcing the DAC Sample Clock Section ................... 36 Replaced Transmit Path Gain and Offset Correction Section ........ 40 Replaced Input Data Ports Section ............................................... 42 Replaced Device Synchronization Section .................................. 45 Deleted Figure 112 to Figure 117 .................................................. 58 8/07—Revision 0: Initial Version Rev. B | Page 3 of 56 AD9776A/AD9778A/AD9779A FUNCTIONAL BLOCK DIAGRAM SYNC_O SYNC_I DATACLK DELAY LINE DATA ASSEMBLER DELAY LINE CLOCK GENERATION/DISTRIBUTION CLOCK MULTIPLIER 2×/4×/8× REFCLK+ REFCLK– SINC^-1 n × fDAC /8 n = 0, 1, 2 ... 7 Q LATCH 2× 2× 2× COMPLEX MODULATOR P1D[15:0] I LATCH 16-BIT I DAC OUT1_P OUT1_N 2× 2× 2× P2D[15:0] SINC^-1 16-BIT Q DAC OUT2_P OUT2_N REFERENCE AND BIAS VREF I120 DIGITAL CONTROLLER 10 10 SERIAL PERIPHERAL INTERFACE POWER-ON RESET 10 GAIN GAIN GAIN GAIN AUX1_P AUX1_N AUX2_P AUX2_N 06452-001 AD9779A 10 SDO SDIO SCLK CSB Figure 2. AD9779A Functional Block Diagram Rev. B | Page 4 of 56 AD9776A/AD9778A/AD9779A SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Output Resistance Gain DAC Monotonicity MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage AUXILIARY DAC OUTPUTS Resolution Full-Scale Output Current1 Output Compliance Range (Source) Output Compliance Range (Sink) Output Resistance Auxiliary DAC Monotonicity REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD33 DVDD18 POWER CONSUMPTION 2 1× Mode, fDAC = 100 MSPS, IF = 1 MHz 2× Mode, fDAC = 320 MSPS, IF = 16 MHz, PLL Off 2× Mode, fDAC = 320 MSPS, IF = 16 MHz, PLL On 4× Mode, fDAC/4 Modulation, fDAC = 500 MSPS, IF = 137.5 MHz, Q DAC Off 8× Mode, fDAC/4 Modulation, fDAC = 1 GSPS, IF = 262.5 MHz Power-Down Mode Power Supply Rejection Ratio, AVDD33 OPERATING RANGE 1 2 Min AD9776A Typ Max 12 ±0.1 ±0.86 Min AD9778A Typ Max 14 ±0.65 ±1.5 Min AD9779A Typ Max 16 ±2.1 ±6.0 Unit Bits LSB LSB −0.001 8.66 −1.0 0 ±2 20.2 +0.001 31.66 +1.0 −0.001 8.66 −1.0 0 ±2 20.2 10 Guaranteed 0.04 100 30 10 +0.001 31.66 +1.0 −0.001 8.66 −1.0 0 ±2 20.2 +0.001 31.66 +1.0 10 Guaranteed 0.04 100 30 10 −1.998 0 0.8 +1.998 1.6 1.6 1 Guaranteed 1.2 5 3.13 1.70 3.13 1.70 3.3 1.8 3.3 1.8 250 498 588 572 980 2.5 −0.3 −40 +25 9.8 +0.3 +85 3.47 2.05 3.47 2.05 300 3.13 1.70 3.13 1.70 −1.998 0 0.8 10 Guaranteed 0.04 100 30 10 +1.998 1.6 1.6 −1.998 0 0.8 +1.998 1.6 1.6 % FSR % FSR mA V MΩ ppm/°C ppm/°C ppm/°C Bits mA V V MΩ 1 Guaranteed 1.2 5 3.3 1.8 3.3 1.8 250 498 588 572 980 2.5 −0.3 −40 +25 9.8 +0.3 +85 3.47 2.05 3.47 2.05 300 3.13 1.70 3.13 1.70 1 Guaranteed 1.2 5 3.3 1.8 3.3 1.8 250 498 588 572 980 2.5 −0.3 −40 +25 9.8 +0.3 +85 3.47 2.05 3.47 2.05 300 V kΩ V V V V mW mW mW mW mW mW % FSR/V °C Based on a 10 kΩ external resistor. See the Power Dissipation section for more details. Rev. B | Page 5 of 56 AD9776A/AD9778A/AD9779A DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input VIN Logic High Input VIN Logic Low Maximum Input Data Rate at Interpolation 1× 2× 4× 8× Conditions Min 2.0 0.8 300 250 200 112.5 125 137.5 2.4 At 250 MHz, into 5 pF load SYNC_I+ = VIA, SYNC_I− = VIB 40 825 −100 20 80 Additional limits on fSYNC_I apply; see description of Register 0x05, Bits[3:1], in Table 14 0.4 0.55 SYNC_O+ = VOA, SYNC_O− = VOB, 100 Ω termination 1375 1025 150 1150 80 400 300 900 1000 1100 250 200 100 800 400 250 1250 120 2000 500 mV mV mV mV Ω mV mV MHz MHz MHz MHz 120 250 50 0.4 60 1575 +100 Typ Max Unit V V MSPS MSPS MSPS MSPS MSPS MSPS V V % mV mV mV Ω MSPS ns ns DVDD18, CVDD18 = 1.8 V ± 5% DVDD18, CVDD18 = 1.9 V ± 5% DVDD18, CVDD18 = 2.0 V ± 2% CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 37) 1 Output VOUT Logic High Output VOUT Logic Low DATACLK Output Duty Cycle LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−) Input Voltage Range, VIA or VIB Input Differential Threshold, VIDTH Input Differential Hysteresis, VIDTHH − VIDTHL Receiver Differential Input Impedance, RIN LVDS Input Rate Setup Time, SYNC_I to REFCLK Hold Time, SYNC_I to REFCLK LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−) Output Voltage High, VOA or VOB Output Voltage Low, VOA or VOB Output Differential Voltage, |VOD| Output Offset Voltage, VOS Output Impedance, RO DAC CLOCK INPUT (REFCLK+, REFCLK−) Differential Peak-to-Peak Voltage Common-Mode Voltage Maximum Clock Rate Single-ended DVDD18, CVDD18 = 1.8 V ± 5%, PLL off DVDD18, CVDD18 = 1.9 V ± 5%, PLL off DVDD18, CVDD18 = 2.0 V ± 2%, PLL off DVDD18, CVDD18 = 2.0 V ± 2%, PLL on 1 Specification is at a DATACLK frequency of 100 MHz into a 1 kΩ load, with maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests using an external buffer for this signal. Rev. B | Page 6 of 56 AD9776A/AD9778A/AD9779A DIGITAL INPUT DATA TIMING SPECIFICATIONS All modes, −40°C to +85°C. Table 3. Parameter INPUT DATA 1 Setup Time Hold Time Setup Time Hold Time LATENCY 1× Interpolation 2× Interpolation 4× Interpolation 8× Interpolation Inverse Sync 3-WIRE INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High, tPWH Minimum Pulse Width Low, tPWL Setup Time, tDS Hold Time, tDH Setup Time, tDS Data Valid, tDV POWER-UP TIME 2 RESET Minimum Pulse Width, High 1 Conditions Input data to DATACLK Input data to DATACLK Input data to REFCLK Input data to REFCLK With or without modulation With or without modulation With or without modulation With or without modulation Min 3.0 −0.05 −0.80 3.80 Typ Max Unit ns ns ns ns 25 70 146 297 18 40 12.5 12.5 DACCLK cycles DACCLK cycles DACCLK cycles DACCLK cycles DACCLK cycles MHz ns ns ns ns ns ns ms DACCLK cycles SDIO to SCLK SDIO to SCLK CSB to SCLK SDO to SCLK 2.8 0.0 2.8 2.0 260 2 Specified values are with PLL disabled. Timing vs. temperature and data valid keep out windows (that is, the minimum amount of time valid data must be presented to the device to ensure proper sampling) are delineated in Table 28. 2 Measured from CSB rising edge when Register 0x00, Bit 4, is written from 1 to 0 with the VREF decoupling capacitor equal to 0.1 μF. Rev. B | Page 7 of 56 AD9776A/AD9778A/AD9779A AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFs = 20 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 100 MSPS, fOUT = 20 MHz fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 70 MHz fDAC = 800 MSPS, fOUT = 70 MHz T WO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 60 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 100 MHz NOISE SPECTRAL DENSITY (NSD), EIGHT-TONE, 500 kHz TONE SPACING fDAC = 200 MSPS, fOUT = 80 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 80 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 100 MHz fDAC = 491.52 MSPS, fOUT = 200 MHz W-CDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 100 MHz fDAC = 491.52 MSPS, fOUT = 200 MHz Min AD9776A Typ Max 82 81 80 85 87 80 75 75 Min AD9778A Typ Max 82 81 80 85 87 85 81 80 Min AD9779A Typ Max 82 82 80 87 91 85 81 81 Unit dBc dBc dBc dBc dBc dBc dBc dBc −152 −155 −157.5 −155 −159 −160 −158 −160 −161 dBm/Hz dBm/Hz dBm/Hz 76 69 78 73 79 74 dBc dBc 77.5 76 80 78 81 78 dBc dBc Rev. B | Page 8 of 56 AD9776A/AD9778A/AD9779A ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD33, DVDD33 DVDD18, CVDD18 AGND DGND CGND I120, VREF, IPTAT OUT1_P, OUT1_N, OUT2_P, OUT2_N, AUX1_P, AUX1_N, AUX2_P, AUX2_N P1D[15:0], P2D[15:0] DATACLK, TXENABLE REFCLK+, REFCLK− RESET, IRQ, PLL_LOCK, SYNC_O+, SYNC_O−, SYNC_I+, SYNC_I−, CSB, SCLK, SDIO, SDO Junction Temperature Storage Temperature Range With Respect To AGND, DGND, CGND AGND, DGND, CGND DGND, CGND AGND, CGND AGND, DGND AGND AGND Rating −0.3 V to +3.6 V −0.3 V to +2.1 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to AVDD33 + 0.3 V −1.0 V to AVDD33 + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE For optimal thermal performance, the exposed paddle (EPAD) should be soldered to the ground plane for the 100-lead, thermally enhanced TQFP package. Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA. Table 6. Thermal Resistance Package Type 100-Lead TQFP EPAD Soldered EPAD Not Soldered θJA 19.1 27.4 θJB 12.4 θJC 7.1 Unit °C/W °C/W DGND DGND CGND DGND −0.3 V to DVDD33 + 0.3 V −0.3 V to DVDD33 + 0.3 V −0.3 V to CVDD18 + 0.3 V −0.3 V to DVDD33 + 0.3 V +125°C −65°C to +150°C ESD CAUTION Rev. B | Page 9 of 56 AD9776A/AD9778A/AD9779A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUT2_N OUT1_N AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK– CGND CGND CVDD18 AVDD33 AUX1_N AUX2_N OUT2_P OUT1_P AUX1_P AUX2_P AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND 1 2 3 4 5 6 7 8 9 PIN 1 75 74 I120 VREF IPTAT AGND IRQ RESET CSB SCLK SDIO SDO PLL_LOCK DGND SYNC_O+ SYNC_O– DVDD33 DVDD18 NC NC NC NC P2D0 DGND DVDD18 P2D1 P2D2 ANALOG DOMAIN 73 72 71 DIGITAL DOMAIN 70 69 68 AD9776A TOP VIEW (Not to Scale) 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CVDD18 10 CGND 11 AGND 12 SYNC_I+ 13 SYNC_I– 14 DGND 15 DVDD18 16 P1D11 17 P1D10 18 P1D9 19 P1D8 20 P1D7 21 DGND 22 DVDD18 23 P1D6 24 P1D5 25 TXENABLE/IQSELECT NC NC NC DGND NC DATACLK DGND P1D4 P1D3 P1D2 P1D1 P1D0 P2D9 P2D8 P2D7 P2D6 P2D5 P2D4 P2D11 DVDD18 DVDD33 P2D10 NOTES 1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE. DVDD18 P2D3 NC = NO CONNECT 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 3. AD9776A Pin Configuration Table 7. AD9776A Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK− CGND CGND CVDD18 CVDD18 CGND AGND SYNC_I+ SYNC_I− DGND DVDD18 Description 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Clock Ground. Differential Clock Input. Differential Clock Input. Clock Ground. Clock Ground. 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Analog Ground. Differential Synchronization Input. Differential Synchronization Input. Digital Ground. 1.8 V Digital Supply. Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Rev. B | Page 10 of 56 Mnemonic P1D11 P1D10 P1D9 P1D8 P1D7 DGND DVDD18 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 NC DGND Description Port 1, Data Input D11 (MSB). Port 1, Data Input D10. Port 1, Data Input D9. Port 1, Data Input D8. Port 1, Data Input D7. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Port 1, Data Input D2. Port 1, Data Input D1. Port 1, Data Input D0 (LSB). No Connect. Digital Ground. 06452-002 AD9776A/AD9778A/AD9779A Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Mnemonic DVDD18 NC NC NC DATACLK DVDD33 TXENABLE/ IQSELECT P2D11 P2D10 P2D9 DVDD18 DGND P2D8 P2D7 P2D6 P2D5 P2D4 P2D3 P2D2 P2D1 DVDD18 DGND P2D0 NC NC NC NC DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK Description 1.8 V Digital Supply. No Connect. No Connect. No Connect. Data Clock Output. 3.3 V Digital Supply. Transmit Enable. In single port mode, this pin also functions as IQSELECT. Port 2, Data Input D11 (MSB). Port 2, Data Input D10. Port 2, Data Input D9. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D8. Port 2, Data Input D7. Port 2, Data Input D6. Port 2, Data Input D5. Port 2, Data Input D4. Port 2, Data Input D3. Port 2, Data Input D2. Port 2, Data Input D1. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D0 (LSB). No Connect. No Connect. No Connect. No Connect. 1.8 V Digital Supply. 3.3 V Digital Supply. Differential Synchronization Output. Differential Synchronization Output. Digital Ground. PLL Lock Indicator. 3-Wire Interface Port Data Output. 3-Wire Interface Port Data Input/Output. 3-Wire Interface Port Clock. Pin No. 69 70 71 72 73 Mnemonic CSB RESET IRQ AGND IPTAT 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VREF I120 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 Description 3-Wire Interface Port Chip Select Bar. Reset, Active High. Interrupt Request. Analog Ground. Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating. Voltage Reference Output. 120 μA Reference Current. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. Analog Ground. Differential DAC Current Output, Channel 2. Differential DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 2. Auxiliary DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 1. Auxiliary DAC Current Output, Channel 1. Analog Ground. Differential DAC Current Output, Channel 1. Differential DAC Current Output, Channel 1. Analog Ground. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Rev. B | Page 11 of 56 AD9776A/AD9778A/AD9779A OUT2_N OUT1_N AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AUX1_N AUX2_N OUT2_P OUT1_P AUX1_P AUX2_P AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK– CGND CGND CVDD18 1 2 3 4 5 6 7 8 9 PIN 1 75 74 I120 VREF IPTAT AGND IRQ RESET CSB SCLK SDIO SDO PLL_LOCK DGND SYNC_O+ SYNC_O– DVDD33 DVDD18 NC NC P2D0 P2D1 P2D2 DGND DVDD18 P2D3 P2D4 ANALOG DOMAIN 73 72 71 DIGITAL DOMAIN 70 69 68 AD9778A TOP VIEW (Not to Scale) 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CVDD18 10 CGND 11 AGND 12 SYNC_I+ 13 SYNC_I– 14 DGND 15 DVDD18 16 P1D13 17 P1D12 18 P1D11 19 P1D10 20 P1D9 21 DGND 22 DVDD18 23 P1D8 24 P1D7 25 TXENABLE/IQSELECT NC DGND NC DATACLK DGND P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 P2D9 P2D8 P2D7 P2D6 P2D13 P2D12 P2D11 DVDD18 DVDD33 NOTES 1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE. DVDD18 P2D10 P2D5 NC = NO CONNECT 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 4. AD9778A Pin Configuration Table 8. AD9778A Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Mnemonic CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK− CGND CGND CVDD18 CVDD18 CGND AGND SYNC_I+ SYNC_I− DGND DVDD18 P1D13 P1D12 Description 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Clock Common. Differential Clock Input. Differential Clock Input. Clock Ground. Clock Ground. 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Analog Ground. Differential Synchronization Input. Differential Synchronization Input. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D13 (MSB). Port 1, Data Input D12. Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Rev. B | Page 12 of 56 Mnemonic P1D11 P1D10 P1D9 DGND DVDD18 P1D8 P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 DGND DVDD18 P1D0 NC NC Description Port 1, Data Input D11. Port 1, Data Input D10. Port 1, Data Input D9. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D8. Port 1, Data Input D7. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Port 1, Data Input D2. Port 1, Data Input D1. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D0 (LSB). No Connect. No Connect. 06452-003 AD9776A/AD9778A/AD9779A Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Mnemonic DATACLK DVDD33 TXENABLE/ IQSELECT P2D13 P2D12 P2D11 DVDD18 DGND P2D10 P2D9 P2D8 P2D7 P2D6 P2D5 P2D4 P2D3 DVDD18 DGND P2D2 P2D1 P2D0 NC NC DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK CSB RESET Description Data Clock Output. 3.3 V Digital Supply. Transmit Enable. In single port mode, this pin also functions as IQSELECT. Port 2, Data Input D13 (MSB). Port 2, Data Input D12. Port 2, Data Input D11. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D10. Port 2, Data Input D9. Port 2, Data Input D8. Port 2, Data Input D7. Port 2, Data Input D6. Port 2, Data Input D5. Port 2, Data Input D4. Port 2, Data Input D3. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D2. Port 2, Data Input D1. Port 2, Data Input D0 (LSB). No Connect. No Connect. 1.8 V Digital Supply. 3.3 V Digital Supply. Differential Synchronization Output. Differential Synchronization Output. Digital Ground. PLL Lock Indicator. 3-Wire Interface Port Data Output. 3-Wire Interface Port Data Input/Output. 3-Wire Interface Port Clock. 3-Wire Interface Port Chip Select Bar. Reset, Active High. Pin No. 71 72 73 Mnemonic IRQ AGND IPTAT 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VREF I120 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 Description Interrupt Request. Analog Ground. Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating. Voltage Reference Output. 120 μA Reference Current. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. Analog Ground. Differential DAC Current Output, Channel 2. Differential DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 2. Auxiliary DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 1. Auxiliary DAC Current Output, Channel 1. Analog Ground. Differential DAC Current Output, Channel 1. Differential DAC Current Output, Channel 1. Analog Ground. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Rev. B | Page 13 of 56 AD9776A/AD9778A/AD9779A OUT2_N OUT1_N AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AUX1_N AUX2_N OUT2_P OUT1_P AUX1_P AUX2_P AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK– CGND CGND CVDD18 1 2 3 4 5 6 7 8 9 PIN 1 75 74 I120 VREF IPTAT AGND IRQ RESET CSB SCLK SDIO SDO PLL_LOCK DGND SYNC_O+ SYNC_O– DVDD33 DVDD18 P2D0 P2D1 P2D2 P2D3 P2D4 DGND DVDD18 P2D5 P2D6 ANALOG DOMAIN 73 72 71 DIGITAL DOMAIN 70 69 68 AD9779A TOP VIEW (Not to Scale) 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CVDD18 10 CGND 11 AGND 12 SYNC_I+ 13 SYNC_I– 14 DGND 15 DVDD18 16 P1D15 17 P1D14 18 P1D13 19 P1D12 20 P1D11 21 DGND 22 DVDD18 23 P1D10 24 P1D9 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TXENABLE/IQSELECT DGND DATACLK DGND P1D8 P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 P2D9 P2D8 P2D15 P2D14 P2D13 P2D12 P2D11 DVDD18 DVDD33 NOTES 1. FOR OPTIMAL THERMAL PERFORMANCE, THE EXPOSED PAD SHOULD BE SOLDERED TO THE GROUND PLANE FOR THE 100-LEAD, THERMALLY ENHANCED TQFP PACKAGE. DVDD18 P2D10 P2D7 Figure 5. AD9779A Pin Configuration Table 9. AD9779A Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Mnemonic CVDD18 CVDD18 CGND CGND REFCLK+ REFCLK− CGND CGND CVDD18 CVDD18 CGND AGND SYNC_I+ SYNC_I− DGND DVDD18 P1D15 P1D14 Description 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Clock Ground. Differential Clock Input. Differential Clock Input. Clock Ground. Clock Ground. 1.8 V Clock Supply. 1.8 V Clock Supply. Clock Ground. Analog Ground. Differential Synchronization Input. Differential Synchronization Input. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D15 (MSB). Port 1, Data Input D14. Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Rev. B | Page 14 of 56 Mnemonic P1D13 P1D12 P1D11 DGND DVDD18 P1D10 P1D9 P1D8 P1D7 P1D6 P1D5 P1D4 P1D3 DGND DVDD18 P1D2 P1D1 P1D0 Description Port 1, Data Input D13. Port 1, Data Input D12. Port 1, Data Input D11. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D10. Port 1, Data Input D9. Port 1, Data Input D8. Port 1, Data Input D7. Port 1, Data Input D6. Port 1, Data Input D5. Port 1, Data Input D4. Port 1, Data Input D3. Digital Ground. 1.8 V Digital Supply. Port 1, Data Input D2. Port 1, Data Input D1. Port 1, Data Input D0 (LSB). 06452-004 AD9776A/AD9778A/AD9779A Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Mnemonic DATACLK DVDD33 TXENABLE/ IQSELECT P2D15 P2D14 P2D13 DVDD18 DGND P2D12 P2D11 P2D10 P2D9 P2D8 P2D7 P2D6 P2D5 DVDD18 DGND P2D4 P2D3 P2D2 P2D1 P2D0 DVDD18 DVDD33 SYNC_O− SYNC_O+ DGND PLL_LOCK SDO SDIO SCLK CSB RESET Description Data Clock Output. 3.3 V Digital Supply. Transmit Enable. In single port mode, this pin also functions as IQSELECT. Port 2, Data Input D15 (MSB). Port 2, Data Input D14. Port 2, Data Input D13. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D12. Port 2, Data Input D11. Port 2, Data Input D10. Port 2, Data Input D9. Port 2, Data Input D8. Port 2, Data Input D7. Port 2, Data Input D6. Port 2, Data Input D5. 1.8 V Digital Supply. Digital Ground. Port 2, Data Input D4. Port 2, Data Input D3. Port 2, Data Input D2. Port 2, Data Input D1. Port 2, Data Input D0 (LSB). 1.8 V Digital Supply. 3.3 V Digital Supply. Differential Synchronization Output. Differential Synchronization Output. Digital Ground. PLL Lock Indicator. 3-Wire Interface Port Data Output. 3-Wire Interface Port Data Input/Output. 3-Wire Interface Port Clock. 3-Wire Interface Port Chip Select Bar. Reset, Active High. Pin No. 71 72 73 Mnemonic IRQ AGND IPTAT 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VREF I120 AVDD33 AGND AVDD33 AGND AVDD33 AGND AGND OUT2_P OUT2_N AGND AUX2_P AUX2_N AGND AUX1_N AUX1_P AGND OUT1_N OUT1_P AGND AGND AVDD33 AGND AVDD33 AGND AVDD33 Description Interrupt Request. Analog Ground. Factory Test Pin. Output current is proportional to absolute temperature, approximately 14 μA at 25°C with approximately 20 nA/°C slope. This pin should remain floating. Voltage Reference Output. 120 μA Reference Current. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. Analog Ground. Differential DAC Current Output, Channel 2. Differential DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 2. Auxiliary DAC Current Output, Channel 2. Analog Ground. Auxiliary DAC Current Output, Channel 1. Auxiliary DAC Current Output, Channel 1. Analog Ground. Differential DAC Current Output, Channel 1. Differential DAC Current Output, Channel 1. Analog Ground. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Analog Ground. 3.3 V Analog Supply. Rev. B | Page 15 of 56 AD9776A/AD9778A/AD9779A TYPICAL PERFORMANCE CHARACTERISTICS 4 3 2 1 INL (16-BIT LSB) 100 fDATA = 160MSPS 90 fDATA = 200MSPS –1 –2 –3 –4 –5 06452-005 SFDR (dBc) 0 80 70 fDATA = 250MSPS 60 –6 50 CODE fOUT (MHz) Figure 6. AD9779A Typical INL Figure 9. AD9779A In-Band SFDR vs. fOUT, 2× Interpolation 100 1.5 1.0 fDATA = 100MSPS 90 fDATA = 200MSPS 0.5 DNL (16-BIT LSB) 0 –0.5 –1.0 SFDR (dBc) 80 fDATA = 150MSPS 70 60 –1.5 –2.0 CODE fOUT (MHz) Figure 7. AD9779A Typical DNL Figure 10. AD9779A In-Band SFDR vs. fOUT, 4× Interpolation 100 100 fDATA = 50MSPS fDATA = 100MSPS 90 fDATA = 160MSPS fDATA = 250MSPS 90 SFDR (dBc) SFDR (dBc) 80 80 fDATA = 125MSPS 70 70 fDATA = 200MSPS 60 60 50 06452-007 fOUT (MHz) fOUT (MHz) Figure 8. AD9779A In-Band SFDR vs. fOUT, 1× Interpolation Figure 11. AD9779A In-Band SFDR vs. fOUT, 8× Interpolation Rev. B | Page 16 of 56 06452-010 0 20 40 60 80 100 50 0 10 20 30 40 50 06452-009 0 10k 20k 30k 40k 50k 60k 06452-006 50 0 20 40 60 80 100 06452-008 0 10k 20k 30k 40k 50k 60k 0 20 40 60 80 100 AD9776A/AD9778A/AD9779A 100 100 90 90 PLL OFF PLL ON fDATA = 160MSPS SFDR (dBc) 70 SFDR (dBc) 80 fDATA = 200MSPS 80 70 60 fDATA = 250MSPS 60 50 06452-011 fOUT (MHz) fOUT (MHz) Figure 12. AD9779A Out-of-Band SFDR vs. fOUT, 2× Interpolation 100 100 Figure 15. AD9779A In-Band SFDR vs. fOUT, 4× Interpolation, fDATA = 100 MSPS, PLL On/Off 0dBFS –3dBFS 90 90 SFDR (dBc) fDATA = 150MSPS 70 SFDR (dBc) 80 80 –6dBFS 70 fDATA = 100MSPS 60 fDATA = 200MSPS 60 50 06452-012 fOUT (MHz) fOUT (MHz) Figure 13. AD9779A Out-of-Band SFDR vs. fOUT, 4× Interpolation 100 100 Figure 16. AD9779A In-Band SFDR vs. fOUT, Digital Full Scale 10mA 90 90 20mA SFDR (dBc) fDATA = 100MSPS 70 SFDR (dBc) 80 fDATA = 50MSPS 80 70 30mA 60 fDATA = 125MSPS 60 50 06452-013 fOUT (MHz) fOUT (MHz) Figure 14. AD9779A Out-of-Band SFDR vs. fOUT, 8× Interpolation Figure 17. AD9779A In-Band SFDR vs. fOUT, Output Full-Scale Current Rev. B | Page 17 of 56 06452-016 0 10 20 30 40 50 50 0 20 40 60 80 06452-015 0 20 40 60 80 100 50 0 20 40 60 80 06452-014 0 20 40 60 80 100 50 0 10 20 30 40 AD9776A/AD9778A/AD9779A 100 100 fDATA = 160MSPS 90 fDATA = 200MSPS 90 IMD (dBc) IMD (dBc) 80 fDATA = 250MSPS 80 fDATA = 75MSPS 70 70 fDATA = 100MSPS 60 60 fDATA = 50MSPS fDATA = 125MSPS 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 200 400 06452-020 06452-022 06452-021 50 fOUT (MHz) 06452-017 0 20 40 60 80 100 120 50 0 fOUT (MHz) Figure 18. AD9779A Third-Order IMD vs. fOUT, 1× Interpolation 100 100 Figure 21. AD9779A Third-Order IMD vs. fOUT, 8× Interpolation fDATA = 160MSPS 90 90 IMD (dBc) IMD (dBc) 80 80 PLL OFF 70 PLL ON 70 fDATA = 200MSPS 60 fDATA = 250MSPS 60 50 06452-018 0 20 40 60 80 100 120 140 160 180 200 220 50 0 20 40 60 80 100 120 140 160 180 fOUT (MHz) fOUT (MHz) Figure 19. AD9779A Third-Order IMD vs. fOUT, 2× Interpolation 100 100 95 90 90 85 IMD (dBc) IMD (dBc) 80 80 75 70 65 60 Figure 22. AD9779A Third-Order IMD vs. fOUT, 4× Interpolation, fDATA = 100 MSPS, PLL On/Off fDATA = 150MSPS 70 fDATA = 100MSPS 60 fDATA = 200MSPS 50 0 40 80 120 160 200 240 280 320 360 400 55 50 06452-019 0 40 80 120 160 200 240 280 320 360 fOUT (MHz) fOUT (MHz) Figure 20. AD9779A Third-Order IMD vs. fOUT, 4× Interpolation Figure 23. AD9779A Third-Order IMD vs. fOUT, Over 50 Parts, 4× Interpolation, fDATA = 200 MSPS Rev. B | Page 18 of 56 AD9776A/AD9778A/AD9779A 100 95 90 85 IMD (dBc) REF 0dBm *PEAK Log 10dB 0dBFS –3dBFS *ATTEN 20dB EXT REF DC-COUPLED 80 75 70 65 60 55 50 0 40 80 120 160 200 240 280 320 360 400 –6dBFS LGAV 51 W1 S2 S3 FC AA £(f): FTUN SWP 06452-117 fOUT (MHz) START 1.0MHz *RES BW 20kHz VBW 20kHz STOP 400.0MHz SWEEP 1.203s (601 pts) Figure 24. AD9779A IMD Performance vs. fOUT, Digital Full-Scale Input Over Output Frequency, 4× Interpolation, fDATA = 200 MSPS 100 Figure 27. AD9779A Two-Tone Spectrum, 4× Interpolation, fDATA = 100 MSPS, fOUT = 30 MHz, 35 MHz –142 95 90 20mA 85 –146 –150 –3dBFS –154 0dBFS –158 –162 –166 –170 06452-118 IMD (dBc) 80 75 70 65 60 55 50 0 40 80 120 30mA NSD (dBm/Hz) 10mA –6dBFS fOUT (MHz) fOUT (MHz) Figure 25. AD9779A IMD Performance vs. fOUT, Full-Scale Output Current Over Output Frequency, 4× Interpolation, fDATA = 200 MSPS REF 0dBm *PEAK log 10dB *ATTEN 20dB Figure 28. AD9779A Noise Spectral Density vs. fOUT, Digital Full-Scale Over Output Frequency of Single-Tone Input, 2× Interpolation, fDATA = 200 MSPS –150 EXT REF DC-COUPLED –154 fDAC = 400MSPS NSD (dBm/Hz) –158 fDAC = 200MSPS LGAV 51 W1 S2 S3 FC AA £(f): FTUN SWP –162 fDAC = 800MSPS –166 06452-023 –170 START 1.0MHz *RES BW 20kHz VBW 20kHz STOP 400.0MHz SWEEP 1.203s (601 pts) fOUT (MHz) Figure 26. AD9779A Single Tone, 4× Interpolation, fDATA = 100 MSPS, fOUT = 30 MHz Figure 29. AD9779A Noise Spectral Density vs. fOUT, fDAC Over Output Frequency for Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS Rev. B | Page 19 of 56 06452-026 0 20 40 60 80 100 06452-025 160 200 240 280 320 360 400 0 20 40 60 80 06452-024 AD9776A/AD9778A/AD9779A –150 –55 –60 –154 –65 NSD (dBm/Hz) ACLR (dBc) –158 fDAC = 200MSPS fDAC = 400MSPS 0dBFS, PLL ENABLED –70 –75 –80 –85 0dBFS, PLL DISABLED –6dBFS, PLL DISABLED –162 fDAC = 800MSPS –166 –3dBFS, PLL DISABLED –170 06452-027 fOUT (MHz) fOUT (MHz) Figure 30. AD9779A Noise Spectral Density vs. fOUT, fDAC Over Output Frequency with a Single-Tone Input at −6 dBFS –55 –60 0dBFS, PLL ENABLED –65 ACLR (dBc) –70 –75 –3dBFS, PLL DISABLED –80 –6dBFS, PLL DISABLED –85 –90 Figure 33. AD9779A ACLR for Second Adjacent Band W-CDMA, 4× Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF –55 –60 –65 ACLR (dBc) 0dBFS, PLL DISABLED –70 –6dBFS, PLL DISABLED –75 –80 –85 –90 0dBFS, PLL DISABLED 0dBFS, PLL ENABLED –3dBFS, PLL DISABLED 06452-300 fOUT (MHz) fOUT (MHz) Figure 31. AD9779A ACLR for First Adjacent Band W-CDMA, 4× Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF REF –25.28dBm *AVG log 10dB *ATTEN 4dB Figure 34. AD9779A ACLR for Third Adjacent Band W-CDMA, 4× Interpolation, fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF REF –30.28dBm *AVG log 10dB *ATTEN 4dB EXT REF EXT REF PAVG 10 W1 S2 CENTER 143.88MHz *RES BW 30kHz VBW 300kHz SPAN 50MHz SWEEP 162.2ms (601 pts) 06452-031 PAVG 10 W1 S2 CENTER 151.38MHz *RES BW 30kHz VBW 300kHz SPAN 50MHz SWEEP 162.2ms (601 pts) LOWER dBm dBc –67.70 –85.57 –70.00 –97.87 –71.65 –99.52 UPPER dBm dBc –67.70 –85.57 –69.32 –87.19 –71.00 –88.88 RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz 10.00MHz –12.49dBm/ 15.00MHz 3.84000MHz 3.840MHz 3.840MHz 3.840MHz Figure 32. AD9779A W-CDMA Signal, 4× Interpolation, fDATA = 122.88 MSPS, fDAC/4 Modulation Rev. B | Page 20 of 56 Figure 35. AD9779A Multicarrier W-CDMA Signal, 4× Interpolation, fDAC = 122.88 MSPS, fDAC/4 Modulation 06452-032 LOWER dBm dBc –76.75 –89.23 –80.94 –93.43 –79.95 –92.44 UPPER dBm dBc –77.42 –89.91 –80.47 –92.96 –78.96 –91.45 TOTAL CARRIER POWER –12.61dBm/15.3600MHz REF CARRIER POWER –17.87dBm/3.84000MHz 1 –17.87dBm 2 –20.65dBm 3 –18.26dBm 4 –18.23dBm FREQ OFFSET 5.000MHz 10.00MHz 15.00MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz 06452-302 0 20 40 60 80 100 120 140 160 180 200 220 240 260 0 20 40 60 80 100 120 140 160 180 200 220 240 260 06452-301 0 20 40 60 80 100 –90 0 20 40 60 80 100 120 140 160 180 200 220 240 260 AD9776A/AD9778A/AD9779A 1.5 100 1.0 90 INL (14-BIT LSB) 0.5 fDATA = 160MSPS SFDR (dBc) 80 fDATA = 200MSPS 0 fDATA = 250MSPS 70 –0.5 –1.0 60 CODE fOUT (MHz) Figure 36. AD9778A Typical INL Figure 39. AD9778A In-Band SFDR vs. fOUT, 2× Interpolation 0.6 0.4 0.2 –60 DNL (14-BIT LSB) ACLR (dBc) 0 –0.2 –0.4 –70 THIRD ADJACENT CHANNEL –80 FIRST ADJACENT CHANNEL –0.6 –0.8 –1.0 –90 06452-034 SECOND ADJACENT CHANNEL 0 2k 4k 6k 8k CODE 10k 12k 14k 16k fOUT (MHz) Figure 37. AD9778A Typical DNL Figure 40. AD9778A ACLR, Single Carrier W-CDMA, 4× Interpolation, fDATA = 122.88 MSPS, Amplitude = −3 dBFS 100 REF –25.39dBm *AVG log 10dB *ATTEN 4dB 90 4× 150MSPS 80 IMD (dBc) 70 4× 100MSPS 60 4× 200MSPS PAVG 10 W1 S2 CENTER 143.88MHz *RES BW 30kHz 06452-035 50 0 40 80 120 160 200 240 280 320 360 400 VBW 300kHz SPAN 50MHz SWEEP 162.2ms (601 pts) 06452-038 fOUT (MHz) RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz –12.74dBm/ 10.00MHz 3.84000MHz 15.00MHz 3.884MHz 3.840MHz 3.840MHz LOWER dBc dBm –76.49 –89.23 –80.13 –92.87 –80.90 –93.64 UPPER dBc dBm –76.89 –89.63 –80.02 –92.76 –79.53 –92.27 Figure 38. AD9778A IMD vs. fOUT, 4× Interpolation Figure 41. AD9778A ACLR, fDATA = 122.88 MSPS, 4× Interpolation, fDAC/4 Modulation Rev. B | Page 21 of 56 06452-037 0 25 50 75 100 125 150 175 200 225 250 06452-036 0 2k 4k 6k 8k 10k 06452-033 –1.5 50 0 20 40 60 80 100 AD9776A/AD9778A/AD9779A –150 0.20 0.15 –154 0.10 DNL (12-BIT LSB) fDAC = 200MSPS NSD (dBm/Hz) –158 0.05 0 –0.05 –0.10 fDAC = 400MSPS –162 fDAC = 800MSPS –166 –0.15 06452-039 0 20 40 60 80 100 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 fOUT (MHz) Figure 42. AD9778A Noise Spectral Density vs. fOUT for Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS –150 100 95 Figure 45. AD9776A Typical DNL –154 90 fDAC = 200MSPS NSD (dBm/Hz) IMD (dBc) 85 –158 fDAC = 400MSPS 80 75 70 65 60 55 4× 150MSPS 0 40 80 120 160 200 240 280 320 360 400 4× 100MSPS 4× 200MSPS –162 fDAC = 800MSPS –166 –170 06452-040 fOUT (MHz) fOUT (MHz) Figure 43. AD9778A Noise Spectral Density vs. fOUT with Single-Tone Input at −6 dBFS, fDATA = 200 MSPS 100 Figure 46. AD9776A IMD vs. fOUT, 4× Interpolation 0.4 0.3 90 0.2 INL (12-BIT LSB) SFDR (dBc) 0.1 0 –0.1 –0.2 –0.3 –0.4 50 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 06452-041 fDATA = 160MSPS 80 70 fDATA = 250MSPS fDATA = 200MSPS 60 fOUT (MHz) Figure 44. AD9776A Typical INL Figure 47. AD9776A In-Band SFDR vs. fOUT, 2× Interpolation Rev. B | Page 22 of 56 06452-044 0 20 40 60 80 100 06452-043 0 20 40 60 80 100 50 06452-042 –170 –0.20 AD9776A/AD9778A/AD9779A –55 –60 –154 –65 NSD (dBm/Hz) –150 fDAC = 200MSPS fDAC = 400MSPS FIRST ADJACENT CHANNEL –158 THIRD ADJACENT CHANNEL ACLR (dBc) –70 –75 –80 –85 –90 fDAC = 800MSPS –162 SECOND ADJACENT CHANNEL –166 06452-045 FOUT (MHz) fOUT (MHz) Figure 48. AD9776A ACLR vs. fOUT, fDATA = 122.88 MSPS, 4× Interpolation, fDAC/4 Modulation REF –25.29dBm *AVG log 10dB *ATTEN 4dB Figure 50. AD9776A Noise Spectral Density vs. fOUT, Eight-Tone Input with 500 kHz Spacing, fDATA = 200 MSPS –150 fDAC = 200MSPS –154 fDAC = 400MSPS NSD (dBm/Hz) –158 fDAC = 800MSPS –162 PAVG 10 W1 S2 CENTER 143.88MHz *RES BW 30kHz VBW 300kHz SPAN 50MHz SWEEP 162.2ms (601 pts) 06452-046 –166 –170 RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz 10.00MHz –12.67dBm/ 15.00MHz 3.84000MHz 3.884MHz 3.840MHz 3.840MHz LOWER dBm dBc –75.00 –87.67 –78.05 –90.73 –77.73 –90.41 UPPER dBm dBc –75.30 –87.97 –77.99 –90.66 –77.50 –90.17 fOUT (MHz) Figure 49. AD9776A Single Carrier W-CDMA, 4× Interpolation, fDATA = 122.88 MSPS, Amplitude = −3 dBFS Figure 51. AD9776A Noise Spectral Density vs. fOUT, Single-Tone Input at −6 dBFS, fDATA = 200 MSPS Rev. B | Page 23 of 56 06452-048 0 10 20 30 40 50 60 70 80 90 100 06452-047 0 25 50 75 100 125 150 175 200 225 250 –170 0 10 20 30 40 50 60 70 80 90 100 AD9776A/AD9778A/AD9779A TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current at Code 0 from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error Gain error is the difference between the actual and the ideal output spans. The actual span is determined by the difference between the full-scale output and the bottom-scale output. Output Compliance Range Output compliance range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. In-Band Spurious-Free Dynamic Range (SFDR) In-band SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Out-of-Band Spurious-Free Dynamic Range (SFDR) Out-of-band SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the band that starts at the frequency of the input data rate and ends at the Nyquist frequency of the DAC output sample rate. Normally, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in dBc of the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. B | Page 24 of 56 AD9776A/AD9778A/AD9779A THEORY OF OPERATION The AD9776A/AD9778A/AD9779A have many features that make them highly suited for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common quadrature modulators when designing single sideband transmitters. The speed and performance of the parts allow wider bandwidths and more carriers to be synthesized than in previously available DACs. The digital engine uses an innovative filter architecture that combines the interpolation with a digital quadrature modulator. This allows the parts to perform digital quadrature frequency upconversions. The on-chip synchronization circuitry enables multiple devices to be synchronized to each other, or to a system clock. This means that the AD9776A/AD9778A/AD9779A PLL remains in lock in a given range over a wider temperature range than the AD9776/AD9778/AD9779. See Table 23 for PLL lock ranges for the AD9776A/AD9778A/AD9779A. PLL Optimal Settings The optimal settings for the AD9776/AD9778/AD9779 differ from the AD9776A/AD9778A/AD9779A. Refer to the PLL Bias Settings section for complete details. Input Data Delay Line, Manual and Automatic Correction Modes The AD9776A/AD9778A/AD9779A can be programmed to not only sense when the timing margin on the input data falls below a preset threshold but to also take action. The device can be programmed to either set the IRQ (pin and register) or automatically reoptimize the timing input data timing. DIFFERENCES BETWEEN AD9776/AD9778/ AD9779 AND AD9776A/AD9778A/AD9779A REFCLK Maximum Frequency vs. Supply With some restrictions on the DVDD18 and CVDD18 power supplies, the AD9776A/AD9778A/AD9779A support a maximum sample rate of 1100 MHz. Table 2 lists the valid operating frequencies vs. power supply voltage. Input Data Timing See Table 28 for timing specifications vs. temperature. The input data timing specifications (setup and hold) are different for the AD9776A/AD9778A/AD9779A than they are for the AD9776/AD9778/AD9779. REFCLK Amplitude With a differential sinusoidal clock applied to REFCLK, the PLL on the AD9776/AD9778/AD9779 does not achieve optimal noise performance unless the REFCLK differential amplitude is increased to 2 V p-p. Note that if an LVPECL driver is used on the AD9776/AD9778/AD9779, the PLL exhibits optimal performance if the REFCLK amplitude is well within LVPECL specifications (100 kΩ). The active output pin is chosen by writing to Bit 7 of Register 0x0E and Register 0x12. The active output can act as either a current source or a current sink. When sourcing current, the output compliance voltage is 0 V to 1.6 V. When sinking current, the output compliance voltage is 0.8 V to 1.6 V. The output pin is chosen to be a current source or current sink by writing to Bit 6 of Register 0x0E and Register 0x12. 0mA TO 2mA (SOURCE) VBIAS AUXP Gain mismatch: The gain in the real and imaginary signal paths of the quadrature modulator may not be matched perfectly. This leads to less than optimal image rejection because the cancellation of the negative frequency image is less than perfect. Local oscillator (LO) feedthrough: The quadrature modulator has a finite dc-referred offset, as well as coupling from its LO port to the signal inputs. These can lead to significant spectral spurs at the frequency of the quadrature modulator LO. • The AD9776A/AD9778A/AD9779A have the capability to correct for both of these analog degradations. Note that these degradations drift over temperature; therefore, if close to optimal single sideband performance is desired, a scheme for sensing these degradations over temperature and correcting for them may be necessary. 0mA TO 2mA (SINK) SOURCE/ SINC AUXN 06452-303 P/N Figure 78. Auxiliary DAC Source/Sink for AD9776A/AD9778A/AD97779A I/Q CHANNEL GAIN MATCHING Gain matching is achieved by adjusting the values in the DAC gain registers. For the I DAC, these values are in the 0x0B and 0x0C I DAC control registers. For the Q DAC, these values are in the 0x0F and 0x10 Q DAC control registers. These are 10-bit values. To perform gain compensation, raise or lower the value of one of these registers by a fixed step size and measure the amplitude of the unwanted image. If the unwanted image is increasing in amplitude, stop the procedure and try the same adjustment on the other DAC control register. Do this until the image rejection cannot be improved through further adjustment of these registers. It should be noted that LO feedthrough compensation is independent of gain. However, gain compensation can affect the LO compensation because the gain compensation may change the common-mode level of the signal. The dc offset of some modulators is common-mode level dependent. Therefore, it is recommended that the gain adjustment be performed prior to LO compensation. The magnitude of the auxiliary DAC1 current is controlled by the 0x0D and 0x0E auxiliary DAC1 control registers; the magnitude of the auxiliary DAC2 current is controlled by the 0x11 and 0x12 auxiliary DAC2 control registers. These auxiliary DACs have the ability to source or sink current. This is programmable via Bit 6 in either auxiliary DAC control register. The choice of sinking or sourcing should be made at circuit design time. There is no advantage to switching between current source or current sink once the circuit is in place. The auxiliary DACs can be used for LO cancellation when the DAC output is followed by a quadrature modulator. This LO feedthrough is caused by the input-referred dc offset voltage of the quadrature modulator (and the DAC output offset voltage mismatch) and may degrade system performance. Typical DAC-to-quadrature modulator interfaces are shown in Figure 79. Often, the input common-mode voltage for the modulator is much higher than the output compliance range of the DAC, making ac coupling or a dc level shift necessary. If the required common-mode input voltage on the quadrature modulator matches that of the DAC, then the dc shown in Figure 79 can be used. A low-pass or band-pass passive filter is recommended when spurious signals from the DAC (distortion and DAC images) at the quadrature modulator inputs may affect the system performance. Placing the filter at the location shown in Figure 79 allows easy design of the filter because the source and load impedances can easily be designed close to 50 Ω. AUXILIARY DAC OPERATION Two auxiliary DACs are provided on the AD9776A/AD9778A/ AD9779A. The full-scale output current on these DACs is derived from the 1.2 V band gap reference and external resistor between the I120 pin and ground. The gain scale from the reference amplifier current (IREFERENCE) to the auxiliary DAC reference current is 16.67 mA with the auxiliary DAC gain set to full Rev. B | Page 44 of 56 AD9776A/AD9778A/AD9779A 90 AUX1_P RESULTS OF GAIN AND OFFSET CORRECTION 250Ω LPI 390nH 39pF C2I LNI 390nH RSLI 100Ω 22 82pF C3I IBBN 21 AD9779A OUT1_P 500 Ω 93 RBIP 50Ω RBIN 92 50Ω 250Ω IBBP 82pF C1I OUT1_N AUX1_N 89 500 Ω The results of gain and offset correction can be seen in Figure 80 and Figure 81. Figure 80 shows the output spectrum of the quadrature demodulator before gain and offset correction. Figure 81 shows the output spectrum after correction. The LO feedthrough spur at 2.1 GHz has been suppressed to the noise level. This result can be achieved by applying the correction, but the correction needs to be repeated after a large change in temperature. Note that the gain matching improved the negative frequency image rejection, but there is still a significant image present. The remaining image is now due to phase mismatch in the quadrature modulator. Phase mismatch can be distinguished from gain mismatch by the shape of the image. Note that the image in Figure 80 is relatively flat and the image in Figure 81 slopes down with frequency. Phase mismatch is frequency dependent, so an image dominated by phase mismatch has this sloping characteristic. 0 REF LVL 0dBm RBW VBW SWT 3kHz 3kHz 56s REF ATT MIXER UNIT 30dB –40dBm dBm AUX2_N 87 500 Ω 250Ω LNQ 390nH OUT2_N 84 RBQN 50Ω RBQP 83 50Ω 250Ω 82pF C3Q 82pF C1Q 9 RSLQ 100Ω 10 QBBN 39pF C2Q LPQ 390nH OUT2_P QBBP 06452-093 AUX2_P 86 500 Ω Figure 79. Typical Use of Auxiliary DACs AC Coupling to Quadrature Modulator –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 2.1GHz 20MHz SPAN 200MHz 06452-304 06452-305 LO FEEDTHROUGH COMPENSATION The LO feedthrough compensation is the most complex of all three operations. This is due to the structure of the offset auxiliary DACs, as shown in Figure 78. To achieve LO feedthrough compensation in a circuit, each of four outputs of these auxiliary DACs can be connected through a 500 Ω resistor to ground and through a 250 Ω resistor to one of the four quadrature modulator signal inputs. The purpose of these connections is to drive a very small amount of current into the nodes at the quadrature modulator inputs, therefore adding a slight dc bias to one of the quadrature modulator signal inputs. To achieve LO feedthrough compensation, the user should start with the default conditions of the auxiliary DAC sign registers, and then increment the magnitude of one or the other auxiliary DAC output currents. While this is being done, the amplitude of the LO feedthrough at the quadrature modulator output should be sensed. If the LO feedthrough amplitude increases, try either changing the sign of the auxiliary DAC being adjusted or adjusting the output current of the other auxiliary DAC. It may take practice before an effective algorithm is achieved. Using the AD9776A/AD9778A/AD9779A evaluation board, the LO feedthrough can typically be adjusted down to the noise floor, although this is not stable over temperature. Figure 80. AD9779A and ADL5372 with a Multitone Signal at 2.1 GHz, No Gain or LO Compensation 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 REF LVL 0dBm RBW VBW SWT 20kHz 20kHz 1.25s REF ATT MIXER UNIT 20dB –40dBm dBm CENTER 2.1GHz 20MHz SPAN 200MHz Figure 81. AD9779A and ADL5372 with a Multitone Signal at 2.1 GHz, Gain and LO Compensation Optimized Rev. B | Page 45 of 56 AD9776A/AD9778A/AD9779A INPUT DATA PORTS The AD9776A/AD9778A/AD9779A can operate in two data input modes: dual port mode and single port mode. For the default dual port mode (single port bit = 0), each DAC receives data from a dedicated input port. In single port mode (single port bit = 1), both DACs receive data from Port 1. In single port mode, DAC1 and DAC2 data is interleaved, and the TXENABLE input is used to steer data to the intended DAC. In dual port mode, the TXENABLE input is used to power down the digital data path. In dual port mode, the data must be delivered at the input data rate. In single port mode, data must be delivered at twice the input data rate of each DAC. Because the data inputs function up to a maximum of 300 MSPS, it is practical to operate with input data rates up to 150 MHz per DAC in single port mode. In dual port and single port modes, a data clock output (DATACLK) signal is available as a fixed time base with which to drive data from an FPGA or other data source. This output signal operates at the input data rate. DUAL PORT MODE In dual port mode, data for each DAC is received on the respective input bus (P1D[15:0] or P2D[15:0]). I and Q data arrive simultaneously and are sampled on the rising edge of the DATACLK signal. The TXENABLE signal must be high to enable the transmit path. INPUT DATA REFERENCED TO DATACLK The simplest method of interfacing to the AD9776A/AD9778A/ AD9779A is when the input data is referenced to the DATACLK output. The DATACLK output is a buffered version (with some fixed delay) of the internal clock that is used to latch the input data. Therefore, if setup and hold times of the input data with respect to DATACLK are met, the input data is latched correctly. Detailed timing diagrams for the single and dual port cases using DATACLK as the timing reference are shown in Figure 82. DATACLK SINGLE PORT MODE In single port mode, data for both DACs is received on the Port 1 input bus (P1D[15:0]). I and Q data samples are interleaved and are sampled on the rising edges of DATACLK. Along with the data, a framing signal must be supplied on the TXENABLE input (Pin 39), which steers incoming data to its respective DAC. When TXENABLE is high, the corresponding data-word is sent to the I DAC. When TXENABLE is low, the corresponding data is sent to the Q DAC. The timing of the digital interface in interleaved mode is shown in Figure 83. The Q first bit (Register 0x02, Bit 0) controls the pairing order of the input data. With the Q first bit set to the default of 0, the I-Q pairing sent to the DACs is the two input data-words corresponding to TXENABLE low followed by TXENABLE high. With the Q first bit set to 1, the I-Q pairing sent to the DACs is the two input data-words corresponding to TXENABLE high, followed by TXENABLE low. Note that with either order pairing, the data sent with TXENABLE high is directed to the I DAC, and the data sent with TXENABLE low is directed to the Q DAC. DATACLK P1D[15:0] TXENABLE I DAC[15:0] Q FIRST = 0 Q DAC[15:0] I DAC[15:0] Q FIRST = 1 Q DAC[15:0] P1D0 P1D1 P1D2 P1D1 P1D1 P1D2 P1D3 P1D4 DATA Figure 82. Input Data Port Timing, Data Referenced to DATACLK Table 28 shows the setup and hold time requirements for the input data over the operating temperature range of the device. Also shown is the keep out window (KOW). The keep out window is the sum of the setup and hold times of the interface. This is the minimum amount of time valid data must be presented to the device to ensure proper sampling. DATACLK Frequency Settings The DATACLK signal is derived from the internal DAC sample clock, DACCLK. The frequency of the DATACLK output depends on several programmable settings. Normally, the frequency of DATACLK is equal to the input data rate. The relationship between the frequency of DACCLK and DATACLK is f DATACLK = f DACCLK IF × ZS × SP × DATACLKDIV where the variables IF, ZS, SP, and DATACLKDIV have the values shown in Table 27. P1D5 P1D6 P1D7 P1D8 P1D3 P1D4 P1D3 P1D2 P1D5 P1D6 06452-306 P1D5 P1D4 Figure 83. Single Port Mode Digital Interface Timing Rev. B | Page 46 of 56 06452-308 tSDATACLK tHDATACLK AD9776A/AD9778A/AD9779A The DATACLKDIV only affects the DATACLK output frequency, not the frequency of the data sampling clock. To maintain an fDATACLK frequency that samples the input data that remains consistent with the expected data rate, DATACLKDIV should be set to 00. Table 27. DACCLK to DATACLK Divisor Values Variable IF ZS SP DATACLKDIV Value Interpolation factor (1, 2, 4, or 8) 1, if zero stuffing is disabled 2, if zero stuffing is enabled 0.5, if single port is enabled 1, if dual port is selected 1, 2, or 4 Address Register Bit 0x01 [7:6] 0x01 0x02 0x03 [0] [6] [5:4] DATA SYNC_I tH_SYNC tS_SYNC REFCLK tSREFCLK Figure 84. Input Data Port Timing, Data Referenced to REFCLK, fDACCLK = fREFCLK INPUT DATA REFERENCED TO REFCLK In some systems, it may be more convenient to use the REFCLK input than the DATACLK output as the input data timing reference. If the frequency of DACCLK is equal to the frequency of the data input (without interpolation), then the data with respect to REFCLK± timing specifications in Table 28 apply directly without further considerations. If the frequency of DACCLK is greater than the frequency of the input data, a divider is used to generate the DATACLK output (and the internal data sampling clock). This divider creates a phase ambiguity between REFCLK and DATACLK, which results in uncertainty in the sampling time. To establish fixed setup and hold times of the data interface, this phase ambiguity must be eliminated. To eliminate the phase ambiguity, the SYNC_I input pins (Pin 13 and Pin 14) must be used to force the data to be sampled on a specific REFCLK edge. The relationship among REFCLK, SYNC_I, and input data is shown in Figure 84 and Figure 85. Therefore, both SYNC_I and data must meet the timing in Table 28 for reliable data transfer into the device. Note that even though the setup and hold times of SYNC_I are relative to REFCLK, the SYNC_I input is sampled at the internal DACCLK rate. In the case where the PLL is employed, SYNC_I must be asserted to meet the setup time with respect to REFCLK (tS_SYNC), but cannot be asserted prior to the previous rising edge of the internal SYNC_I sample clock. In other words, the SYNC_I assert edge has to be placed between its successive keep out windows that replicate at the DACCLK rate, not the REFCLK rate. The valid window for asserting SYNC_I is shaded gray in Figure 85 for the case where the PLL provides a DACCLK frequency of four times the REFCLK frequency. Thus, the minimum setup time is tS_SYNC, and the maximum setup time is tDACCLK − tH_SYNC. tDACCLK SYNC_I tH_SYNC tS_SYNC REFCLK DACCLK tSREFCLK DATA Figure 85. Input Data Port Timing, Data Referenced to REFCLK, fDACCLK = fREFCLK × 4 More details of the synchronization circuitry are found in the Device Synchronization section of this data sheet. Table 28. Data Timing Specifications vs. Temperature Timing Parameter Data with Respect to REFCLK± Temperature −40°C +25°C +85°C −40°C to +85°C −40°C +25°C +85°C −40°C to +85°C −40°C +25°C +85°C −40°C to +85°C Min tS (ns) −0.80 −1.00 −1.10 −0.80 2.50 2.70 3.00 3.00 0.30 0.25 0.15 0.30 PLL Disabled Min tH (ns) Min KOW (ns) 3.35 2.55 3.50 2.50 3.80 2.70 3.80 3.00 −0.05 2.45 −0.20 2.50 −0.40 2.60 −0.05 2.95 0.65 0.95 0.75 1.00 0.90 1.05 0.90 1.20 Min tS (ns) −0.83 −1.06 −1.19 −0.83 2.50 2.70 3.00 3.00 0.27 0.19 0.06 0.27 PLL Enabled Min tH (ns) Min KOW (ns) 3.87 2.99 4.04 2.98 4.37 3.16 4.37 3.54 −0.05 2.45 −0.20 2.50 −0.40 2.60 −0.05 2.95 1.17 1.39 1.29 1.48 1.47 1.51 1.47 1.74 Data with Respect to DATACLK SYNC_I± to REFCLK± Rev. B | Page 47 of 56 06452-310 tHREFCLK 06452-309 tHREFCLK AD9776A/AD9778A/AD9779A OPTIMIZING THE DATA INPUT TIMING The AD9776A/AD9778A/AD9779A have on-chip circuitry that enables the user to optimize the input data timing by adjusting the relationship between the DATACLK output and DCLK_SMP (the internal clock that samples the input data). This optimization is made by a sequence of 3-wire interface register read and write operations. The timing optimization can be done under strict control of the user, or the device can be programmed to maintain a configurable timing margin automatically. This function is only available when the input data is referenced to the DATACLK output. Each of these methods is detailed in the following section. Figure 86 shows the circuitry that detects sample timing errors and adjusts the data interface timing. The DCLK_SMP signal is the internal clock used to latch the input data. Ultimately, it is the rising edge of this signal that needs to be centered in the valid sampling period of the input data. This is accomplished by adjusting the time delay, tD, which changes the DATACLK timing and, as a result, the arrival time of the input data with respect to DCLK_SMP. ΔtM TIMING MARGIN[3:0] PD1[0] D CLK Q TIMING ERROR DETECTION Q TIMING ERROR IRQ TIMING ERROR TYPE In addition to setting the data timing error IRQ, the data timing error type bit is indicated when an error occurs. The data timing error type bit is set low to indicate a hold error and high to indicate a setup error. Figure 87 shows a timing diagram of the data interface and the status of the data timing error type bit. DATA TIMING ERROR = 0 ΔtM Δt M DATA ΔtM DATA TIMING ERROR = 1 DATA TIMING ERROR TYPE = 0 DELAYED CLOCK SAMPLING Δt M TIMING ERROR = 1 DATA TIMING ERROR TYPE = 1 ΔtM DELAYED DATA SAMPLING Δt M Figure 87. Timing Diagram of Margin Test Data Automatic Timing Optimization When automatic timing optimization mode is enabled (Register 0x03, Bit 7 = 1), the device continuously monitors the data timing error IRQ and data timing error type bits. The DATACLK Delay[3:0] is increased if a setup error is detected and decreased if a hold error is detected. The value of the DATACLK Delay[3:0] setting currently in use can be read back by the user. 06452-402 D ΔtM CLK DATACLK DELAY[3:0] DCLK_SMP ΔtD DATACLK Manual Timing Optimization When the device is operating in manual timing optimization mode (Register 0x03, Bit 7 = 0), the device does not alter the DATACLK Delay[3:0] value from what is programmed by the user. By default, the DATACLK delay enable bit is inactive. This bit must be set high for the DATACLK Delay[3:0] value to be realized. The delay (in absolute time) when programming DATACLK delay between 00000 and 11111 varies from about 700 ps to about 6.5 ns. The typical delays per increment over temperature are shown in Table 29. Table 29. Data Delay Line Typical Delays Over Temperature Delay Zero Code Delay (Delay Upon Enabling Delay Line) Average Unit Delay −40°C 630 175 +25°C 700 190 +85°C 740 210 Unit ps ps Figure 86. Timing Error Detection and Optimization Circuitry The error detect circuitry works by creating two sets of sampled data (referred to as the margin test data) in addition to the actual sampled data used in the device data path. One set of sampled data is latched before the actual data sampling point. The other set of sampled data is latched after the actual data sampling point. If the margin test data match the actual data, the sampling is considered valid and no error is declared. If there is a mismatch between the actual data and the margin test data, an error is declared. The Data Timing Margin[3:0] variable determines how much before and after the actual data sampling point the margin test data are latched. Therefore, the data timing margin variable determines how much setup and hold margin the interface needs for the data timing error IRQ to remain inactive (show error free operation). Therefore, the timing error IRQ is set whenever the setup and hold margins drop below the Data Timing Margin[3:0] value and does not necessarily indicate that the data latched into the device is incorrect. When the device is placed into manual mode, the error checking logic is activated. If the IRQs are enabled, an interrupt is generated if a setup/hold violation is detected. One error check operation is performed per device configuration. Any change to the Data Timing Margin[3:0] or DATACLK Delay[3:0] values triggers a new error check operation. Rev. B | Page 48 of 56 06452-403 ACTUAL SAMPLING INSTANT AD9776A/AD9778A/AD9779A DEVICE SYNCHRONIZATION System demands can impose two different requirements for synchronization. Some systems require multiple DACs to be synchronized to each other. This is the case when supporting transmit diversity or beam forming, where multiple antennas are used to transmit a correlated signal. In this case, the DAC outputs need to be phase aligned with each other, but there may not be a requirement for the DAC outputs to be aligned with a system level reference clock. In systems with a time division multiplexing transmit chain, one or more DACs may need to be synchronized with a system level reference clock. The options for synchronizing devices under these two conditions are described in the Synchronization Logic Overview section and the Synchronizing Devices to a System Clock section. multiple of 32 DACCLK periods. In any case, the maximum frequency of SYNC_I must be less than fDATACLK. Table 30. Settings Required to Support Various SYNC_I Frequencies SYNC_I Ratio[2:0] 000 001 010 011 100 101 110 111 SYNC_I Rising Edges Required for Synchronization Pulse 1 (default) 2 4 8 16 Invalid setting Invalid setting Invalid setting SYNCHRONIZATION LOGIC OVERVIEW Figure 88 shows the block diagram of the on-chip synchronization logic. The basic operation of the synchronization logic is to generate a single DACCLK-cycle-wide initialization pulse that sets the clock generation state machine logic to a known state. This initialization pulse loads the clock generation state machine with the Clock State[4:0] value as its next state. If the initialization pulse from the synchronization logic is generated properly, it is active for one DACCLK cycle, every 32 DACCLK cycles. Because the clock generation state machine has 32 states operating at the DACCLK rate, every initialization pulse received after the first pulse loads the state in which the state machine is already in, maintaining proper clocking operation of the device. PLL BYPASS INTERNAL PLL DACCLK CLOCK GENERATION STATE MACHINE BIT 0 (1× INTERPOLATION) BIT 1 (2×) BIT 2 (4×) BIT 3 (8×) BIT 4 (8× WITH ZERO STUFFING) REFCLK As an example, if a SYNC_I signal with a frequency of fDACCLK/4 is used, then both 011 and 100 are valid settings for the SYNC_I Ratio[2:0] value. A setting of 011 results in one initialization pulse being generated every 32 DACCLK cycles, and a setting of 100 results in one initialization pulse being generated every 64 DACCLK cycles. Both cases result in proper device synchronization. The Clock State[4:0] value is the state to which the clock generation state machine resets upon initialization. By varying this value, the timing of the internal clocks with respect to the SYNC_I signal can be adjusted. Every increment of the Clock State[4:0] value advances the internal clocks by one DACCLK period. Synchronization Timing Error Detection MUX LOAD DACCLK OFFSET VALUE (REG 0x07, BITS[4:0]), ONE DACCLK CYCLE/INCREMENT SYNC_I SYNC DELAY DELAY REGISTER (REG 0x0, BITS[7:4]) ERROR DETECT CIRCUITRY SYNC IRQ Figure 88. Synchronization Circuitry Block Diagram Nominally, the SYNC_I input should have one rising edge every 32 clock cycles (or multiple of 32 clock cycles) to maintain proper synchronization. The pulse generation logic can be programmed to suppress outgoing pulses if the incoming SYNC_I frequency is greater than DACCLK/32. Extra pulses can be suppressed by the ratios listed in Table 30. The SYNC_I frequency can be lower than DACCLK/32 as long as output pulses are generated from the pulse generation circuit on a Rev. B | Page 49 of 56 06452-094 fSYNC_1 < fDATA/2^N PULSE GENERATION LOGIC The synchronization logic has error detection circuitry similar to the input data timing. The SYNC_I Timing Margin[3:0] variable determines how much setup and hold margin the synchronization interface needs for the sync timing error IRQ bit to remain inactive (that is, to indicate error free operation). Therefore, the sync timing error IRQ bit is set whenever the setup and hold margins drop below the SYNC_I Timing Margin[3:0] value and, therefore, does not necessarily indicate that the SYNC_I input was latched incorrectly. When the sync timing error IRQ bit is set, corrective action can be taken to restore timing margin. One course of action is to temporarily reduce the timing margin until the sync timing error IRQ is cleared. Then, increase the SYNC_I delay by two increments and check whether the timing margin has increased or decreased. If it has increased, continue incrementing the value of SYNC_I delay until the margin is maximized. However, if incrementing the SYNC_I delay reduced the timing margin, then the delay should be reduced until the timing margin is optimized. AD9776A/AD9778A/AD9779A SYNCHRONIZING DEVICES TO A SYSTEM CLOCK The AD9776A/AD9778A/AD9779A offer a pulse mode synchronization scheme (see Figure 89) to align the DAC outputs of multiple devices within a system to the same DACCLK edge. The internal clocks are synchronized by providing either a onetime pulse or a periodic signal to the SYNC_I inputs (SYNC_I+, SYNC_I−). The SYNC_I signal is sampled by the internal DACCLK sample rate clock. The SYNC_I input frequency has the following constraint: fSYNC_I ≤ fDATA When the internal clocks are synchronized, the data-sampling clocks between all devices are phase aligned. The data input timing relationships can be referenced to either REFCLK or DATACLK. For this synchronization scheme, all devices are slave devices, and the system clock generation/distribution chip serves as the master. It is vital that the SYNC_I signal be distributed between the DACs with low skew. Likewise, the REFCLK signals must be distributed with low skew. Any skew on these signals between the DACs must be accounted for in the timing budget. Figure 89 shows an example clock and synchronization input scheme. Figure 90 shows the timing of the SYNC_I input with respect to the REFCLK input. Note that although the timing is relative to the REFCLK signal, SYNC_I is sampled at the DACCLK rate. This means that the rising edge of the SYNC_I signal must occur after the hold time of the preceding DACCLK rising edge, not the preceding REFCLK rising edge. INTERRUPT REQUEST OPERATION The IRQ pin (Pin 71) acts as an alert in the event that the device has a timing error and should be queried (by reading Register 0x19) to determine the exact fault condition. The IRQ pin is an open-drain, active low output. The IRQ pin should be pulled high external to the device. This pin can be tied to the IRQ pins of other devices with open-drain outputs to wire-OR these pins together. There are two different error flags that can trigger an interrupt request: a data timing error flag or a sync timing error flag. By default, when either or both of these error flags are set, the IRQ pin is active low. Either or both of these error flags can be masked to prevent them from activating an interrupt on the IRQ pin. The error flags are latched and remain active until the interrupt register, Register 0x19, is either read from or the error flag bits are overwritten. MATCHED LENGTH TRACES REFCLK OUT SYNC_I SYSTEM CLOCK LOW SKEW CLOCK DRIVER REFCLK OUT SYNC_I PULSE GENERATOR LOW SKEW CLOCK DRIVER MATCHED LENGTH TRACES Figure 89. Multichip Synchronization in Pulse Mode SYNC_I tH_SYNC REFCLK tS_SYNC DACCLK Figure 90. Timing Diagram of SYNC_I with Respect to REFCLK When Synchronizing Multiple Devices to Each Other Rev. B | Page 50 of 56 06452-312 06452-311 AD9776A/AD9778A/AD9779A POWER DISSIPATION Figure 91 to Figure 99 show the power dissipation of the 1.8 V and 3.3 V digital and clock supplies in single DAC mode and dual DAC mode. In addition to this, the power dissipation/current of the 3.3 V analog supply (mode and speed independent) in single DAC mode is 102 mW/31 mA. In dual DAC mode, this is 182 mW/55 mA. When the PLL is enabled, it adds 50 mA/90 mW to the 1.8 V clock supply. 0.7 8× INTERPOLATION 0.075 0.6 0.5 POWER (W) 8× INTERPOLATION, ZERO STUFFING 4× INTERPOLATION 4× INTERPOLATION, ZERO STUFFING 0.050 0.4 0.3 0.2 1× INTERPOLATION 2× INTERPOLATION, ZERO STUFFING 2× INTERPOLATION 1× INTERPOLATION, ZERO STUFFING ALL INTERPOLATION MODES 0.1 0 0 06452-076 fDATA (MSPS) fDATA (MSPS) Figure 91. Total Power Dissipation, I Data Only, Real Mode 0.4 Figure 94. Power Dissipation, Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation Modes and Zero Stuffing 1.0 0.9 8× INTERPOLATION, ZERO STUFFING 8× INTERPOLATION, ALL MODULATION MODES 4× INTERPOLATION, ALL MODULATION MODES 8× INTERPOLATION 0.3 4× INTERPOLATION 0.8 0.7 POWER (W) 0.2 2× INTERPOLATION POWER (W) 0.6 0.5 0.4 0.3 2× INTERPOLATION, ALL MODULATION MODES 0.1 1× INTERPOLATION 0.2 0.1 4× INTERPOLATION, ZERO STUFFING 2× INTERPOLATION, ZERO STUFFING 1× INTERPOLATION, ZERO STUFFING 1× INTERPOLATION 0 06452-078 fDATA (MSPS) fDATA (MSPS) Figure 92. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode, Does Not Include Zero Stuffing 0.08 0.8 0.7 Figure 95. Total Power Dissipation, Dual DAC Mode 8× INTERPOLATION, fDAC /8, fDAC /4, fDAC /2, NO MODULATION 4× INTERPOLATION 0.06 0.6 8× INTERPOLATION 4× INTERPOLATION POWER (W) POWER (W) 0.5 0.4 0.3 0.2 0.04 2× INTERPOLATION 2× INTERPOLATION 0.02 1× INTERPOLATION 0.1 0 06452-079 1× INTERPOLATION, NO MODULATION 0 fDATA (MSPS) fDATA (MSPS) Figure 93. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode, Includes Modulation Modes, Does Not Include Zero Stuffing Figure 96. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC Mode, Does Not Include Zero Stuffing Rev. B | Page 51 of 56 06452-081 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 06452-077 0 25 50 75 100 125 150 175 200 225 250 0 0 25 50 75 100 125 150 175 200 225 250 275 300 06452-080 0 POWER (W) 0.025 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 AD9776A/AD9778A/AD9779A 0.125 8× INTERPOLATION, fDAC /8, fDAC /4, fDAC /2, NO MODULATION 0.100 POWER-DOWN AND SLEEP MODES 4× INTERPOLATION POWER (W) 0.075 2× INTERPOLATION 0.050 0.025 1× INTERPOLATION, NO MODULATION 06452-082 0 0 25 50 75 100 125 150 175 200 225 250 fDATA (MSPS) Figure 97. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC Mode, Does Not Include Zero Stuffing 0.075 The AD9776A/AD9778A/AD9779A have a variety of power-down modes; thus, the digital engine, main TxDACs, or auxiliary DACs can be powered down individually or together. Via the 3-wire interface port, the main TxDACs can be placed in sleep or powerdown mode. In sleep mode, the TxDAC output is turned off, thus reducing power dissipation. The reference remains powered on, however, so that recovery from sleep mode is very fast. With the power-down mode bit set (Register 0x00, Bit 4), all analog and digital circuitry, including the reference, is powered down. The 3-wire interface port remains active in this mode. This mode offers more substantial power savings than sleep mode, but the turn-on time is much longer. The auxiliary DACs also have the capability to be programmed into sleep mode via the 3-wire interface port. The auto power-down enable bit (Register 0x00, Bit 3) controls the power-down function for the digital section of the devices. The auto power-down function works in conjunction with the TXENABLE pin (Pin 39); see Table 31 for details. Table 31. 0.050 POWER (W) ALL INTERPOLATION MODES TXENABLE (Pin 39) 0 0.025 0 1 fDATA (MSPS) 06452-083 Description If auto power-down enable bit = 0, flush data path with 0s. If auto power-down enable bit = 1, flush data for multiple REFCLK cycles; then, automatically place the digital engine in power-down state. DACs, reference, and 3-wire interface port are not affected. Normal operation. 0 25 50 75 100 125 150 175 200 225 250 Figure 98. Power Dissipation, Digital 3.3 V Supply, I and Q Data, Dual DAC Mode 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 POWER (W) fDAC (MSPS) Figure 99. DVDD18 Power Dissipation of Inverse Sinc Filter Rev. B | Page 52 of 56 06452-084 0 200 400 600 800 1000 1200 AD9776A/AD9778A/AD9779A EVALUATION BOARD OVERVIEW EVALUATION BOARD OPERATION The AD9776A/AD9778A/AD9779A evaluation board is provided to help users quickly become familiar with the operation of the device and to evaluate the device performance. To operate the evaluation board, the user needs a PC, a 5 V power supply, a clock source, and a digital data source. The user also needs a spectrum analyzer or an oscilloscope to observe the DAC output. The typical evaluation setup is shown in Figure 100. A sine or square wave clock can be used to source the DAC sample clock. The spectral purity of the clock directly affects the device performance. A low noise, low jitter clock source is required. All necessary connections to the evaluation board are shown in more detail in Figure 101. CLOCK GENERATOR ADAPTER CABLES CLKIN SPI PORT SPECTRUM ANALYZER DIGITAL PATTERN GENERATOR CLOCK IN DATACLK OUT AD9776A/ AD9778A/ AD9779A EVALUATION BOARD 1.8V POWER SUPPLY 3.3V POWER SUPPLY 06452-097 06452-095 Figure 100. Typical Test Setup DVDD18 DVDD33 CVDD18 AVDD33 J2 5V SUPPLY P4 DIGITAL INPUT CONNECTOR J1 CLOCK IN JP4 JP15 JP8 JP14 JP3 JP16 JP2 JP17 MODULATOR OUTPUT S5 OUTPUT 1 ADL537x +5V GND AD9779A S7 DCLKOUT S6 OUTPUT 2 LOCAL OSC INPUT ANALOG DEVICES AD9776A/ AD9778A/ AD9779A SPI PORT Figure 101. AD9776A/AD9778A/AD9779A Evaluation Board Showing All Connections Rev. B | Page 53 of 56 AD9776A/AD9778A/AD9779A The evaluation board comes with software that allows the user to program the on-chip configuration registers. Via the 3-wire interface port, the devices can be programmed into any of its various operating modes. The default software window is shown in Figure 102. 1. SET INTERPOLATION RATE 2. SET INTERPOLATION FILTER MODE 3. SET INPUT DATA FORMAT 4. SET DATACLK POLARITY TO MATCH INPUT TIMING The evaluation board also comes populated with the ADL537x modulator to allow for the evaluation of an RF subsystem. Complete details on the evaluation board and the 3-wire interface software can be downloaded from the Analog Devices website. Figure 102. 3-Wire Interface Port Software Window Rev. B | Page 54 of 56 06452-099 AD9776A/AD9778A/AD9779A OUTLINE DIMENSIONS 0.75 0.60 0.45 SEATING PLANE 1.20 MAX 100 1 PIN 1 16.00 BSC SQ 14.00 BSC SQ 76 75 76 75 100 1 BOTTOM VIEW (PINS UP) TOP VIEW (PINS DOWN) CONDUCTIVE HEAT SINK 25 26 51 50 51 50 26 25 0.20 0.09 7° 3.5° 0° 1.05 1.00 0.95 6.50 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.50 BSC 0.27 0.22 0.17 0.15 0.05 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MS-026-AED-HDT Figure 103. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-1) Dimensions shown in millimeters ORDERING GUIDE Model AD9776ABSVZ 1 AD9776ABSVZRL1 AD9778ABSVZ1 AD9778ABSVZRL1 AD9779ABSVZ1 AD9779ABSVZRL1 AD9776A-EBZ1 AD9778A-EBZ1 AD9779A-EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Evaluation Board Evaluation Board Evaluation Board Package Option SV-100-1 SV-100-1 SV-100-1 SV-100-1 SV-100-1 SV-100-1 Z = RoHS Compliant Part. Rev. B | Page 55 of 56 072408-A AD9776A/AD9778A/AD9779A NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06452-0-9/08(B) Rev. B | Page 56 of 56