FEATURES
PIN CONNECTION DIAGRAM
Rail-to-rail input/output
Low power: 0.625 mA typical per amplifier at ±15 V
Gain bandwidth product: 15.9 MHz at AV = 100 typical
Unity-gain crossover: 9.9 MHz typical
−3 dB closed-loop bandwidth: 13.9 MHz typical at ±15 V
Low offset voltage: 100 µV maximum (SOIC)
Unity-gain stable
High slew rate: 4.6 V/µs typical
Low noise: 3.9 nV/√Hz typical at 1 kHz
Long-term offset voltage drift (10,000 hours): 3 µV typical
Temperature hysteresis: 4 µV typical
ADA4084-2
OUT A 1
8 V+
–IN A 2
7 OUT B
+IN A 3
6 –IN B
V– 4
5 +IN B
NOTES
1. FOR THE LFCSP PACKAGE,
THE EXPOSED PAD MUST BE
CONNECTED TO V–.
08237-001
Data Sheet
30 V, Low Noise, Rail-to-Rail Input/Output,
Low Power Operational Amplifiers
ADA4084-1/ADA4084-2/ADA4084-4
Figure 1. ADA4084-2, 8-Lead LFCSP (CP); for Additional Packages and
Models, See the Pin Configurations and Function Descriptions Section
APPLICATIONS
Battery-powered instrumentation
High-side and low-side sensing
Power supply control and protection
Telecommunications
Digital-to-analog converter (DAC) output amplifiers
Analog-to-digital converter (ADC) input buffers
GENERAL DESCRIPTION
The ADA4084-1 (single), ADA4084-2 (dual), and ADA4084-4
(quad) are single-supply, 10 MHz bandwidth amplifiers featuring
rail-to-rail inputs and outputs. They are guaranteed to operate
from +3 V to +30 V (or ±1.5 V to ±15 V).
These amplifiers are well suited for single-supply applications
requiring both ac and precision dc performance. The combination
of wide bandwidth, low noise, and precision makes the
ADA4084-1/ADA4084-2/ADA4084-4 useful in a wide variety of
applications, including filters and instrumentation.
Other applications for these amplifiers include portable telecommunications equipment, power supply control and protection, and
use as amplifiers or buffers for transducers with wide output
ranges. Sensors requiring a rail-to-rail input amplifier include
Hall effect, piezoelectric, and resistive transducers.
The ability to swing rail to rail at both the input and output
enables designers to build multistage filters in single-supply
systems and to maintain high signal-to-noise ratios.
The single ADA4084-1 is available in the 5-lead SOT-23 and
8-lead SOIC; the dual ADA4084-2 is available in the 8-lead
SOIC, 8-lead MSOP, and 8-lead LFCSP surface-mount
packages; and the ADA4084-4 is offered in the 14-lead TSSOP
and 16-lead LFCSP.
The ADA4084-1/ADA4084-2/ADA4084-4 are members of a
growing series of high voltage, low noise op amps offered by
Analog Devices, Inc. (see Table 1).
Table 1. Low Noise Op Amps
Single
AD8597
ADA4004-1
AD8675
AD8671
OP27, OP37
ADA4084-1
Dual
AD8599
ADA4004-2
AD8676
AD8672
Quad
ADA4004-4
ADA4084-2
ADA4084-4
AD8674
Voltage Noise
1.1 nV/Hz
1.8 nV/Hz
2.8 nV/Hz rail-to-rail output
2.8 nV/Hz
3.2 nV/Hz
3.9 nV/Hz rail-to-rail
input/output
The ADA4084-1/ADA4084-2/ADA4084-4 are specified over
the industrial temperature range of −40°C to +125°C.
Rev. I
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ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
±5 V Characteristics................................................................... 17
Applications ....................................................................................... 1
±15 V Characteristics ................................................................ 23
Pin Connection Diagram ................................................................ 1
Applications Information .............................................................. 29
General Description ......................................................................... 1
Functional Description .............................................................. 29
Revision History ............................................................................... 2
Start-Up Characteristics ............................................................ 30
Specifications..................................................................................... 4
Input Protection ......................................................................... 30
Electrical Characteristics ............................................................. 4
Output Phase Reversal ............................................................... 30
Absolute Maximum Ratings............................................................ 7
Designing Low Noise Circuits in Single-Supply Applications .. 31
Thermal Resistance ...................................................................... 7
Comparator Operation .............................................................. 31
ESD Caution .................................................................................. 7
Long-Term Drift ......................................................................... 32
Pin Configurations and Function Descriptions ........................... 8
Temperature Hysteresis ............................................................. 32
Typical Performance Characteristics ........................................... 11
Outline Dimensions ....................................................................... 33
±1.5 V Characteristics................................................................ 11
Ordering Guide .......................................................................... 36
REVISION HISTORY
5/2017—Rev. H to Rev. I
Changed CP-8-12 to CP-8-11 ...................................... Throughout
Changed CP-16-26 to CP-16-17 .................................. Throughout
Changes to Features Section............................................................ 1
Added Long-Term Drift Section, Temperature Hysteresis
Section, Figure 112, Figure 113, and Figure 114; Renumbered
Sequentially ..................................................................................... 32
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 36
8/2015—Rev. G to Rev. H
Added 5-Lead SOT-23 ....................................................... Universal
Changes to Pin Connection Diagram Section, Figure 1, and
General Description Section ........................................................... 1
Deleted Figure 3; Renumbered Sequentially................................. 1
Changes to Large Signal Voltage Gain Parameter, Table 2 .......... 4
Changes to Large Signal Voltage Gain Parameter, Table 3 .......... 5
Changes to Large Signal Voltage Gain Parameter, Table 4 .......... 6
Changes to Table 6 ............................................................................ 7
Moved Figure 3 ................................................................................. 8
Added Pin Configurations and Function Descriptions Section,
Figure 4, Figure 5, Table 7, Table 8, and Table 9; Renumbered
Sequentially ....................................................................................... 8
Added Figure 6, Figure 7, Figure 8, Table 10, and Table 11 ........ 9
Moved Figure 9 ............................................................................... 10
Added Table 12 ............................................................................... 10
Added Figure 11 and Figure 15..................................................... 11
Added Figure 42 and Figure 46..................................................... 17
Added Figure 73 and Figure 77..................................................... 23
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 35
6/2015—Rev. F to Rev. G
Changes to Figure 96 and Figure 97............................................. 24
1/2015—Rev. E to Rev. F
Moved Revision History ...................................................................3
Changes to Table 5.............................................................................7
Changes to Ordering Guide .......................................................... 29
7/2014—Rev. D to Rev. E
Added ADA4084-1 ............................................................. Universal
Added Figure 1; Renumbered Sequentially ...................................1
Changes to Output Voltage High Parameter, Table 2 ...................3
Changes to Current Noise Density Parameter, Table 3 ................4
Changes to Current Noise Density Parameter, Table 4 ................5
Changes to Figure 8 Caption, and Figure 9 to Figure 11 .............7
Changes to Figure 13.........................................................................8
Changes to Figure 21.........................................................................9
Added Figure 31; Renumbered Sequentially .............................. 11
Changes to Figure 30 Caption, and Figure 32 to Figure 34 ...... 11
Changes to Figure 36 Caption to Figure 39 Caption ................. 12
Changes to Figure 50...................................................................... 14
Added Figure 60 ............................................................................. 16
Changes to Figure 59 Caption, Figure 62, and Figure 63 .......... 16
Changes to Figure 65 Caption to Figure 68 Caption ................. 17
Changes to Figure 79...................................................................... 19
Added Figure 89 ............................................................................. 21
Changes to Figure 88 Caption, Figure 91 Caption, and
Figure 92 Caption ........................................................................... 21
Changes to Ordering Guide .......................................................... 28
Rev. I | Page 2 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
11/2013—Rev. C to Rev. D
Added 14-Lead TSSOP and 16-Lead LFCSP Packages ....... Universal
Added ADA4084-4..................................................................... Universal
Change to Features Section and Applications Section ................. 1
Added Figure 2 and Figure 3; Renumbered Sequentially ............ 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4 ............................................................................ 5
Changes to Table 5 and Table 6 ....................................................... 6
Changes to Typical Performance Characteristics Section ........... 7
Updated Outline Dimensions ........................................................27
Changes to Ordering Guide ...........................................................28
4/2013—Rev. B to Rev. C
Changes to Figure 48 Caption .......................................................15
Updated Outline Dimensions ........................................................25
6/2012—Rev. A to Rev. B
Added LFCSP Package....................................................... Universal
Changes to Figure 1........................................................................... 1
Changes to Output Voltage High Parameter, Table 4 ................... 5
Added Figure 5 and Figure 7, Renumbered Sequentially ............ 7
Added Figure 30 and Figure 32 .....................................................12
Added Figure 55 and Figure 57 ..................................................... 17
Added Startup Characteristics Section ........................................ 23
Moved Figure 78 .............................................................................. 23
Changes to Output Phase Reversal Section and Comparator
Operation Section ........................................................................... 24
Updated Outline Dimensions........................................................ 25
Changes to Ordering Guide ........................................................... 26
2/2012—Rev. 0 to Rev. A
Changes to Data Sheet Title ............................................................. 1
Changes to Voltage Range in General Description ...................... 1
Changes to Supply Current/Amplifier Parameter, Table 2 .......... 3
Changes to Common-Mode Rejection Ratio Parameter, Table 3 .. 4
Changes to Common-Mode Rejection Ratio Parameter, Table 4 .. 5
Changes to Figure 2 .......................................................................... 6
Changes to Figure 24 ...................................................................... 10
Changes to Figure 32 ...................................................................... 12
Changes to Figure 47 ...................................................................... 14
Changes to Figure 55 ...................................................................... 16
Changes to Figure 62 ...................................................................... 17
Changes to Figure 73 ...................................................................... 20
10/2011—Revision 0: Initial Version
Rev. I | Page 3 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSY = 3 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
VOS
SOIC package
−40°C ≤ TA ≤ +125°C
SOT-23, MSOP, TSSOP packages
−40°C ≤ TA ≤ +125°C
ADA4084-2 LFCSP package
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
TA = 25°C
ADA4084-4 LFCSP package
Offset Voltage Drift
Offset Voltage Matching
Δt/ΔT
Input Bias Current
IB
Min
Typ
Max
Unit
20
100
200
130
250
200
300
1.75
150
200
250
400
25
50
3
µV
µV
µV
µV
µV
µV
µV/°C
µV
µV
nA
nA
nA
nA
V
dB
dB
dB
dB
50
80
0.5
140
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
5
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Input Impedance
Differential
Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
Settling Time
Total Harmonic Distortion Plus Noise
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
VOH
VOL
ISC
ZOUT
PSRR
VCM = 0 V to 3 V
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ, 0.5 V ≤ VOUT ≤ 2.5 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
0
64
60
100
97
2.90
2.80
2.85
2.70
104
100||1.1
80||2.9
kΩ||pF
MΩ||pF
2.95
V
V
V
V
mV
mV
mV
mV
mA
Ω
2.9
10
20
20
40
30
50
−17/+10
0.1
f = 1 kHz, AV = 1
VSY = ±1.25 V to ±1.75 V
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
−40°C ≤ TA ≤ +125°C
100
90
SR
GBP
UGC
ΦM
−3 dB
tS
THD + N
RL = 2 kΩ
VIN = 5 mV p-p, RL = 10 kΩ, AV = 100
VIN = 5 mV p-p, RL = 10 kΩ, AV = 1
2.0
en p-p
en
in
ISY
88
110
0.565
0.650
0.950
dB
dB
mA
mA
AV = 1, VIN = 5 mV p-p
AV = 10, VIN = 2 V p-p, 0.1%
VIN = 300 mV rms, RL = 2 kΩ, f = 1 kHz
2.6
15.4
8.08
86
12.3
4
0.009
V/µs
MHz
MHz
Degrees
MHz
µs
%
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.14
3.9
0.55
µV p-p
nV/√Hz
pA/√Hz
Rev. I | Page 4 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
VSY = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
VOS
SOIC package
−40°C ≤ TA ≤ +125°C
SOT-23, MSOP, TSSOP packages
−40°C ≤ TA ≤ +125°C
ADA4084-2 LFCSP package
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
TA = 25°C
ADA4084-4 LFCSP package
Offset Voltage Drift
Offset Voltage Matching
ΔVOS/ΔT
Input Bias Current
IB
Min
Typ
Max
Unit
30
100
200
130
250
200
300
1.75
150
200
250
400
25
50
+5
µV
µV
µV
µV
µV
µV
µV/°C
µV
µV
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
60
90
0.5
140
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
5
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Input Impedance
Differential
Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
Settling Time
Total Harmonic Distortion Plus Noise
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
VOH
VOL
ISC
ZOUT
PSRR
VCM = ±4 V, −40°C ≤ TA ≤ +125°C
VCM = ±5 V
VCM = ±5 V, −40°C ≤ TA ≤ +125°C
RL = 2 kΩ, −4 V ≤ VOUT ≤ 4 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
−5
106
76
70
108
103
4.9
4.8
4.8
4.7
112
100||1.1
200||2.5
kΩ||pF
MΩ||pF
4.95
V
V
V
V
V
V
V
V
mA
Ω
4.85
−4.95
−4.95
−4.9
−4.8
−4.8
−4.7
−24/+17
0.1
f = 1 kHz, AV = 1
VSY = ±2 V to ±18 V
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
−40°C ≤ TA ≤ +125°C
110
105
SR
GBP
UGC
ΦM
−3 dB
tS
THD + N
RL = 2 kΩ to VCM
VIN = 5 mV p-p, RL = 10 kΩ, AV = 100
VIN = 5 mV p-p, RL = 10 kΩ, AV = 1
2.4
en p-p
en
in
ISY
124
120
0.595
0.700
1.00
dB
dB
mA
mA
AV = 1, VIN = 5 mV p-p
AV = 10, VIN = 8 V p-p, 0.1%
VIN = 2 V rms, RL = 2 kΩ, f = 1 kHz
3.7
15.9
9.6
85
13.9
4
0.003
V/µs
MHz
MHz
Degrees
MHz
µs
%
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.14
3.9
0.55
µV p-p
nV/√Hz
pA/√Hz
Rev. I | Page 5 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
VSY = ±15.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Test Conditions/Comments
VOS
SOIC package
−40°C ≤ TA ≤ +125°C
SOT-23, MSOP, TSSOP packages
−40°C ≤ TA ≤ +125°C
ADA4084-2 LFCSP package
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Offset Voltage Matching
ΔVOS/ΔT
Input Bias Current
IB
Min
Typ
Max
Unit
40
100
200
130
250
200
300
1.75
150
200
250
400
25
50
+15
µV
µV
µV
µV
µV
µV
µV/°C
µV
µV
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
70
100
0.5
TA = 25°C
ADA4084-4 LFCSP package
140
−40°C ≤ TA ≤ +125°C
Input Offset Current
IOS
5
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Input Impedance
Differential
Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Unity-Gain Crossover
Phase Margin
−3 dB Closed-Loop Bandwidth
Settling Time
Total Harmonic Distortion Plus Noise
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
VOH
VOL
ISC
ZOUT
PSRR
VCM = ±14 V, −40°C ≤ TA ≤ +125°C
VCM = ±15 V
VCM = ±15 V, −40°C ≤ TA ≤ +125°C
RL = 2 kΩ, −13.5 V ≤ VOUT ≤ +13.5 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to VCM
−40°C ≤ TA ≤ +125°C
−15
106
85
80
110
105
14.85
14.8
14.5
14.0
117
100||1.1
200||2.5
kΩ||pF
MΩ||pF
14.9
V
V
V
V
V
V
V
V
mA
Ω
14.6
−14.95
−14.9
−14.9
−14.8
−14.8
−14.7
±30
0.1
f = 1 kHz, AV = +1
VSY = ±2 V to ±18 V
−40°C ≤ TA ≤ +125°C
IOUT = 0 mA
−40°C ≤ TA ≤ +125°C
110
105
SR
GBP
UGC
ΦM
−3 dB
tS
THD + N
RL = 2 kΩ
VIN = 5 mV p-p, RL = 10 kΩ, AV = 100
VIN = 5 mV p-p, RL = 10 kΩ, AV = 1
2.4
en p-p
en
in
ISY
124
120
0.625
0.750
1.050
dB
dB
mA
mA
AV = 1, VIN = 5 mV p-p
AV = 10, VIN = 10 V p-p, 0.1%
VIN = 5 V rms, RL = 2 kΩ, f = 1 kHz
4.6
15.9
9.9
86
13.9
4
0.003
V/µs
MHz
MHz
Degrees
MHz
µs
%
0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
0.1
3.9
0.55
µV p-p
nV/√Hz
pA/√Hz
Rev. I | Page 6 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage1
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering 60 sec)
ESD
Human Body Model2
Machine Model3
Field-Induced Charged-Device Model
(FICDM)4
θJA is specified for the device soldered on a 4-layer JEDEC
standard printed circuit board (PCB) with zero airflow.
Rating
±18 V
V− ≤ VIN ≤ V+
±0.6 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Table 6. Thermal Resistance
Package Type
5-Lead SOT-23 (RJ-5)
8-Lead SOIC_N (R-8)
8-Lead MSOP (RM-8)
8-Lead LFCSP (CP-8-11)1, 3
14-Lead TSSOP (RU-14)
16-Lead LFCSP (CP-16-17)2, 3
4.5 kV
200 V
1.25 kV
θJA
219.4
121
142
84
112
55
θJC
155.6
43
45
40
43
30
Values are based on 4-layer (2S2P) JEDEC standard PCB, with four thermal
vias. Exposed pad soldered to PCB.
2
Values are based on 4-layer (2S2P) JEDEC standard PCB, with nine thermal
vias. Exposed pad soldered to PCB.
3
θJC measured on top of package.
1
For input differential voltages greater than 0.6 V, limit the input current to
less than 5 mA to prevent degradation or destruction of the input devices.
2
Applicable standard: MIL-STD-883, Method 3015.7.
3
Applicable standard: JESD22-A115-A (ESD machine model standard of
JEDEC).
4
Applicable standard: JESD22-C101-C (ESD FICDM standard of JEDEC).
1
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
VCC
R4
R3
R6
Q24
D2
Q1
Q23
D1
Q2
MIRROR
D100
Q4
D101
FOLDED
CASCADE
Q3
VOUT
R7 C2
Q13
D5
VBIAS
D4
R5
Q18
C1
R2
Q21
D20
Figure 2. Simplified Schematic
Rev. I | Page 7 of 36
VEE
08237-002
Q19
R1
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
NIC
1
8
NIC
–IN
2
ADA4084-1
7
V+
+IN
3
6
OUT
V–
TOP VIEW
(Not to Scale)
4
5
NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
08237-101
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. ADA4084-1, 8-Lead SOIC (R)
Table 7. 8-Lead SOIC, ADA4084-1 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
NIC
−IN
+IN
V−
NIC
OUT
V+
NIC
Description
Not Internally Connected
Negative Input
Positive Input
Negative Supply
Not Internally Connected
Output
Positive Supply
Not Internally Connected
ADA4084-1
OUT 1
5
V+
4
–IN
+IN 3
08237-301
V– 2
Figure 4. ADA4084-1, 5-Lead SOT-23 (RJ)
Table 8. 5-Lead SOT-23, ADA4084-1 Pin Function Descriptions
Mnemonic
OUT
V−
+IN
−IN
V+
Description
Output
Negative Supply
Positive Input
Negative Input
Positive Supply
OUT A 1
–IN A 2
+IN A 3
8 V+
ADA4084-2
TOP VIEW
(Not to Scale)
7 OUT B
6 –IN B
5 +IN B
V– 4
NOTES
1. FOR THE LFCSP PACKAGE,
THE EXPOSED PAD MUST BE
CONNECTED TO V–.
08237-104
Pin No.
1
2
3
4
5
Figure 5. ADA4084-2, 8-Lead LFCSP (CP)
Table 9. 8-Lead LFCSP, ADA4084-2 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
EPAD
Description
Output, Channel A
Negative Input, Channel A
Positive Input, Channel A
Negative Supply
Positive Input, Channel B
Negative Input, Channel B
Output, Channel B
Positive Supply
Exposed Pad. For the LFCSP package, the exposed pad must be connected to V−.
Rev. I | Page 8 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
8
V+
–IN A 2
7
+IN A 3
V– 4
TOP VIEW
(Not to Scale)
1
8
V+
OUT B
–IN A
2
7
OUT B
6
–IN B
+IN A
3
6
–IN B
5
+IN B
V–
4
5
+IN B
TOP VIEW
(Not to Scale)
08237-302
ADA4084-2
OUT A
Figure 7. ADA4084-2, 8-Lead SOIC (R)
Figure 6. ADA4084-2, 8-Lead MSOP (RM)
Table 10. 8-Lead MSOP, 8-Lead SOIC, ADA4084-2 Pin Function Descriptions
Mnemonic
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
Description
Output, Channel A
Negative Input, Channel A
Positive Input, Channel A
Negative Supply
Positive Input, Channel B
Negative Input, Channel B
Output, Channel B
Positive Supply B
OUT A
1
14 OUT D
–IN A
2
13 –IN D
+IN A
3
V+
4
+IN B
5
–IN B
6
9
–IN C
OUT B
7
8
OUT C
ADA4084-4
TOP VIEW
(Not to Scale)
12 +IN D
11 V–
10 +IN C
08237-102
Pin No.
1
2
3
4
5
6
7
8
Figure 8. ADA4084-4, 14-Lead TSSOP (RU)
Table 11. 14-Lead TSSOP, ADA4804-4 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
OUT A
−IN A
+IN A
V+
+IN B
−IN B
OUT B
OUT C
−IN C
+IN C
V−
+IN D
−IN D
OUT D
08237-303
ADA4084-2
OUT A 1
Description
Output, Channel A
Negative Input, Channel A
Positive Input, Channel A
Positive Supply
Positive Input, Channel B
Negative Input, Channel B
Output, Channel B
Output, Channel C
Negative Input, Channel C
Positive Input, Channel C
Negative Supply
Positive Input, Channel D
Negative Input, Channel D
Output, Channel D
Rev. I | Page 9 of 36
13 NIC
14 OUT D
16 NIC
Data Sheet
15 OUT A
ADA4084-1/ADA4084-2/ADA4084-4
–IN A 1
12 –IN D
ADA4084-4
TOP
VIEW
V+ 3
11 +IN D
10 V–
9
+IN C
–IN C 8
OUT C 7
–IN B 5
OUT B 6
+IN B 4
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. FOR THE LFCSP PACKAGE, THE EXPOSED PAD
MUST BE CONNECTED TO V–.
Figure 9. ADA4084-4, 16-Lead LFCSP (CP)
Table 12. 16-Lead LFCSP, ADA4084-4 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
−IN A
+IN A
V+
+IN B
−IN B
OUT B
OUT C
−IN C
+IN C
V−
+IN D
−IN D
NIC
OUT D
OUT A
NIC
Description
Negative Input Channel A
Positive Input, Channel A
Positive Supply
Positive Input, Channel B
Negative Input, Channel B
Output, Channel B
Output, Channel C
Negative Input, Channel C
Positive Input, Channel C
Negative Supply
Positive Input, Channel D
Negative Input, Channel D
Not Internally Connected
Output, Channel D
Output, Channel A
Not Internally Connected
Rev. I | Page 10 of 36
08237-103
+IN A 2
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
±1.5 V CHARACTERISTICS
120
VSY = ±1.5V
TA = 25°C
RL = ∞
NUMBER OF AMPLIFIERS
100
NUMBER OF AMPLIFIERS
200
VSY = ±1.5V
TA = 25°C
RL = ∞
80
60
40
150
100
50
–50
–75
–25
0
25
50
100
75
0
–200
08237-003
0
–100
VOS (µV)
0
50
100
60
50
NUMBER OF AMPLIFIERS
80
NUMBER OF AMPLIFIERS
–50
Figure 13. Input Offset Voltage (VOS) Distribution, LFCSP
VSY = ±1.5V
TA = 25°C
RL = ∞
90
–100
VOS (µV)
Figure 10. Input Offset Voltage (VOS) Distribution, SOIC
100
–150
08237-081
20
70
60
50
40
30
40
30
20
20
10
–75
–50
–25
0
25
50
75
100
VOS (µV)
0
08237-306
0
–100
0
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Figure 14. TCVOS Distribution, SOIC, MSOP, and TSSOP
20
VSY = ±1.5V
TA = 25°C
RL = ∞
NUMBER OF AMPLIFIERS
16
35
30
25
20
15
14
12
10
8
6
4
5
2
–75
–50
–25
0
25
50
75
100
VOS (µV)
08237-004
10
0
–100
VSY = ±1.5V
RL = ∞
–40°C ≤ TA ≤ +125°C
18
40
NUMBER OF AMPLIFIERS
0.6
Figure 12. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
TCVOS (µV/°C)
Figure 15. TCVOS Distribution, SOT-23
Rev. I | Page 11 of 36
1.8
2.0
08237-309
50
0.4
TCVOS (µV/°C)
Figure 11. Input Offset Voltage (VOS) Distribution, SOT-23
45
0.2
08237-005
VSY = ±1.5V
RL = ∞
–40°C ≤ TA ≤ +125°C
10
ADA4084-1/ADA4084-2/ADA4084-4
50
30
VSY = ±1.5V
RL = ∞
–40°C ≤ TA ≤ +125°C
VSY = ±1.5V
VCM = 0V
RL = ∞
INPUT BIAS CURRENT (nA)
25
NUMBER OF AMPLIFIERS
Data Sheet
20
15
10
IB+
–100
–150
IB –
–200
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TCVOS (µV/°C)
–250
–50
08237-082
0
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
08237-213
5
Figure 19. Input Bias Current vs. Temperature
Figure 16. TCVOS Distribution, LFCSP
600
500
VSY = ±1.5V
400
200
100
0
–100
–200
–300
VSY = ±1.5V
TA = 25°C
RL = ∞
–400
–500
–1.50
–1.00
–0.50
0
0.50
1.00
1.50
COMMON-MODE VOLTAGE (V)
200
TA = +125°C
0
TA = +85°C
–200
TA = +25°C
–400
–600
–1.5
–1.0
–0.5
0
TA = –40°C
0.5
1.0
1.5
VCM (V)
Figure 17. Input Offset Voltage vs. Common-Mode Voltage
08237-008
INPUT BIAS CURRENT (nA)
300
08237-006
INPUT OFFSET VOLTAGE (µV)
400
Figure 20. Input Bias Current vs. VCM for Various Temperatures
100
VSY = ±1.5V
VSY = ±1.5V
TA = 25°C
75
50
VDO (mV)
25
0
–25
100
(V+) – VOH
10
–50
–100
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
150
1
0.001
0.01
0.1
1
10
SOURCE CURRENT (mA)
Figure 18. Input Offset Voltage vs. Temperature
Figure 21. Dropout Voltage (VDO) vs. Source Current
Rev. I | Page 12 of 36
08237-009
–75
08237-108
INPUT OFFSET VOLTAGE (µV)
1000
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
1000
VSY = ±1.5V
TA = 25°C
VSY = ±1.5V
TA = 25°C
1000
AV = +10
ZOUT (Ω)
100
VOL – (V–)
0.01
1
0.1
1
10
0.01
10
225
120
80
180
100
60
135
40
90
20
45
0
0
100
1k
FREQUENCY (kHz)
40
PSRR (dB)
PSRR–
PSRR+
100
10k
100k
1M
10M
100M
FREQUENCY (Hz)
140
VSY = ±1.5V
TA = 25°C
120
AV = +100
100
CMRR (dB)
AV = +10
80
60
10
AV = +1
40
20
–10
–20
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 27. CMRR vs. Frequency
Figure 24. Closed-Loop Gain vs. Frequency
Rev. I | Page 13 of 36
10M
100M
08237-221
0
08237-012
GAIN (dB)
1k
Figure 26. PSRR vs. Frequency
30
20
100M
60
–20
10
VSY = ±1.5V
TA = 25°C
50
10M
80
Figure 23. Open-Loop Gain and Phase vs. Frequency
60
1M
0
–90
100k
10k
100k
VSY = ±1.5V
TA = 25°C
20
–45
–20
10
10k
40
08237-011
GAIN (dB)
PHASE (Degrees)
140
VSY = ±1.5V
TA = 25°C
RL = 10kΩ
100
1k
Figure 25. Output Impedance (ZOUT) vs. Frequency
270
120
100
FREQUENCY (Hz)
Figure 22. Dropout Voltage (VDO) vs. Sink Current
1
AV = +1
0.10
SINK CURRENT (mA)
–40
0.1
AV = +100
08237-013
1
0.001
10
08237-014
10
08237-010
VDO (mV)
100
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
1.5
VOLTAGE NOISE DENSITY (nV/√Hz)
10
1.0
0
–0.5
VSY = ±1.5V
TA = 25°C
RL = 2kΩ
CL = 100pF
–1.5
0
2
4
6
8
10
VSY = ±1.5V
TA = 25°C
12
14
16
18
TIME (µs)
1
08237-016
–1.0
4
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 28. Large Signal Transient Response
08237-019
VOLTAGE (V)
0.5
Figure 31. Voltage Noise Density vs. Frequency
80
60
VSY = ±1.5V
VIN = 100mV p-p
RL = 2kΩ
TA = 25°C
60
50
OS+
OVERSHOOT (%)
VOLTAGE (mV)
40
20
0
–20
40
30
20
OS–
–40
VSY = ±1.5V
TA = 25°C
RL = 2kΩ
CL = 100pF
10
0
2
4
6
8
10
12
14
18
16
TIME (µs)
0
1
100
1000
LOAD CAPACITANCE (pF)
Figure 29. Small Signal Transient Response
Figure 32. Overshoot vs. Load Capacitance
2
0.08
INPUT
0
10
08237-020
–80
08237-017
–60
80
60
0.06
OUTPUT
–6
0
–8
–0.02
VOLTAGE (V)
0.02
–4
20
0
–20
–40
–60
–10
–1
–0.04
0
1
2
3
4
5
6
TIME (µs)
7
8
9
Figure 30. Settling Time
VSY = ±1.5V
TA = 25°C
–80
0
1
2
3
4
5
6
7
8
TIME (Seconds)
Figure 33. Voltage Noise, 0.1 Hz to 10 Hz
Rev. I | Page 14 of 36
9
10
08237-021
VSY = ±1.5V
TA = 25°C
08237-018
VOLTAGE (V)
VOLTAGE NOISE (nV)
40
0.04
–2
Data Sheet
CHANNEL SEPARATION (dB)
–20
VCC
VCC
–
VEE
10V p-p
CH A
2kΩ
VSY = ±1.5V
TA = 25°C
VIN = 300mV rms
80kHz FILTER
1kΩ
–
+
–40
0.1
10kΩ
VSY = ±1.5V
TA = 25°C
VIN = 1V p-p
+
VEE
CH B,
CH C,
CH D
2kΩ
–60
0.01
THD + N (%)
0
ADA4084-1/ADA4084-2/ADA4084-4
–80
–100
RL = 2kΩ
0.001
–120
RL = 10kΩ
1k
10k
100k
FREQUENCY (Hz)
0.0001
10
08237-022
–160
100
1k
10k
100k
FREQUENCY (Hz)
Figure 34. Channel Separation vs. Frequency
Figure 37. THD + N vs. Frequency, 80 kHz Filter
2.0
1
VSY = ±1.5V
TA = 25°C
RL = 10kΩ
VIN AT 1kHz
VSY = ±1.5V
TA = 25°C
1.5
1.0
VOLTAGE (V)
0.1
THD + N (%)
100
08237-231
–140
0.01
0.5
OUTPUT
0
–0.5
INPUT
–1.0
0.001
–2.0
0.01
0.1
1
AMPLITUDE (VRMS)
100
200
400
500
600
700
800
900
1000
TIME (µs)
Figure 38. No Phase Reversal
Figure 35. THD + N vs. Amplitude
0.01
300
08237-125
0
0.0001
0.001
0.5
VSY = ±1.5V
TA = 25°C
VIN = 300mV rms
500kHz FILTER
08237-025
–1.5
4
RL = 2kΩ
0
3
RL = 10kΩ
–0.5
2
–1.0
1
VOLTAGE (V)
VOLTAGE (V)
THD + N (%)
INPUT
OUTPUT
–1.5
0
0.1
1
10
100
FREQUENCY (kHz)
Figure 36. THD + N vs. Frequency, 500 kHz Filter
–2.0
–2
–1
0
2
4
6
8
10
12
14
TIME (µs)
Figure 39. Positive 50% Overload Recovery
Rev. I | Page 15 of 36
16
18
08237-233
0.001
0.01
08237-126
VSY = ±1.5V
TA = 25°C
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
0.5
3
0
2
1
OUTPUT
–1.0
0
–1.5
–1
VOLTAGE (V)
–0.5
VSY = ±1.5V
TA = 25°C
–2.0
–2
–2
0
2
4
6
8
10
12
14
TIME (µs)
16
18
08237-234
VOLTAGE (V)
INPUT
Figure 40. Negative 50% Overload Recovery
Rev. I | Page 16 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
±5 V CHARACTERISTICS
120
100
VSY = ±5V
TA = 25°C
RL = ∞
200
NUMBER OF AMPLIFIERS
80
60
40
150
100
50
20
–75
–50
–25
0
25
50
75
0
–200
08237-026
0
–100
100
VOS (µV)
0
50
50
100
VSY = ±5V
RL = ∞
–40°C ≤ TA ≤ +125°C
45
40
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
–50
Figure 44. Input Offset Voltage (VOS) Distribution, LFCSP
VSY = ±5V
TA = 25°C
RL = ∞
100
–100
VOS (µV)
Figure 41. Input Offset Voltage (VOS) Distribution, SOIC
120
–150
08237-080
NUMBER OF AMPLIFIERS
250
VSY = ±5V
TA = 25°C
RL = ∞
80
60
40
35
30
25
20
15
10
20
–75
–50
–25
0
25
50
75
100
VOS (µV)
0
08237-335
0
–100
0
50
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TCVOS (µV/°C)
Figure 42. Input Offset Voltage (VOS) Distribution, SOT-23
60
0.2
08237-028
5
Figure 45. TCVOS Distribution, SOIC, MSOP, and TSSOP
20
VSY = ±5V
TA = 25°C
RL = ∞
VSY = ±5V
RL = ∞
–40°C ≤ TA ≤ +125°C
18
NUMBER OF AMPLIFIERS
40
30
20
14
12
10
8
6
4
10
0
–100
–75
–50
–25
0
25
50
75
100
VOS (µV)
Figure 43. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
TCVOS (µV/°C)
Figure 46. TCVOS Distribution for SOT-23
Rev. I | Page 17 of 36
1.8
2
08237-338
2
08237-027
NUMBER OF AMPLIFIERS
16
ADA4084-1/ADA4084-2/ADA4084-4
35
–50
VSY = ±5V
RL = ∞
–40°C ≤ TA ≤ +125°C
INPUT BIAS CURRENT (nA)
30
NUMBER OF AMPLIFIERS
Data Sheet
25
20
15
10
VSY = ±5V
VCM = 0V
RL = ∞
–100
IB+
–150
IB–
–200
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TCVOS (µV/°C)
–250
–40
08237-084
0
600
800
20
35
50
65
80
95
110
125
VSY = ±5V
600
300
INPUT BIAS CURRENT (nA)
INPUT OFFSET VOLTAGE (µV)
5
Figure 50. Input Bias Current vs. Temperature
VSY = ±5V
TA = 25°C
RL = ∞
400
–10
TEMPERATURE (°C)
Figure 47. TCVOS Distribution, LFCSP
500
–25
08237-030
5
200
100
0
–100
–200
–300
400
200
TA = +85°C
TA = +125°C
0
–200
TA = +25°C
–400
TA = –40°C
–400
–4
–3
–2
–1
0
1
2
3
4
5
COMMON-MODE VOLTAGE (V)
08237-029
–600
–5
–800
–5
–4
–3
–2
–1
0
1
2
3
4
5
VCM (V)
Figure 48. Input Offset Voltage vs. Common-Mode Voltage
100
Figure 51. Input Bias Current vs. VCM for Various Temperatures
VSY = ±5V
1000
75
VSY = ±5V
TA = 25°C
50
VDO (mV)
25
0
–25
100
(V+) – VOH
10
–50
–100
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
150
Figure 49. Input Offset Voltage vs. Temperature
1
0.001
0.01
0.1
1
10
SOURCE CURRENT (mA)
Figure 52. Dropout Voltage (VDO) vs. Source Current
Rev. I | Page 18 of 36
08237-032
–75
08237-133
INPUT OFFSET VOLTAGE (µV)
08237-031
–600
–500
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
1000
1000
VSY = ±5V
TA = 25°C
VSY = ±5V
TA = 25°C
100
ZOUT (Ω)
VDO (mV)
100
AV = +10
10
AV = +1
AV = +100
1
VOL – (V–)
10
0.1
1
10
0.01
10
SINK CURRENT (mA)
140
225
120
80
180
100
60
135
40
90
20
45
0
0
10
100
1k
FREQUENCY (kHz)
PSRR (dB)
60
–20
10
PSRR–
PSRR+
100
40
100k
1M
140
10M
100M
VSY = ±5V
TA = 25°C
120
AV = +100
100
CMRR (dB)
AV = +10
80
60
10
AV = +1
40
20
–10
–20
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 58. CMRR vs. Frequency
Figure 55. Closed-Loop Gain vs. Frequency
Rev. I | Page 19 of 36
10M
100M
08237-221
0
08237-035
GAIN (dB)
10k
Figure 57. PSRR vs. Frequency
30
20
1k
FREQUENCY (Hz)
VSY = ±5V
TA = 25°C
50
100M
80
Figure 54. Open-Loop Gain and Phase vs. Frequency
60
10M
0
–90
100k
10k
1M
VSY = ±5V
TA = 25°C
20
–45
–20
1
100k
40
08237-034
GAIN (dB)
PHASE (Degrees)
270
–40
0.1
10k
Figure 56. Output Impedance (ZOUT) vs. Frequency
VSY = ±5V
TA = 25°C
RL = 10kΩ
100
1k
FREQUENCY (Hz)
Figure 53. Dropout Voltage (VDO) vs. Sink Current
120
100
08237-037
0.01
08237-033
1
0.001
08237-036
0.10
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
5
10
3
VOLTAGE (V)
2
1
0
–1
–2
–3
VSY = ±5V
TA = 25°C
RL = 2kΩ
CL = 100pF
–5
0
2
4
6
8
10
12
14
16
18
TIME (µs)
VSY = ±5V
TA = 25°C
1
08237-039
–4
4
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 59. Large Signal Transient Response
08237-042
VOLTAGE NOISE DENSITY (nV/√Hz)
4
Figure 62. Voltage Noise Density vs. Frequency
80
60
VSY = ±5V
VIN = 100mV p-p
RL = 2kΩ
TA = 25°C
60
50
OS+
OVERSHOOT (%)
VOLTAGE (mV)
40
20
0
–20
40
30
20
OS–
–40
VSY = ±5V
TA = 25°C
RL = 2kΩ
CL = 100pF
10
0
1
2
3
4
5
6
7
8
9
10
TIME (µs)
0
1
1000
Figure 63. Overshoot vs. Load Capacitance
0.16
VSY = ±5V
TA = 25°C
80
0.12
60
0
0.08
40
–5
0.04
5
0
–15
–0.04
–20
–0.08
VOLTAGE (V)
OUTPUT
–10
VOLTAGE NOISE (nV)
INPUT
VSY = ±5V
TA = 25°C
20
0
–20
–40
–25
–2
–0.12
0
2
4
6
8
10
12
TIME (µs)
14
16
18
Figure 61. Settling Time
–80
0
1
2
3
4
5
6
7
8
TIME (Seconds)
Figure 64. Voltage Noise, 0.1 Hz to 10 Hz
Rev. I | Page 20 of 36
9
10
08237-044
–60
08237-041
VOLTAGE (V)
100
LOAD CAPACITANCE (pF)
Figure 60. Small Signal Transient Response
10
10
08237-043
–80
08237-040
–60
Data Sheet
CHANNEL SEPARATION (dB)
–20
VCC
VCC
–
VEE
10V p-p
CH A
2kΩ
2kΩ
–60
VSY = ±5V
TA = 25°C
VIN = 300mV rms
80kHz FILTER
1kΩ
–
+
–40
0.1
10kΩ
VSY = ±5V
TA = 25°C
VIN = 5V p-p
+
VEE
CH B,
CH C,
CH D
RL = 2kΩ
0.01
THD + N (%)
0
ADA4084-1/ADA4084-2/ADA4084-4
–80
–100
–120
0.001
0.0001
RL = 10kΩ
1k
10k
100k
FREQUENCY (Hz)
0.00001
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 65. Channel Separation vs. Frequency
08237-260
–160
100
08237-045
–140
Figure 68. THD + N vs. Frequency, 80 kHz Filter
6
1
VSY = ±5V
TA = 25°C
VSY = ±5V
TA = 25°C
RL = 10kΩ
VIN AT 1kHz
4
0.1
VOLTAGE (V)
THD + N (%)
2
0.01
0
OUTPUT
–2
INPUT
0.001
–6
0.01
0.1
1
AMPLITUDE (VRMS)
0
08237-150
0.0001
0.001
100
200
400
500
700
800
900
1000
Figure 69. No Phase Reversal
1
VSY = ±5V
TA = 25°C
VIN = 2V rms
500kHz FILTER
10
0
8
VOLTAGE (V)
RL = 2kΩ
0.01
–1
6
–2
4
–3
2
RL = 10kΩ
0.001
VOLTAGE (V)
INPUT
0.1
THD + N (%)
600
TIME (µs)
Figure 66. THD + N vs. Amplitude
1
300
08237-048
–4
OUTPUT
–4
0
0.1
1
10
100
FREQUENCY (kHz)
–5
–2
08237-151
0.0001
0.01
–2
0
2
4
6
8
10
12
14
TIME (µs)
Figure 70. Positive 50% Overload Recovery
Figure 67. THD + N vs. Frequency, 500 kHz Filter
Rev. I | Page 21 of 36
16
18
08237-262
VSY = ±5V
TA = 25°C
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
1
6
0
4
INPUT
OUTPUT
–2
0
–3
–2
–4
VOLTAGE (V)
2
–4
VSY = ±5V
TA = 25°C
–5
–2
–6
0
2
4
6
8
10
12
14
TIME (µs)
16
18
08237-263
VOLTAGE (V)
–1
Figure 71. Negative 50% Overload Recovery
Rev. I | Page 22 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
±15 V CHARACTERISTICS
100
200
VSY = ±15V
TA = 25°C
RL = ∞
90
VSY = ±15V
TA = 25°C
RL = ∞
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
80
70
60
50
40
30
150
100
50
20
–75
–50
–25
0
25
50
75
0
–200
08237-049
0
–100
100
VOS (µV)
–100
–50
0
50
100
VOS (µV)
Figure 72. Input Offset Voltage (VOS) Distribution, SOIC
Figure 75. Input Offset Voltage (VOS) Distribution, LFCSP
100
60
VSY = ±1.5V
T = 25°C
90 RA = ∞
L
VSY = ±15V
RL = ∞
–40°C ≤ TA ≤ +125°C
50
NUMBER OF AMPLIFIERS
80
NUMBER OF AMPLIFIERS
–150
08237-079
10
70
60
50
40
30
20
40
30
20
10
10
–50
–25
0
25
50
75
100
VOS (µV)
0
0
1.0
1.2
1.4
1.6
1.8
2.0
VSY = ±15V
RL = ∞
–40°C ≤ TA ≤ +125°C
NUMBER OF AMPLIFIERS
20
30
20
15
10
–75
–50
–25
0
25
50
75
100
VOS (µV)
Figure 74. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
TCVOS (µV)
Figure 77. TCVOS Distribution, SOT-23
Rev. I | Page 23 of 36
1.8
2.0
08237-367
5
10
08237-050
NUMBER OF AMPLIFIERS
0.8
25
40
0
–100
0.6
Figure 76. TCVOS Distribution, SOIC, MSOP, and TSSOP
VSY = ±15V
TA = 25°C
RL = ∞
50
0.4
TCVOS (µV/°C)
Figure 73. Input Offset Voltage (VOS) Distribution, SOT-23
60
0.2
08237-051
–75
08237-364
0
–100
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
–50
30
VSY = ±15V
RL = ∞
–40°C ≤ TA ≤ +125°C
INPUT BIAS CURRENT (nA)
20
15
10
IB+
–100
–150
IB–
–200
VSY = ±15V
VCM = 0V
RL = ∞
5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
TCVOS (µV/°C)
–250
–40
08237-085
0
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 81. Input Bias Current vs. Temperature
Figure 78. TCVOS Distribution, LFCSP
1200
600
VSY = ±15V
500 T = 25°C
A
RL = ∞
400
VSY = ±15V
800
300
INPUT BIAS CURRENT (nA)
INPUT OFFSET VOLTAGE (µV)
–25
08237-053
NUMBER OF AMPLIFIERS
25
200
100
0
–100
–200
–300
400
TA = +125°C
TA = +85°C
0
TA = +25°C
–400
–400
TA = –40°C
–800
–10
–5
0
5
10
15
COMMON-MODE VOLTAGE (V)
–1200
–15
0
5
10
15
Figure 82. Input Bias Current vs. VCM for Various Temperatures
VSY = ±15V
10000
75
50
1000
VDO (mV)
25
0
100
–25
(V+) – VOH
–50
10
–75
–25
0
25
50
75
100
125
TEMPERATURE (°C)
150
Figure 80. Input Offset Voltage vs. Temperature
1
0.001
VSY = ±15V
TA = 25°C
0.01
0.1
1
10
SOURCE CURRENT (mA)
Figure 83. Dropout Voltage (VDO) vs. Source Current
Rev. I | Page 24 of 36
08237-055
–100
–50
08237-165
INPUT OFFSET VOLTAGE (µV)
–5
VCM (V)
Figure 79. Input Offset Voltage vs. Common-Mode Voltage
100
–10
08237-054
–600
–15
08237-052
–500
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
1000
VSY = ±15V
TA = 25°C
10000
100
AV = +10
ZOUT (Ω)
VDO (mV)
1000
100
AV = +100
1
AV = +1
VOL – (V–)
10
10
0.1
0.1
1
10
SINK CURRENT (mA)
120
80
180
100
60
135
40
90
20
45
0
0
100k
1M
PSRR (dB)
PHASE (Degrees)
80
60
PSRR–
PSRR+
0
FREQUENCY (Hz)
–20
10
100
50
10k
100k
1M
100M
10M
Figure 88. PSRR vs. Frequency
140
VSY = ±15V
TA = 25°C
40
1k
FREQUENCY (Hz)
Figure 85. Open-Loop Gain and Phase vs. Frequency
60
100M
10M
VSY = ±15V
TA = 25°C
20
–90
100M
10M
1M
40
–45
–20
10k
100k
140
08237-057
GAIN (dB)
100
1k
10k
Figure 87. Output Impedance (ZOUT) vs. Frequency
270
VSY = ±15V
TA = 25°C
RL = 10kΩ 225
–40
100
1k
FREQUENCY (Hz)
Figure 84. Dropout Voltage (VDO) vs. Sink Current
120
100
08237-060
0.01
08237-056
1
0.001
08237-059
VSY = ±15V
TA = 25°C
0.01
10
VSY = ±15V
TA = 25°C
120
AV = +100
100
CMRR (dB)
AV = +10
10
0
AV = +1
60
40
20
–10
–20
10
80
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 86. Closed-Loop Gain vs. Frequency
0
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 89. CMRR vs. Frequency
Rev. I | Page 25 of 36
10M
100M
08237-279
20
08237-058
GAIN (dB)
30
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
10
VOLTAGE NOISE DENSITY (nV/√Hz)
15
10
0
–5
VSY = ±15V
TA = 25°C
RL = 2kΩ
CL = 100pF
0
4
8
12
16
20
24
28
32
36
TIME (µs)
1
1
80
70
60
60
10k
100k
VSY = ±15V
VIN = 100mV p-p
RL = 2kΩ
TA = 25°C
OS+
50
OVERSHOOT (%)
20
0
–20
40
30
20
–40
VSY = ±15V
TA = 25°C
RL = 2kΩ
CL = 100pF
10
–80
0
1
3
2
4
5
6
7
8
9
10
TIME (µs)
0
08237-063
–60
OS–
1
0.20
60
0.15
5
40
0.10
–5
0.05
OUTPUT
–10
0
–15
–0.05
–20
VOLTAGE (V)
0
VOLTAGE NOISE (nV)
INPUT
8
10
12
TIME (µs)
14
16
0
–20
VSY = ±15V
TA = 25°C
–0.15
18
08237-064
6
20
–40
–0.10
VSY = ±15V
TA = 25°C
4
1000
Figure 94. Overshoot vs. Load Capacitance
10
2
100
LOAD CAPACITANCE (pF)
Figure 91. Small Signal Transient Response
0
10
08237-066
VOLTAGE (mV)
1k
Figure 93. Voltage Noise Density vs. Frequency
40
VOLTAGE (V)
100
FREQUENCY (Hz)
Figure 90. Large Signal Transient Response
–25
–2
10
08237-065
VSY = ±15V
TA = 25°C
–15
08237-062
–10
4
Figure 92. Settling Time
–60
0
2
4
6
8
TIME (Seconds)
Figure 95. Voltage Noise 0.1 Hz to 10 Hz
Rev. I | Page 26 of 36
10
08237-067
VOLTAGE (V)
5
Data Sheet
–20
VCC
VCC
–
VEE
10V p-p
CH A
–60
2kΩ
2kΩ
VSY = ±15V
TA = 25°C
VIN = 300mV rms
80kHz FILTER
1kΩ
–
+
–40
CHANNEL SEPARATION (dB)
0.1
10kΩ
VSY = ±15V
TA = 25°C
VIN = 10V p-p
+
VEE
CH B,
CH C,
CH D
RL = 2kΩ
0.01
THD + N (%)
0
ADA4084-1/ADA4084-2/ADA4084-4
–80
–100
0.001
–120
0.0001
–140
RL = 10kΩ
1k
10k
100k
FREQUENCY (Hz)
0.00001
10
100
Figure 96. Channel Separation vs. Frequency
10k
100k
Figure 99. THD + N vs. Frequency, 80 kHz Filter
20
1
VSY = ±15V
RL = 10kΩ
VIN AT 1kHz
VSY = ±15V
TA = 25°C
15
10
VOLTAGE (V)
0.1
THD + N (%)
1k
FREQUENCY (Hz)
08237-289
–180
100
08237-068
–160
0.01
5
0
OUTPUT
–5
INPUT
–10
0.001
–20
0
0.01
0.1
1
10
AMPLITUDE (VRMS)
100
200
08237-175
0.0001
0.001
400
500
600
700
800
900
TIME (µs)
Figure 97. THD + N vs. Amplitude
1
300
Figure 100. No Phase Reversal
VSY = ±15V
TA = 25°C
VIN = 5V rms
500kHz FILTER
VIN
1
0.1
THD + N (%)
1000
08237-071
–15
CH1 AMPL
202mV
VOUT
RL = 2kΩ
0.01
RL = 10kΩ
0.001
2
1
10
100
FREQUENCY (kHz)
08237-176
0.1
CH1 100mV
CH2 5V
M1µs
T 10.2%
A CH1
–84mV
Figure 101. Positive 50% Overload Recovery
Figure 98. THD + N vs. Frequency, 500 kHz Filter
Rev. I | Page 27 of 36
08237-178
VSY = ±15V
0.0001
0.01
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
140
VSY = ±15V
VCM = ±14V
120
CH1 AMPL
200mV
VIN
100
CMRR (dB)
1
2
VCM = ±4V
80
VCM = ±1.5V
60
40
VOUT
CH2 5V
M2µs
T 10.4%
A CH1
44mV
0
–50
–25
0
25
50
75
100
125
150
125
150
TEMPERATURE (°C)
Figure 104. CMRR vs. Temperature
Figure 102. Negative 50% Overload Recovery
150
1000
140
900
+125°C
800
130
+85°C
VSY = ±2V TO ±18V, VCM = 0V
120
700
+25°C
600
PSRR (dB)
–40°C
500
400
110
VSY = ±1.25V TO ±1.75V, VCM = 0V
100
90
80
300
70
200
60
100
0
0
4
8
12
16
20
VSY (V)
24
28
32
36
08237-072
TA = 25°C
RL = ∞
Figure 103. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY) for
Various Temperatures
Rev. I | Page 28 of 36
50
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 105. PSRR vs. Temperature
08237-181
ISY/AMPLIFIER (µA)
08237-180
CH1 100mV
08237-179
20
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
The ADA4084-1/ADA4084-2/ADA4084-4 devices are precision
single-supply, rail-to-rail operational amplifiers. Intended for
portable instrumentation, the ADA4084-1/ADA4084-2/
ADA4084-4 devices combine the attributes of precision, wide
bandwidth, and low noise, making them an ideal choice in
single-supply applications that require both ac and precision dc
performance. Other low supply voltage applications for which
the ADA4084-1/ADA4084-2/ADA4084-4 devices are well suited
include active filters, audio microphone preamplifiers, power
supply control, and telecommunications. To combine all of
these attributes with rail-to-rail input/output operation, novel
circuit design techniques are used.
R4
R3
D2
Q1
D1
Q2
D100
Q4
D101
Q3
A key issue in the input stage is the behavior of the input bias
currents over the input common-mode voltage range. Input bias
currents in the ADA4084-1/ADA4084-2/ADA4084-4 are the
arithmetic sum of the base currents in Q1 and Q4 and in Q2 and
Q3. As a result of this design approach, the input bias currents in
the ADA4084-1/ADA4084-2/ADA4084-4 not only exhibit
different amplitudes, but they also exhibit different polarities. This
effect is best shown in Figure 19, Figure 20, Figure 50, Figure 51,
Figure 81, and Figure 82. It is, therefore, important that the
effective source impedances that are connected to the ADA4084-1/
ADA4084-2/ADA4084-4 inputs be balanced for optimum dc
and ac performance.
To achieve rail-to-rail output, the ADA4084-1/ADA4084-2/
ADA4084-4 output stage design employs a unique topology for
both sourcing and sinking current. This circuit topology is shown
in Figure 107. The output stage is voltage driven from the second
gain stage. The signal path through the output stage is inverting;
that is, for positive input signals, Q13 provides the base current
drive to Q19 so that it conducts (sinks) current. For negative input
signals, the signal path via Q18 to the mirror to Q24 provides
the base current drive for Q23 to conduct (source) current. Both
transistors provide output current until they are forced into
saturation.
VCC
D5
D4
R6
R1
R2
08237-073
Q24
Q23
MIRROR
Figure 106. Equivalent Input Circuit
VOUT
R7 C2
Q13
VBIAS
R5
Q18
C1
Q19
Q21
D20
VEE
08237-074
For example, Figure 106 illustrates a simplified equivalent
circuit for the input stage of the ADA4084-1/ADA4084-2/
ADA4084-4. It comprises a PNP differential pair, Q1 and Q2,
and an NPN differential pair, Q3 and Q4, operating concurrently.
Diode D100 and Diode D101 serve to clamp the applied
differential input voltage to the ADA4084-1/ADA4084-2/
ADA4084-4, thereby protecting the input transistors against Zener
breakdown of the emitter-base junctions. Input stage voltage
gains are kept low for input rail-to-rail operation. The two pairs of
differential output voltages are connected to the second stage of
the ADA4084-1/ADA4084-2/ADA4084-4, which is a modified
compound folded cascade gain stage. It is also in the second
gain stage that the two pairs of differential output voltages are
combined into a single-ended output signal voltage used to
drive the output stage.
Figure 107. Equivalent Output Circuit
Thus, the saturation voltage of the output transistors sets the
limit on the ADA4084-1/ADA4084-2/ADA4084-4 maximum
output voltage swing. Output short-circuit current limiting is
determined by the maximum signal current into the base of
Q13 from the second gain stage. The output stage also exhibits
voltage gain. This is accomplished by the use of common-emitter
amplifiers, and, as a result, the voltage gain of the output stage
(thus, the open-loop gain of the device) exhibits a dependence
on the total load resistance at the output of the ADA4084-1/
ADA4084-2/ADA4084-4.
Rev. I | Page 29 of 36
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
R2
START-UP CHARACTERISTICS
INPUT PROTECTION
As with any semiconductor device, if conditions exist where the
applied input voltages to the device exceed either supply voltage,
the input overvoltage I-to-V characteristic of the device must be
considered. When an overvoltage occurs, the amplifier may be
damaged, depending on the magnitude of the applied voltage
and the magnitude of the fault current.
The D1, D2, D4, and D5 diodes conduct when the input commonmode voltage exceeds either supply pin by a diode drop. This
diode drop voltage varies with temperature and is in the range
of 0.3 V to 0.8 V. As shown in the simplified equivalent input
circuit of Figure 106, the ADA4084-1/ADA4084-2/ADA4084-4
do not have any internal current limiting resistors; thus, fault
currents can quickly rise to damaging levels.
This input current is not inherently damaging to the device,
provided that it is limited to 5 mA or less. If a fault condition
causes more than 5 mA to flow, add an external series resistor at
the expense of additional thermal noise. Figure 108 shows a
typical noninverting configuration for an overvoltage protected
amplifier, where the series resistance (R1) is chosen, such that
R1 =
VIN ( MAX ) − VSUPPLY
5 mA
For example, a 1 kΩ resistor protects the ADA4084-1/ADA4084-2/
ADA4084-4 against input signals up to 5 V above and below the
supplies. Note that the thermal noise of a 1 kΩ resistor at room
temperature is 4 nV/√Hz, which exceeds the voltage noise of the
ADA4084-1/ADA4084-2/ADA4084-4. For other configurations
in which both inputs are used, add a series resistor to limit the
input current. To ensure optimum dc and ac performance,
balance the source impedance levels.
1/2
ADA4084-1/
ADA4084-2/
ADA4084-4
VIN
VOUT
R1
08237-075
The ADA4084-1/ADA4084-2/ADA4084-4 are specified to operate
from 3 V to 30 V (±1.5 V to ±15 V) under nominal power
supplies. During power-up as the supply voltage increases from
0 V to the nominal power supply voltage, the supply current (ISY)
increases as well, to the point at which it stabilizes and the amplifier
is ready to operate. The stabilization varies with temperature, as
shown in Figure 103. For example, at −40°C, it requires a higher
voltage and stabilizes at a lower supply current than at hot
temperatures. At hot temperatures, it requires a lower voltage but
stabilizes at a higher current. In all cases, the ADA4084-1/
ADA4084-2/ADA4084-4 are specified to start up and operate at
a minimum of 3 V under all temperature conditions.
Figure 108. Resistance in Series with the Input
Limits Overvoltage Currents to Safe Values
To protect the Q1/Q2 and Q3/Q4 pairs from large differential
voltages that may result in Zener breakdown of the emitter-base
junction, D100 and D101 are connected between the two inputs.
This precludes operation as a comparator. For a more complete
description, see the MT-035 Tutorial, Op Amp Inputs, Outputs,
Single-Supply, and Rail-to-Rail Issues; the MT-083 Tutorial,
Comparators; the MT-084 Tutorial, Using Op Amps as
Comparators; and the AN-849 Application Note, Using Op
Amps as Comparators.
OUTPUT PHASE REVERSAL
Some operational amplifiers designed for single-supply operation
exhibit an output voltage phase reversal when their inputs are
driven beyond their useful common-mode range. Typically, for
single-supply bipolar op amps, the negative supply determines
the lower limit of their common-mode range. With these devices,
external clamping diodes, with the anode connected to ground
and the cathode to the inputs, prevent input signal excursions
from exceeding the negative supply of the device (that is, GND),
preventing a condition that causes the output voltage to change
phase. JFET input amplifiers can also exhibit phase reversal, and, if
so, a series input resistor is usually required to prevent it.
The ADA4084-1/ADA4084-2/ADA4084-4 are free from
reasonable input voltage range restrictions, provided that input
voltages no greater than the supply voltages are applied (see
Figure 38, Figure 69, and Figure 100).
Although device output does not change phase, large currents can
flow through the input protection diodes. Therefore, apply the
technique recommended in the Input Protection section to
those applications where the likelihood of input voltages
exceeding the supply voltages is high.
Rev. I | Page 30 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
In single-supply applications, devices like the ADA4084-1/
ADA4084-2/ADA4084-4 extend the dynamic range of the
application through the use of rail-to-rail operation. Referring to
the op amp noise model circuit configuration illustrated in
Figure 109, the expression for the total equivalent input noise
voltage of an amplifier for a source resistance level, RS, is given by
]
e nT = 2[(e nR )2 + (inOA × RS )2 + (e nOA )2 , units in
V
Hz
where:
(enR)2 is the source resistance thermal noise voltage power (4kTR).
k is the Boltzmann’s constant, 1.38 × 10–23 J/K.
T is the ambient temperature in Kelvin of the circuit, 273.15 +
TA (°C).
(inOA)2 is the op amp equivalent input noise current spectral
power (1 Hz bandwidth).
RS = 2R, the effective, or equivalent, circuit source resistance.
(enOA)2 is the op amp equivalent input noise voltage spectral
power (1 Hz bandwidth).
enR
NOISELESS
enOA
inOA
IDEAL
NOISELESS
OP AMP
RS = 2R
enR
R
NOISELESS
inOA
08237-076
R
Figure 109. Op Amp Noise Circuit Model Used to Determine Total Circuit
Equivalent Input Noise Voltage and Noise Figure
As a design aid, Figure 110 shows the equivalent thermal noise
of the ADA4084-1/ADA4084-2/ADA4084-4 vs. the total source
resistance. Note that for source resistance less than 1 kΩ, the
equivalent input noise voltage of the ADA4084-1/ADA4084-2/
ADA4084-4 is dominant.
Because circuit SNR is the critical parameter in the final analysis,
the noise behavior of a circuit is sometimes expressed in terms
of its noise figure (NF). The noise figure is defined as the ratio
of the signal-to-noise output of a circuit to its signal-to-noise input.
Noise figure is generally used for RF and microwave circuit analysis
in a 50 Ω system. This is not very useful for op amp circuits where
the input and output impedances can vary greatly. For a more
complete description of noise figure, see the MT-052 Tutorial,
Op Amp Noise Figure: Don’t be Misled.
Signal levels in the application invariably increase to maximize
circuit SNR, which is not an option in low voltage, single-supply
applications.
Therefore, to achieve optimum circuit SNR in single-supply
applications, choose an operational amplifier with the lowest
equivalent input noise voltage, along with source resistance
levels that are consistent with maintaining low total circuit noise.
COMPARATOR OPERATION
Although op amps are quite different from comparators,
occasionally an unused section of a dual or a quad op amp can
be used as a comparator; however, this is not recommended for
any rail-to-rail output op amps. For rail-to-rail output op amps,
the output stage is generally a ratioed current mirror with bipolar
or MOSFET transistors. With the device operating open-loop,
the second stage increases the current drive to the ratioed mirror
to close the loop. However, the loop cannot close, which results in
an increase in supply current. With the op amp configured as a
comparator, the supply current can be significantly higher (see
Figure 111). Configure an unused section as a voltage follower
with the noninverting input connected to a voltage within the
input voltage range. The ADA4084-1/ADA4084-2/ADA4084-4
have unique second stage and output stage designs that greatly
reduce the excess supply current when the op amp is operating
open-loop.
800
COMPARATOR
OUTPUT LOW
700
SUPPLY CURRENT (µA)
FREQUENCY = 1kHz
TA = 25°C
ADA4084-1/ADA4084-2/ADA4084-4
TOTAL EQUIVALENT NOISE
10
RESISTOR THERMAL
NOISE ONLY
600
BUFFER
COMPARATOR
OUTPUT HIGH
500
400
300
200
100
TA = 25°C
RL = ∞
0
0
1
100
1k
10k
100k
TOTAL SOURCE RESISTANCE, RS (Ω)
08237-077
EQUIVALENT THERMAL NOISE (nV/ Hz)
100
Figure 110. Equivalent Thermal Noise vs. Total Source Resistance
Rev. I | Page 31 of 36
4
8
12
16
20
24
28
32
VSY (V)
Figure 111. Supply Current vs. Supply Voltage (VSY)
36
08237-078
DESIGNING LOW NOISE CIRCUITS IN SINGLESUPPLY APPLICATIONS
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
LONG-TERM DRIFT
TEMPERATURE HYSTERESIS
The stability of a precision signal path over its lifetime or
between calibration procedures is dependent on the long-term
stability of the analog components in the path, such as op amps,
references, and data converters. To help system designers
predict the long-term drift of circuits that use the ADA4084-1/
ADA4084-2/ADA4084-4, Analog Devices measured the offset
voltage of multiple units for 10,000 hours (more than 13 months)
using a high precision measurement system, including an
ultrastable oil bath. To replicate real-world system performance,
the devices under test (DUTs) were soldered onto an FR4 PCB
using a standard reflow profile (as defined in the JEDEC J-STD020D standard), as opposed to testing them in sockets. This
manner of testing is important because expansion and
contraction of the PCB can apply stress to the integrated circuit
(IC) package and contribute to shifts in the offset voltage.
In addition to stability over time as described in the Long-Term
Drift section, it is useful to know the temperature hysteresis,
that is, the stability vs. cycling of temperature. Hysteresis is an
important parameter because it tells the system designer how
closely the signal returns to its starting amplitude after the
ambient temperature changes and subsequent return to room
temperature. Figure 113 shows the change in input offset
voltage as the temperature cycles three times from room
temperature to +125°C to −40°C and back to room temperature.
The dotted line is an initial preconditioning cycle to eliminate
the original temperature-induced offset shift from exposure to
production solder reflow temperatures. In the three full cycles,
the offset hysteresis is typically only 4 μV, or 2% of its 200 µV
maximum offset voltage over the full operating temperature
range. The histogram in Figure 114 shows that the hysteresis is
larger when the device is cycled through only a half cycle, from
room temperature to 125°C and back to room temperature.
10
5
0
60
40
20
0
–20
–40
–60
–100
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
08237-113
–80
–5
NUMBER OF DEVICES
10,000
08237-112
8000
7000
6000
5000
4000
3000
2000
1000
TIME (Hours)
9000
VSY = 10V
27 UNITS
TA = 25°C
SAMPLE 1
SAMPLE 2
SAMPLE 3
Figure 112. Measured Long-Term Drift of the ADA4084-1/ADA4084-2/
ADA4084-4 Offset Voltage over 10,000 Hours
40
VSY = 10V
HALF CYCLE
35 27 UNITS × 3 CYCLES
FULL CYCLE
HALF CYCLE = +26°C, +125°C, +26°C
30 FULL
CYCLE = +26°C, +125°C, +26°C, –40°C, +26°C
25
20
15
10
5
0
40
35
30
25
20
15
10
5
0
–40 –32 –24 –18
–8
0
8
18
24
32
40
OFFSET VOLTAGE HYSTERESIS (µV)
08237-114
Figure 113. Change in Offset Voltage over Three Full Temperature Cycles
–10
–15
PRECONDITION
CYCLE 1
CYCLE 2
CYCLE 3
VSY = 10V
80
MEAN
MEAN PLUS ONE STANDARD DEVIATION
MEAN MINUS ONE STANDARD DEVIATION
0
CHANGE IN OFFSET VOLTAGE (µV)
15
100
CHANGE IN OFFSET VOLTAGE (µV)
The ADA4084-1/ADA4084-2/ADA4084-4 have extremely low
long-term drift, as shown in Figure 112. The red, blue, and
green traces show sample units. Note that the mean drift of the
ADA4084-1/ADA4084-2/ADA4084-4 over 10,000 hours is less
than 3 μV, or less than 3% of their maximum specified offset
voltage of 100 µV at room temperature.
Figure 114. Histogram Showing the Temperature Hysteresis of the Offset
Voltage over Three Full Cycles and over Three Half Cycles
Rev. I | Page 32 of 36
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 115. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.00
2.90
2.80
1.70
1.60
1.50
5
1
4
2
3.00
2.80
2.60
3
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.50 MAX
0.35 MIN
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
5°
0°
0.60
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 116. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
Rev. I | Page 33 of 36
0.55
0.45
0.35
11-01-2010-A
1.30
1.15
0.90
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.80
0.55
0.40
0.23
0.09
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 117. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
DETAIL A
(JEDEC 95)
2.44
2.34
2.24
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
AREA
TOP VIEW
PKG-005136
SEATING
PLANE
SIDE VIEW
0.30
0.25
0.20
4
1
0.20 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET
COMPLIANT TO JEDEC STANDARDS MO-229-W3030D-4
Figure 118. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-11)
Dimensions shown in millimeters
Rev. I | Page 34 of 36
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
02-10-2017-C
0.50
0.40
0.30
0.80
0.75
0.70
1.70
1.60
1.50
EXPOSED
PAD
Data Sheet
ADA4084-1/ADA4084-2/ADA4084-4
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.35
0.30
0.25
0.65
BSC
16
13
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
12
1
EXPOSED
PAD
4
2.70
2.60 SQ
2.50
9
SIDE VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-004828
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-22-2017-C
0.80
0.75
0.70
5
8
0.45
0.40
0.35
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 119. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 075 mm Package Height
(CP-16-17)
Dimensions shown in millimeters
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 120. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. I | Page 35 of 36
0.75
0.60
0.45
061908-A
1.05
1.00
0.80
ADA4084-1/ADA4084-2/ADA4084-4
Data Sheet
ORDERING GUIDE
Model 1
ADA4084-1ARZ
ADA4084-1ARZ-R7
ADA4084-1ARZ-RL
ADA4084-1ARJZ-R2
ADA4084-1ARJZ-R7
ADA4084-1ARJZ-RL
ADA4084-2ARMZ
ADA4084-2ARMZ-R7
ADA4084-2ARMZ-RL
ADA4084-2ARZ
ADA4084-2ARZ-R7
ADA4084-2ARZ-RL
ADA4084-2ACPZ-R7
ADA4084-2ACPZ-RL
ADA4084-4ACPZ-R7
ADA4084-4ACPZ-RL
ADA4084-4ARUZ
ADA4084-4ARUZ-RL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
5-Lead Small Outline Transistor Package [SOT-23]
5-Lead Small Outline Transistor Package [SOT-23]
5-Lead Small Outline Transistor Package [SOT-23]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Lead Frame Chip Scale Package [LFCSP]
8-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
Z = RoHS Compliant Part.
©2011–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08237-0-5/17(I)
Rev. I | Page 36 of 36
Package Option
R-8
R-8
R-8
RJ-5
RJ-5
RJ-5
RM-8
RM-8
RM-8
R-8
R-8
R-8
CP-8-11
CP-8-11
CP-16-17
CP-16-17
RU-14
RU-14
Branding
A38
A38
A38
A2Q
A2Q
A2Q
A2Q
A2Q
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