ADF4360-1BCP

Integrated Synthesizer and VCO ADF4360-1 FEATURES Output frequency range: 2050 MHz to 2450 MHz Divide-by-2 output 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable dual-modulus prescaler 8/9, 16/17, 32/33 Programmable output power level 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode GENERAL DESCRIPTION The ADF4360-1 is a fully integrated integer-N synthesizer and voltage controlled oscillator (VCO). The ADF4360-1 is designed for a center frequency of 2250 MHz. In addition, there is a divide-by-2 option available, whereby the user gets an RF output of between 1025 MHz and 1225 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. APPLICATIONS Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD CE RSET ADF4360-1 MULTIPLEXER REFIN 14-BIT R COUNTER LOCK DETECT CLK DATA LE 24-BIT DATA REGISTER 24-BIT FUNCTION LATCH PHASE COMPARATOR VVCO VTUNE CC CN MUTE MUXOUT CHARGE PUMP CP INTEGER REGISTER VCO CORE OUTPUT STAGE RFOUTA 13-BIT B COUNTER PRESCALER P/P+1 N = (BP + A) LOAD LOAD 5-BIT A COUNTER MULTIPLEXER RFOUTB DIVSEL = 1 ÷2 AGND DGND CPGND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. 04414-0-001 DIVSEL = 2 ADF4360-1 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 Transistor Count ........................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Functional Descriptions .......................... 7 Typical Performance Characteristics ............................................. 8 Circuit Description ........................................................................... 9 Reference Input Section ............................................................... 9 Prescaler (P/P + 1)........................................................................ 9 A and B Counters ......................................................................... 9 R Counter ...................................................................................... 9 PFD and Charge Pump ................................................................ 9 MUXOUT and Lock Detect ...................................................... 10 Input Shift Register..................................................................... 10 VCO ............................................................................................. 10 Output Stage................................................................................ 11 Latch Structure ........................................................................... 12 Control Latch .............................................................................. 16 N Counter Latch ......................................................................... 17 R Counter Latch ......................................................................... 17 Applications..................................................................................... 18 Direct Conversion Modulator .................................................. 18 Fixed Frequency LO ................................................................... 19 Power-Up ..................................................................................... 19 Interfacing ................................................................................... 19 PCB Design Guidelines for Chip-Scale Package .......................... 20 Output Matching ........................................................................ 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADF4360-1 SPECIFICATIONS1 Table 1. AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Parameter REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency2 CHARGE PUMP ICP Sink/Source3 High Value Low Value RSET Range ICP 3-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH,, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage IOH, Output High Current VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VVCO AIDD4 DIDD4 IVCO4, 5 IRFOUT4 Low Power Sleep Mode4 RF OUTPUT CHARACTERISTICS5 VCO Output Frequency VCO Sensitivity Lock Time6 Frequency Pushing, (Open Loop) Frequency Pulling, (Open Loop) Harmonic Content (Second) Harmonic Content (Third) Output Power5, 7 Output Power Variation VCO Tuning Range B Version 10/250 −3/0 0 to AVDD 5.0 ±100 8 Unit MHz min/max dBm min/max V max pF max µA max MHz max With RSET = 4.7 kΩ. 2.5 0.312 2.7/10 0.2 2 1.5 2 1.5 0.6 ±1 3.0 DVDD – 0.4 500 0.4 3.0/3.6 AVDD AVDD 10 2.5 24.0 3.5–11.0 7 2050/2450 57 400 6 15 −20 −35 −13/−6 ±3 1.25/2.5 mA typ mA typ kΩ nA typ % typ % typ % typ V min V max µA max pF max V min µA max V max V min/V max CMOS output chosen. IOL = 500 µA. Conditions/Comments For f < 10 MHz, use dc-coupled CMOS compatible square wave. AC-coupled. CMOS compatible. 1.25 V ≤ VCP ≤ 2.5 V. 1.25 V ≤ VCP ≤ 2.5 V. VCP = 2.0 V. mA typ mA typ mA typ mA typ µA typ MHz min/max MHz/V typ µs typ MHz/V typ kHz typ dBc typ dBc typ dBm typ dB typ V min/max ICORE = 15 mA. RF output stage is programmeable. ICORE = 15 mA. To within 10 Hz of final frequency. Into 2.00 VSWR load. Programmable in 3 dB steps. Table 7. For tuned loads, see Output Matching section. Rev. 0 | Page 3 of 24 ADF4360-1 Parameter NOISE CHARACTERISTICS1, 5 VCO Phase Noise Performance8 B Version −110 −130 −141 −172 −163 −147 −81 0.72 −70 Unit dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ Degrees typ dBc typ Conditions/Comments @ 100 kHz offset from carrier @ 1 MHz offset from carrier @ 3 MHz offset from carrier @ 25 kHz PFD frequency @ 200 kHz PFD frequency @ 8 MHz PFD frequency @ 1 kHz offset from carrier 100 Hz to 100 kHz Synthesizer Phase Noise Floor9 In-Band Phase Noise10, 11 RMS Integrated Phase Error12 Spurious Signals due to PFD Frequency11, 13 1 2 3 Operating temperature range is: –40°C to +85°C. Guaranteed by design. Sample tested to ensure compliance. ICP is internally modified to maintain constant loop gain over the frequency range. 4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; P = 32. 5 These characteristics are guaranteed for VCO Core Power = 15 mA. 6 Jumping from 2.05 GHz to 2.45 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7 Using 50 Ω resistors to VVCO, into a 50 Ω load. For tuned loads, see Output Matching section. 8 The noise of the VCO is measured in open-loop conditions. 9 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). 10 The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer; offset frequency = 1 kHz. 11 fREFIN = 10 MHz; fPFD = 200 kHz; N = 12500; Loop B/W = 10 kHz. 12 fREFIN = 10 MHz; fPFD = 1 MHz; N = 2400; Loop B/W = 25 kHz. 13 The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer; fREFOUT = 10 MHz @ 0 dBm. Rev. 0 | Page 4 of 24 ADF4360-1 TIMING CHARACTERISTICS Table 2. AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width t4 CLOCK t5 t2 DATA DB23 (MSB) DB22 t3 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 LE t6 04414-0-002 Figure 2. Timing Diagram Rev. 0 | Page 5 of 24 ADF4360-1 ABSOLUTE MAXIMUM RATINGS Table 3. TA = 25°C, unless otherwise noted. Parameter AVDD to GND* AVDD to DVDD VVCO to GND VVCO to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Range Maximum Junction Temperature CSP θJA Thermal Impedance (Paddle Soldered) (Paddle Not Soldered) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) *GND = AGND = DGND = 0 V. Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V 150°C 50°C/W 88°C/W 215°C 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of 1 MHz), a divider can be switched on to divide the R counter output to a smaller value (see Table 9). Divide-by-2 DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2 function is chosen. When it is set to 0, normal operation occurs. Divide-by-2 Select DB23 is the divide-by-2 select bit. When programmed to 1, the divide-by-2 output is selected as the prescaler input. When set to 0, the fundamental is used as the prescaler input. For example, using the output divide-by-2 feature and a PFD frequency of 200 kHz, the user will need a value of N = 12,000 to generate 1.1 GHz. With the divide-by-2 select bit high, the user may keep N = 6,000. Reserved Bits DB23 to DB22 are spare bits and have been designated as Reser ved. They should be programmed to 0. Rev. 0 | Page 17 of 24 ADF4360-1 APPLICATIONS DIRECT CONVERSION MODULATOR Direct conversion architectures are increasingly being used to implement base station transmitters. Figure 16 shows how ADI parts can be used to implement such a system. The circuit block diagram shows the AD9761 TxDAC® being used with the AD8349. The use of dual integrated DACs, such as the AD9761 with its specified ±0.02 dB and ±0.004 dB gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain. The local oscillator is implemented using the ADF4360-1. The low-pass filter was designed using ADIsimPLL for a channel spacing of 1 MHz and an open-loop bandwidth of 25 kHz. The frequency range of the ADF4360-1 (2.05 GHz to 2.45 GHz) makes it ideally suited for implementation of a Bluetooth® transceiver. The LO ports of the AD8349 can be driven differentially from the complementar y RFOUTA and RFOUTB outputs of the ADF4360-1. This gives a better performance than a singleended LO driver and eliminates the often necessar y use of a balun to convert from a single-ended LO input to the more desirable differential LO inputs for the AD8349. The typical rms phase noise (100 Hz to 100 kHz) of the LO in this configuration is 1.09°. The AD8349 accepts LO drive levels from −10 dBm to 0 dBm. The optimum LO power can be software programmed on the ADF4360-1, which allows levels from −13 dBm to −6 dBm from each output. The RF output is designed to drive a 50 Ω load but must be accoupled, as shown in Figure 16. If the I and Q inputs are driven in quadrature by 2 V p-p signals, the resulting output power from the modulator will be approximately 2 dBm. REFIO MODULATED DIGITAL DATA IOUTA AD9761 TxDAC IOUTB LOW-PASS FILTER QOUTA FSADJ 2kΩ QOUTB LOW-PASS FILTER VVCO VDD LOCK DETECT VPS1 VPS2 100pF TO RF PA 10µF 6 21 2 23 20 IBBP 3.9kΩ 10nF 2kΩ QBBP VVCO QBBN 47nH RFOUTA 4 47nH 1.5pF 3.9nH LOIP LOIN 1.5pF 3.9nH IBBN 330pF FREFIN VVCO DVDD AVDD CE MUXOUT VTUNE 7 14 CN CP 24 1nF 1nF 16 REFIN 51Ω 17 18 680pF CLK DATA LE CC RSET AD8349 ADF4360-1 SPI COMPATIBLE SERIAL BUS 19 12 1nF 4.7kΩ 13 1 3 8 9 10 11 22 15 Figure 16. Direct Conversion Modulator Rev. 0 | Page 18 of 24 04414-0-019 CPGND AGND DGND RFOUTB 5 PHASE SPLITTER ADF4360-1 FIXED FREQUENCY LO Figure 17 shows the ADF4360-1 used as a fixed frequency LO at 2.2 GHz. The low-pass filter was designed using ADIsimPLL for a channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz. The maximum PFD frequency of the ADF4360-1 is 8 MHz. Since using a larger PFD frequency allows users to use a smaller N, the in-band phase noise is reduced to as low as possible, –99 dBc/Hz. The 40 kHz bandwidth is chosen to be just greater than the point at which the open-loop phase noise of the VCO is –99 dBc/Hz, thus giving the best possible integrated noise. The typical rms phase noise (100 Hz to 100 kHz) of the LO in this configuration is 0.3°. The reference frequency is from a 16 MHz TCXO from Fox, thus an R value of 2 is programmed. Taking into account the high PFD frequency and its effect on the band select logic, the band select clock divider is enabled. In this case, a value of 8 is chosen. A ver y simple pull-up resistor and dc blocking capacitor complete the RF output stage. VVCO VVDD LOCK DETECT ADuC812 Interface Figure 18 shows the interface between the ADF4360 family and the ADuC812 MicroConverter® Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4360 family needs a 24-bit word, which is accomplished by writing three 8bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. SCLOCK MOSI SCLK SDATA LE CE MUXOUT (Lock Detect) ADuC812 I/O Ports ADF4360-x 10µF FOX 801BE-160 16MHz 6 21 2 23 20 VVCO DVDD AVDD CE MUXOUT VTUNE 7 14 CN CP 24 1nF 1nF 16 REFIN 51Ω 17 CLK 18 DATA Figure 18. ADuC812 to ADF4360-x Interface 15.0nF 620Ω VVCO 51Ω 51Ω 3.3nF ADF4360-1 SPI COMPATIBLE SERIAL BUS 19 LE 12 CC 1nF 4.7kΩ 13 RSET 100pF RFOUTA 4 AGND 3 8 9 10 11 22 I/O port lines on the ADuC812 are also used to control powerdown (CE input) and detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the described mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz. CPGND 1 DGND RF OUTB 5 15 100pF ADSP-2181 Interface Figure 19 shows the interface between the ADF4360 family and the ADSP-21xx digital signal processor. The ADF4360 family needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Figure 17. Fixed Frequency LO POWER-UP After power-up, the part needs three writes for normal operation. The correct sequence is to the R counter latch, followed by the control latch, and N counter latch. 04414-0-023 SCLOCK MOSI TFS SCLK SDATA LE CE MUXOUT (Lock Detect) INTERFACING The ADF4360 family has a simple SPI® compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE goes high, the 24 bits that have been clocked into the appropriate register on each rising edge of CLK will get transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. The maximum allowable serial clock rate is 20 MHz. This means the maximum update rate possible is 833 kHz or one update ever y 1.2 microseconds. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds. ADSP-21xx I/O Ports ADF4360-x Figure 19. ADSP-21xx to ADF4360-x Interface Set up the word length for 8 bits and use three memor y locations for each 24-bit word. To program each 24-bit latch, store the 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. Rev. 0 | Page 19 of 24 04414-0-025 04414-0-024 ADF4360-1 PCB DESIGN GUIDELINES FOR CHIP-SCALE PACKAGE The leads on the chip-scale package (CP-24) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package lead length and 0.05 mm wider than the package lead width. The lead should be centered on the pad to ensure that the solder joint size is maximized. The bottom of the chip-scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ounce of copper to plug the via. The user should connect the printed circuit thermal pad to AGND. This is internally connected to AGND. Experiments have shown that Figure 21 provides an excellent match to 50 Ω over the operating range of the ADF4360-1. This gives approximately −4 dBm output power across the frequency range of the ADF4360-1. Both single-ended architectures can be examined using the EVAL_ADF4360-1EB1 evaluation board. VVCO 47nH 1.5pF 3.9nH 50Ω 04414-0-021 RFOUT Figure 21. Optimum ADF4360-1 Output Stage If the user does not need the differential outputs available on the ADF4360, the user may either terminate the unused output or combine both outputs using a balun. The circuit in Figure 22 shows how best to combine the outputs. VVCO 1nH RFOUTA 3.6nH 1.5pF 3.6nH 47nH 10pF 50Ω 04414-0-022 OUTPUT MATCHING There are a number of ways to match the output of the ADF4360-1 for optimum operation; the most basic is to use a 50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is connected in series as shown Figure 20. Because the resistor is not frequency dependent, this provides a good broadband match. The output power in the circuit below typically gives−6 dBm output power into a 50 Ω load. VVCO 51Ω 100pF 50Ω 04414-0-020 RFOUTB 1nH 1.5pF Figure 22. Balun for Combining ADF4360-1 RF Outputs RFOUT Figure 20. Simple ADF4360-1 Output Stage A better solution is to use a shunt inductor (acting as an RF choke) to VVCO. This gives a better match and hence more output power. Additionally, a series inductor is added after the dc bypass capacitor to provide a resonant LC circuit. This tunes the oscillator output and provides approximately 10 dB additional rejection of the second harmonic. The shunt inductor needs to be a relatively high value (>40 nH). The circuit in Figure 22 is a lumped lattice type LC balun. It is designed for a center frequency of 2.2 GHz and outputs 1.0 dBm at this frequency. The series 1 nH inductor is used to tune out any parasitic capacitance due to the board layout from each input, and the remainder of the circuit is used to shift the output of one RF input by 90° and the second by −90°, thus combining the two. The action of the 3.6 nH inductor and the 1.5 pF capacitor accomplish this. The 47 nH is used to provide an RF choke in order to feed the supply voltage, and the 10 pF capacitor provides the necessar y dc block. To ensure good RF performance, the circuits in Figure 21 and Figure 22 were implemented with Coilcraft 0402/0603 inductors and AVX 0402 thin-film capacitors. Alternatively, instead of the LC balun shown above, both outputs may be combined using a 180° rat-race coupler. Rev. 0 | Page 20 of 24 ADF4360-1 OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 0.60 MAX 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 19 18 24 1 PIN 1 INDICATOR 2.25 2.10 SQ 1.95 6 PIN 1 INDICATOR TOP VIEW 3.75 BSC SQ BOTTOM VIEW 13 12 7 0.25 MIN 2.50 REF 0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08 SEATING PLANE 0.30 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 Figure 23. 24-Lead Lead Frame Chip-Scale Package [LFCSP] (CP-24) Dimensions shown in millimeters ORDERING GUIDE Model ADF4360-1BCP ADF4360-1BCPRL ADF4360-1BCPRL7 EVAL-ADF4360-1EB1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Frequency Range 2050 MHz to 2450 MHz 2050 MHz to 2450 MHz 2050 MHz to 2450 MHz Package Option CP-24 CP-24 CP-24 Evaluation Board Rev. 0 | Page 21 of 24 ADF4360-1 NOTES Rev. 0 | Page 22 of 24 ADF4360-1 NOTES Rev. 0 | Page 23 of 24 ADF4360-1 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04414-0-8/03(0) Rev. 0 | Page 24 of 24