8-Channel Fault-Protected
Analog Multiplexer
ADG528F
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low on resistance (300 Ω typical)
Fast switching times
tON: 250 ns maximum
tOFF: 250 ns maximum
Low power dissipation (3.3 mW maximum)
Fault and overvoltage protection (−40 V to +55 V)
All switches off with power supply off
Analog output of on channel clamped within power
supplies if an overvoltage occurs
Latch-up proof construction
Break-before-make construction
TTL and CMOS compatible inputs
ADG528F
S1
D
S8
RS
APPLICATIONS
A0 A1 A2 EN
Figure 1.
Existing multiplexer applications (both fault-protected and
nonfault-protected)
New designs requiring multiplexer functions
GENERAL DESCRIPTION
1
The ADG528F is a CMOS analog multiplexer, with the
comprising eight single channels. This multiplexer provides
fault protection. Using a series n-channel, p-channel, n-channel
MOSFET structure, both device and signal source protection is
provided in the event of an overvoltage or power loss. The
multiplexer can withstand continuous overvoltage inputs
from −40 V to +55 V. During fault conditions, the multiplexer
input (or output) appears as an open circuit and only a few
nanoamperes of leakage current will flow. This protects not
only the multiplexer and the circuitry driven by the multiplexer,
but also protects the sensors or signal sources that drive the
multiplexer.
The ADG528F switches one of eight inputs to a common output
as determined by the 3-bit binary address lines A0, A1, and A2.
The ADG528F has on-chip address and control latches that
facilitate microprocessor interfacing. An EN input on the device
is used to enable or disable the device. When disabled, all channels
are switched off.
1 OF 8
DECODER
09655-001
WR
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Fault protection.
The ADG528F can withstand continuous voltage inputs
from −40 V to +55 V. When a fault occurs due to the
power supplies being turned off, all the channels are turned
off and only a leakage current of a few nanoamperes flows.
On channel turns off while fault exists.
Low RON.
Fast switching times.
Break-before-make switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
Trench isolation eliminates latch-up.
A dielectric trench separates the p-channel and n-channel
MOSFETs thereby preventing latch-up.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.
ADG528F
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
Applications ....................................................................................... 1
ESD Caution...................................................................................6
Functional Block Diagram .............................................................. 1
Pin Configuration and Function Descriptions..............................7
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................8
Product Highlights ........................................................................... 1
Terminology .................................................................................... 10
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 11
Specifications..................................................................................... 3
Test Circuits ..................................................................................... 12
Dual Supply ................................................................................... 3
Outline Dimensions ....................................................................... 15
Truth Table .................................................................................... 4
Ordering Guide .......................................................................... 15
Timing Diagrams.......................................................................... 5
REVISION HISTORY
7/11—Rev. E to Rev. F
Deleted ADG508F/ADG509F .......................................... Universal
Changes to Table 3 ............................................................................ 6
Added Table 4.................................................................................... 7
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
7/09—Rev. D to Rev. E
Updated Format .................................................................. Universal
Added TSSOP ..................................................................... Universal
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 18
4/01—Data Sheet Changed from Rev. C to Rev. D.
Changes to Ordering Guide ............................................................ 1
Changes to Specifications Table ...................................................... 2
Max Ratings Changed ...................................................................... 4
Deleted 16-Lead Cerdip from Outline Dimensions .................. 11
Deleted 18-Lead Cerdip from Outline Dimensions .................. 12
Rev. F | Page 2 of 16
ADG528F
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
RON Drift
RON Match
LEAKAGE CURRENTS
Source Off Leakage IS (Off )
Drain Off Leakage ID (Off )
Channel On Leakage ID, IS (On)
FAULT
Output Leakage Current
(With Overvoltage)
Input Leakage Current
(With Overvoltage)
Input Leakage Current
(With Power Supplies Off )
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS 1
tTRANSITION
tOPEN
tON (EN, WR)
tOFF (EN, RS)
tSETT, Settling Time
0.1%
0.01%
tW, Write Pulse Width
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulse Width
+25°C
300
B Version
−40°C to +85°C
Unit
VSS + 3
VDD − 1.5
350
V min
V max
Ω typ
400
Ω max
Test Conditions/Comments
0.6
5
%/°C typ
% max
−10 V ≤ VS ≤ +10 V, IS = 1 mA;
VDD = +15 V ± 10%, VSS = −15 V ± 10%
−10 V ≤ VS ≤ +10 V, IS = 1 mA;
VDD = +15 V ± 5%, VSS = −15 V ± 5%
VS = 0 V, IS = 1 mA
VS = 0 V, IS = 1 mA
±0.02
±1
±0.04
±1
±0.04
±1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = ±10 V, VS = +10 V;
See Figure 19
VD = ±10 V, VS = +10 V;
See Figure 20
VS = VD = ± 10 V;
See Figure 21
nA typ
μA max
μA typ
μA max
μA typ
μA max
VS = ±33 V, VD = 0 V, see Figure 20
±0.02
±2
±0.005
±2
±0.001
±2
±50
±60
±60
±2
2.4
0.8
±1
5
200
300
50
25
200
250
200
250
100
400
10
400
400
1
2.5
120
100
10
100
V min
V max
μA max
pF typ
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
μs typ
μs typ
ns min
ns min
ns min
ns min
Rev. F | Page 3 of 16
VS = ±25 V, VD = +10 V, see Figure 22
VS = ±25 V, VD = VEN = A0, A1, A2 = 0 V
See Figure 23
VIN = 0 or VDD
RL = 1 MΩ, CL = 35 pF;
VS1 = ±10 V, VS8 = +10 V; see Figure 24
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; see Figure 25
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; see Figure 26
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; see Figure 26
RL = 1 kΩ, CL = 35 pF;
VS = 5 V
ADG528F
Parameter
Charge Injection
Off Isolation
+25°C
4
68
50
5
50
CS (Off )
CD (Off )
POWER REQUIREMENTS
IDD
ISS
1
B Version
−40°C to +85°C
0.1
0.1
0.2
0.1
Unit
pC typ
dB typ
dB min
pF typ
pF typ
Test Conditions/Comments
VS = 0 V, RS = 0 Ω, CL= 1 nF; see Figure 29
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 7 V rms; see Figure 30
mA max
mA max
VIN = 0 V or 5 V
Guaranteed by design, not subject to production test.
TRUTH TABLE
Table 2. ADG528F Truth Table 1
A2
X
X
X
0
0
0
0
1
1
1
1
1
A1
X
X
X
0
0
1
1
0
0
1
1
A0
X
X
X
0
1
0
1
0
1
0
1
EN
X
X
0
1
1
1
1
1
1
1
1
WR
RS
X
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
On Switch
Retains previous switch condition
None (address and enable latches cleared)
None
1
2
3
4
5
6
7
8
X = don’t care.
Rev. F | Page 4 of 16
ADG528F
TIMING DIAGRAMS
This input data is latched on the rising edge of WR. Figure 3
shows the reset pulse width, tRS, and the reset turnoff time, tOFF
(RS). Note that all digital input signals rise and fall times are
measured from 10% to 90% of 3 V. tR = tF = 20 ns.
Figure 2 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent
and the switches respond to the address and enable inputs.
3V
WR
50%
50%
0V
tW
tS
tH
3V
A0, A1, A2
EN
09655-002
2V
0.8V
0V
Figure 2. Timing Sequence for Latching the Switch Address and Enable Inputs
3V
RS
50%
50%
0V
tRS
tOFF (RS)
VOUT
0.8VOUT
09655-003
SWITCH
OUTPUT
0V
Figure 3. Reset Pulse Width
Rev. F | Page 5 of 16
ADG528F
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Digital Input, EN, Ax
VS, Analog Input Overvoltage with
Power On (VDD = +15 V, VSS = −15 V)
VS, Analog Input Overvoltage with
Power Off (VDD = 0 V, VSS = 0 V)
Continuous Current, S or D
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
θJA, Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
44 V
−0.3 V to +25 V
+0.3 V to −25 V
−0.3 V to VDD + 2 V or 20 mA,
whichever occurs first
VSS − 25 V to VDD + 40 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40 V to +55 V
20 mA
40 mA
−40°C to +85°C
−65°C to +150°C
150°C
90°C/W
215°C
220°C
Rev. F | Page 6 of 16
ADG528F
S3
8
RS
A1
ADG528F
TOP VIEW
(Not to Scale)
9
10
11
12
13
18
A2
17
GND
16
VDD
15
S5
14
S6
NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
09655-007
7
S7
6
S2
19
S8
S1
20
NC
5
1
D
4
2
PIN 1
INDENTFIER
S4
EN
VSS
NC
3
WR
A0
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
Mnemonic
NC
WR
A0
EN
5
VSS
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
S1
S2
S3
S4
D
NC
S8
S7
S6
S5
VDD
GND
A2
A1
RS
Description
No Connect. This pin is open.
Write. The WR signal latches the state of the address control lines and the enable line.
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
No Connect. This pin is open.
Source Terminal 8. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Reset. The RS signal clears both the address and enable data in the latches resulting in no
output (all switches off ).
Rev. F | Page 7 of 16
ADG528F
TYPICAL PERFORMANCE CHARACTERISTICS
2000
2000
TA = 25°C
1750
1500
1500
1250
VDD = +5V
VSS = –5V
1000
RON (Ω)
750
750
TA = 85°C
VDD = +10V
VSS = –10V
250
250
VDD = +15V
VSS = –15V
–10
–5
0
VD, VS (V)
5
10
TA = 25°C
15
0
–15
09655-008
0
–15
Figure 5. On Resistance as a Function of VD (VS)
–10
–5
0
VD, VS (V)
5
10
15
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures
1m
1m
100µ
100µ
VDD = 0V
VSS = 0V
VD = 0V
1µ
100n
10n
OPERATING RANGE
1n
1µ
100n
10n
100p
10p
10p
–20
–10
0
10
20
30
VIN INPUT VOLTAGE (V)
40
50
60
1p
–50
09655-009
–30
Figure 6. Input Leakage Current as a Function of VS (Power Supplies Off)
During Overvoltage Conditions
OPERATING RANGE
1n
100p
–40
VDD = +15V
VSS = –15V
VD = 0V
10µ
IS INPUT LEAKAGE (A)
10µ
IS INPUT LEAKAGE (A)
TA = 125°C
500
09655-011
500
–40
–30
–20
–10
0
10
20
INPUT VOLTAGE (V)
30
40
50
60
Figure 9. Input Leakage Current as a Function of VS (Power Supplies On)
During Overvoltage Conditions
0.3
1m
100µ
VDD = +15V
VSS = –15V
VD = 0V
1µ
100n
10n
1n
VDD = +15V
VSS = –15V
TA = 25°C
0.2
LEAKAGE CURRENTS (nA)
10µ
ID INPUT LEAKAGE (A)
1000
09655-012
RON (Ω)
1250
1p
–50
VDD = +15V
VSS = –15V
1750
OPERATING RANGE
100p
IS (OFF)
0.1
IS (OFF)
0
IS (ON)
–0.1
–40
–30
–20
–10
0
10
20
30
VIN INPUT VOLTAGE (V)
40
50
60
Figure 7. Output Leakage Current as a Function of VS (Power Supplies On)
During Overvoltage Conditions
Rev. F | Page 8 of 16
–0.2
–14
–10
–6
–2
2
VS, VD (V)
6
10
Figure 10. Leakage Currents as a Function of VD (VS)
14
09655-013
1p
–50
09655-010
10p
ADG528F
280
tON (EN)
240
ID (OFF)
1
IS (OFF)
0.1
220
200
tTRANSITION
180
160
140
ID (ON)
0.01
25
35
45
55
65
75
85
95
TEMPERATURE (°C)
105
115
125
09655-014
120
Figure 11. Leakage Currents as a Function of Temperature
VIN = 2V
tON (EN)
180
tTRANSITION
160
140
tOFF (EN)
120
100
10
11
12
13
POWER SUPPLY (V)
14
15
09655-015
SWITCHING TIME (ns)
220
200
tOFF (EN)
25
45
65
85
TEMPERATURE (°C)
105
Figure 13. Switching Time vs. Temperature
260
240
100
Figure 12. Switching Time vs. Power Supply
Rev. F | Page 9 of 16
125
09655-016
10
VDD = +15V
VSS = –15V
VIN = +5V
260
VDD = +15V
VSS = –15V
VD = +10V
VS = –10V
SWITCHING TIME (ns)
LEAKAGE CURRENTS (nA)
100
ADG528F
TERMINOLOGY
VDD
Most positive power supply potential.
VSS
Most negative power supply potential.
GND
Ground (0 V) reference.
RON
Ohmic resistance between D and S.
RON Drift
Change in RON when temperature changes by one degree
Celsius.
RON Match
Difference between the RON of any two channels.
IS (Off)
Source leakage current when the switch is off.
ID (Off)
Drain leakage current when the switch is off.
ID, IS (On)
Channel leakage current when the switch is on.
VD (VS)
Analog Voltage on Terminal D and Terminal S.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
tOPEN
Off time measured between 80% points of both switches when
switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling through an off channel.
CS (Off)
Channel input capacitance for off condition.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD (Off)
Channel output capacitance for off condition.
IDD
Positive supply current.
CD, CS (On)
On switch capacitance.
ISS
Negative supply current.
CIN
Digital input capacitance.
Rev. F | Page 10 of 16
ADG528F
THEORY OF OPERATION
During fault conditions, the leakage current into and out of
the ADG528F is limited to a few microamps. This protects the
multiplexer and succeeding circuitry from over stresses as well
as protecting the signal sources, which drive the multiplexer.
Also, the other channels of the multiplexer will be undisturbed
by the overvoltage and will continue to operate normally.
–40V
OVERVOLTAGE
Rev. F | Page 11 of 16
Q1
n-CHANNEL
MOSFET IS
ON
VSS
Q2
VDD
Q3
p-CHANNEL
MOSFET IS
OFF
Figure 15. −40 V Overvoltage on an Off Channel with
Multiplexer Power On
+55V
OVERVOLTAGE
Q1
Q2
Q3
n-CHANNEL
MOSFET IS
OFF
Figure 16. +55 V Overvoltage with Power Off
n-CHANNEL
MOSFET IS
ON
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off because the gate to source voltage applied to this
MOSFET is negative.
VSS
Figure 14. +55 V Overvoltage Input to the On Channel
–40V
OVERVOLTAGE
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will turn off when an overvoltage occurs.
Q3
09655-017
n-CHANNEL
MOSFET IS
OFF
VDD
Q2
09655-018
Figure 14 to Figure 17 show the conditions of the three MOSFETs
for the various overvoltage situations. When the analog input
applied to an on channel approaches the positive power supply
line, the n-channel MOSFET turns off because the voltage on
the analog input exceeds the difference between VDD and the
n-channel threshold voltage (VTN). When a voltage more negative than VSS is applied to the multiplexer, the p-channel
MOSFET will turn off because the analog input is more
negative than the difference between VSS and the p-channel
threshold voltage (VTP). Because VTN is nominally 1.5 V and
VTP is typically 3 V, the analog input range to the multiplexer is
limited to −12 V to +13.5 V when a ±15 V power supply is used.
Q1
09655-019
When an analog input of VSS + 3 V to VDD − 1.5 V is applied
to the ADG528F, the multiplexer behaves as a standard multiplexer, with specifications similar to a standard multiplexer,
for example, the on-resistance is 400 Ω maximum. However,
when an overvoltage is applied to the device, one of the three
MOSFETs will turn off.
+55V
OVERVOLTAGE
Q1
Q2
Q3
p-CHANNEL
MOSFET IS
OFF
Figure 17. −40 V Overvoltage with Power Off
09655-020
The ADG528F multiplexer is capable of withstanding overvoltages
from −40 V to +55 V, irrespective of whether the power supplies
are present or not. Each channel of the multiplexer consists of an
n-channel MOSFET, a p-channel MOSFET, and an n-channel
MOSFET, connected in series. When the analog input exceeds the
power supplies, one of the MOSFETs will switch off, limiting the
current to submicroamp levels, thereby preventing the overvoltage
from damaging any circuitry following the multiplexer. Figure 14
illustrates the channel architecture that enables these multiplexers
to withstand continuous overvoltages.
ADG528F
TEST CIRCUITS
IDS
VDD
VSS
VDD
VSS
V1
S1
ID (ON)
A
S2
D
S
D
VD
S8
VS
RON = V1/IDS
Figure 18. On Resistance
A
S1
VSS
VDD
VSS
A
D
S2
VS
Figure 21. ID (On)
VSS
D
EN
0.8V
09655-022
EN
Figure 22. Input Leakage Current (with Overvoltage)
VSS
0V
VSS
0V
0V
VDD
VSS
A2
A1
D
S2
A0
A
EN
0.8V
GND
VS
D
WR
09655-027
09655-023
A
S8
RS
VD
VS
S1
ADG528F
ID (OFF)
S8
EN
0.8V
VS
Figure 19. IS (Off)
VDD
VDD
S8
VD
S1
VSS
S2
S8
VDD
S1
VDD
09655-026
IS (OFF)
VDD
2.4V
09655-025
09655-021
EN
VS
Figure 20. ID (Off)
Figure 23. Input Leakage Current (with Power Supplies Off)
Rev. F | Page 12 of 16
ADG528F
VIN
VDD
VSS
VDD
A2
VSS
A1
50Ω
S1
VS1
ADDRESS
DRIVE (VIN)
S2 TO S7
A0
ADG528F
2.4V
3V
S8
EN
RS
VS8
D
VOUT
RL
1MΩ
WR
GND
50%
50%
CL
35pF
90%
VOUT
tTRANSITION
09655-024
90%
tTRANSITION
Figure 24. Switching Time of Multiplexer, tTRANSITION
VDD
VSS
VSS
VDD
A2
VIN
A1
50Ω
3V
ADDRESS
DRIVE (VIN)
VS
S1
S2 TO S7
A0
ADG528F S8
2.4V
D
VOUT
RL
1kΩ
WR
GND
CL
35pF
VOUT
80%
80%
09655-029
RS
EN
tOPEN
Figure 25. Break-Before-Make Delay, tOPEN
VDD
A2
A1
VSS
3V
VSS
ENABLE
DRIVE (VIN)
VS
S1
tOFF (EN)
ADG528F
RS
EN
VIN
VOUT
D
WR
GND
VRS
50%
0V
S2 TO S8
A0
50%
VOUT
RL
1kΩ
CL
35pF
0.9VOUT
OUTPUT
09655-030
VDD
0V
tON (EN)
Figure 26. Enable Delay, tON (EN), tOFF (EN)
VSS
VDD
A2
VSS
A1
A0
2.4V
WR
VS
S1
tON (WR)
ADG528F
VOUT
EN
WR
VWR
D
GND
50%
0V
S2 TO S8
RS
VRS
3V
VOUT
RL
1kΩ
CL
35pF
OUTPUT
0.2VOUT
0V
Figure 27. Write Turn-On Time, tON (WR)
Rev. F | Page 13 of 16
09655-031
VDD
ADG528F
VSS
VDD
A2
VSS
3V
RS
VS
S1
A1
ADG528F
2.4V
EN
VOUT
RL
1kΩ
WR
GND
VIN
tRS
tOFF (RS)
VOUT
D
RS
50%
0V
S2 TO S8
A0
50%
CL
35pF
0.8VOUT
SWITCH
OUTPUT
09655-032
VDD
0V
Figure 28. Reset Turn-Off Time, tOFF (RS)
VDD
A2
VSS
A1
A0
RS
3V
RS
2.4V
ADG528
0V
D
S
VOUT
EN
VS
VIN
LOGIC
INPUT (VIN)
GND
CL
1nF
∆VOUT
VOUT
WR
QINJ = CL × ∆VOUT
Figure 29. Charge Injection
VDD
VDD
A2
S1
A1
S8
A0
VIN
ADG528F
2.4V
RS
EN
GND
D
WR
VSS
VOUT
RL
1kΩ
VSS
Figure 30. Off Isolation
Rev. F | Page 14 of 16
09655-033
VSS
09655-034
VDD
ADG528F
OUTLINE DIMENSIONS
0.180 (4.57)
0.165 (4.19)
0.048 (1.22 )
0.042 (1.07)
3
0.048 (1.22)
0.042 (1.07)
4
0.056 (1.42)
0.042 (1.07)
PIN 1
IDENTIFIER
18
TOP VIEW
(PINS DOWN)
8
0.020
(0.51)
R
9
0.20 (0.51)
MIN
19
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
14
13
0.356 (9.04)
SQ
0.350 (8.89)
0.395 (10.03)
SQ
0.385 (9.78)
0.020 (0.50)
R
BOTTOM
VIEW
(PINS UP)
0.045 (1.14)
R
0.025 (0.64)
0.120 (3.04)
0.090 (2.29)
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 31. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model 1
ADG528FBP
ADG528FBPZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
20-Lead PLCC
20-Lead PLCC
Z = RoHS Compliant Part.
Rev. F | Page 15 of 16
Package Option
P-20
P-20
ADG528F
NOTES
©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09655-0-7/11(F)
Rev. F | Page 16 of 16
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