I2C-Compatible, Wide Bandwidth, Triple 3:1 Multiplexer ADG793A/ADG793G
FEATURES
Bandwidth: 195 MHz Low insertion loss and on resistance: 2.6 Ω typical On-resistance flatness 0.3 Ω typical 3.3 V analog signal range (5 V supply, 75 Ω load) Single 3 V/5 V supply operation Low quiescent supply current: 1 nA typical Fast switching times: tON = 185 ns, tOFF = 181 ns I2C®-compatible interface Compact, 24-lead LFCSP Two I2C-controllable logic outputs ESD protection 4 kV human body model (HBM) 200 V machine model (MM) 1 kV field-induced charged device model (FICDM)
FUNCTIONAL BLOCK DIAGRAMS
VDD GND VDD GND
ADG793A
S1A S1B S1C S2A S2B S2C S3A S3B S3C I2C SERIAL INTERFACE D3 D2 D1 S1A S1B S1C S2A S2B S2C S3A S3B S3C GPO1
ADG793G
D1
D2
D3
I2C SERIAL INTERFACE
GPO2
06030-001
APPLICATIONS
RGB/YPbPr video switches HDTV Projection TV DVD-R/RW AV receivers
A0
A1
A2 SDA SCL
A0
A1
A2 SDA SCL
Figure 1.
GENERAL DESCRIPTION
The ADG793A/ADG793G are monolithic CMOS devices comprising three 3:1 multiplexers/demultiplexers controllable via a standard I2C serial interface. The CMOS process provides ultralow power dissipation, yet gives high switching speed and low on resistance. The on-resistance profile is very flat over the full analog input range, and the wide bandwidth ensures excellent linearity and low distortion. These features, combined with a wide input signal range, make the ADG793A/ADG793G the ideal switching solution for a wide range of TV applications, including RGB and YPbPr video switches. The switches conduct equally well in both directions when on. In the off condition, signal levels up to the supplies are blocked. The ADG793A/ADG793G switches exhibit break-before-make switching action. The ADG793G has two general-purpose logic output pins controllable through the I2C interface, which can be used to control other non-I2C-compatible devices such as video filters. The integrated I2C interface provides a large degree of flexibility in the system design. It has three configurable I2C address pins that allow the user to connect up to eight devices to the same bus to build larger switching arrays. The ADG793A/ADG793G operate from a single 3 V or 5 V supply voltage and are available in a compact, 4 mm × 4 mm body, 24-lead, lead-free chip scale package (LFCSP).
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 5. 6. Wide bandwidth: 195 MHz. Ultralow power dissipation. Extended input signal range. Integrated I2C serial interface. Compact, 4 mm × 4 mm body, 24-lead, lead-free chip scale package (LFCSP). ESD protection tested as per ESD Association standards: 4 kV HBM (ANSI/ESD STM5.1-2001) 200 V MM (ANSI/ESD STM5.2-1999) 1 kV FICDM (ANSI/ESDSTM5.3.1-1999)
Rev. 0
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ADG793A/ADG793G TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 I2C Timing Specifications ................................................................ 7 Timing Diagram ........................................................................... 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 11 Test Circuits..................................................................................... 14 Terminology .................................................................................... 16 Theory of Operation ...................................................................... 17 I2C Serial Interface ..................................................................... 17 I2C Address.................................................................................. 17 Write Operation.......................................................................... 17 LDSW Bit..................................................................................... 19 Power On/Software Reset.......................................................... 19 Read Operation........................................................................... 19 Evaluation Board ............................................................................ 20 Using the ADG793G Evaluation Board .................................. 20 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
7/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADG793A/ADG793G SPECIFICATIONS
VDD = 5 V ± 10%, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range 2 On Resistance, RON On-Resistance Matching Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS(OFF) Drain Off Leakage, ID(OFF) Channel On Leakage, ID(ON), IS(ON) DYNAMIC CHARACTERISTICS 3 tON, tENABLE tOFF, tDISABLE Break-Before-Make Time Delay, tD I2C-to-GPO Propagation Delay, tH, tL Off Isolation Channel-to-Channel Crosstalk Same Multiplexer Different Multiplexer −3 dB Bandwidth THD + N Charge Injection CS(OFF) CD(OFF) CD(ON), CS(ON) Power Supply Rejection Ratio, PSSR Differential Gain Error Differential Phase Error LOGIC INPUTS3 A0, A1, A2 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Input Capacitance, CIN SCL, SDA Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN Conditions VS = VDD, RL = 1 MΩ VS = VDD, RL = 75 Ω VD = 0 V, IS = −10 mA, see Figure 22 VD = 0 V to 1 V, IS = −10 mA, see Figure 22 VD = 0 V, IS = −10 mA VD = 1 V, IS = −10 mA VD = 0 V to 1 V, IS = −10 mA VD = 4 V/1 V, VS = 1 V/4 V, see Figure 23 VD = 4 V/1 V, VS = 1 V/4 V, see Figure 23 VD = VS = 4 V/1 V, see Figure 24 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V, see Figure 29 ADG793G only f = 10 MHz, RL = 50 Ω, see Figure 26 f = 10 MHz, RL = 50 Ω, see Figure 27 Min 0 0 2.6 0.15 Typ 1 Max 4 3.3 3.5 4 0.5 0.6 0.55 Unit V V Ω Ω Ω Ω Ω nA nA nA 240 235 ns ns ns ns dB dB dB MHz % pC pF pF pF dB % Degrees
0.3 ±0.25 ±0.25 ±0.25 185 181 3
1
130 −60 −55 −75 195 0.14 5 10 26 37 70 0.59 0.83
RL = 50 Ω, see Figure 25 RL = 100 Ω CL = 1 nF, VS = 0 V, see Figure 30
f = 20 kHz CCIR330 test signal CCIR330 test signal
2.0 VIN = 0 V to VDD 0.005 3 0.7 × VDD −0.3 VIN = 0 V to VDD 0.005 0.05 × VDD 3 0.8 ±1
V V μA pF V V μA V pF
VDD + 0.3 +0.3 × VDD ±1
Rev. 0 | Page 3 of 24
ADG793A/ADG793G
Parameter LOGIC OUTPUTS3 SDA Pin Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance GPO1 Pin and GPO2 Pin Output Low Voltage, VOL Output High Voltage, VOH POWER REQUIREMENTS IDD Conditions Min Typ 1 Max Unit
ISINK = 3 mA ISINK = 6 mA
0.4 0.6 ±1 10 0.4 2.0 0.001 1 0.2 0.7
V V μA pF V V μA mA mA
ILOAD = +2 mA ILOAD = −2 mA Digital inputs = 0 V or VDD, I2C interface inactive I2C interface active, fSCL = 400 kHz I2C interface active, fSCL = 3.4 MHz
1 2 3
All typical values are at TA = 25°C, unless otherwise stated. Guaranteed by initial characterization, not subject to production test. Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 24
ADG793A/ADG793G
VDD = 3 V ± 10%, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range 2 On Resistance, RON On-Resistance Matching Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS(OFF) Drain Off Leakage, ID(OFF) Channel On Leakage, ID(ON), IS(ON) DYNAMIC CHARACTERISTICS 3 tON, tENABLE tOFF, tDISABLE Break-Before-Make Time Delay, tD I2C-to-GPO Propagation Delay, tH, tL Off Isolation Channel-to-Channel Crosstalk Same Multiplexer Different Multiplexer −3 dB Bandwidth THD + N Charge Injection CS(OFF) CD(OFF) CD(ON), CS(ON) Power Supply Rejection Ratio, PSRR Differential Gain Error Differential Phase Error LOGIC INPUTS3 A0, A1, A2 Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Input Capacitance, CIN SCL, SDA Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN Conditions VS = VDD, RL = 1 MΩ VS = VDD, RL = 75 Ω VD = 0 V, IS = −10 mA, see Figure 22 VD = 0 V to 1 V, IS = −10 mA, see Figure 22 VD = 0 V, IS = −10 mA VD = 1 V, IS = −10 mA VD = 0 V to 1 V, IS = −10 mA VD = 3 V/1 V, VS = 1 V/3 V, see Figure 23 VD = 3 V/1 V, VS = 1 V/3 V, see Figure 23 VD = VS = 3 V/1 V, see Figure 24 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 CL = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V, see Figure 29 ADG793G only f = 10 MHz, RL = 50 Ω, see Figure 26 f = 10 MHz, RL = 50 Ω, see Figure 27 Min 0 0 3 0.15 Typ 1 Max 2.2 1.7 4 6 0.6 1.1 2.8 Unit V V Ω Ω Ω Ω Ω nA nA nA 260 255 ns ns ns ns dB dB dB MHz % pC pF pF pF dB % Degrees
0.3 ±0.25 ±0.25 ±0.25 200 197 3
1
121 −60 −55 −75 190 0.14 3.5 10 26 37 70 0.51 0.62
RL = 50 Ω, see Figure 25 RL = 100 Ω CL = 1 nF, VS = 0 V, see Figure 30
f = 20 kHz CCIR330 test signal CCIR330 test signal
2.0 VIN = 0 V to VDD 0.005 3 0.7 × VDD −0.3 VIN = 0 V to VDD 0.005 0.05 × VDD 3 0.8 ±1
V V μA pF V V μA V pF
VDD + 0.3 +0.3 × VDD ±1
Rev. 0 | Page 5 of 24
ADG793A/ADG793G
Parameter LOGIC OUTPUTS3 SDA Pin Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance GPO1 Pin and GPO2 Pin Output Low Voltage, VOL Output High Voltage, VOH POWER REQUIREMENTS IDD Conditions Min Typ 1 Max Unit
ISINK = 3 mA ISINK = 6 mA 3 ILOAD = +2 mA ILOAD = −2 mA Digital inputs = 0 V or VDD, I2C interface inactive I2C interface active, fSCL = 400 kHz I2C interface active, fSCL = 3.4 MHz
0.4 0.6 ±1
V V μA pF V V μA mA mA
0.4 2.0 0.001 1 0.1 0.2
1 2 3
All typical values are at TA = 25°C, unless otherwise stated. Guaranteed by initial characterization, not subject to production test. Guaranteed by design, not subject to production test.
Rev. 0 | Page 6 of 24
ADG793A/ADG793G I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; GND = 0 V; TA = −40°C to +85°C, unless otherwise noted. See Figure 2 for timing diagram. Table 3.
Parameter 1 fSCL Conditions Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode Standard mode Fast mode Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Min Max 100 400 3.4 1.7 4 0.6 60 120 4.7 1.3 160 320 250 100 10 0 0 0 0 4.7 0.6 160 4 0.6 160 4.7 1.3 4 0.6 160 20 + 0.1 CB 10 20 20 + 0.1 CB 10 20 Unit kHz kHz MHz MHz μs μs ns ns μs μs ns ns ns ns ns μs μs ns ns μs μs ns μs μs ns μs μs μs μs ns ns ns ns ns ns ns ns ns Description Serial clock frequency
t1
tHIGH, SCL high time
t2
tLOW, SCL low time
t3
tSU;DAT, data setup time
t4 2
3.45 0.9 703 150
tHD;DAT, data hold time
t5
tSU;STA, setup time for a repeated start condition
t6
tHD;STA, hold time (repeated) start condition
t7 t8
tBUF, bus free-time between a stop and a start condition tSU;STO, setup time for stop condition
t9
1000 300 80 160 300 300 80 160
tRDA, rise time of SDA signal
t10
tFDA, fall time of SDA signal
Rev. 0 | Page 7 of 24
ADG793A/ADG793G
Parameter 1 t11 Conditions Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Standard mode Fast mode High speed mode CB = 100 pF max CB = 400 pF max Fast mode High speed mode Min 20 + 0.1 CB 10 20 Max 1000 300 40 80 1000 300 80 160 300 300 40 80 50 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description tRCL, rise time of SCL signal
t11A
tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit
20 + 0.1 CB 10 20 20 + 0.1 CB 10 20 0 0
t12
tFCL, fall time of SCL signal
tSP
Pulse width of suppressed spike
1 2
Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD. A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
t11
SCL
t12
t2 t6 t4 t1 t3 t5 t10
t6
t8 t9
06030-002
SDA
t7
P S S P
Figure 2. Timing Diagram for 2-Wire Serial Interface
Rev. 0 | Page 8 of 24
ADG793A/ADG793G ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Table 4.
Parameter VDD to GND Analog, Digital Inputs Continuous Current, S or D Pins Peak Current, S or D Pins Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature θJA Thermal Impedance 24-Lead LFCSP Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (