ADP3197

6-Bit Programmable 2-/3-Phase Synchronous Buck Controller ADP3197 FEATURES Selectable 2-phase and 3-phase operation at up to 1 MHz per phase ±10 mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power good/crowbar blanking that supports on-the-fly VID code changes Digitally programmable 0.3750 V to 1.55 V output Programmable short-circuit protection with programmable latch-off delay FUNCTIONAL BLOCK DIAGRAM VCC 24 RT 9 RAMPADJ 10 SHUNT REGULATOR OSCILLATOR SET GND 15 EN 16 OD UVLO SHUTDOWN 800mV EN 1 – + CURRENT BALANCING CIRCUIT + CMP – + CMP – + CMP – RESET 23 PWM1 2.2V CSREF – + RESET 2-/3-PHASE DRIVER LOGIC RESET 22 PWM2 + DAC – 250mV – 21 PWM3 CURRENT LIMIT PWRGD 2 DELAY CROWBAR 20 SW1 TTSENSE 31 19 SW2 THERMAL THROTTLING CONTROL 18 SW3 APPLICATIONS Desktop PC power supplies for Next-generation AMD processors Voltage regulator modules (VRM) VRHOT 32 14 CSCOMP ILIMIT DELAY 8 7 CURRENT MEASUREMENT AND LIMIT + – 13 CSSUM 12 CSREF GENERAL DESCRIPTION The ADP31971 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance, Advanced Micro Devices, AMD processors. It uses an internal 6-bit digital-to-analog converter (DAC) to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.3750 V and 1.55 V. It uses a multimode pulse-width modulation (PWM) architecture to drive the logic level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-phase or 3-phase operation, allowing for the construction of up to three complementary buck switching stages. The ADP3197 supports a programmable slope function to adjust the output voltage as a function of the load current so it is always optimally positioned for a system transient. This can be disabled by connecting the LLSET pin to the CSREF pin. The ADP3197 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU. 1 IREF 17 COMP 5 PRECISION REFERENCE FBRTN 3 SOFT START CONTROL – + + – 4 FB 11 LLSET 6 SS VID DAC ADP3197 25 26 27 VID3 28 VID2 29 VID1 30 VID0 VID5 VID4 Figure 1. The ADP3197 has a built-in shunt regulator that allows the part to be connected to the 12 V system supply through a series resistor. The ADP3197 is specified over the extended commercial temperature range of 0°C to 85°C and is available in a 32-lead LFCSP. Protected by U.S. Patent Number 6,683,441; other patents pending. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. 06668-001 ADP3197 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 8 Test Circuits....................................................................................... 9 Theory of Operation ...................................................................... 10 Start-Up Sequence...................................................................... 10 Phase Detection Sequence......................................................... 10 Master Clock Frequency............................................................ 11 Output Voltage Differential Sensing ........................................ 11 Output Current Sensing ............................................................ 11 Active Impedance Control Mode............................................. 11 Current Control Mode and Thermal Balance ........................ 11 Voltage Control Mode................................................................ 12 Current Reference ...................................................................... 12 Enhanced PWM Mode .............................................................. 12 Delay Timer................................................................................. 12 Soft Start ...................................................................................... 12 Current Limit, Short-Circuit, and Latch-Off Protection ...... 13 Dynamic VID.............................................................................. 13 Power-Good Monitoring........................................................... 13 Output Crowbar ......................................................................... 14 Output Enable and UVLO ........................................................ 14 Thermal Monitoring .................................................................. 14 Typical Application Circuit....................................................... 16 Applications Information .............................................................. 17 Setting the Clock Frequency..................................................... 17 Soft Start Delay Time................................................................. 17 Current-Limit Latch-Off Delay Times .................................... 17 Inductor Selection ...................................................................... 18 Current Sense Amplifier............................................................ 18 Inductor DCR Temperature Correction ................................. 19 Output Offset .............................................................................. 20 COUT Selection ............................................................................. 20 Power MOSFETs......................................................................... 21 Ramp Resistor Selection............................................................ 22 COMP Pin Ramp ....................................................................... 23 Current-Limit Setpoint.............................................................. 23 Feedback Loop Compensation Design.................................... 23 CIN Selection and Input Current di/dt Reduction.................. 25 Thermal Monitor Design .......................................................... 25 Shunt Resistor Design................................................................ 25 Tuning the ADP3197 ................................................................. 26 Layout and Component Placement ......................................... 27 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29 REVISION HISTORY 5/07—Revision 0: Initial Version Rev. 0 | Page 2 of 32 ADP3197 SPECIFICATIONS VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted 1 Table 1. Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range 2 Accuracy Load Line Positioning Accuracy Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate LLSET Input Voltage Range LLSET Input Bias Current VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation Symbol VIREF IIREF VCOMP VFB Conditions Min Typ 1.5 15 Max Unit V μA V mV mV LSB μA μA μA MHz V/μs mV nA V V μA ns MHz kHz kHz kHz V mV μA mV nA MHz V/μs V V μA ms mV kΩ μA % μA V RIREF = 100 kΩ 14.25 0.05 −10 −78 −1 −9 15.75 4.4 10 Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF (see Figure 4) CSREF – LLSET = 80 mV IFB = 0.5 × IIREF FB forced to VOUT – 3% COMP = FB COMP = FB Relative to CSREF −80 −7.5 65 500 20 25 IFB IFBRTN ICOMP GBW(ERR) VLLSET ILLSET VIL(VID) VIH(VID) IIN(VID) −82 +1 −6 200 −250 −10 +250 +10 0.6 VIDx, VIDSEL VIDx, VIDSEL VID code change to FB change 1.4 −10 400 0.25 180 3 220 fOSC fPHASE Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Current Limit Latch-off Delay Time CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR ILIMIT Bias Current ILIMIT Voltage VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSSUM) GBW(CSA) TA = 25°C, RT = 280 kΩ, 3-phase TA = 25°C, RT = 130 kΩ, 3-phase TA = 25°C, RT = 57.6 kΩ, 3-phase RT = 280 kΩ to GND RAMPADJ − FB, DAC=1.55 V 1.9 −50 1 −1.0 −10 200 400 800 2.0 2.1 +50 50 +1.0 +10 CSSUM – CSREF (see Figure 5) CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF 10 10 0 0.05 500 8 −600 10 8 −4 9 1.09 +200 26 20 +4 11 1.33 3.5 3.5 ICSCOMP tOC(DELAY) VSWxCM RSWx ISWx ΔISWx IILIMIT VILIMIT CDELAY = 10 nF SWx = 0 V SWx = 0 V SWx = 0 V IILIMIT = 2/3 × IIREF RILIMIT = 121 kΩ (VILIMIT = IILIMIT × RILIMIT) 17 12 10 1.21 Rev. 0 | Page 3 of 32 ADP3197 Parameter Maximum Output Voltage Current Limit Threshold Voltage Current Limit Setting Ratio DELAY TIMER Normal Mode Output Current Output Current in Current Limit Threshold Voltage SOFT START Output Current (Startup) Output Current (DAC Code Change) ENABLE INPUT Threshold Voltage Hysteresis Input Current Delay Time OD OUTPUT Output Low Voltage Output High Voltage OD Pulldown Resistor THERMAL THROTTLING CONTROL T TSENSE Voltage Range T TSENSE Bias Current T TSENSE VRHOT Threshold Voltage T TSENSE Hysteresis VRHOT Output Low Voltage POWER-GOOD COMPARATOR Overvoltage Threshold Undervoltage Threshold Output Low Voltage Power-Good Delay Time During Soft Start2 VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY VCC DC Supply Current UVLO Turn On Current UVLO Threshold Voltage UVLO Threshold Voltage 1 2 Symbol VCL Conditions VCSREF − VCSCOMP, RILIMIT = 121 kΩ VCL/IILIMIT IDELAY = IIREF IDELAY(CL) = 0.25 × IIREF Min 3 80 Typ 100 82.6 15 3.75 1.7 3.75 18.75 800 100 −1 2 160 Max 125 Unit V mV mV/V μA μA V μA μA mV mV μA ms mV V kΩ IDELAY IDELAY(CL) VDELAY(TH) ISS(STARTUP) ISS(DAC) VTH(EN) VHYS(EN) IIN(EN) tDELAY(EN) VOL(OD) VOH(OD) 12 3.0 1.6 3 15 750 80 18 4.5 1.8 4.5 22.5 850 125 During startup, ISS(STARTUP) = 0.25 × IIREF DAC code change, ISS(DAC) = 1.25 × IIREF EN > 950 mV, CDELAY = 10 nF 500 4 5 60 Internally limited 0 −135 665 −123 710 50 150 5 −111 755 V μA mV mV mV mV mV mV mV mV ms μs ns V mV mV V V mA mA V VOL(VRHOT) VPWRGD(OV) VPWRGD(UV) VOL(PWRGD) IVRHOT(SINK) = −4 mA Relative to nominal DAC output; DAC = 0.5 V to 1.55 V Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V Relative to nominal DAC output; DAC = 0.5 V to 1.55 V Relative to nominal DAC output; DAC = 0.375 V to 0.4785 V IPWRGD(SINK) = −4 mA CDELAY = 10 nF 100 200 190 −300 −310 300 300 310 −200 −190 300 250 250 −250 −250 150 2 250 200 1.8 300 160 5 5 6.5 VCROWBAR Relative to FBRTN Relative to FBRTN IPWM(SINK) = −400 μA IPWM(SOURCE) = +400 μA VSYSTEM = 12 V, RSHUNT = 340 Ω (see Figure 4) 1.75 1.85 VOL(PWM) VOH(PWM) VCC IVCC VUVLO VUVLO 500 4.0 4.65 5.55 25 11 VCC rising VCC falling 9 4.1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization; not tested in production. Rev. 0 | Page 4 of 32 ADP3197 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN PWM3, RAMPADJ SW1 to SW3 370 nH at 18 A) should be inserted between the converter and the supply bus. This inductor also acts as a filter between the converter and the primary power source. THERMAL MONITOR DESIGN A thermistor is used on the TTSENSE input of the ADP3197 for monitoring the temperature of the VR. A constant current of 123 μA is sourced out of this pin and runs through a thermistor network such as the one shown in Figure 13. ADP3197 OPTIONAL TEMPERATURE ADJUST RESISTOR 32 7.5 8.0 8.5 9.0 VIN (UVLO) 9.5 10.0 10.5 Figure 14. Typical Shunt Resistor Value and Power Dissipation for Different UVLO Voltage The maximum power dissipated is calculated using Equation 45. PMAX = (V IN ( MAX ) − VCC ( MIN ) ) 2 VRHOT R SHUNT (45) 31 TTSENSE RTTSENSE Figure 13. VR Thermal Monitor Circuit A voltage is generated from this current through the thermistor and sensed inside the IC. When the voltage reaches 0.71 V, the VRHOT is set. This corresponds to RTTSENSE value of 6.58 kΩ. These values correspond to a thermistor temperature of ~100°C and ~110°C when using the same type of 100 kΩ NTC thermistor used in the current sense amplifier. 06668-022 PLACE THERMISTOR NEAR CLOSEST PHASE 0.1µF where: VIN(MAX) is the maximum voltage from the 12 V input supply (if the 12 V input supply is 12 V ± 5%, VIN(MAX) = 12.6 V; if the 12 V input supply is 12 V ± 10%, VIN(MAX) = 13.2 V). VCC(MIN) is the minimum VCC voltage of the ADP3197. This is specified as 4.75 V. RSHUNT is the shunt resistor value. The CECC standard specification for power rating in surface mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W, 1206 = 0.25 W. Rev. 0 | Page 25 of 32 06668-019 ADP3197 TUNING THE ADP3197 1. 2. Build a circuit based on the compensation values computed from the design spreadsheet. Hook up the dc load to the circuit, turn it on, and verify its operation. Also, check for jitter at no load and full load. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with 50% duty cycle. 14. Measure the output waveform (use dc offset on scope to see the waveform). Try to use a vertical scale of 100 mV/div or finer. This waveform should look similar to Figure 15. DC Load Line Setting Measure the output voltage at no load (VNL). Verify that it is within tolerance. 4. Measure the output voltage at full load cold (VFLCOLD). Let the board sit for ~10 minutes at full load, and then measure the output (VFLHOT). If there is a change of more than a few millivolts, adjust RCS1 and RCS2 using Equation 46 and Equation 49. V − V FLCOLD (46) R CS2 ( NEW ) = R CS2 (OLD ) × NL V NL − V FLHOT 5. Repeat Step 4 until the cold and hot voltage measurements remain the same. 6. Measure the output voltage from no load to full load using 5 A steps. Compute the load line slope for each change, and then average to find the overall load line slope (ROMEAS). 7. If ROMEAS is off from RO by more than 0.05 mΩ, use Equation 47 to adjust the RPH values. R (47) R PH ( NEW ) = R PH (OLD ) × OMEAS RO 8. Repeat Step 6 and Step 7 to check the load line. Repeat adjustments if necessary. 9. When the dc load line adjustment is complete, do not change RPH, RCS1, RCS2, or RTH for the remainder of the procedure. 10. Measure the output ripple at no load and full load with a scope, and make sure it is within specifications. 3. VACDRP VDCDRP Figure 15. AC Load Line Waveform 15. Use the horizontal cursors to measure VACDRP and VDCDRP, as shown in Figure 15. Do not measure the undershoot or overshoot that happens immediately after this step. 16. If VACDRP and VDCDRP are different by more than a few millivolts, use Equation 49 to adjust CCS. Users may need to parallel different values to get the right one because limited standard capacitor values are available. It is a good idea to have locations for two capacitors in the layout for this. V (48) C CS ( NEW ) = C CS (OLD ) × ACDRP V DCDRP 17. Repeat Step 11 to Step 13 and repeat the adjustments, if necessary. Once complete, do not change CCS for the remainder of the procedure. Set the dynamic load step to maximum step size. Do not use a step size larger than needed. Verify that the output waveform is square, which means that VACDRP and VDCDRP are equal. AC Load Line Setting 11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 μs/div. RCS1( NEW ) = RCS1(OLD ) × RTH (25° C ) + RCS1(OLD ) − RCS2( NEW ) × RCS1(OLD ) − RTH (25° C ) ( 1 RCS1(OLD ) + RTH (25° C ) 06668-016 )( ) − 1 RTH (25° C ) (49) Rev. 0 | Page 26 of 32 ADP3197 Initial Transient Setting 18. With the dynamic load still set at the maximum step size, expand the scope time scale to either 2 μs/div or 5 μs/div. The waveform can have two overshoots and one minor undershoot (see Figure 16). Here, VDROOP is the final desired value. Because the ADP3197 turns off all of the phases (switches inductors to ground), no ripple voltage is present during load release. Therefore, the user does not have to add headroom for ripple. This allows load release VTRANREL to be larger than VTRAN1 by the amount of ripple and still meet specifications. If VTRAN1 and VTRANREL are less than the desired final droop, capacitors can be removed. When removing capacitors, also check the output ripple voltage to make sure it is still within specifications. VDROOP LAYOUT AND COMPONENT PLACEMENT The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Recommendations VTRAN1 VTRAN2 06668-017 Figure 16. Transient Setting Waveform 19. If both overshoots are larger than desired, try making the adjustments using the following suggestions: • • • Make the ramp resistor larger by 25% (RRAMP). For VTRAN1, increase CB or increase the switching frequency. For VTRAN2, increase RA and decrease CA by 25%. For good results, a PCB with at least four layers is recommended. This provides the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 mΩ at room temperature. Whenever high currents must be routed between PCB layers, use vias liberally to create several parallel current paths, so the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3197) must cross through power circuitry, it is best to interpose a signal ground plane between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3197 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing into it. The components around the ADP3197 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB pin and the CSSUM pin. The output capacitors should be connected as close as possible to the load (or connector), for example, a microprocessor core, that receives the power. If the load is distributed, the capacitors should also be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop (as described in the Power Circuitry Recommendations section). If these adjustments do not change the response, the design is limited by the output decoupling. Check the output response every time a change is made, and check the switching nodes to ensure that the response is still stable. 20. For load release (see Figure 17), if VTRANREL is larger than the allowed overshoot, there is not enough output capacitance. Either more capacitance is needed, or the inductor values need to be made smaller. When changing inductors, start the design again using a spreadsheet and this tuning procedure. VTRANREL VDROOP Figure 17. Transient Setting Waveform 06668-018 Rev. 0 | Page 27 of 32 ADP3197 Power Circuitry Recommendations The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system and noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing; and it accommodates the high current demand with minimal voltage loss. When a power dissipating component, for example, a power MOSFET, is soldered to a PCB, it is recommended that vias be used liberally, both directly on the mounting pad and immediately surrounding it. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat-sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation in the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. Signal Circuitry Recommendations The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB trace and FBRTN trace should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller. Rev. 0 | Page 28 of 32 ADP3197 OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 17 16 8 3.25 3.10 SQ 2.95 0.50 0.40 0.30 9 0.25 MIN 3.50 REF 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model ADP3197JCPZ-RL1 1 Temperature Range 0°C to 85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Package Option CP-32-2 Ordering Quantity 2,500 Z = RoHS Compliant Part. Rev. 0 | Page 29 of 32 ADP3197 NOTES Rev. 0 | Page 30 of 32 ADP3197 NOTES Rev. 0 | Page 31 of 32 ADP3197 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 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