ADP5041CP-1-EVALZ

Micro PMU with 1.2 A Buck, Two 300 mA LDOs, Supervisory, Watchdog, and Manual Reset ADP5041 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VOUT1 RFILT = 30Ω AVIN L1 1µH SW VBIAS VIN1 = 2.3V TO 5.5V VOUT1 AT 1.2A C6 10µF R1 R2 VIN1 PGND C1 4.7µF EN_BK ON VIN2 C2 1µF LDO1 (DIGITAL) ON PSM/PWM VOUT2 VOUT2 AT 300mA R3 FB2 EN_LDO1 OFF FPWM MODE EN1 OFF VIN2 = 1.7V TO 5.5V BUCK FB1 R4 C5 2.2µF EN2 nRSTO VBIAS MR SUPERVISOR µP WDI VTHR ON OFF VIN3 = 1.7V TO 5.5V EN3 VIN3 C3 1µF R4 EN_LDO2 VOUT3 LDO2 (ANALOG) FB3 R3 AGND R5 VOUT3 AT 300mA R7 C6 2.2µF 09652-001 Input voltage range: 2.3 V to 5.5 V One 1.2 A buck regulator Two 300 mA LDOs 20-lead, 4 mm × 4 mm LFCSP package Overcurrent and thermal protection Soft start Undervoltage lockout Open-drain processor reset with externally adjustable threshold monitoring Guaranteed reset output valid to VAVIN = 1 V Manual reset input Watchdog refresh input Buck key specifications Output voltage range: 0.8 V to 3.8 V Current mode topology for excellent transient response 3 MHz operating frequency Peak efficiency up to 96% Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PWM/PSM mode 100% duty cycle low dropout mode LDOs key specifications Output voltage range: 0.8 V to 5.2 V Low input supply voltage from 1.7 V to 5.5 V Stable with 2.2 μF ceramic output capacitors High PSRR Low output noise Low dropout voltage −40°C to +125°C junction temperature range Figure 1. GENERAL DESCRIPTION The ADP5041 combines one high performance buck regulator and two low dropout (LDO) regulators in a small 20-lead LFCSP to meet demanding performance and board space requirements. range of the ADP5041 LDOs extend the battery life of portable devices. The ADP5041 LDOs maintain a power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. The high switching frequency of the buck regulator enables use of tiny multilayer external components and minimizes board space. Each regulator in the ADP5041 is activated by a high level on the respective enable pin. The output voltages of the regulators and the reset threshold are programmed through external resistor dividers to address a variety of applications. The ADP5041 contains supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. They also provide power-on reset signals. An on-chip watchdog timer can reset the microprocessor if it fails to strobe within a preset timeout period. When the MODE pin is set to logic high, the buck regulator operates in forced PWM mode. When the MODE pin is set to logic low, the buck regulator operates in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold, the regulator operates in power save mode (PSM), improving the light load efficiency. The low quiescent current, low dropout voltage, and wide input voltage Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5041 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Buck Section................................................................................ 27 Functional Block Diagram .............................................................. 1 LDO Section ............................................................................... 28 General Description ......................................................................... 1 Supervisory Section ................................................................... 28 Revision History ............................................................................... 2 Applications Information .............................................................. 31 Specifications..................................................................................... 3 Buck External Component Selection....................................... 31 General Specifications ................................................................. 3 LDO External Component Selection ...................................... 32 Supervisory Specifications .......................................................... 3 Output Capacitor........................................................................ 32 Buck Specifications....................................................................... 4 Supervisory Section ................................................................... 33 LDO1, LDO2 Specifications ....................................................... 5 Power Dissipation/Thermal Considerations ............................. 34 Input and Output Capacitor, Recommended Specifications .. 6 Application Diagram ................................................................. 36 Absolute Maximum Ratings............................................................ 7 PCB Layout Guidelines .................................................................. 37 Thermal Resistance ...................................................................... 7 Suggested Layout ........................................................................ 37 ESD Caution .................................................................................. 7 Bill of Materials ........................................................................... 38 Pin Configuration and Function Descriptions ............................. 8 Factory Programmable Options ................................................... 39 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 40 Theory of Operation ...................................................................... 26 Ordering Guide .......................................................................... 40 Power Management Unit ........................................................... 26 REVISION HISTORY 5/2019—Rev. A to Rev. B Changes to Figure 109 .................................................................... 32 4/2018—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 40 Changes to Ordering Guide .......................................................... 40 12/2011—Revision 0: Initial Version Rev. B | Page 2 of 40 Data Sheet ADP5041 SPECIFICATIONS GENERAL SPECIFICATIONS AVIN, VIN1 = 2.3 V to 5.5 V; AVIN, VIN1 ≥ VIN2, VIN3; VIN2, VIN3 = 1.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 1. Parameter AVIN UNDERVOLTAGE LOCKOUT Input Voltage Rising Option 0 Option 1 Input Voltage Falling Option 0 Option 1 SHUTDOWN CURRENT Thermal Shutdown Threshold Thermal Shutdown Hysteresis START-UP TIME1 Buck LDO1, LDO2 ENx, WDI, MODE, MR INPUTS Input Logic High Input Logic Low Input Leakage Current OPEN-DRAIN OUTPUT nRSTO Output Voltage Symbol UVLOAVIN UVLOAVINRISE Min Typ Max Unit 2.275 3.9 V V 2 V V μA °C °C UVLOAVINFALL 1.95 3.1 IGND-SD TSSD TSSD-HYS ENx = GND TJ rising 0.1 150 20 tSTART1 tSTART2 VOUT2, VOUT3 = 3.3 V VIH VIL VI-LEAKAGE 2.5 V ≤ AVIN ≤ 5.5 V 2.5 V ≤ AVIN ≤ 5.5 V ENx = AVIN or GND VOL1V VOL1V2 VOL2V7 VOL4V5 AVIN ≥ 1.0 V, ISINK = 50 μA AVIN ≥ 1.2 V, ISINK = 100 μA AVIN ≥ 2.7 V, ISINK = 1.2 mA AVIN ≥ 4.5 V, ISINK = 3.2 mA AVIN = 5.5 V Open-Drain Reset Output Leakage Current 1 Test Conditions/Comments 250 85 μs μs 1.2 0.05 0.4 1 V V μA 0.3 0.3 0.3 0.4 1 V V V V μA Start-up time is defined as the time from the moment EN1 = EN2 = EN3 transfers from 0 V to VAVIN to the moment VOUT1, VOUT2, and VOUT3 are reaching 90% of their nominal levels. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information. SUPERVISORY SPECIFICATIONS AVIN, VIN1 = 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. Table 2. Parameter SUPPLY Supply Current (Supervisory Circuit Only) Min Typ Max Unit Test Conditions/Comments 0.495 55 52 0.505 μA μA V AVIN = VIN1 = EN1 = EN2 = EN3 = 5.5 V AVIN = VIN1 = EN1 = EN2 = EN3 = 3.6 V THRESHOLD VOLTAGE RESET TIMEOUT PERIOD Option 0 Option 1 VCC TO RESET DELAY (tRD) 45 43 0.500 30 200 80 36 240 ms ms μs 24 160 Rev. B | Page 3 of 40 VIN falling at 1 mV/μs ADP5041 Data Sheet Parameter WATCHDOG INPUT Watchdog Timeout Period Option 0 Option 1 WDI Pulse Width WDI Input Threshold Min Typ Max Unit Test Conditions/Comments 81.6 1.28 80 102 1.6 122.4 1.92 ms sec ns VIL = 0.4 V, VIH = 1.2 V 1.2 V 20 −15 μA μA VWDI = VCC, time average VWDI = 0 V, time average μs ns kΩ Ns VCC = 5 V 0.4 WDI Input Current (Source) WDI Input Current (Sink) MANUAL RESET INPUT MR Input Pulse Width MR Glitch Rejection MR Pull-Up Resistance MR to Reset Delay 8 −30 15 −25 1 25 220 52 280 90 BUCK SPECIFICATIONS AVIN, VIN1 = 2.3 V to 5.5 V; VOUT1 = 1.8 V; L = 1 μH; CIN = 10 μF; COUT = 10 μF; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.1 Table 3. Parameter INPUT CHARACTERISTICS Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Accuracy Line Regulation Load Regulation VOLTAGE FEEDBACK PWM TO POWER SAVE MODE CURRENT THRESHOLD INPUT CURRENT CHARACTERISTICS DC Operating Current Symbol Shutdown Current SW CHARACTERISTICS SW On Resistance ISHTD VIN1 VOUT1 (ΔVOUT1/VOUT1)/ΔVIN1 (ΔVOUT1/VOUT1)/ΔIOUT1 VFB1 IPSM_L INOLOAD RPFET RNFET Current Limit ACTIVE PULL-DOWN OSCILLATOR FREQUENCY 1 Test Conditions/Comments ILIMIT Min Typ 2.3 PWM mode, ILOAD = 0 mA to 1200 mA PWM mode ILOAD = 0 mA to 1200 mA, PWM mode −3 0.485 MODE = ground ILOAD = 0 mA, device not switching, all other channels disabled EN1 = 0 V, TA = TJ = −40°C to +125°C −0.05 −0.1 0.5 100 Max Unit 5.5 V +3 % %/V %/A V mA 0.515 21 35 μA 0.2 1.0 μA PFET, AVIN = VIN1 = 3.6 V 180 240 mΩ PFET, AVIN = VIN1 = 5 V NFET, AVIN = VIN1 = 3.6 V NFET, AVIN = VIN1 = 5 V PFET switch peak current limit EN1 = 0 V 140 170 150 1950 85 3.0 190 235 210 2300 mΩ mΩ mΩ mA Ω MHz fOSC 1600 2.5 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Rev. B | Page 4 of 40 3.5 Data Sheet ADP5041 LDO1, LDO2 SPECIFICATIONS VIN2, VIN3 = (VOUT2, VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; AVIN, VIN1 ≥ VIN2, VIN3; CIN = 1 μF, COUT = 2.2 μF; TJ= −40°C to +125°C for minimum/maximum specifications and TA = 25°C for typical specifications, unless otherwise noted.1 Table 4. Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Bias Current per LDO2 Symbol VIN2, VIN3 Conditions TJ = −40°C to +125°C Min 1.7 Typ Max 5.5 Unit V IOUT3 = IOUT4 = 0 μA 10 30 μA IOUT2 = IOUT3 = 10 mA IOUT2 = IOUT3 = 300 mA 60 165 100 245 μA μA LDO1 or LDO2 Only Includes all current into AVIN, VIN1, VIN2, and VIN3 IOUT2 = IOUT3 = 0 μA, all other channels disabled 53 μA LDO1 and LDO2 Only IOUT2 = IOUT3 = 0 μA, buck disabled 74 μA Total System Input Current OUTPUT VOLTAGE ACCURACY IVIN2BIAS/IVIN3BIAS IIN VOUT2, VOUT3 100 μA < IOUT2 < 300 mA, 100 μA < IOUT3 < 300 mA VIN2 = (VOUT2 + 0.5 V) to 5.5 V VIN3 = (VOUT3 + 0.5 V) to 5.5 V REFERENCE VOLTAGE REGULATION Line Regulation Load Regulation3 DROPOUT VOLTAGE4 ACTIVE PULL-DOWN CURRENT-LIMIT THRESHOLD5 OUTPUT NOISE VFB2,VFB3 (ΔVOUT2/VOUT2)/ΔVIN2 (ΔVOUT3/VOUT3)/ΔVIN3 (ΔVOUT2/VOUT2)/ΔIOUT2 (ΔVOUT3/VOUT3)/ΔIOUT3 VDROPOUT RPDLDO ILIMIT OUTLDO2NOISE OUTLDO1NOISE POWER SUPPLY REJECTION RATIO PSRR −3 0.485 VIN2 = (VOUT2 + 0.5 V) to 5.5 V VIN3 = (VOUT3 + 0.5 V) to 5.5 V 0.500 −0.03 +3 % 0.515 V +0.03 %/ V 0.0075 %/mA IOUT2 = IOUT3 = 1 mA IOUT2 = IOUT3 = 1 mA to 300 mA 0.002 VOUT2 = VOUT3 = 5.0 V, IOUT2 = IOUT3 = 300 mA 72 VOUT2 = VOUT3 = 3.3 V, IOUT2 = IOUT3 = 300 mA 86 VOUT2 = VOUT3 = 2.5 V, IOUT2 = IOUT3 = 300 mA 107 VOUT2 = VOUT3 = 1.8 V, IOUT2 = IOUT3 = 300 mA 180 mV EN2/EN3 = 0 V TJ = −40°C to +125°C 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V 1 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 100 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 600 470 123 110 59 140 129 66 66 Ω mA μV rms μV rms μV rms μV rms μV rms μV rms 57 dB 60 dB 1 335 mV 140 mV mV dB All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). This is the input current into VIN2 and VIN3 that is not delivered to the output load. Based on an end-point calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. 2 3 Rev. B | Page 5 of 40 ADP5041 Data Sheet INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 5. Parameter INPUT CAPACITANCE (BUCK)1 OUTPUT CAPACITANCE (BUCK)2 INPUT AND OUTPUT CAPACITANCE3 (LDO1, LDO2) CAPACITOR ESR Symbol CMIN1 CMIN2 CMIN34 RESR Test Conditions/Comments TJ = −40°C to +125°C TJ = −40°C to +125°C TJ = −40°C to +125°C TJ = −40°C to +125°C 1 Min 4.7 7 0.70 0.001 Typ Max 40 40 1 Unit μF μF μF Ω The minimum input capacitance should be greater than 4.7 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas Y5V and Z5U capacitors are not recommended for use with the buck. 2 The minimum output capacitance should be greater than 7 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas Y5V and Z5U capacitors are not recommended for use with the buck. 3 The minimum input and output capacitance should be greater than 0.70 μF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas Y5V and Z5U capacitors are not recommended for use with LDOs. Rev. B | Page 6 of 40 Data Sheet ADP5041 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVIN to AGND VIN1 to AVIN PGND to AGDN VIN2, VIN3, VOUTx, ENx, MODE, MR, WDI, nRSTO, FBx, VTHR, SW to AGND SW to PGND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions ESD Human Body Model ESD Charged Device Model ESD Machine Model THERMAL RESISTANCE Rating −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to (AVIN + 0.3 V) −0.3 V to (VIN1 + 0.3 V) −65°C to +150°C −40°C to +125°C JEDEC J-STD-020 3000 V 1500 V 200 V Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 7. Thermal Resistance Package Type 20-Lead, 0.5 mm pitch LFCSP ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 7 of 40 θJA 38 θJC 4.2 Unit °C/W ADP5041 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP5041 20 19 18 17 16 MR WDI VTHR MODE EN2 TOP VIEW (Not to Scale) 15 14 13 12 11 1 2 3 4 5 FB2 VOUT2 VIN2 FB1 VOUT1 NOTES 1. EXPOSED PAD MUST BE CONNECTED TO SYSTEM GROUND PLANE. 09652-002 AVIN 6 VIN1 7 SW 8 PGND 9 EN1 10 FB3 VOUT3 VIN3 EN3 nRSTO Figure 2. Pin Configuration—View from Top of the Die Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Mnemonic FB3 VOUT3 VIN3 EN3 nRSTO AVIN VIN1 SW PGND EN1 VOUT1 FB1 VIN2 VOUT2 FB2 EN2 MODE 18 19 20 0 VTHR WDI MR EPAD Description LDO2 Feedback Input. LDO2 Output Voltage. LDO2 Input Supply (1.7 V to 5.5 V). Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2. Open-Drain Reset Output, Active Low. Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V). Buck Input Supply (2.3 V to 5.5 V). Buck Switching Node. Dedicated Power Ground for Buck Regulator. Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck. Buck Output Sensing Node. Buck Feedback Input. LDO1 Input Supply (1.7 V to 5.5 V). LDO1 Output Voltage. LDO1 Feedback Input. Enable LDO1. EN2 = high: turn on LDO1; EN2 = low: turn off LDO1. Buck Mode. MODE = high; buck regulator operates in fixed PWM mode; MODE = low; buck regulator operates in power saving mode (PSM) at light load and in constant PWM at higher load. Reset Threshold Programming. Watchdog Refresh Input from Processor. If WDI is in high-Z, watchdog is disabled. Manual Reset Input, Active Low. Exposed Pad (Analog Ground). The exposed pad must be connected to the system ground plane. Rev. B | Page 8 of 40 Data Sheet ADP5041 TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted. 4 VOUT1 SW 2 VOUT1 2 VOUT2 3 EN VOUT3 4 CH4 2.0V/DIV 1MΩ BW 500M CH2 2.0V/DIV 1MΩ BW 20.0M CH3 2.0V/DIV 1MΩ BW 500M A CH2 1.88V 3 IIN CH1 CH2 CH3 CH4 200µs/DIV 1.0MS/s 1.0µs/pt 1MΩ BW 20.0M 1MΩ BW 500M 1MΩ BW 20.0M 1MΩ BW 500M A CH1 2.32V 50µs/DIV 2.0MS/s 500ns/pt Figure 6. Buck Startup, VOUT1 = 3.3 V, IOUT2 = 20 mA Figure 3. 3-Channel Start-Up Waveforms VOUT3 4 4.0V/DIV 3.0V/DIV 200mA/DIV 5.0V/DIV 09652-006 09652-003 1 SW 4 VOUT2 2 2 VOUT1 VOUT1 1 EN 1 CH1 CH2 CH3 CH4 2.0V/DIV 2.0V/DIV 300mA/DIV 2.0V/DIV 1MΩ BW 20.0M 1MΩ BW 20.0M 1MΩ BW 20.0M 1MΩ BW 20.0M A CH1 1.08V 3 200µs/DIV 5.0MS/s 200ns/pt IIN CH1 CH2 CH3 CH4 Figure 4. Total Inrush Current, All Channels Started Simultaneously 8.0V/DIV 2.0V/DIV 200mA/DIV 5.0V/DIV 09652-007 09652-004 IIN 3 1MΩ BW 20.0M A CH1 1MΩ BW 500.0M 1MΩ BW 20.0M 1MΩ BW 500.0M 1.12V 50µs/DIV 2.0MS/s 500ns/pt Figure 7. Buck Startup, VOUT1 = 1.8 V, IOUT = 20 mA 1.0 0.9 SW 0.8 4 0.7 IIN (mA) 0.6 VOUT1 0.5 2 0.4 EN 0.3 1 0.2 2.9 3.4 3.9 VIN (V) 4.4 4.9 5.4 09652-005 0 2.4 IIN CH1 CH2 CH3 CH4 8.0V/DIV 2.0V/DIV 200mA/DIV 5.0V/DIV 09652-008 3 0.1 1MΩ BW 20.0M A CH1 1MΩ BW 500.0M 1MΩ BW 20.0M 1MΩ BW 500.0M 640mV 50µs/DIV 2.0MS/s 500ns/pt Figure 8. Buck Startup, VOUT1 = 1.2 V, IOUT = 20 mA Figure 5. System Quiescent Current (Sum of All the Input Currents) vs. Input Voltage, VOUT1 = 1.8 V, VOUT2 = VOUT3 = 3.3 V, (UVLO = 3.3 V) Rev. B | Page 9 of 40 ADP5041 Data Sheet 3.90 1.24 –40°C +25°C +85°C 3.88 1.23 OUTPUT VOLTAGE (V) 3.84 3.82 3.80 3.78 3.76 3.74 0.1 1 OUTPUT CURRENT (A) 0.1 1 OUTPUT CURRENT (A) Figure 12. Buck Load Regulation Across Temperature, VOUT1 = 1.2 V, Auto Mode Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 3.8 V, Auto Mode 3.90 3.39 –40°C +25°C +85°C 3.37 –40°C +25°C +85°C 3.88 3.86 3.35 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.20 1.18 0.01 09652-009 3.70 0.01 1.21 1.19 –40°C +25°C +85°C 3.72 1.22 09652-012 OUTPUT VOLTAGE (V) 3.86 3.33 3.31 3.29 3.84 3.82 3.80 3.78 3.76 3.74 3.27 0.1 1 OUTPUT CURRENT (A) 3.70 0.01 3.32 1.820 –40°C +25°C +85°C 1.815 –40°C +25°C +85°C 3.31 OUTPUT VOLTAGE (V) 1.810 1.805 1.800 1.795 1.790 3.30 3.29 3.28 3.27 3.26 1.785 1 OUTPUT CURRENT (A) Figure 11. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, Auto Mode 3.25 0.01 09652-011 0.1 0.1 1 OUTPUT CURRENT (A) Figure 14. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, PWM Mode Rev. B | Page 10 of 40 09652-014 OUTPUT VOLTAGE (V) 1 Figure 13. Buck Load Regulation Across Temperature, VOUT1 = 3.8 V, PWM Mode Figure 10. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode 1.780 0.01 0.1 OUTPUT CURRENT (A) 09652-013 3.72 09652-010 3.25 0.01 Data Sheet ADP5041 1.820 100 –40°C +25°C +85°C 1.815 90 VIN = 4.5V 80 VIN = 5.5V 70 EFFICIENCY (%) OUTPUT VOLTAGE (V) 1.810 1.805 1.800 1.795 60 50 40 30 1.790 20 1.785 0 0.001 09652-015 0.1 1 OUTPUT CURRENT (A) 0.1 1 OUTPUT CURRENT (A) Figure 15. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode Figure 18. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.8 V, PWM Mode 1.205 100 –40°C +25°C +85°C 1.200 90 80 VIN = 3.6V VIN = 4.5V VIN = 5.5V 70 EFFICIENCY (%) OUTPUT VOLTAGE (V) 0.01 09652-018 10 1.780 0.01 1.195 1.190 60 50 40 30 1.185 20 0 0.0001 09652-016 0.1 1 OUTPUT CURRENT (A) 1 100 90 90 VIN = 4.5V VIN = 3.6 VIN = 4.5 80 VIN = 5.5V VIN = 5.5 70 EFFICIENCY (%) 70 50 40 60 50 40 30 30 20 20 10 10 0.001 0.01 0.1 1 OUTPUT CURRENT (A) Figure 17. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.8 V, Auto Mode 0 0.001 0.01 0.1 1 OUTPUT CURRENT (A) Figure 20. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, PWM Mode Rev. B | Page 11 of 40 09652-020 60 09652-017 EFFICIENCY (%) 0.1 Figure 19. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, Auto Mode 100 0 0.0001 0.01 OUTPUT CURRENT (A) Figure 16. Buck Load Regulation Across Temperature, VOUT1 = 1.2 V, PWM Mode 80 0.001 09652-019 10 1.180 0.01 Data Sheet 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 60 50 40 30 30 10 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 10 0 0.001 100 100 90 90 80 80 70 70 EFFICIENCY (%) EFFICIENCY (%) 1 Figure 24. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.2 V, PWM Mode 60 50 40 60 50 40 30 30 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 10 0 0.001 0.01 0.1 20 1 OUTPUT CURRENT (A) –40°C +25°C +85°C 10 0 0.0001 09652-022 20 0.001 0.01 0.1 1 OUTPUT CURRENT (A) Figure 22. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.8 V, PWM Mode Figure 25. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 3.3 V, Auto Mode 100 90 90 80 80 70 70 EFFICIENCY (%) 100 60 50 40 60 50 40 30 30 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 20 10 0.001 0.01 0.1 1 OUTPUT CURRENT (A) Figure 23. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.2 V, Auto Mode 20 –40°C +25°C +85°C 10 0 0.001 09652-023 EFFICIENCY (%) 0.1 OUTPUT CURRENT (A) Figure 21. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.8 V, Auto Mode 0 0.0001 0.01 09652-025 0 0.0001 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 20 09652-021 20 09652-024 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 0.01 0.1 1 OUTPUT CURRENT (A) Figure 26. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 3.3 V, PWM Mode Rev. B | Page 12 of 40 09652-026 EFFICIENCY (%) ADP5041 ADP5041 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 60 50 40 30 30 20 0.001 0.01 0.1 1 OUTPUT CURRENT (A) –40°C +25°C +85°C 10 0 0.001 09652-027 10 0 0.0001 20 –40°C +25°C +85°C 0.01 0.1 09652-030 EFFICIENCY (%) Data Sheet 1 OUTPUT CURRENT (A) Figure 30. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.2 V, PWM Mode Figure 27. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.8 V, Auto Mode 100 2.5 90 OUTPUT CURRENT (A) 60 50 40 30 0.5 –40°C +25°C +85°C 0 0.001 0.01 0.1 0 3.4 09652-028 10 1 OUTPUT CURRENT (A) 90 1.8 80 1.6 70 1.4 OUTPUT CURRENT (A) 2.0 60 50 40 30 0.01 0.1 1 OUTPUT CURRENT (A) 5.4 VOUT = 1.8V 1.2 1.0 0.8 0.6 0.2 0 2.4 09652-029 0.001 4.9 0.4 –40°C +25°C +85°C 10 4.4 Figure 31. Buck DC Current Capability vs. Input Voltage 100 20 3.9 VIN (V) Figure 28. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.8 V, PWM Mode EFFICIENCY (%) 1.0 09652-031 20 1.5 2.9 3.4 3.9 4.4 4.9 VIN (V) Figure 32. Buck DC Current Capability vs. Input Voltage Figure 29. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.2 V, Auto Mode Rev. B | Page 13 of 40 5.4 09652-032 EFFICIENCY (%) 70 0 0.0001 VOUT = 3.3V 2.0 80 ADP5041 Data Sheet 2.0 VOUT VOUT = 1.2V 1.8 1.6 4 OUTPUT CURRENT (A) 1.4 1.2 ISW 2 1.0 0.8 0.6 SW 0.4 0.2 3.4 3.9 4.4 4.9 CH2 200mA/DIV 1MΩ BW 20.0M CH3 3.0V/DIV 1MΩ BW 20.0M 20.0M CH4 40.0mV/DIV 09652-033 2.9 5.4 VIN (V) A CH1 640mV 5µs/DIV 500MS/s 2.0ns/pt 09652-036 3 0 2.4 Figure 36. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, Auto Mode Figure 33. Buck DC Current Capability vs. Input Voltage 2.94 VOUT 2.92 2.90 ISW 2.88 2 2.86 2.84 SW –40°C +25°C +85°C 2.80 0 0.2 0.4 0.6 0.8 1.0 3 1.2 OUTPUT CURRENT (A) 09652-034 2.82 Figure 34. Buck Switching Frequency vs. Output Current, Across Temperature, VOUT1 = 1.8 V, PWM Mode 4 CH2 200mA/DIV 1MΩ BW 20.0M CH3 3.0V/DIV 1MΩ BW 20.0M 20.0M CH4 40.0mV/DIV A CH3 1.14V 5µs/DIV 500MS/s 2.0ns/pt 09652-037 FREQUENCY (MHz) 4 Figure 37. Typical Waveforms, VOUT1 = 1.2 V, IOUT1 = 30 mA, Auto Mode VOUT VOUT 4 ISW ISW 2 2 SW SW A CH1 640mV 5µs/DIV 500MS/s 2.0ns/pt CH2 200mA/DIV 1MΩ BW 20.0M CH3 3.0V/DIV 1MΩ BW 20.0M 20.0M CH4 10.0mV/DIV 09652-035 CH2 200mA/DIV 1MΩ BW 20.0M CH3 3.0V/DIV 1MΩ BW 20.0M 20.0M CH4 40.0mV/DIV Figure 35. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode A CH1 640mV 200ns/DIV 500MS/s 2.0ns/pt 09652-038 3 3 Figure 38. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode Rev. B | Page 14 of 40 Data Sheet ADP5041 VOUT 4 VIN ISW VOUT 2 2 3 SW SW 1 A CH1 640mV 200ns/DIV 500MS/s 2.0ns/pt B 400M CH1 3.0V/DIV W B 20.0M CH2 30.0mV/DIV W 1MΩ BW 20.0M CH3 1.0V/DIV 09652-039 CH2 200mA/DIV 1MΩ BW 20.0M CH3 3.0V/DIV 1MΩ BW 20.0M 20.0M CH4 20.0mV/DIV Figure 39. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode A CH3 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt 09652-042 3 Figure 42. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.8 V, IOUT1 = 5 mA, Auto Mode VOUT VIN 4 ISW VOUT 2 2 SW 3 SW 1 A CH3 1.14V 200ns/DIV 500MS/s 2.0ns/pt B 400M CH1 3.0V/DIV W B 20.0M CH2 50.0mV/DIV W B 1MΩ CH3 1.0V/DIV W 20.0M 09652-040 CH2 200mA/DIV 1MΩ BW 20.0M CH3 3.0V/DIV 1MΩ BW 20.0M 20.0M CH4 40.0mV/DIV Figure 40. Typical Waveforms, VOUT1 = 1.2 V, IOUT1 = 30 mA, PWM Mode A CH3 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt 09652-043 3 Figure 43. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.2 V, IOUT1 = 5 mA, Auto Mode VIN VIN VOUT VOUT 2 3 SW 1 SW 1 A CH3 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt B 400M CH1 3.0V/DIV W B 20.0M CH2 50.0mV/DIV W 1MΩ BW 20.0M CH3 1.0V/DIV 09652-041 B 400M CH1 3.0V/DIV W B 20.0M CH2 50.0mV/DIV W 1MΩ BW 20.0M CH3 1.0V/DIV Figure 41. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 3.3 V, IOUT1 = 5 mA, Auto Mode A CH3 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt 09652-044 3 2 Figure 44. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 3.3 V, PWM Mode Rev. B | Page 15 of 40 ADP5041 Data Sheet SW VIN 1 VOUT VOUT 2 3 2 SW IOUT 1 A CH3 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M 09652-045 B 400M CH1 3.0V/DIV W B 20.0M CH2 20.0mV/DIV W 1MΩ BW 20.0M CH3 1.0V/DIV Figure 45. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.8 V, PWM Mode A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 09652-048 3 Figure 48. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 3.3 V, Auto Mode SW VIN 1 2 3 VOUT VOUT 2 SW 1 IOUT A CH3 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M 09652-046 B 20.0M CH1 3.0V/DIV W B 20.0M CH2 50.0mV/DIV W 1MΩ BW 20.0M CH3 1.0V/DIV Figure 46. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.2 V, PWM Mode A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 09652-049 3 Figure 49. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.8 V, Auto Mode SW SW 1 1 VOUT VOUT 2 2 IOUT IOUT 3 A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M 09652-047 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M Figure 47. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 3.3 V, Auto Mode A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 09652-050 3 Figure 50. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 1.8 V, Auto Mode Rev. B | Page 16 of 40 Data Sheet ADP5041 SW SW 1 1 VOUT VOUT 2 2 IOUT IOUT A CH3 94.0mA 200µs/DIV 500kS/s 2.0µs/pt 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M 09652-051 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 100mA/DIV 1MΩ BW 120M Figure 51. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.2 V, Auto Mode A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 09652-054 3 3 Figure 54. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 3.3 V, PWM Mode SW SW 1 1 VOUT VOUT 2 2 3 A CH3 92.0mA 200µs/DIV 500kS/s 2.0µs/pt 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M 09652-052 B 20.0M CH1 4.0V/DIV W B 20.0M CH2 50.0mV/DIV W CH3 200mA/DIV 1MΩ BW 120M Figure 52. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 1.2 V, Auto Mode IOUT A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 09652-055 IOUT 3 Figure 55. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.8 V, PWM Mode SW SW 1 1 VOUT VOUT 2 2 3 A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M 09652-053 1MΩ BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 300mA/DIV 1MΩ BW 20.0M Figure 53. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 3.3 V, PWM Mode IOUT A CH3 150mA 500µs/DIV 20.0MS/s 50.0ns/pt 09652-056 IOUT 3 Figure 56. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 1.8 V, PWM Mode Rev. B | Page 17 of 40 ADP5041 Data Sheet 1 SW IIN VOUT 2 VOUT IOUT EN 94.0mA 200µs/DIV 500kS/s 2.0ns/pt CH1 2.0V/DIV CH2 2.0V/DIV CH3 200mA/DIV 09652-057 B 20.0M A CH3 CH1 4.0V/DIV W B 20.0M CH2 50.0mV/DIV W CH3 100mA/DIV 1MΩ BW 120.0M Figure 57. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.2 V, PWM Mode 1 1.72V 50.0µs/DIV 200MS/s 5.0ns/pt Figure 60. LDO1, LDO2 Startup, VOUT = 3.3 V, IOUT = 5 mA 3 SW 1MΩ BW 20.0M A CH1 1MΩ BW 20.0M B 20.0M W 09652-060 3 IIN VOUT 2 2 VOUT EN IOUT 1 92.0mA 200µs/DIV 500kS/s 2.0ns/pt CH1 2.0V/DIV CH2 1.0V/DIV CH3 200mA/DIV 09652-058 20.0M A CH3 CH1 4.0V/DIV CH2 50.0mV/DIV 20.0M CH3 200mA/DIV 1MΩ BW 20.0M 50.0µs/DIV 200MS/s 5.0ns/pt 3 IIN VOUT VOUT 2 2 EN EN 1 CH1 2.0V/DIV CH2 2.0V/DIV CH3 200mA/DIV 1MΩ BW 20.0M A CH1 1MΩ BW 20.0M B 20.0M W 1.72V 50.0µs/DIV 200MS/s 5.0ns/pt CH1 2.0V/DIV CH2 1.0V/DIV CH3 200mA/DIV 09652-059 1 Figure 59. LDO1, LDO2 Startup, VOUT = 4.7 V, IOUT = 5 mA 1MΩ BW 20.0M A CH1 1MΩ BW 20.0M B 20.0M W 1.72V 50.0µs/DIV 200MS/s 5.0ns/pt Figure 62. LDO1, LDO2 Startup, VOUT = 1.2 V, IOUT = 5 mA Rev. B | Page 18 of 40 09652-062 3 760mV Figure 61. LDO1, LDO2 Startup, VOUT = 1.8 V, IOUT = 5 mA Figure 58. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 1.2 V, PWM Mode IIN 1MΩ BW 20.0M A CH1 1MΩ BW 20.0M B 20.0M W 09652-061 3 Data Sheet ADP5041 1.220 3.6V 4.5V 5.5V 2.8V 1.215 1.210 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4.758 5.5V 4.708 4.658 5.0V 1.205 1.200 1.195 1.190 1.180 0.001 3.40 3.38 3.38 3.36 3.36 OUTPUT VOLTAGE (V) 3.34 5.5V 3.30 4.5V 3.26 3.6V 3.30 3.28 3.26 3.24 3.22 3.22 0.01 0.1 OUTPUT CURRENT (A) 3.20 0.001 0.1 Figure 67. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V, VOUT = 3.3 V 1.800 1.800 3.6V 4.5V 5.5V 2.8V –40°C +25°C +85°C 1.795 OUTPUT VOLTAGE (V) 1.795 1.790 1.785 1.780 1.775 1.790 1.785 1.780 1.775 0.01 OUTPUT CURRENT (A) 0.1 1.770 0.001 09652-065 1.770 0.001 0.01 OUTPUT CURRENT (A) Figure 64. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 3.3 V OUTPUT VOLTAGE (V) 3.32 3.24 3.20 0.001 –40°C +25°C +85°C 3.34 09652-064 OUTPUT VOLTAGE (V) Figure 66. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 1.2 V 3.40 3.28 0.1 OUTPUT CURRENT (A) Figure 63. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 4.7 V 3.32 0.01 09652-066 0.1 09652-067 0.01 OUTPUT CURRENT (A) 0.01 OUTPUT CURRENT (A) Figure 65. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 1.8 V 0.1 09652-068 4.608 0.001 09652-063 1.185 Figure 68. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V, VOUT = 1.8 V Rev. B | Page 19 of 40 ADP5041 Data Sheet 1.820 1.220 –40°C +25°C +85°C 1.215 OUTPUT VOLTAGE (V) 1.205 1.200 1.195 1.810 1.805 1.800 1.190 1.795 1.185 0.01 1.790 2.5 09652-069 1.180 0.001 0.1 OUTPUT CURRENT (A) 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) Figure 72. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 1.8 V Figure 69. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V, VOUT = 1.2 V 1.201 4.75 100µA 1mA 10mA 100mA 200mA 100µA 1mA 10mA 100mA 200mA 1.200 1.199 OUTPUT VOLTAGE (V) 4.73 3.0 09652-072 OUTPUT VOLTAGE (V) 1.210 OUTPUT VOLTAGE (V) 100µA 1mA 10mA 100mA 200mA 1.815 4.71 4.69 1.198 1.197 1.196 1.195 1.194 4.67 5.1 5.2 5.3 5.4 5.5 INPUT VOLTAGE (V) 1.192 2.5 09652-070 4.65 5.0 4.0 4.5 5.0 5.5 Figure 73. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 1.2 V 200 3.310 100µA 1mA 10mA 100mA 200mA 180 160 GROUND CURRENT (µA) OUTPUT VOLTAGE (V) 3.5 INPUT VOLTAGE (V) Figure 70. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 4.7 V 3.305 3.0 09652-073 1.193 3.300 3.295 3.290 140 120 100 80 60 40 3.285 4.2 4.5 4.8 INPUT VOLTAGE (V) 5.1 5.4 0 09652-071 3.9 0 0.05 0.10 0.15 0.20 OUTPUT CURRENT (A) Figure 71. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 3.3 V 0.25 0.30 09652-074 20 3.280 3.6 Figure 74. LDO1, LDO2 Ground Current vs. Output Current, VOUT = 3.3 V Rev. B | Page 20 of 40 Data Sheet ADP5041 200 180 VOUT 2 140 120 100 80 40 20 0 3.8 4.3 4.8 3 5.3 INPUT VOLTAGE (V) Figure 75. LDO1, LDO2 Ground Current vs. Input Voltage, Across Output Load (A), VOUT = 3.3 V IOUT CH2 30.0mV/DIV CH3 50.0mA/DIV B 20.0M A CH3 W 1MΩ BW 120M 42.0mA 200µs/DIV 500kS/s 2.0µs/pt 09652-078 0.000001A 0.0001A 0.001A 0.01A 0.1A 0.15A 0.3A 60 09652-075 GROUND CURRENT (µA) 160 Figure 78. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to 80 mA, VOUT = 3.3 V VOUT 2 2 IOUT IOUT 27.2mA 200µs/DIV 5.0MS/s 200ns/pt CH2 50.0mV/DIV CH3 80.0mA/DIV Figure 76. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to 80 mA, VOUT = 4.7 V B 20.0M A CH3 W 1MΩ BW 120M 89.6mA 200µs/DIV 500kS/s 2.0µs/pt 09652-079 B 20.0M A CH3 CH2 30.0mV/DIV W CH3 80.0mA/DIV 1MΩ BW 20.0M 3 09652-076 3 VOUT Figure 79. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to 200 mA, VOUT = 3.3 V VOUT 2 2 IOUT IOUT B 20.0M A CH3 CH2 30.0mV/DIV W CH3 80.0mA/DIV 1MΩ BW 20.0M 27.2mA 200µs/DIV 5.0MS/s 200ns/pt CH2 30.0mV/DIV CH3 80.0mA/DIV Figure 77. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to 200 mA, VOUT = 4.7 V B 20.0M A CH3 W 1MΩ BW 120M 89.6mA 200µs/DIV 500kS/s 2.0µs/pt 09652-080 3 09652-077 3 VOUT Figure 80. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to 80 mA, VOUT = 1.8 V Rev. B | Page 21 of 40 ADP5041 2 Data Sheet VIN VOUT VOUT 2 3 IOUT B 20.0M A CH3 W 1MΩ BW 120M 89.6mA 200µs/DIV 500kS/s 2.0µs/pt Figure 81. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to 200 mA, VOUT = 1.8 V 2 B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1MΩ BW 20.0M 09652-081 CH2 50.0mV/DIV CH3 80.0mA/DIV 4.84V 200µs/DIV 1.0MS/s 1.0µs/pt 09652-084 3 Figure 84. LDO1, LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT = 3.3 V VOUT VIN VOUT 2 3 B 20.0M A CH3 CH2 30.0mV/DIV W CH3 80.0mA/DIV 1MΩ BW 20.0M 27.2mA 200µs/DIV 5.0MS/s 200ns/pt Figure 82. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to 80 mA, VOUT = 1.2 V 2 B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1MΩ BW 20.0M 4.86V 500µs/DIV 1.0MS/s 1.0µs/pt 09652-085 IOUT 09652-082 3 Figure 85. LDO1, LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT = 1.8 V VOUT VIN 2 VOUT 3 B 20.0M A CH3 CH2 30.0mV/DIV W CH3 80.0mA/DIV 1MΩ BW 20.0M 27.2mA 200µs/DIV 5.0MS/s 200ns/pt B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1MΩ BW 20.0M Figure 83. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to 200 mA, VOUT = 1.2 V 4.48V 200µs/DIV 1.0MS/s 1.0µs/pt 09652-086 IOUT 09652-083 3 Figure 86. LDO1, LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT = 1.2 V Rev. B | Page 22 of 40 Data Sheet ADP5041 RMS NOISE (µV) VIN 3 4.02V 200µs/DIV 1.0MS/s 1.0µs/pt 10 0.0001 09652-087 B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1MΩ BW 20.0M Figure 87. LDO1, LDO2 Response to Line Transient, Input Voltage from 3.3 V to 3.8 V, VOUT = 1.8 V VOUT 2 0.001 0.01 0.1 1 LOAD (mA) 10 100 1k Figure 90. LDO1 Output Noise vs. Load Current, Across Input and Output Voltage RMS NOISE (µV) VIN CH2; VOUT = 3.3V; VIN = 5V CH2; VOUT = 3.3V; VIN = 3.6V CH2; VOUT = 2.8V; VIN = 3.1V CH2; VOUT = 1.5V; VIN = 5V CH2; VOUT = 1.5V; VIN = 1.8V 09652-104 VOUT 2 100 100 4.84V 200µs/DIV 1.0MS/s 1.0µs/pt 10 0.0001 09652-088 B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1MΩ BW 20.0M Figure 88. LDO1, LDO2 Response to Line Transient, Input Voltage from 3.3 V to 3.8 V, VOUT = 1.2 V 0.001 100 0.6 0.01 0.1 1 LOAD (mA) 10 100 1k Figure 91. LDO2 Output Noise vs. Load Current, Across Input and Output Voltage 0.7 VOUT2 = 3.3V, VIN2 = 3.6V, ILOAD = 300mA VOUT2 = 1.5V, VIN2 = 1.8V, ILOAD = 300mA VOUT2 = 2.8V, VIN2 = 3.1V, ILOAD = 300mA VOUT = 3.3V 10 NOISE (µV/√Hz) 0.5 0.4 0.3 1.0 0.2 0.1 0 3.6 4.1 4.6 5.1 5.6 VIN (V) 0.01 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 92. LDO1 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.3 V Figure 89. LDO1, LDO2 Output Current Capability vs. Input Voltage Rev. B | Page 23 of 40 09652-106 0.1 09652-089 OUTPUT CURRENT (A) CH3; VOUT = 3.3V; VIN = 5V CH3; VOUT = 3.3V; VIN = 3.6V CH3; VOUT = 2.8V; VIN = 3.1V CH3; VOUT = 1.5V; VIN = 5V CH3; VOUT = 1.5V; VIN = 1.8V 09652-105 3 ADP5041 100 Data Sheet –10 VOUT3 = 3.3V, VIN3 = 3.6V, ILOAD = 300mA VOUT3 = 1.5V, VIN3 = 1.8V, ILOAD = 300mA VOUT3 = 2.8V, VIN3 = 3.1V, ILOAD = 300mA –20 –30 –40 PSRR (dB) NOISE (µV/√Hz) 10 1mA 10mA 100mA 200mA 300mA 1 –50 –60 –70 0.1 –80 10 100 1k 10k FREQUENCY (Hz) 100k 1M 09652-115 1 –100 10 Figure 93. LDO2 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.3 V 100 VOUT2 = 3.3V, VOUT3 = 3.3V, VOUT2 = 1.5V, VIN2 = 3.6V, VIN3 = 3.6V, VIN2 = 1.8V, 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 09652-110 –90 0.01 Figure 96. LDO2 PSRR Across Output Load, VIN3 = 3.1 V, VOUT3 = 2.8 V –10 ILOAD = 300mA ILOAD = 300mA ILOAD = 300mA –20 1mA 10mA 100mA 200mA –30 10 PSRR (dB) 1.0 –50 –60 –70 0.1 1k 10k 100k FREQUENCY (Hz) 1M 10M –100 10 –20 –30 –10 1mA 10mA 100mA 200mA 300mA –20 –30 PSRR (dB) –50 –60 1M 10M 1mA 10mA 100mA 200mA 300mA –50 –60 –70 –70 –80 –80 –90 –90 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 09652-109 PSRR (dB) 10k 100k FREQUENCY (Hz) –40 –40 –100 10 1k Figure 97. LDO2 PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.3 V Figure 94. LDO1 vs. LDO2 Noise Spectrum –10 100 09652-111 100 –90 09652-108 0.01 10 –80 VOUT3 = 1.5V, VIN3 = 1.8V, I LOAD = 300mA VOUT2 = 2.8V, VIN2 = 3.1V, I LOAD = 300mA VOUT3 = 2.8V, VIN3 = 3.1V, I LOAD = 300mA –100 10 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 98. LDO2 PSRR Across Output Load, VIN3 = 3.6 V, VOUT3 = 3.3 V Figure 95. LDO2 PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V Rev. B | Page 24 of 40 10M 09652-112 NOISE (µV/√Hz) –40 Data Sheet –20 –30 –10 1mA 10mA 100mA 200mA 300mA –20 –30 –40 PSRR (dB) –50 –60 –50 –60 –70 –70 –80 –80 –90 –90 100 1k 10k 100k FREQUENCY (Hz) 1M 10M –100 10 09652-113 PSRR (dB) –40 –100 10 1mA 10mA 100mA 200mA 300mA 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 100. LDO1 PSRR Across Output Load, VIN2 = 1.8 V, VOUT2 = 1.5 V Figure 99. LDO1 PSRR Across Output Load, VIN2 = 5.0 V, VOUT2 = 1.5 V Rev. B | Page 25 of 40 10M 09652-114 –10 ADP5041 ADP5041 Data Sheet THEORY OF OPERATION VOUT1 FB1 VTHR MR WDI 85Ω ENWD ENBK AVIN VDDA WATCHDOG DETECTOR GM ERROR AMP PWM COMP VDDA SOFT START VIN1 52kΩ ILIMIT DEBOUNCE PSM COMP PWM/ PSM CONTROL BUCK1 LOW CURRENT nRSTO SW RESET GENERATOR VREF OSCILLATOR DRIVER AND ANTISHOOT THROUGH SYSTEM UNDERVOLTAGE LOCK OUT PGND MODE MODE EN1 EN2 EN3 600Ω ENLDO2 THERMAL SHUTDOWN ENABLE AND MODE CONTROL SEL ENBK ENLDO1 ENLDO2 LDO1 CONTROL VDDA VDDA LDO2 CONTROL OPMODE_FUSES 600Ω VIN2 FB2 AGND VOUT2 VIN3 FB3 VOUT3 09652-090 ENLDO1 ADP5041 Figure 101. Functional Block Diagram POWER MANAGEMENT UNIT The ADP5041 is a micro power management unit (micro PMU) combing one step-down (buck) dc-to-dc regulator, two LDO linear regulators, and a supervisory circuit, with watchdog, for processor control. The high switching frequency and tiny 20-pin LFCSP package allow for a small power management solution. The regulators are activated by a logic level high applied to the respective EN pin. The EN1 pin controls the buck regulator, the EN2 pin controls LDO1, and the EN3 pin controls LDO2. Other features available on this device are the MODE pin to control the buck switching operation and a push-button reset input. The regulator output voltages and the reset threshold are set through external resistor dividers. When a regulator is turned on, the output voltage ramp is controlled through a soft start circuit to avoid a large inrush current due to the discharged output capacitors. The buck regulator can operate in forced PWM mode if the MODE pin is at a logic high level. In forced PWM mode, the switching frequency of the buck is always constant and does not change with the load current. If the MODE pin is at a logic low level, the switching regulator operates in auto PWM/PSM mode. In this mode, the regulator operates at fixed PWM frequency when the load current is above the power save current threshold. When the load current falls below the power saving current threshold, the regulator enters power saving mode, where the switching occurs in bursts. The burst repetition rate is a function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses. Rev. B | Page 26 of 40 Data Sheet ADP5041 Thermal Protection VOUT1 VIN1 In the event that the junction temperature rises above 150°C, the thermal shutdown circuit turns off the buck and the LDOs. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20°C hysteresis is included in the thermal shutdown circuit so that when thermal shutdown occurs, the buck and the LDOs do not return to normal operation until the on-chip temperature drops below 130°C. When coming out of thermal shutdown, all regulators start with soft start control. L1 – 1µH SW VOUT1 BUCK FB1 R2 C5 10µF 09652-091 AGND R1 Undervoltage Lockout Figure 102. Buck External Output Voltage Setting To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the ADP5041. If the input voltage on AVIN drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channel, both the power switch and the synchronous rectifier turn off. When the voltage on AVIN rises above the UVLO threshold, the part is enabled once more. Alternatively, the user can select device models with a UVLO set at a higher level, suitable for 5 V applications. For these models, the device reaches the turn-off threshold when the input supply drops to 3.65 V typical. Enable/Shutdown The ADP5041 has individual control pins for each regulator. A logic level high applied to the ENx pin activates a regulator, whereas a logic level low turns off a regulator. Active Pull-Down The ADP5041 can be ordered with the active pull-down option enabled. The pull-down resistors are connected between each regulator output and AGND. The pull-downs are enabled, when the regulators are turned off. The typical value of the pull-down resistor is 600 Ω for the LDOs and 85 Ω for the buck. BUCK SECTION The buck uses a fixed frequency and high speed current mode architecture. The buck operates with an input voltage of 2.3 V to 5.5 V. The buck output voltage is set through external resistor dividers, shown in Figure 102. VOUT1 must be connected to the output capacitor. VFB1 is internally set to 0.5 V. The output voltage can be set from 0.8 V to 3.8 V. Control Scheme The buck operates with a fixed frequency, current mode PWM control architecture at medium to high loads for high efficiency, but operation shifts to a power save mode (PSM) control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in PSM at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. PWM Mode In PWM mode, the buck operates at a fixed frequency of 3 MHz, set by an internal oscillator. At the start of each oscillator cycle, the PFET switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the PFET switch and turns on the NFET synchronous rectifier. This sends a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle. The buck regulates the output voltage by adjusting the peak inductor current threshold. Power Save Mode (PSM) The buck smoothly transitions to PSM operation when the load current decreases below the PSM current threshold. When the buck enters power-save mode, an offset is introduced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level that is approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle mode. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. This process is repeated while the load current is below the PSM current threshold. The ADP5041 has a dedicated MODE pin controlling the PSM and PWM operation. A high logic level applied to the MODE pin forces the buck to operate in PWM mode. A logic level low sets the buck to operate in auto PSM/PWM. Rev. B | Page 27 of 40 ADP5041 Data Sheet PSM Current Threshold The PSM current threshold is set to 100 mA. The buck employs a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to, and exit from, the PSM mode. The PSM current threshold is optimized for excellent efficiency over all load currents. Each LDO output voltage is set though external resistor dividers, as shown in Figure 103. VFB2 and VFB3 are internally set to 0.5 V. The output voltage can be set from 0.8 V to 5.2 V. VOUT2, VOUT3 VIN2, VIN3 LD01, LD02 FB2, FB3 Soft Start The buck has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. Current Limit The buck has protection circuitry to limit the amount of positive current flowing through the PFET switch and the amount of negative current flowing through the synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% Duty Operation With a drop in input voltage, or with an increase in load current, the buck may reach a limit where, even with the PFET switch on 100% of the time, the output voltage drops below the desired output voltage. At this limit, the buck transitions to a mode where the PFET switch stays on 100% of the time. When the input conditions change again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage. LDO SECTION The ADP5041 contains two LDOs with low quiescent current that provide output currents up to 300 mA. The low 10 μA typical quiescent current at no load makes the LDO ideal for battery-operated portable equipment. The LDOs operate with an input voltage range of 1.7 V to 5.5 V. The wide operating range makes these LDOs suitable for cascade configurations where the LDO supply voltage is provided from the buck regulator. C7 2.2µF RB 09652-092 Short-Circuit Protection The buck includes frequency foldback to prevent current runaway on a hard short at the output. When the voltage at the feedback pin falls below half the internal reference voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. RA VOUT2, VOUT3 Figure 103. LDOs External Output Voltage Setting The LDOs also provide high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with small ceramic 1 μF input and 2.2 μF output capacitors. LDO2 is optimized to supply analog circuits because it offers better noise performance compared to LDO1. LDO1 should be used in applications where noise performance is not critical. SUPERVISORY SECTION The ADP5041 provides microprocessor supply voltage supervision by controlling the reset input of the microprocessor. Code execution errors are avoided during power-up, powerdown, and brownout conditions by asserting a reset signal when the supply voltage is below a preset threshold and by allowing supply voltage stabilization with a fixed timeout reset pulse after the supply voltage rises above the threshold. In addition, problems with microprocessor code execution can be monitored and corrected with a watchdog timer. Reset Output The ADP5041 has an active low, open-drain reset output. This output structure requires an external pull-up resistor to connect the reset output to a voltage rail that is no higher than 6 V. The resistor should comply with the logic low and logic high voltage level requirements of the microprocessor while supplying input current and leakage paths on the nRSTO pin. A 10 kΩ resistor is adequate in most situations. The reset output is asserted when the monitored rail is below the reset threshold (VTH) or when WDI is not serviced within the watchdog timeout period (tWDI). Reset remains asserted for the duration of the reset active timeout period (tRP) after the monitored rail rises above the reset threshold or after the watchdog timer times out. Figure 104 illustrates the behavior of the reset output, nRSTO, and it assumes that VOUT2 is selected as the rail to be monitored and supplies the external pull-up connected to the nRSTO output. Rev. B | Page 28 of 40 Data Sheet VTH Manual Reset Input VTH VOUT2 1V 0V VOUT2 nRSTO tRP tRD RSTO tRP 1V 0V 09652-093 0V tRD Figure 104. Reset Timing Diagram The ADP5041 has a reset threshold programming input pin, VTHR, to monitor a supply rail. The reset threshold voltage at VTHR input is typically 0.5 V. To monitor a voltage greater than 0.5 V, connect a resistor divider network to the device as shown in Figure 105, where VMONITORED Watchdog Input  R1  R 2   0.5V    R2  The ADP5041 features a watchdog timer that monitors microprocessor activity. The watchdog timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (WDI), which detects pulses as short as 80 ns. If the timer counts through the preset watchdog timeout period (tWDI), an output reset is asserted. The microprocessor is required to toggle the WDI pin to avoid being reset. Failure of the microprocessor to toggle WDI within the timeout period, therefore, indicates a code execution error, and the reset pulse generated restarts the microprocessor in a known state. MONITORED VOLTAGE R1 VTHR VREF = 0.5V 09652-094 R2 The ADP5041 features a manual reset input (MR) which, when driven low, asserts the reset output. When MR transitions from low to high, the reset remains asserted for the duration of the reset active timeout period before deasserting. The MR input has a 52 kΩ, internal pull-up connected to AVIN, so that the input is always high when unconnected. An external pushbutton switch can be connected between MR and ground so that the user can generate a reset. Debounce circuitry for this purpose is integrated on chip. Noise immunity is provided on the MR input, and fast negative-going transients of up to 100 ns (typical) are ignored. A 0.1 μF capacitor between MR and ground provides additional noise immunity. Figure 105. External Reset Threshold Programming Do not allow the VTHR input to float or to be grounded. Connect it to a supply voltage greater than its specified threshold voltage. A small capacitor can be added on VTHR to improve the noise rejection and to prevent false reset generation. The ADP5041 can be factory programmed to a 2.25 V or 3.6 V UVLO threshold. When monitoring the input supply voltage, if the selected reset threshold is below the UVLO level, the reset output, nRSTO, is asserted low as soon as the input voltage falls below the UVLO threshold. Below the UVLO threshold, the reset output is maintained low down to ~1 V input voltage. This is to ensure that the reset output is not released when there is sufficient voltage on the rail supplying a processor to restart the processor operations. As well as logic transitions on WDI, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on the monitored rail. When reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deasserts. The watchdog timer can be disabled by leaving WDI floating or by three-stating the WDI driver. The ADP5041 can be factory programmed to two possible watchdog timer values as indicated in Table 18. VTH VSENSED 1V 0V tRP nRSTO tWD tRP 0V 09652-095 VOUT2 ADP5041 WDI 0V Figure 106. Watchdog Timing Diagram Rev. B | Page 29 of 40 ADP5041 Data Sheet NO POWER APPLIED TO AVIN. ALL REGULATORS AND SUPERVISORY TURNED OFF NO POWER AVIN > VUVLO AVIN < VUVLO TRANSITION STATE POR INTERNAL CIRCUIT BIASED REGULATORS AND SUPERVISORY NOT ACTIVATED END OF POR STANDBY ENx = HIGH AVIN < VUVLO ALL ENx = LOW AVIN < VUVLO ACTIVE ALL REGULATORS AND SUPERVISORS ACTIVATED END OF RESET PULSE (tRP ) WDOG1 TIMEOUT (tWD) RESET NORMAL Figure 107. ADP5041 State Flow Rev. B | Page 30 of 40 09652-096 VMON < VTH Data Sheet ADP5041 APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Trade-offs between performance parameters such as efficiency and transient response are made by varying the choice of external components in the applications circuit, as shown in Figure 1. Feedback Resistors Referring to Figure 102, the total combined resistance for R1 and R2 is not to exceed 400 kΩ. Inductor The high switching frequency of the ADP5041 buck allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 μH and 3.0 μH. Suggested inductors are shown in Table 9. The peak-to-peak inductor current ripple is calculated using the following equation: I RIPPLE  VOUT  (VIN  VOUT ) VIN  f SW  L The worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: CEFF = COUT × (1 − TEMPCO) × (1 − TOL) where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT is 9.24 μF at 1.8 V, as shown in Figure 108. where: fSW is the switching frequency. L is the inductor value. The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current is calculated using the following equation: I PEAK  I LOAD ( MAX )  Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are highly recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. I RIPPLE 2 Substituting these values in the equation yields CEFF = 9.24 μF × (1 − 0.15) × (1 − 0.1) = 7.07μF To guarantee the performance of the buck, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 12 Table 9. Suggested 1.0 μH Inductors Dimensions (mm) ISAT (mA) DCR (mΩ) Murata Murata Tayo Yuden Coilcraft Coilcraft Toko LQM2MPN1R0NG0B LQM18FN1R0M00B CBC322ST1R0MR XFL4020-102ME XPL2010-102ML MDT2520-CN 2.0 × 1.6 × 0.9 3.2 × 2.5 × 1.5 3.2 × 2.5 × 2.5 4.0 × 4.0 × 2.1 1.9 × 2.0 × 1.0 2.5 × 2.0 × 1.2 1400 2300 2000 5400 1800 1350 85 54 71 11 89 85 Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the buck is a high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low EMI. Output Capacitor 10 8 6 4 2 0 0 1 2 3 4 5 DC BIAS VOLTAGE (V) 6 09652-097 Model CAPACITANCE (µF) Vendor Figure 108. Typical Capacitor Performance The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing the capacitor value, it is also important to account for the loss of capacitance due to output voltage dc bias. Rev. B | Page 31 of 40 VRIPPLE  I RIPPLE VIN  8  f SW  COUT  2  f SW 2  L  COUT ADP5041 Data Sheet Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: ESR COUT  To minimize supply noise, place the input capacitor as close to the VIN pin of the buck as possible. As with the output capacitor, a low ESR capacitor is recommended. VRIPPLE I RIPPLE The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 μF and a maximum of 10 μF. A list of suggested capacitors is shown in Table 11. The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 μF and a maximum of 40 μF. Table 11. Suggested 4.7 μF Capacitors Table 10. Suggested 10 μF Capacitors Vendor Murata Taiyo Yuden TDK Panasonic Type X5R X5R Model GRM188R60J106 JMK107BJ106MA-T Case Size 0603 0603 Voltage Rating (V) 6.3 6.3 X5R X5R C1608JB0J106K ECJ1VB0J106M 0603 0603 6.3 6.3 Vendor Murata Taiyo Yuden Panasonic Model GRM188R60J475ME19D JMK107BJ475 ECJ-0EB0J475M Case Size 0603 0603 0402 Voltage Rating (V) 6.3 6.3 6.3 LDO EXTERNAL COMPONENT SELECTION Feedback Resistors The maximum value of RB is not to exceed 200 kΩ (see Figure 103). The buck regulator requires 10 μF output capacitors to guarantee stability and response to rapid load variations and to transition in and out the PWM/PSM modes. In certain applications where the buck regulator powers a processor, the operating state is known because it is controlled by software. In this condition, the processor can drive the MODE pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 μF to 4.7 μF because the regulator does not expect a large load variation when working in PSM mode (see Figure 109). OUTPUT CAPACITOR The ADP5041 LDOs are designed for operation with small, space-saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 μF capacitance with an ESR of 1 Ω or less is recommended to ensure stability of the LDO. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the LDO to large changes in load current. ADP5041 AVIN MICRO PMU SW L1 1µH PROCESSOR VCORE VOUT1 C5 4.7µF VIN1 C1 10µF FB1 R1 PGND C2 1µF VIN3 C3 1µF When operating at output currents higher than 200 mA a minimum of 2.2 μF capacitance with an ESR of 1 Ω or less is recommended to ensure stability of the LDO. R2 VIN2 VOUT2 FB2 VDDIO R7 100kΩ R4 nRSTO Vendor Murata TDK Panasonic Taiyo Yuden RESET WDI GPIO1 MODE GPIO2 3 ENx R5 C7 2.2µF Model GRM188B31A225K C1608JB0J225KT ECJ1VB0J225K JMK107BJ225KK-T Case Size 0402 0402 0402 0402 Voltage Rating (V) 10.0 6.3 6.3 6.3 Input Bypass Capacitor VANALOG ANALOG SUBSYSTEM R6 Figure 109. Processor System Power Management with PSM/PWM Control Input Capacitor Connecting 1 μF capacitors from VIN2 and VIN3 to ground reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance is encountered. If greater than 1 μF of output capacitance is required, increase the input capacitor to match it. A higher value input capacitor helps to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation: I CIN  I LOAD( MAX ) Type X5R X5R X5R X5R GPIO[x:y] VOUT3 FB3 Table 12. Suggested 2.2 μF Capacitors C6 2.2µF R3 09652-098 RFLT 30Ω VIN 2.3V TO 5.5V Type X5R X5R X5R VOUT (VIN  VOUT ) VIN Rev. B | Page 32 of 40 Data Sheet ADP5041 Table 13. Suggested 1.0 μF Capacitors Vendor Murata TDK Panasonic Taiyo Yuden Type X5R X5R X5R X5R Model GRM155B30J105K C1005JB0J105KT ECJ0EB0J105K LMK105BJ105MV-F Case Size 0402 0402 0402 0402 Voltage Rating (V) 6.3 6.3 6.3 10.0 Input and Output Capacitor Properties Use any good quality ceramic capacitor with the ADP5041 as long as it meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 110 depicts the capacitance vs. dc voltage bias characteristic of a 0402 1 μF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating. 1.2 CAPACITANCE (µF) 1.0 0.8 0.6 0.4 0.2 X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 μF at 1.8 V, as shown in Figure 110. Substituting these values into the following equation yields: CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.72 μF Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5041, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. SUPERVISORY SECTION Threshold Setting Resistors Referring to Figure 105, the maximum value of R2 is not to exceed 200 kΩ. Watchdog Input Current To minimize watchdog input current (and minimize overall power consumption), leave WDI low for the majority of the watchdog timeout period. When driven high, WDI can draw as much as 25 μA. Pulsing WDI low-to-high-to-low at a low duty cycle reduces the effect of the large input current. When WDI is unconnected, a window comparator disconnects the watchdog timer from the reset output circuitry so that reset is not asserted when the watchdog timer times out. Negative-Going Transients at the Monitored Rail To avoid unnecessary resets caused by fast power supply transients, the ADP5041 is equipped with glitch rejection circuitry. The typical performance characteristic in Figure 111 plots the monitored rail voltage, VTH, transient duration vs. the transient magnitude. The curve shows combinations of transient magnitude and duration for which a reset is not generated. In this example, with the 3.00 V threshold, a transient that goes 100 mV below the threshold and lasts 8 μs typically does not cause a reset, but if the transient is any larger in magnitude or duration, a reset is generated. In this example, the reset threshold programming resistor values were R2 = 200 kΩ, R1 = 1 MΩ (see Figure 105). 900 2 3 4 DC BIAS VOLTAGE (V) 5 6 800 Figure 110. Capacitance vs. Voltage Characteristic Use the following equation to determine the worst-case capacitance, accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an Rev. B | Page 33 of 40 700 600 500 400 300 200 100 0 0.1 1 10 COMPARATOR OVERDRIVE (% OF VTH) Figure 111. Maximum VTH Transient Duration vs. Reset Threshold Overdrive 100 09652-100 1 TRANSIENT DURATION (µs) 0 09652-099 0 ADP5041 Data Sheet Watchdog Software Considerations The efficiency for each regulator on the ADP5041 is given by In implementing the watchdog strobe code of the microprocessor, quickly switching WDI low to high and then high to low (minimizing WDI high time) is desirable for current consumption reasons. However, a more effective way of using the watchdog function can be considered. A low-to-high-to-low WDI pulse within a given subroutine prevents the watchdog from timing out. However, if the subroutine is held in an infinite loop, the watchdog cannot detect this because the subroutine continues to toggle WDI. A more effective coding scheme for detecting this error involves using a slightly longer watchdog timeout. In the program that calls the subroutine, WDI is set high. The subroutine sets WDI low when it is called. If the program executes without error, WDI is toggled high and low with every loop of the program. If the subroutine enters an infinite loop, WDI is kept low, the watchdog times out, and the microprocessor is reset (see Figure 112). START SET WDI HIGH RESET PROGRAM CODE SUBROUTINE INFINITE LOOP: WATCHDOG TIMES OUT RETURN 09652-101 SET WDI LOW Figure 112. Watchdog Flow Diagram POWER DISSIPATION/THERMAL CONSIDERATIONS The ADP5041 is a highly efficient micropower management unit (micro PMU), and in most cases the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and with maximum loading conditions, the junction temperature can reach the maximum allowable operating limit (125°C). When the junction temperature exceeds 150°C, the ADP5041 turns off all the regulators, allowing the device to cool down. Once the die temperature falls below 135°C, the ADP5041 resumes normal operation. This section provides guidelines to calculate the power dissipated in the device and to make sure the ADP5041 operates below the maximum allowable junction temperature.  POUT  100% PIN (1) where: η is efficiency. PIN is the input power. POUT is the output power. Power loss is given by PLOSS = PIN − POUT (2a) PLOSS = POUT (1-η)/η (2b) or The power dissipation of the supervisory function is small and negligible. Power dissipation can be calculated in several ways. The most intuitive and practical is to measure the power dissipated at the input and all the outputs. The measurements should be performed at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 4 to derive the power lost in the inductor, and from this use Equation 3 to calculate the power dissipation in the ADP5041 buck regulator. A second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, wheras the power lost on a LDO is calculated using Equation 12. When the buck efficiency is known, use Equation 2b to derive the total power lost in the buck regulator and inductor. Use Equation 4 to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the LDOs to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of VIN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and the losses in the LDOs provided by Equation 12. Buck Regulator Power Dissipation The power loss of the buck regulator is approximated by PLOSS = PDBUCK + PL (3) where: PDBUCK is the power dissipation on the ADP5041 buck regulator. PL is the inductor power losses. The inductor losses are external to the device and they do not have any effect on the die temperature. Rev. B | Page 34 of 40 Data Sheet ADP5041 The inductor losses are estimated (without core losses) by PL  I OUT1( RMS )2  DCRL (4) where: DCRL is the inductor series resistance. IOUT1(RMS) is the rms load current of the buck regulator. IOUT1(RMS)  IOUT1  1+ r/12 (5) where r is the normalized inductor ripple current. r ≈ VOUT1 × (1-D)/(IOUT1 × L × fSW) (6) The power loss of a LDO regulator is given by: PDLDO = [(VIN − VOUT) × ILOAD] + (VIN × IGND) D = VOUT1/VIN1 (7) The ADP5041 buck regulator power dissipation, PDBUCK, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. Equation 8 shows the calculation made to estimate the power dissipation in the buck regulator. PDBUCK = PCOND + PSW + PTRAN PCOND = [RDSON-P × D + RDSON-N × (1 − D)] × IOUT12 (9) For the ADP5041, at 125°C junction temperature and VIN1 = 3.6 V, RDSON-P is approximately 0.2 Ω, and RDSON-N is approximately 0.16 Ω. At VIN1 = 2.3 V, these values change to 0.31 Ω and 0.21 Ω respectively, and at VIN1 = 5.5 V, the values are 0.16 Ω and 0.14 Ω, respectively. Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by: (10) where: CGATE-P is the PMOSFET gate capacitance. CGATE-N is the NMOSFET gate capacitance. (12) where: ILOAD is the load current of the LDO regulator. VIN and VOUT are input and output voltages of the LDO, respectively. IGND is the ground current of the LDO regulator. Power dissipation due to the ground current is small and it can be ignored. The total power dissipation in the ADP5041 simplifies to: PD = {[PDBUCK + PDLDO1 + PDLDO2]} (8) The power switch conductive losses are due to the output current, IOUT1, flowing through the PMOSFET and the NMOSFET power switches that have internal resistance, RDSON-P and RDSON-N. The amount of conductive power loss is found by: (13) Junction Temperature In cases where the board temperature, TA, is known, the thermal resistance parameter, θJA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD × θJA) (14) The typical θJA value for the 20-lead, 4 mm × 4 mm LFCSP is 38°C/W (see Table 7). A very important factor to consider is that θJA is based on a 4-layer, 4 inch × 3 inch, 2.5 oz copper, as per JEDEC standard, and real applications may use different sizes and layers. To remove heat from the device, it is important to maximize the use of copper. Copper exposed to air dissipates heat better than copper used in the inner layers. The exposed pad (EP) should be connected to the ground plane with several vias as shown in Figure 114. If the case temperature can be measured, the junction temperature is calculated by TJ = TC + (PD × θJC) For the ADP5041, the total of (CGATE-P + CGATE-N) is approximately 150 pF. The transition losses occur because the PMOSFET cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near VOUT1 (and from VOUT1 to ground). The amount of transition loss is calculated by: PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW If the preceding equations and parameters are used for estimating the converter efficiency, it must be noted that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout; therefore, a sufficient safety margin should be included in the estimate. LDO Regulator Power Dissipation where: L is inductance. fSW is switching frequency. D is duty cycle. PSW = (CGATE-P + CGATE-N) × VIN12 × fSW where tRISE and tFALL are the rise time and the fall time of the switching node, SW. For the ADP5041, the rise and fall times of SW are in the order of 5 ns. (11) (15) where: TC is the case temperature. θJC is the junction-to-case thermal resistance provided in Table 7. When designing an application for a particular ambient temperature range, calculate the expected ADP5041 power dissipation (PD) due to the losses of all channels by using Equation 8 to Equation 13. From this power calculation, the junction temperature, TJ, can be estimated using Equation 14. Rev. B | Page 35 of 40 ADP5041 Data Sheet affected by increasing the junction temperature. Additional information about product reliability can be found in the Analog Devices, Inc., Reliability Handbook, which is available at http://www.analog.com/reliability_handbook. The reliable operation of the buck regulator and the LDO regulator can be achieved only if the estimated die junction temperature of the ADP5041 (Equation 14) is less than 125°C. Reliability and mean time between failures (MTBF) is highly APPLICATION DIAGRAM 11 6 8 BUCK 12 VOUT1 L1 1µH SW VOUT1 AT 1.2A R1 FB1 C4 10µF R2 VIN1 = 2.3V TO 5.5V VIN1 ON OFF VIN2 = 1.7V TO 5.5V 7 C1 4.7µF EN1 VIN2 9 EN_BK 17 13 LDO1 (DIGITAL) 14 FPWM PWM/PSM VOUT2 R4 16 SUPERVISOR MR VOUT2 AT 300mA FB2 EN_LDO1 EN2 C5 2.2µF R3 15 ON MODE 10 C2 1µF OFF PGND 20 PUSH-BUTTON RESET RESET 5 WDOG 19 VDD R9 nRSTO WDI MAIN MICROCONTROLLER RFILT 30Ω AVIN VTH ON OFF EN3 VTHR R5 18 4 R6 2 VIN3 = 1.7V TO 5.5V VIN3 C3 1µF 3 LDO2 (ANALOG) EP 1 VOUT3 FB3 R7 R8 AGND Figure 113. Application Diagram Rev. B | Page 36 of 40 C6 2.2µF VOUT3 AT 300mA 09652-103 EN_LDO2 Data Sheet ADP5041 PCB LAYOUT GUIDELINES SUGGESTED LAYOUT Poor layout can affect ADP5041 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines:  See Figure 114 for an example layout. Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Maximize the size of ground metal on the component side to help with thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.    0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 PPL 5.5 6.0 6.5 VOUT3 7.0 mm GPL 0.5 C6 – 2.2µF 6.3V/XR5 0402 C3 – 1µF 10V/XR5 0402 GPL PPL PPL AVIN 2.5 VIN 1 MR GPL C1 – 4.7µF 10V/XR5 0603 WDI GPL AGND SW L1 – 1µH 0603 GPL PGND VTHR GPL MODE ADP5041 4.0 EN1 FB2 VOUT2 VIN2 FB1 GPL VIAS LEGEND: PPL = POWER PLANE (+4V) GPL = GROUND PLANE C4 – 10µF 6.3V/XR5 0603 5.5 6.0 VOUT1 5.0 GPL GPL GPL 4.5 EN2 C2 – 1µF 10V/XR5 0402 C5 – 2.2µF 6.3V/XR5 0402 VOUT1 TOP LAYER 2ND LAYER PPL mm VOUT2 Figure 114. Suggested Board Layout Rev. B | Page 37 of 40 09652-102 3.5 FB3 PPL 2.0 3.0 VOUT3 VIN3 EN3 RFILT 30Ω 0402 1.5 Pin 1 nRSTO 1.0 ADP5041 Data Sheet BILL OF MATERIALS Table 14. Reference C1 C2, C3 C4 C5,C6 L1 IC1 Value 4.7 μF, X5R, 6.3 V 1 μF, X5R, 6.3 V 10 μF, X5R, 6.3 V 2.2 μF, X5R, 6.3 V 1 μH, 85 mΩ, 1400 mA 1 μH, 85 mΩ, 1350 mA 1 μH, 89 mΩ, 1800 mA 3-regulator micro PMU Part Number JMK107BJ475 LMK105BJ105MV-F JMK107BJ106MA-T JMK105BJ225MV-F LQM2MPN1R0NG0B MDT2520-CN XPL2010-1102ML ADP5041 Rev. B | Page 38 of 40 Vendor Taiyo-Yuden Taiyo-Yuden Taiyo-Yuden Taiyo-Yuden Murata Toko Coilcraft Analog Devices Package 0603 0402 0603 0402 2.0 × 1.6 × 0.9 (mm) 2.5 × 2.0 × 1.2 (mm) 1.9 × 2.0 × 1.0 (mm) 20-Lead LFCSP Data Sheet ADP5041 FACTORY PROGRAMMABLE OPTIONS Table 15. Regulator Output Discharge Resistor Options Options Option 0 Option 1 Description All discharge resistors disabled All discharge resistors enabled Table 16. Undervoltage Lockout Options Options Option 0 Option 1 Min 1.95 3.10 Typ 2.15 3.65 Max 2.275 3.90 Unit V V Min 24 160 Typ 30 200 Max 36 240 Unit ms ms Typ 102 1.6 Max 122.4 1.92 Unit ms sec Table 17. Reset Timeout Options Options Option 0 Option 1 Table 18. Watchdog Timer Options Selection Option 0 Option 1 Min 81.6 1.28 Rev. B | Page 39 of 40 ADP5041 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) PIN 1 INDICATOR AREA 4.10 4.00 SQ 3.90 0.30 0.25 0.18 0.50 BSC 16 P IN 1 I N D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 20 1 15 2.75 2.60 SQ 2.35 EXPOSED PAD 5 11 0.80 0.75 0.70 SIDE VIEW PKG-003502 SEATING PLANE 10 0.20 MIN 6 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 09-24-2018-C TOP VIEW 0.50 0.40 0.30 COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-11. Figure 115. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-20-8) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP5041ACPZ-1-R7 Settings WD tOUT = 1.6 sec Min reset tOUT = 160 ms VUVLO = 2.15 V Discharge resistors enabled Temperature Range TJ = −40°C to +125°C ADP5041CP-1-EVALZ 1 Package Description 20-Lead LFCSP Evaluation Board Z = RoHS Compliant Part. ©2011–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09652-0-5/19(B) Rev. B | Page 40 of 40 Package Option CP-20-8