FEATURES
FUNCTIONAL BLOCK DIAGRAM
RoHS compliant, 16-lead, wide body SOIC package
Low power operation: 5 V
1.3 mA per channel maximum at 0 Mbps to 2 Mbps
3.3 mA per channel maximum at 10 Mbps
High temperature operation: 105°C
Up to 10 Mbps data rate (NRZ)
default output state
Safety and regulatory approvals
UL recognition: 3750 V rms for 1 minute per UL 1577
VDD1 1
GND1 2
ADuM1510
16
VDD2
15
GND2
VIA 3
ENCODE
DECODE
14
VOA
VIB 4
ENCODE
DECODE
13
VOB
VIC 5
ENCODE
DECODE
12
VOC
VID 6
ENCODE
DECODE
11
VOD
VIE 7
ENCODE
DECODE
10
VOE
GND1 8
9
GND2
06790-001
Data Sheet
5-Channel, Unidirectional Digital Isolator
ADuM1510
Figure 1.
APPLICATIONS
General-purpose, unidirectional, multichannel isolation
GENERAL DESCRIPTION
The ADuM15101 is a unidirectional, 5-channel isolator based
on the Analog Devices, Inc., iCoupler® technology. Combining
high speed CMOS and monolithic air core transformer technology,
these isolation components provide outstanding performance
characteristics superior to alternatives such as optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
eliminate the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
1
characteristics. The need for external drivers and other discrete
components is eliminated with iCoupler products. In addition,
iCoupler devices run at one-tenth to one-sixth the power
consumption of optocouplers at comparable signal data rates.
The ADuM1510 isolator provides five independent isolation
channels supporting data rates up to 10 Mbps. The ADuM1510
operates with the supply voltage of either side ranging from 4.5 V
to 5.5 V. Unlike other optocoupler alternatives, the ADuM1510
isolator has a patented refresh feature that ensures dc correctness in
the absence of input logic transitions and during power-up/
power-down conditions.
Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
Rev. D
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ADuM1510
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................6
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................7
Functional Block Diagram .............................................................. 1
Applications Information .................................................................8
Revision History ............................................................................... 2
PCB Layout ....................................................................................8
Specifications..................................................................................... 3
Propagation Delay-Related Parameters ......................................8
Electrical Characteristics—5 V Operation................................ 3
DC Correctness and Magnetic Field Immunity ............................8
Package Characteristics ............................................................... 4
Power Consumption .....................................................................9
Regulatory Information ............................................................... 4
Power-Up/Power-Down Considerations ...................................9
Insulation and Safety-Related Specifications ............................ 4
Outline Dimensions ....................................................................... 11
Recommended Operating Conditions ...................................... 4
Ordering Guide .......................................................................... 11
Absolute Maximum Ratings............................................................ 5
REVISION HISTORY
10/15—Rev. C to Rev. D
Change to Features Section ............................................................. 1
Changes to Table 3 ............................................................................ 4
5/14—Rev. B to Rev. C
Changed Double/Reinforced Insulation to Single Protection,
Table 3 ................................................................................................ 4
3/12—Rev. A to Rev. B
Created Hyperlink for Safety and Regulatory Approvals Entry
in Features Section............................................................................ 1
Change to PCB Layout Section ....................................................... 8
Updated Outline Dimensions ....................................................... 11
9/08—Revision A: Initial Version
Rev. D | Page 2 of 12
Data Sheet
ADuM1510
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
DC SPECIFICATIONS
Input Quiescent Supply Current per Channel
Output Quiescent Supply Current per Channel
Total Supply Current, Five Channels 1
VDD1 Supply Current, Quiescent
VDD2 Supply Current, Quiescent
VDD1 Supply Current, 10 Mbps Data Rate
VDD2 Supply Current, 10 Mbps Data Rate
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
Minimum Pulse Width 2
Maximum Data Rate 3
Propagation Delay 4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew 5
Channel-to-Channel Matching 6
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Logic High Output 7
Common-Mode Transient Immunity at
Logic Low Output7
Refresh Rate
Input Dynamic Supply Current per Channel 8
Output Dynamic Supply Current per Channel8
Symbol
Min
Typ
Max
Unit
IDDI (Q)
IDDO (Q)
0.40
0.30
0.80
0.50
mA
mA
IDD1 (Q)
IDD2 (Q)
IDD1 (10)
IDD2 (10)
IIA, IIB, IIC, IID, IIE −10
VIH
VIL
0.8
VDD2 − 0.4
VOAH, VOBH,
VOCH, VODH,
VOEH
VOAL, VOBL,
VOCL, VODL, VOEL
2.0
1.5
7.5
3.1
+1
4.0
2.5
12.0
4.5
+10
2.0
mA
mA
mA
mA
µA
V
V
V
IOx = −4 mA, VIx = VIH
0.4
V
IOx = +4 mA, VIx = VIL
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
4.8
0.2
PW
tPSK
tPSKCD
tR/tF
|CMH|
25
2.5
35
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
kV/µs
|CML|
25
35
kV/µs
1.0
0.122
0.036
Mbps
mA/Mbps
mA/Mbps
tPHL, tPLH
PWD
10
20
30
50
5
5
30
5
fr
IDDI (D)
IDDO (D)
Test Conditions/Comments
VIA = VIB = VIC = VID = VIE = 0 V
VIA = VIB = VIC = VID = VIE = 0 V
5 MHz logic signal frequency
5 MHz logic signal frequency
VIA, VIB, VIC, VID, VIE ≥ 0 V
Supply current values are for all five channels combined running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate is calculated as described in the Power Consumption section. See Figure 4 through
Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See Figure 7 and Figure 8 for total IDD1
and IDD2 supply currents as a function of the data rate for the ADuM1510.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Operation below the minimum pulse width is not
recommended.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6
Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels within the same component.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VOx > 0.8 × VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VOx < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The
transient magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 4 through Figure 6 for information on the per-channel supply current as a function of the data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on
calculating the per-channel supply current for a given data rate.
1
Rev. D | Page 3 of 12
ADuM1510
Data Sheet
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Resistance (Input-to-Output) 1
Capacitance (Input-to-Output)2
Input Capacitance 2
IC Junction-to-Case Thermal Resistance, Side 1
Symbol
RI-O
CI-O
CI
θJCI
IC Junction-to-Case Thermal Resistance, Side 2
θJCO
1
2
Min
Typ
1012
2.2
4.0
33
Max
28
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of
package underside
Thermocouple located at center of
package underside
The device is considered a two-terminal device. Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM1510 has been approved by the following organization upon product release, as shown in Table 3.
Table 3.
UL
Recognized under UL 1577 Component Recognition Program 1
Single protection, 3750 V rms isolation voltage
File E214100
1
In accordance with UL 1577, each ADuM1510 is proof-tested by applying an insulation test voltage ≥ 4500 V rms for 1 sec (current leakage detection limit > 7.5 µA).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
2500
7.7 min
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
8.1 min
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
CTI
Isolation Group
Maximum Working Voltage Compatible with 50 Years VIORM
Service Life
0.017 min mm
>175
V
IIIa
565
V peak
Test Conditions/Comments
1 minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation.
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Continuous peak voltage across the isolation
barrier
RECOMMENDED OPERATING CONDITIONS
All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on
immunity to external magnetic fields.
Table 5.
Parameter
Operating Temperature
Supply Voltages
Input Signal Rise and Fall Times
Symbol
TA
VDD1, VDD2
Rev. D | Page 4 of 12
Min
−40
4.5
Typ
Max
+105
5.5
1.0
Unit
°C
V
ms
Data Sheet
ADuM1510
ABSOLUTE MAXIMUM RATINGS
Ambient temperature TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 6.
Parameter
Storage Temperature (TST) Range
Ambient Operating Temperature (TA)
Range
Supply Voltages1 (VDD1, VDD2)
Input Voltages1 (VIA, VIB, VIC, VID, VIE)
Output Voltages1 (VOA, VOB, VOC, VOD, VOE)
Average Output Current per Pin2
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients3
1
2
3
Rating
−65°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
ESD CAUTION
−18 mA to +18 mA
−22 mA to +22 mA
−100 kV/μs to +100 kV/μs
All voltages are relative to their respective ground.
See Figure 3 for maximum rated current values for various temperatures.
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latchup or permanent damage.
Rev. D | Page 5 of 12
ADuM1510
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1
16 VDD2
15 GND2*
VIA 3
ADuM1510
VIB 4
TOP VIEW
(Not to Scale)
VIC 5
14 VOA
13 VOB
12 VOC
VID 6
11 VOD
VIE 7
10 VOE
GND1* 8
9
GND2*
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
06790-002
GND1* 2
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2, 8
Mnemonic
VDD1
GND1
3
4
5
6
7
9, 15
VIA
VIB
VIC
VID
VIE
GND2
10
11
12
13
14
16
VOE
VOD
VOC
VOB
VOA
VDD2
Description
Supply Voltage for Isolator Side 1 (4.5 V to 5.5 V).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to
GND1 is recommended.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Logic Input E.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to
GND2 is recommended.
Logic Output E.
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Supply Voltage for Isolator Side 2 (4.5 V to 5.5 V).
Table 8. Truth Table (Positive Logic)
VIx
Input1
H
L
X
VDD1
State
Powered
Powered
Unpowered
VDD2
State
Powered
Powered
Powered
VOx
Output1
H
L
L
X
Powered
Unpowered
Z
1
Description
Normal operation, data is high.
Normal operation, data is low.
Input unpowered. Outputs return to input state within 1 μs of VDD1 power restoration.
See the Power-Up/Power-Down Considerations section for more details.
Output unpowered. Output pins are in high impedance state. Outputs return to
input state within 1 μs of VDD2 power restoration. See the Power-Up/Power-Down
Considerations section for more details.
VIx and VOx refer to the input and output signals of a given channel (A, B, C, D, or E).
Rev. D | Page 6 of 12
Data Sheet
ADuM1510
TYPICAL PERFORMANCE CHARACTERISTICS
350
250
SIDE 2
200
150
SIDE 1
100
50
0
50
100
150
CASE TEMPERATURE (°C)
200
1.0
0.8
0.6
0.4
0.2
1.6
8
1.4
7
1.2
6
1.0
0.8
0.6
0.4
4
6
DATA RATE (Mbps)
8
10
5
4
3
2
1
2
4
6
DATA RATE (Mbps)
8
10
0
06790-004
0
Figure 4. Typical Input Supply Current per Channel vs. Data Rate
1.4
7
VDD2 CURRENT, 15pF LOAD (mA)
8
1.2
1.0
0.8
0.6
0.4
2
4
6
DATA RATE (Mbps)
8
10
06790-005
0.2
0
0
2
4
6
DATA RATE (Mbps)
8
10
Figure 7. Typical Total VDD1 Supply Current vs. Data Rate
1.6
0
2
06790-007
0.2
0
0
Figure 6. Typical Output Supply Current per Channel vs. Data Rate
(15 pF Output Load)
VDD1 CURRENT (mA)
VDD1 CURRENT/CHANNEL (mA)
1.2
0
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
VDD2 CURRENT/CHANNEL (mA)
1.4
Figure 5. Typical Output Supply Current per Channel vs. Data Rate
(No Output Load)
6
5
4
3
2
1
0
0
2
4
6
DATA RATE (Mbps)
8
Figure 8. Typical Total VDD2 Supply Current vs. Data Rate
(15 pF Output Load)
Rev. D | Page 7 of 12
10
06790-008
0
06790-003
SAFETY-LIMITING CURRENT (mA)
300
06790-006
VDD2 CURRENT/CHANNEL, 15pF LOAD (mA)
1.6
ADuM1510
Data Sheet
APPLICATIONS INFORMATION
PCB LAYOUT
VDD2
GND2
VOA
VOB
VOC
VOD
VOE
GND2
ADuM1510
V = (−dβ/dt) Σπrn2; n = 1, 2, … N
where:
Figure 9. Recommended PCB Layout
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of
time it takes for a logic signal to propagate through a component.
The propagation delay to a logic low output can differ from the
propagation delay to a logic high output.
INPUT (VIx)
β is the magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM1510 and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field can be calculated, as shown in Figure 11.
100
06790-010
tPHL
50%
Figure 10. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM1510 component.
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
50%
tPLH
OUTPUT (VOx)
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold of approximately
0.5 V, thus establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
10
1
0.1
0.01
0.001
1k
Propagation delay skew refers to the maximum amount that
the propagation delay differs among multiple ADuM1510
components operated under the same conditions.
1M
10k
100k
10M
MAGNETIC FIELD FREQUENCY (Hz)
100M
06790-011
VDD1
GND1
VIA
VIB
VIC
VID
VIE
GND1
The limitation on the magnetic field immunity of the device is
set by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The analysis below defines such conditions. In the following analysis, the ADuM1510 is examined in a 3 V operating
condition because it represents the most susceptible mode of
operation of all products in its product family.
06790-009
The ADuM1510 digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 9). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16
for VDD2. The capacitor value should be between 0.01 μF and
0.1 μF. The total lead length between both ends of the capacitor
and the input power supply pin must not exceed 10 mm. Bypassing
between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should
also be considered unless the ground pair on each package side
is connected close to the package.
If the decoder receives no pulses for more than approximately 5 μs,
the input side is assumed to be unpowered or nonfunctional, in
which case, the isolator output is forced to a default low state by
the watchdog timer circuit (see Table 8).
Figure 11. Maximum Allowable External Magnetic Flux Density
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the decoder.
The decoder is bistable and is, therefore, either set or reset by
the pulses indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1 μs, a periodic set
of refresh pulses indicative of the correct input state is sent to
ensure dc correctness at the output.
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This voltage is approximately
50% of the sensing threshold and does not cause a faulty output
transition. Similarly, if such an event occurs during a transmitted
pulse (and is of the worst-case polarity), the received pulse is
reduced from >1.0 V to 0.75 V, still well above the 0.5 V sensing
threshold of the decoder.
Rev. D | Page 8 of 12
Data Sheet
ADuM1510
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM1510 transformers. Figure 12 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As seen in Figure 12, the ADuM1510 is extremely
immune and is affected only by extremely large currents
operated at high frequency and very close to the component.
For example, at a magnetic field frequency of 1 MHz, a 0.5 kA
current would need to be placed 5 mm away from the
ADuM1510 to affect the operation of the component.
POWER-UP/POWER-DOWN CONSIDERATIONS
Given that the ADuM1510 has separate supplies on each side of
the isolation barrier, the power-up and power-down characteristics
relative to each supply voltage need to be considered individually.
DISTANCE = 1m
100
As shown in Table 8, when VDD1 input power is off, the ADuM1510
outputs take on a default low logic condition. As the VDD1 supply
is increased or decreased, the output of each channel transitions
from/to the default condition to/from the state matching its
respective signals (see Figure 13 and Figure 14).
10
DISTANCE = 100mm
1
DISTANCE = 5mm
OUTPUT
DATA
0.1
0.01
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
V DD1
2V
(TYP)
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce sufficiently
large error voltages to trigger the thresholds of succeeding
circuitry. Take care in the layout of such traces to avoid this
possibility.
06790-013
Figure 12. Maximum Allowable Current for
Various Current-to-ADuM1510 Spacings
Figure 13. VDD1 Power-Up/Power-Down Characteristics, Input Data = High
VDD1
POWER CONSUMPTION
The supply current at a given channel of the ADuM1510
isolator is a function of the supply voltage, the channel
data rate, and the channel output load.
OUTPUT DATA
06790-014
1k
06790-012
MAXIMUM ALLOWABLE CURRENT (kA)
1000
To calculate the total IDD1 and IDD2 supply current, the supply
currents for each input and output channel corresponding to
IDD1 and IDD2 are calculated and totaled. Figure 4 and Figure 5
provide per-channel supply currents as a function of the data
rate for an unloaded output condition. Figure 6 provides perchannel supply current as a function of the data rate for a 15 pF
output condition. Figure 7 and Figure 8 provide total IDD1 and
IDD2 supply current as a function of the data rate for ADuM1510
products.
Figure 14. VDD1 Power-Up/Power-Down Characteristics, Input Data = Low
For each input channel, the supply current is given by
IDDI = IDDI (Q)
f ≤ 0.5fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
f > 0.5fr
For each output channel, the supply current is given by
IDDO = IDDO (Q)
f ≤ 0.5fr
IDDO = (IDDO (D) + CLVDDO) × (2f − fr) + IDDO (Q)
f ≤ 0.5fr
where:
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
fr is the input stage refresh rate (Mbps).
When VDD1 crosses the threshold for activating the refresh circuit
(approximately 2 V), there can be a delay of up to 2 μs before the
output is updated to the correct state, depending on the timing
of the next refresh pulse. When VDD1 is reduced from an on state
below the 2 V threshold, there can be a delay of up to 5 μs before
the output takes on its default low state. This corresponds to the
duration that the watchdog timer circuit at the input is designed
to wait before triggering an output default state.
When the VDD2 output supply is below the level at which the
ADuM1510 output transistors are biased (approximately 1 V),
the outputs take on a high impedance state.
Rev. D | Page 9 of 12
ADuM1510
Data Sheet
OUTPUT
LOW
OUTPUT
LOW
OUTPUT
HIGH-Z
06790-016
D
D2
V
OUTPUT
HIGH-Z
OUTPUT
LOW
OUTPUT
LOW
OUTPUT
HIGH-Z
D2
D2
VD
06790-015
~1V
VD
Figure 16. VDD2 Power-Up/Power-Down Characteristics, Input Data = Low
~2V
D
D2
~2V
~1V
OUTPUT HIGH
V
OUTPUT LOW
OUTPUT
HIGH-Z
When VDD2 is above a value of approximately 2 V, each channel
output takes on a state matching that of its respective input.
Between the values of 1 V and 2 V, the outputs are set low. This
behavior is shown in Figure 15 and Figure 16.
Figure 15. VDD2 Power-Up/Power-Down Characteristics, Input Data = High
Rev. D | Page 10 of 12
Data Sheet
ADuM1510
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
03-27-2007-B
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 17. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Number
of Inputs,
Model 1
VDD1 Side
ADuM1510BRWZ
5
ADuM1510BRWZ-RL 5
1
Number
of Inputs,
VDD2 Side
0
0
Maximum
Data Rate
(Mbps)
10
10
Maximum
Propagation
Delay, 5 V (ns)
50
50
Maximum
Pulse Width
Distortion (ns)
5
5
Z = RoHS Compliant Part.
Rev. D | Page 11 of 12
Temperature
Range
−40°C to +105°C
−40°C to +105°C
Package
Description
16-Lead SOIC_W
16-Lead SOIC_W,
13” Tape and Reel
Package
Option
RW-16
RW-16
ADuM1510
Data Sheet
NOTES
©2008–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06790-0-10/15(D)
Rev. D | Page 12 of 12
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