LT8708ILWE-1#PBF

LT8708-1 80V Synchronous 4-Switch Buck-Boost DC/DC Slave Controller for LT8708 Multiphase System FEATURES DESCRIPTION Slave Chip of LT8708 to Deliver Additional Power n Good Current Matching to the Average Output Current of LT8708 Through Current Regulation n Easily Paralleled with LT8708 Through Four Pins n Synchronized Start-Up with LT8708 n Same Conduction Modes as LT8708 n Synchronous Rectification: Up to 98% Efficiency n Frequency Range: 100kHz to 400kHz n Available in 40-Lead (5mm × 8mm) QFN with High Voltage Pin Spacing and 64-Lead (10mm × 10mm) eLQFP n AEC-Q100 in Progress The LT®8708-1 is a high performance buck-boost switching regulator controller that is paralleled with the LT8708 to add power and phases to an LT8708 system. The LT8708-1 always operates as a slave to the master LT8708 and has the capability of delivering as much current or power as the master. One or more slaves can be connected to a single master, proportionally increasing power and current capability of the system. n APPLICATIONS The LT8708-1 has the same conduction modes as LT8708, allowing the LT8708-1 to conduct current and power in the same direction(s) as the master. The master controls the overall current and voltage limits for an LT8708 multiphase system, and the slaves comply with these limits. LT8708-1s can be easily paralleled with the LT8708 by connecting four signals together. Two additional current limits (forward VIN current and reverse VIN current) are available on each slave that can be set independently. High Voltage Buck-Boost Converters n Bidirectional Charging Systems n Automotive 48V Systems n All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION The LT8708-1 Two-Phase 12V Bidirectional Dual Battery System with FHCM and RHCM VBAT2 VBAT1 TO DIODE DB2 TO DIODE DB1 MASTER TG1 BOOST1 SW1 BG1 CSP CSN CSNIN LD033 LT8708* SWEN *REFER TO LT8708 DATA SHEET FOR MASTER SETUP RVSOFF CLKOUT ICP DIR ICN RVS (0V) FWD (3V) POWER TRANSFER DECISION LOGIC LD033 LD033 97 96 CSNOUT EXTVCC VOUTLOMON INTVCC 94 LT8708-1 SLAVE MODE VC 98 95 VBAT2 = 13.5V VBAT2 CHARGING CURRENT = 30A 10 12 14 VBAT1 (V) LD033 16 87081 TA01b GATEVCC DIR FBIN 99 GND BG2 SW2 BOOST2 TG2 CSPOUT CSPIN VINCHIP SHDN SWEN RVSOFF SYNC ICP ICN VINHIMON 100 10V TO 16V BATTERY EFFICIENCY (%) 10V TO 16V BATTERY Efficiency RT IMON_OP IMON_ON IMON_INP IMON_INN SS CLKOUT FBOUT DB1 DB2 TO TO BOOST1 BOOST2 120kHz 87081 TA01a Rev A Document Feedback For more information www.analog.com 1 LT8708-1 TABLE OF CONTENTS Features...................................................... 1 Applications................................................. 1 Typical Application ......................................... 1 Description.................................................. 1 Absolute Maximum Ratings............................... 3 Pin Configuration........................................... 3 Order Information........................................... 4 Electrical Characteristics.................................. 4 Typical Performance Characteristics.................... 8 Pin Functions............................................... 10 Block Diagram.............................................. 13 Operation................................................... 14 Common LT8708-1 and LT8708 Features................ 14 Adding Phases to an LT8708 Application................. 14 Adding Phases: The Master LT8708 ..................... 14 Adding Phases: The Slave LT8708-1 ..................... 16 Start-Up................................................................... 17 Start-Up: SWEN Pin............................................... 17 Start-Up: Soft-Start of Switching Regulator.......... 18 Control Overview..................................................... 18 Power Switch Control ............................................. 19 Unidirectional and Bidirectional Conduction............ 19 Error Amplifiers....................................................... 19 Transfer Function: IOUT(SLAVE) vs IOUT(MASTER)........... 20 Transfer Function: CCM......................................... 21 Transfer Function: DCM, HCM and Burst Mode Operation................................................................. 21 Current Monitoring and Limiting.............................. 21 Monitoring: IOUT(SLAVE)..................................................... 21 Monitoring and Limiting: IIN(SLAVE) ....................... 21 Multiphase Clocking................................................22 Applications Information................................. 23 Quick-Start Multiphase Setup..................................23 Quick Setup: Design the Master Phase..................23 Quick Setup: Design the Slave Phase(s)................23 Quick Setup: Evaluation.........................................23 Choosing the Total Number of Phases.....................23 Operating Frequency Selection................................ 24 CIN and COUT Selection............................................ 24 CIN and COUT Selection: VIN Capacitance............... 24 CIN and COUT Selection: VOUT Capacitance............25 VINHIMON, VOUTLOMON and RVSOFF ..................25 Configuring the IIN(SLAVE) Current Limits.................26 Regulating IOUT(SLAVE)......................................................... 26 IOUT(SLAVE): Circuit Description..............................26 IOUT(SLAVE): Configuration..................................... 28 Loop Compensation................................................. 28 Voltage Lockouts.....................................................29 Circuit Board Layout Checklist ................................29 Design Example ......................................................29 Typical Applications....................................... 31 Package Description...................................... 35 Revision History........................................... 37 Typical Application........................................ 38 Related Parts............................................... 38 Rev A 2 For more information www.analog.com LT8708-1 ABSOLUTE MAXIMUM RATINGS (Note 1) VCSP – VCSN, VCSPIN – VCSNIN, VCSPOUT – VCSNOUT................................ –0.3V to 0.3V CSP, CSN Voltage.......................................... –0.3V to 3V VC Voltage (Note 2).................................... –0.3V to 2.2V RT, FBOUT, SS Voltage................................. –0.3V to 5V IMON_INP, IMON_INN, IMON_OP, IMON_ON, ICP, ICN Voltage...................... –0.3V to 5V SYNC Voltage............................................. –0.3V to 5.5V INTVCC, GATEVCC Voltage............................. –0.3V to 7V VBOOST1 – VSW1, VBOOST2 – VSW2................. –0.3V to 7V SWEN, RVSOFF Voltage................................ –0.3V to 7V SWEN Current........................................................0.5mA RVSOFF Current........................................................1mA FBIN, SHDN Voltage ................................... –0.3V to 30V VINHIMON Voltage...................................... –0.3V to 30V VOUTLOMON Voltage................................... –0.3V to 5V DIR, MODE Voltage....................................... –0.3V to 5V CSNIN, CSPIN, CSPOUT, CSNOUT Voltage....–0.3V to 80V VINCHIP, EXTVCC Voltage............................. –0.3V to 80V SW1, SW2 Voltage ...................................... 81V (Note 6) BOOST1, BOOST2 Voltage.......................... –0.3V to 87V BG1, BG2, TG1, TG2............................................ (Note 5) LDO33, CLKOUT................................................. (Note 8) Operating Junction Temperature Range LT8708-1E (Notes 3, 8)........................–40°C to 125°C LT8708-1I (Notes 3, 8).........................–40°C to 125°C LT8708-1H (Notes 3, 8)........................–40°C to 150°C Storage Temperature Range....................–65°C to 150°C PIN CONFIGURATION TOP VIEW 40 39 38 37 36 35 NC CLKOUT LDO33 IMON_ON IMON_OP MODE SWEN INTVCC NC VINCHIP NC CSPIN CSNIN NC NC NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VINCHIP INTVCC SWEN MODE IMON_OP IMON_ON LDO33 TOP VIEW 34 CLKOUT 1 33 CSPIN SS 2 32 CSNIN SHDN 3 31 CSNOUT 30 CSPOUT CSN 4 CSP 5 29 EXTVCC ICN 6 DIR 7 41 GND FBIN 8 28 ICP 27 VINHIMON FBOUT 9 26 VOUTLOMON VC 10 25 RVSOFF IMON_INP 11 24 BOOST1 IMON_INN 12 RT 13 23 TG1 NC SS SHDN CSN CSP ICN DIR FBIN FBOUT VC IMON_INP IMON_INN RT SYNC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NC CSNOUT CSPOUT NC NC NC EXTVCC NC ICP VINHIMON VOUTLOMON RVSOFF NC BOOST1 TG1 SW1 NC NC GND BG1 GATEVCC BG2 NC BOOST2 TG2 SW2 NC NC NC NC NC NC SW2 TG2 BOOST2 BG2 GND GATEVCC 19 20 21 BG1 15 16 17 18 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 22 SW1 SYNC 14 UHG PACKAGE 40-LEAD (5mm × 8mm) PLASTIC QFN TJMAX = 150°C, θJA = 36°C/W, θJC = 38°C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB LWE PACKAGE 64-LEAD (10mm × 10mm) PLASTIC LQFP TJMAX = 150°C, θJA = 17°C/W, θJC = 2.5°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB Rev A For more information www.analog.com 3 LT8708-1 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8708EUHG-1#PBF LT8708EUHG-1#TRPBF 87081 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C LT8708IUHG-1#PBF LT8708IUHG-1#TRPBF 87081 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C LT8708HUHG-1#PBF LT8708HUHG-1#TRPBF 87081 40-Lead (5mm × 8mm) Plastic QFN –40°C to 150°C LT8708EUHG-1#WPBF LT8708EUHG-1#WTRPBF 87081 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C LT8708IUHG-1#WPBF LT8708IUHG-1#WTRPBF 87081 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C LT8708HUHG-1#WPBF LT8708HUHG-1#WTRPBF 87081 40-Lead (5mm × 8mm) Plastic QFN –40°C to 150°C AUTOMOTIVE PRODUCTS** TRAY PART MARKING* PACKAGE DESCRIPTION LT8708ELWE-1#PBF LT8708LWE-1 64-Lead (10mm × 10mm) Plastic eLQFP MSL RATING 3 TEMPERATURE RANGE –40°C to 125°C LT8708ILWE-1#PBF LT8708LWE-1 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 125°C LT8708HLWE-1#PBF LT8708LWE-1 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 150°C LT8708ELWE-1#WPBF LT8708LWE-1 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 125°C LT8708ILWE-1#WPBF LT8708LWE-1 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 125°C LT8708HLWE-1#WPBF LT8708LWE-1 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 150°C AUTOMOTIVE PRODUCTS** Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VINCHIP =12V, SHDN = 3V, DIR = 3.3V unless otherwise noted. (Note 3). PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage Supplies and Regulators VINCHIP Operating Voltage Range EXTVCC = 0V EXTVCC = 7.5V VINCHIP Quiescent Current Not Switching, VEXTVCC = 0 SWEN = 3.3V SWEN = 0V VINCHIP Quiescent Current in Shutdown VSHDN = 0V EXTVCC Switchover Voltage IINTVCC = –20mA, VEXTVCC Rising l l l 5.5 2.8 6.15 EXTVCC Switchover Hysteresis INTVCC Current Limit 80 80 V V 4.7 2.45 7.5 4.5 mA mA 0 1 µA 6.4 6.6 V 0.2 V Max Current Draw from INTVCC and LDO33 Pins Combined. Regulated from VINCHIP or EXTVCC (12V) INTVCC = 5.25V l INTVCC = 4.4V l 90 28 127 42 165 55 mA mA INTVCC Voltage Regulated from VINCHIP, IINTVCC = 20mA Regulated from EXTVCC (12V), IINTVCC = 20mA 6.1 6.1 6.3 6.3 6.5 6.5 V V INTVCC Load Regulation IINTVCC = 0mA to 50mA –0.5 –1.5 % INTVCC, GATEVCC Undervoltage Lockout INTVCC Falling, GATEVCC Connected to INTVCC 4.65 4.85 V l l l 4.45 Rev A 4 For more information www.analog.com LT8708-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VINCHIP =12V, SHDN = 3V, DIR = 3.3V unless otherwise noted. (Note 3). PARAMETER CONDITIONS INTVCC, GATEVCC Undervoltage Lockout Hysteresis GATEVCC Connected to INTVCC INTVCC Regulator Dropout Voltage VINCHIP – VINTVCC, IINTVCC = 20mA LDO33 Pin Voltage 5mA from LDO33 Pin LDO33 Pin Load Regulation ILDO33 = 0.1mA to 5mA LDO33 Pin Current Limit SYNC = 3V LDO33 Pin Undervoltage Lockout LDO33 Falling MIN TYP MAX 160 mV 245 l l 3.23 mV 3.295 3.35 V –0.25 –1 % mA 12 17.25 22 2.96 3.04 3.12 LDO33 Pin Undervoltage Lockout Hysteresis UNITS 35 V mV Switching Regulator Control Maximum Current Sense Threshold (VCSP – VCSN) Boost Mode, Minimum M3 Switch Duty Cycle l 76 93 Maximum Current Sense Threshold (VCSN – VCSP) Buck Mode, Minimum M2 Switch Duty Cycle l 68 Maximum Current Sense Threshold (VCSN – VCSP) Boost Mode, Minimum M3 Switch Duty Cycle l 79 Maximum Current Sense Threshold (VCSP – VCSN) Buck Mode, Minimum M2 Switch Duty Cycle l 72 Gain from VC to Max Current Sense Voltage (VCSP – VCSN) (A5 in the Block Diagram) Boost Mode Buck Mode SHDN Input Voltage High SHDN Rising to Enable the Device QFN LWE SHDN Pin Bias Current mV 82 97 mV 93 108 mV 84 96 135 –135 l 1.175 l 1.175 SHDN Input Voltage High Hysteresis SHDN Input Voltage Low 110 1.221 1.275 1.221 1.29 40 Device Disabled, Low Quiescent Current (LT8708E-1, LT8708I-1) (LT8708H-1) l l VSHDN = 3V VSHDN = 12V 0 14 l 1.156 SWEN Rising Threshold Voltage SWEN Threshold Voltage Hysteresis mV mV/V mV/V V V mV 0.35 0.3 V V 1 22 µA µA 1.208 1.256 22 V mV ISWEN = 200µA SHDN = 0V or VINCHIP = 0V SHDN = 3V l l SHDN = 3V l 0.75 MODE Pin Continuous Conduction Mode (CCM) Threshold l 0.4 MODE Pin Hybrid DCM/CCM Mode (HCM) Range l 0.8 1.2 V MODE Pin Discontinuous Conduction Mode (DCM) Range l 1.6 2.0 V MODE Pin Burst Mode Operation Threshold l DIR Pin Forward Operation Threshold l DIR Pin Reverse Operation Threshold l SWEN Output Voltage Low SWEN Internal Pull-Down Release Voltage RVSOFF Output Voltage Low IRVSOFF = 200µA RVSOFF Falling Threshold Voltage 0.9 0.2 0.8 V 2.4 V V 1.2 l 0.08 l 1.155 1.209 1.275 0.5 165 VSS = 0V VSS = 0.5V V V V 1.6 RVSOFF Threshold Voltage Hysteresis Soft-Start Charging Current 1.1 0.5 V V V mV 13 21 19 31 25 41 µA µA IMON_ON Rising Threshold for FDCM Operation MODE = 1V (HCM), DIR = 3.3V l 235 255 280 mV IMON_ON Falling Threshold for CCM Operation MODE = 1V (HCM), DIR = 3.3V l 185 205 235 mV IMON_INP Rising Threshold for RDCM Operation MODE = 1V (HCM), DIR = 0V l 235 255 280 mV IMON_INP Falling Threshold for CCM Operation MODE = 1V (HCM), DIR = 0V l 185 205 235 mV Rev A For more information www.analog.com 5 LT8708-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VINCHIP =12V, SHDN = 3V, DIR = 3.3V unless otherwise noted. (Note 3). PARAMETER CONDITIONS MIN TYP MAX UNITS ICP Rising Threshold for Start Switching l 485 510 536 mV ICN Rising Threshold for Start Switching l 485 510 536 mV ICP Rising Threshold for Enabling Non-CCM Offset Current l 680 704 730 mV ICP Falling Threshold for Disabling Non-CCM Offset Current l 500 530 560 mV ICN Rising Threshold for Enabling Non-CCM Offset Current l 680 704 730 mV ICN Falling Threshold for Disabling Non-CCM Offset Current l 500 530 560 mV Voltage Regulation Loops (Refer to Block Diagram to Locate Amplifiers) Regulation Voltage for FBOUT Regulate VC to 1.2V l 1.193 1.207 1.222 V Regulation Voltage for FBIN Regulate VC to 1.2V l 1.184 1.205 1.226 V 0.002 0.005 %/V Line Regulation for FBOUT and FBIN Error Amp Reference Voltage VINCHIP = 12V to 80V, Not Switching FBOUT Pin Bias Current Current Out of Pin FBOUT Error Amp EA4 gm FBOUT Error Amp EA4 Voltage Gain VOUTLOMON Voltage Activation Threshold Falling l 1.185 VOUTLOMON Threshold Voltage Hysteresis 15 nA 345 µmho 245 V/V 1.207 1.225 24 VVOUTLOMON = 1.24V, Current Into Pin VVOUTLOMON = 1.17V, Current Into Pin VOUTLOMON Pin Bias Current FBIN Pin Bias Current l 0.8 Current Out of Pin 0.01 1 V mV 1.2 µA µA 10 nA FBIN Error Amp EA3 gm 235 µmho FBIN Error Amp EA3 Voltage Gain 150 V/V VINHIMON Voltage Activation Threshold Rising l 1.185 VINHIMON Threshold Voltage Hysteresis 1.207 1.23 24 VVINHIMON = 1.17V, Current Into Pin VVINHIMON = 1.24V, Current Out of Pin VINHIMON Pin Bias Current l 0.8 0.01 1 V mV 1.2 µA µA Current Regulation Loops (Refer to Block Diagram to Locate Amplifiers) Regulation Voltages for IMON_INP and IMON_OP VC = 1.2V l 1.185 1.209 1.231 V Regulation Voltages for IMON_INN VC = 1.2V l 1.185 1.21 1.24 V Line Regulation for IMON_INP, IMON_INN and IMON_OP Error Amp Reference Voltage VINCHIP = 12V to 80V 0.002 0.005 %/V CSPIN Bias Current VCSPIN = 12V VCSPIN = 1.5V 0.01 0.01 µA µA CSNIN Bias Current BOOST Capacitor Charge Control Block Not Active VSWEN = 3.3V, VCSPIN = VCSNIN = 12V VSWEN = 3.3V, VCSPIN = VCSNIN = 1.5V VSWEN = 0V 84 4.25 0.01 µA µA µA CSPIN, CSNIN Common Mode Operating Voltage Range l 0 80 V CSPIN, CSNIN Differential Mode Operating Voltage Range l –100 100 mV IMON_INP Output Current IMON_INN Output Current VCSPIN – VCSNIN = 50mV, VCSNIN = 5V VCSPIN – VCSNIN = 50mV, VCSNIN = 5V VCSPIN – VCSNIN = 5mV, VCSNIN = 5V VCSPIN – VCSNIN = 5mV, VCSNIN = 5V VCSNIN – VCSPIN = 50mV, VCSNIN = 5V VCSNIN – VCSPIN = 50mV, VCSNIN = 5V VCSNIN – VCSPIN = 5mV, VCSNIN = 5V VCSNIN – VCSPIN = 5mV, VCSNIN = 5V l l l l 67 64.5 22.5 20 70 70 25 25 73 75.5 27.5 30 µA µA µA µA 66 65 19 18 70 70 25 25 74 75 30.5 32 µA µA µA µA Rev A 6 For more information www.analog.com LT8708-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VINCHIP =12V, SHDN = 3V, DIR = 3.3V unless otherwise noted. (Note 3). PARAMETER CONDITIONS MIN IMON_INP and IMON_INN Max Output Current l TYP MAX 120 µA 190 IMON_INP Error Amp EA5 gm IMON_INP Error Amp EA5 Voltage Gain UNITS µmho 130 V/V IMON_INN Error Amp EA1 gm FBIN = 0V, FBOUT = 3.3V 190 µmho IMON_INN Error Amp EA1 Voltage Gain FBIN = 0V, FBOUT = 3.3V 130 V/V CSPOUT Bias Current VCSPOUT = 12V VCSPOUT = 1.5V 0.01 0.01 µA µA CSNOUT Bias Current BOOST Capacitor Charge Control Block Not Active VSWEN = 3.3V, VCSPOUT = VCSNOUT = 12V VSWEN = 3.3V, VCSPOUT = VCSNOUT = 1.5V VSWEN = 0V 83 4.25 0.01 µA µA µA CSPOUT, CSNOUT Common Mode Operating Voltage Range l 0 80 V CSPOUT, CSNOUT Differential Mode Operating Voltage Range l –100 100 mV 73 75 27.5 29 17.5 19.5 µA µA µA µA µA µA VCSNOUT – VCSPOUT = 50mV, VCSNOUT = 5V VCSNOUT – VCSPOUT = 50mV, VCSNOUT = 5V VCSNOUT – VCSPOUT = 5mV, VCSNOUT = 5V VCSNOUT – VCSPOUT = 5mV, VCSNOUT = 5V VCSNOUT – VCSPOUT = −5mV, VCSNOUT = 5V VCSNOUT – VCSPOUT = −5mV, VCSNOUT = 5V IMON_ON Output Current IMON_ON Max Output Current Regulate VC to 1.2V RIMON_OP = 17.4kΩ VCSNOUT = 12V CSPOUT–CSNOUT Regulation Voltage l 67 65 22.5 20.5 12.5 10.5 l 120 l l 70 70 25 25 15 15 µA ICP = 1.218V, ICN = 0V l 43 50 55 mV ICP = 0V, ICN = 1.218V l –55 –50 –44 mV ICP = ICN = 0.348V –6 0 6 mV l NMOS Gate Drivers TG1, TG2 Rise Time CLOAD = 3300pF (Note 4) 20 ns TG1, TG2 Fall Time CLOAD = 3300pF (Note 4) 20 ns BG1, BG2 Rise Time CLOAD = 3300pF (Note 4) 20 ns BG1, BG2 Fall Time CLOAD = 3300pF (Note 4) 20 ns TG1 Off to BG1 On Delay CLOAD = 3300pF Each Driver 90 ns BG1 Off to TG1 On Delay CLOAD = 3300pF Each Driver 80 ns TG2 Off to BG2 On Delay CLOAD = 3300pF Each Driver 90 ns BG2 Off to TG2 On Delay CLOAD = 3300pF Each Driver 80 ns Min On-Time for Main Switch in Boost Operation (tON(M3,MIN)) Switch M3, CLOAD = 3300pF 200 ns Min On-Time for Synchronous Switch in Buck Operation (tON(M2,MIN)) Switch M2, CLOAD = 3300pF 200 ns Switch M3, CLOAD = 3300pF 230 ns Min Off-Time for Synchronous Switch in Steady-State Buck Operation Switch M2, CLOAD = 3300pF 230 ns Min Off-Time for Main Switch in Steady-State Boost Operation Oscillator Switch Frequency Range SYNCing or Free Running Switching Frequency, fOSC RT = 365k RT = 215k RT = 124k 100 l l l 102 170 310 SYNC High Level for Synchronization l 1.3 SYNC Low Level for Synchronization l SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V Recommended Min SYNC Ratio fSYNC/fOSC 120 202 350 400 kHz 142 235 400 kHz kHz kHz V 20 0.5 V 80 % 3/4 Rev A For more information www.analog.com 7 LT8708-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VINCHIP =12V, SHDN = 3V, DIR = 3.3V unless otherwise noted. (Note 3). PARAMETER CONDITIONS CLKOUT Output Voltage High VLDO33 – VCLKOUT, 1mA Out of CLKOUT Pin, ILDO33 = 0µA CLKOUT Output Voltage Low 1mA Into CLKOUT Pin CLKOUT Duty Cycle TJ = –40°C TJ = 25°C TJ = 125°C CLKOUT Rise Time CLOAD = 200pF CLKOUT Fall Time CLOAD = 200pF CLKOUT Phase Delay SYNC Rising to CLKOUT Rising, fOSC = 100kHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not force voltage on the VC pin. Note 3: The LT8708E-1 is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8708I-1 is guaranteed over the full –40°C to 125°C junction temperature range. The LT8708H-1 is guaranteed over the full –40°C to 150°C operating junction temperature range. Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. MIN 90 80 80 70 70 70 30 20 10 0 0.01 0.1 1 IOUT (A) 10 60 50 40 VIN = 16V VOUT = 12V HCM DCM CCM 30 20 10 30 87081 G01 EFFICIENCY (%) 90 80 EFFICIENCY (%) 90 EFFICIENCY (%) 100 VIN = 11.5V VOUT = 14.5V HCM DCM CCM 0 0.01 0.1 250 mV 25 100 mV 22.7 44.1 77 % % % 20 ns l 160 180 ns 200 Degree Efficiency vs Output Current (Buck-Boost Region – Page 32) 100 40 100 TA = 25°C, unless otherwise noted. 100 50 UNITS Note 5: Do not apply a voltage or current source to these pins. They must be connected to capacitive loads only, otherwise permanent damage may occur. Note 6: Negative voltages on the SW1 and SW2 pins are limited, in an application, by the body diodes of the external NMOS devices, M2 and M3, or parallel Schottky diodes when present. The SW1 and SW2 pins are tolerant of these negative voltages in excess of one diode drop below ground, guaranteed by design. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 8: Do not force voltage or current into these pins. Efficiency vs Output Current (Buck Region – Page 32) 60 MAX 20 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Output Current (Boost Region – Page 32) TYP 1 IOUT (A) 10 60 50 40 VIN = 14.5V VOUT = 14.5V HCM DCM CCM 30 20 10 30 87081 G02 0 0.01 0.1 1 IOUT (A) 10 30 87081 G03 Rev A 8 For more information www.analog.com LT8708-1 TYPICAL PERFORMANCE CHARACTERISTICS CSPOUT – CSNOUT Voltages (ICP = 1.218V, ICN = 0V) (Five Parts) CSNOUT – CSPOUT Voltages (ICP = 1.218V, ICN = 0V) (Five Parts) 80 70 60 50 40 30 20 –50 –30 –10 10 30 50 70 90 110 130 150 TEMPERATURE (°C) 190 60 50 40 150 110 70 30 30 –10 –150 Maximum and Minimum VC vs SS (ICP or ICN = 1V) 2.5 TJ = 25°C MAXIMUM VC 1.5 1.5 0 0 0.25 0.50 0.75 ICP/ICN VOLTAGE (V) 1 VC (V) 1.5 VC (V) 2.0 2.0 1.0 0.5 MINIMUM VC 1.25 0 0.5 87081 G07 1 SS (V) 1.5 1.0 2 0 MINIMUM VC 0 0.25 0.75 1 Load Step (Page 32) VIN = 14.5V VOUT = 14.5V LT8708 IL 10A/DIV LT8708 IL 10A/DIV LT8708-1 IL 10A/DIV LT8708-1 IL 10A/DIV 500μs/DIV 87081 G10 VBAT1 = 12V, VBAT2 REGULATED TO 14.5V LOAD STEP = 10A TO 25A LOAD APPLIED AT VBAT2 WITH BATTERY DISCONNECTED 0.50 SS (V) 87081 G09 87081 G08 Load Step (Page 32) VIN = 12V VOUT = 14.5V 500μs/DIV MAXIMUM VC 0.5 MINIMUM VC 0 TJ = 25°C MAXIMUM VC 2.0 0.5 150 87081 G06 Maximum and Minimum VC vs SS (ICP = ICN =0.348V) 1.0 –75 0 75 CSPOUT–CSNOUT (mV) 87081 G05 2.5 TJ = 25°C ICP = ICN = 0.348V 70 Maximum and Minimum VC vs ICP_ICN (SS = 0) VC (V) VC = ~1.3V 20 –50 –30 –10 10 30 50 70 90 110 130 150 TEMPERATURE (°C) 87081 G04 2.5 IMON_OP Output Current 230 IMON_OP CURRENT (µA) VC ≅ 1.3V CSNOUT–CSPOUT VOLTAGES (mV) CSPOUT–CSNOUT VOLTAGES (mV) 80 TA = 25°C, unless otherwise noted. 87081 G11 VBAT1 = 14.5V, VBAT2 REGULATED TO 14.5V LOAD STEP = 10A TO 25A LOAD APPLIED AT VBAT2 WITH BATTERY DISCONNECTED Rev A For more information www.analog.com 9 LT8708-1 TYPICAL PERFORMANCE CHARACTERISTICS Load Step (Page 32) VIN = 16V VOUT = 14.5V Load Step (Page 33) VIN = 48V VOUT = 14.5V LT8708 IL 20A/DIV LT8708 IL 10A/DIV PHASE 1 PHASE 2 LT8708-1 IL 20A/DIV LT8708-1 IL 20A/DIV LT8708-1 IL 20A/DIV LT8708-1 IL 10A/DIV 500μs/DIV PIN FUNCTIONS PHASE 3 PHASE 4 500μs/DIV 87081 G12 VBAT1 = 16V, VBAT2 REGULATED TO 14.5V LOAD STEP = 10A TO 25A LOAD APPLIED AT VBAT2 WITH BATTERY DISCONNECTED TA = 25°C, unless otherwise noted. 87081 G13 VBAT1 = 48V, VBAT2 REGULATED TO 14.5V LOAD STEP = 20A TO 55A LOAD APPLIED AT VBAT2 WITH BATTERY DISCONNECTED (QFN/eLQFP) CLKOUT (Pin 1/Pin 63): Clock Output Pin. Use this pin to synchronize one or more compatible switching regulator ICs. CLKOUT toggles at the same frequency as the internal oscillator or as the SYNC pin, but is approximately 180° out of phase. CLKOUT may also be used as a temperature monitor since the CLKOUT duty cycle varies linearly with the part’s junction temperature. The CLKOUT pin can drive capacitive loads up to 200pF. ICN (Pin 6/Pin 6): Negative VOUT Current Command Pin. The voltage on this pin determines the negative VOUT current for LT8708-1 to regulate to. Connect this pin to the master LT8708’s ICN pin. See the Applications Information section for more information. SS (Pin 2/Pin 2): Soft-Start Pin. Place a capacitor from this pin to ground. A capacitor identical to the SS pin capacitor used on the master LT8708 is recommended. Upon start-up, this pin will be charged by an internal resistor to 3.3V. DIR (Pin 7/Pin 7): Direction pin when MODE is set for DCM (discontinuous conduction mode) or HCM (hybrid conduction mode) operation. Otherwise this pin is ignored. Connect the pin to GND to process power from the VOUT to VIN. Connect the pin to LDO33 to process power from the VIN to VOUT. Drive this pin with the same control signal, or connect this pin to the same voltages as the master LT8708. SHDN (Pin 3/Pin 3): Shutdown Pin. Tie high to enable chip. Ground to shut down and reduce quiescent current to a minimum. Do not float this pin. FBIN (Pin 8/Pin 8): VIN Feedback Pin. This pin is connected to the input of error amplifier EA3. Typically, connect this pin to LDO33 to disable the EA3. CSN (Pin 4/Pin 4): The (–) Input to the Inductor Current Sense and DCM Detect Comparator. FBOUT (Pin 9/Pin 9): VOUT Feedback Pin. This pin is connected to the input of error amplifier EA4. Typically, connect this pin to GND to disable the EA4. CSP (Pin 5/Pin 5): The (+) Input to the Inductor Current Sense and DCM Detect Comparator. The VC pin voltage and built-in offsets between CSP and CSN pins, in conjunction with the RSENSE value, set the inductor current trip threshold. It is recommended to use the same value RSENSE as the master LT8708. VC (Pin 10/Pin 10): Error Amplifier Output Pin. Tie external compensation network to this pin. IMON_INP (Pin 11/Pin 11): Positive VIN Current Monitor and Limit Pin. The current out of this pin is 20µA plus a current proportional to the positive average VIN current. IMON_INP also connects to error amplifier EA5 and can Rev A 10 For more information www.analog.com LT8708-1 PIN FUNCTIONS (QFN/eLQFP) be used to limit the maximum positive VIN current. See the Applications Information section for more information. IMON_INN (Pin 12/Pin 12): Negative VIN Current Monitor and Limit Pin. The current out of this pin is 20µA plus a current proportional to the negative average VIN current. IMON_INN also connects to error amplifier EA1 and can be used to limit the maximum negative VIN current. See the Applications Information section for more information. RT (Pin 13/Pin 13): Timing Resistor Pin. Adjusts the switching frequency. Place a resistor from this pin to ground to set the frequency. It is recommended to use the same value RT resistor as the master LT8708. Do not float this pin. SYNC (Pin 14/Pin 14): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less than 0.5V. In a two-phase system, connect this pin to the master LT8708’s CLKOUT pin to have a 180° phase shift. See the Applications Information section for more information. BG1, BG2 (Pin 16/Pin 20, Pin 18/Pin 22): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFETs between ground and GATEVCC. GATEVCC (Pin 17/Pin 21): Power supply for bottom gate drivers. Must be connected to the INTVCC pin. Do not power from any other supply. Locally bypass to GND. It is recommended to use the same value bypass cap as the master LT8708. BOOST1, BOOST2 (Pin 24/Pin 35, Pin 19/Pin 24): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor connects here. The BOOST1 pin swings from a diode voltage below GATEVCC up to VIN + GATEVCC. The BOOST2 pin swings from a diode voltage below GATEVCC up to VOUT + GATEVCC. TG1, TG2 (Pin 23/Pin 34, Pin 20/Pin 25): Top Gate Drive. Drives the top N-channel MOSFETs with voltage swings equal to GATEVCC superimposed on the switch node voltages. SW1, SW2 (Pin 22/Pin 33, Pin 21/Pin 26): Switch Nodes. The (–) terminals of the bootstrap capacitors connect here. RVSOFF (Pin 25/Pin 37): Reverse Conduction Disable Pin. This is an input/output open-drain pin that requires a pull-up resistor. Pulling this pin low disables reverse current operation. Typically, connect this pin to the LT8708’s RVSOFF pin. See the Unidirectional and Bidirectional Conduction section for more information. VOUTLOMON (Pin 26/Pin 38): VOUT Low Voltage Monitor Pin. Connect a ±1% resistor divider between VOUT, VOUTLOMON and GND to set an undervoltage level on VOUT. When VOUT is lower than this level, reverse conduction is disabled to prevent drawing current from VOUT. See the Applications Information section for more information. VINHIMON (Pin 27/Pin 39): VIN High Voltage Monitor Pin. Connect a ±1% resistor divider between VIN, VINHIMON and GND in order to set an overvoltage level on VIN. When VIN is higher than this level, reverse conduction is disabled to prevent current flow into VIN. See the Applications Information section for more information. ICP (Pin 28/Pin 40): Positive VOUT Current Command Pin. The voltage on this pin determines the positive VOUT current for LT8708-1 to regulate to. Connect this pin to LT8708’s ICP pin. See the Applications Information section for more information. EXTVCC (Pin 29/Pin 42): External VCC Input. When EXTVCC exceeds 6.4V (typical), INTVCC will be powered from this pin. When EXTVCC is lower than 6.4V, the INTVCC will be powered from VINCHIP. It is recommended to use the same value bypass cap as the master LT8708. CSPOUT (Pin 30/Pin 46): The (+) Input to the VOUT Current Monitor Amplifier. This pin and the CSNOUT pin measure the voltage across the sense resistor, RSENSE2, to provide the VOUT current signals. It is recommended to use the same value RSENSE2 between the CSPOUT and CSNOUT pins as the master LT8708. See Applications Information section for proper use of this pin. CSNOUT (Pin 31/Pin 47): The (–) Input to the VOUT Current Monitor Amplifier. See Applications Information section for proper use of this pin. CSNIN (Pin 32/Pin 52): The (–) Input to the VIN Current Monitor Amplifier. This pin and the CSPIN pin measure the voltage across the sense resistor, RSENSE1, to provide Rev A For more information www.analog.com 11 LT8708-1 PIN FUNCTIONS (QFN/eLQFP) the VIN current signals. Connect this pin to VIN when not in use. See Applications Information section for proper use of this pin. CSPIN (Pin 33/Pin 53): The (+) Input to the VIN Current Monitor Amplifier. Connect this pin to VIN when not in use. See Applications Information section for proper use of this pin. VINCHIP (Pin 34/Pin 55): Main Input Supply Pin for the LT8708‑1. It must be locally bypassed to ground. It is recommended to use the same value bypass cap as the master LT8708. INTVCC (Pin 35/Pin 57): 6.35V Regulator Output. Must be connected to the GATEVCC pin. INTVCC is powered from EXTVCC when the EXTVCC voltage is higher than 6.4V, otherwise INTVCC is powered from VINCHIP. Bypass this pin to ground with a minimum 4.7µF ceramic capacitor. It is recommended to use the same value bypass cap as the master LT8708. SWEN (Pin 36/Pin 58): Switching Regulator Enable Pin. Tie high through a resistor to enable the switching. Ground to disable switching. This pin is pulled down during shutdown, a thermal lockout or when an internal UVLO (Under Voltage Lockout) is detected. Do not float this pin. Connect this pin to the LT8708’s SWEN pin for synchronized start-up. See the Start-Up: SWEN Pin section for more details. MODE (Pin 37/Pin 59): Conduction Mode Select Pin. The voltage applied to this pin sets the conduction mode of the controller. Apply less than 0.4V to enable continuous conduction mode (CCM). Apply 0.8V to 1.2V to enable the hybrid conduction mode (HCM). Apply 1.6V to 2.0V to enable the discontinuous conduction mode (DCM). Apply more than 2.4V to enable Burst Mode operation. It is recommended to drive this pin with the same control signal, or connect this pin to the same value resistor dividers or voltages as the master LT8708. IMON_OP (Pin 38/Pin 60): Average VOUT Current Regulation Pin. This pin servos to 1.207V to regulate the average output current based on the ICP and ICN voltages. Always connect a 17.4k resistor in parallel with a compensation network from this pin to GND. See the Applications Information section for more information. IMON_ON (Pin 39/Pin 61): Negative VOUT Current Monitor Pin. The current out of this pin is 20µA plus a current proportional to the negative average VOUT current. See the Applications Information section for more information. LDO33 (Pin 40/Pin 62): 3.3V Regulator Output. Bypass this pin to ground with a minimum 0.1µF ceramic capacitor. It is recommended to use the same value bypass cap as the master LT8708. GND (Pin 15/Pin 19, Exposed Pad Pin 41/Pin 65): Ground. Tie directly to local ground plane. Rev A 12 For more information www.analog.com LT8708-1 BLOCK DIAGRAM TO LT8708’s VIN RSENSE1 RSENSE TO LT8708’s SWEN CSN CSNIN – CSPIN + SWEN CSP + VINCHIP TG1 A5 M1 GATEVCC – IMON_INN CB1 SW1 – A4 DB1 BOOST1 + + A3 – CONTROL AND STATE LOGIC RVS D1 (OPT) D2 (OPT) M2 BG1 GND IMON_INP BOOST CAPACITOR CHARGE CONTROL BG2 RT LDO33 TO LT8708’s CLKOUT OSC TG2 M4 CB2 SYNC BOOST2 + RVSOFF A2 DIR – RVS VINHIMON – LDO33 M3 SW2 CLKOUT DB2 TO LT8708’s RRVSOFF D3 (OPT) D4 (OPT) TO LT8708’s VIN RHIMON1 RHIMON3 1.207V RHIMON2 A7 + 3.3V + MODE VOUTLOMON 1.207V RLOMON3 IMON_OP A6 – SS UV_INTVCC A1 OT CSPOUT + – + CSNOUT – – + TO LT8708’s ICN EA8 ICP TO LT8708’s ICP – SHDN + 1.221V – UV_LDO33 UV_VIN + UV_GATEVCC EA5 RSHDN2 – TO LT8708’s VIN – EN VIN EN 6.3V LDO REG LDO REG FBIN + 3.3V LDO REG – + INTERNAL SUPPLY1 LDO33 1.207V EA4 VC RFBIN2 1.205V INTERNAL SUPPLY2 INTVCC RFBIN1 EA3 – 1.21V + EXTVCC 6.3V LDO REG RLOMON2 IMON_INP + 6.4V VOUT RLOMON1 IMON_ON 1.209V – RSHDN1 ICN + EA6 START-UP LOGIC RSENSE2 IMON_INN EA1 FBOUT RFBOUT1 RFBOUT2 87081 F01 Figure 1. Block Diagram Rev A For more information www.analog.com 13 LT8708-1 OPERATION The LT8708-1 is a high performance 4-switch buck-boost slave controller that is paralleled with the master LT8708 to increase power capability. Using LT8708-1(s) with the LT8708, an application can command power to be delivered from VIN to VOUT or from VOUT to VIN as needed. Table 1. LT8708 Data Sheet Sections that Apply to the LT8708-1 LT8708 DATA SHEET SECTION ADDITIONAL INFORMATION IN THIS DATA SHEET Operation Start-Up: SHDN Pin Power Switch Control COMMON LT8708-1 AND LT8708 FEATURES The LT8708-1 and LT8708 share many common functions and features that are already documented in the LT8708 data sheet. Table 1 lists the LT8708 data sheet sections that also apply to the LT8708-1. For some of these features, additional LT8708-1 specific information is provided in this data sheet, as indicated in Table 1. The focus of this data sheet is on how to use the LT8708-1 to increase the number of switching phases in an LT8708‑based application. As such, functionality that is identical in both the LT8708 and LT8708-1 will not necessarily be repeated here. It is assumed that readers of this data sheet are already familiar with the LT8708. ADDING PHASES TO AN LT8708 APPLICATION In a multiphase LT8708 application, a single LT8708 is the master of the system. One or more LT8708-1s are slaves that provide additional current as needed. As the master of the multiphase system, the LT8708 and its respective error amplifiers, determine the current necessary to regulate the VIN voltage, VOUT voltage, VIN current and VOUT current. The slave LT8708-1 operates by sensing the IOUT(MASTER) (see Figure 2) and delivering a proportional amount of IOUT(SLAVE). Again, since IOUT(SLAVE) is proportional to IOUT(MASTER), the master LT8708 is in control of setting regulation voltages and current limits to the system. Each LT8708 and LT8708-1, connected in parallel, is hereon referred to as a phase, the master and slave VIN current is referred to as IIN(MASTER) and IIN(SLAVE), respectively. For multiphase operation, the LT8708 should be configured according to the LT8708 data sheet. Configuration of LT8708-1s should follow instructions in this data sheet. Figure 2 shows a simplified drawing of a multiphase system with one LT8708 and multiple Unidirectional and Bidirectional Conduction Yes INTVCC/EXTVCC/GATEVCC/LDO33 Power CLKOUT and Temperature Sensing Applications Information Internal Oscillator SYNC Pin and Clock Synchronization CLKOUT Pin and Clock Synchronization Inductor Current Sensing and Slope Compensation RSENSE Selection and Maximum Current RSENSE Filtering Inductor (L) Selection Power MOSFET Selection Schottky Diode (D1, D2, D3, D4) Selection Topside MOSFET Driver Supply (CB1, DB1, CB2, DB2) VINHIMON, VOUTLOMON and RVSOFF Yes INTVCC Regulators and EXTVCC Connection LDO33 Regulator Voltage Lockouts Yes Junction Temperature Measurement Thermal Shutdown Efficiency Considerations Circuit Board Layout Checklist Yes LT8708-1s. It illustrates the basic connections needed to add LT8708-1s to a multiphase system. Adding Phases: The Master LT8708 The master controls the overall current delivered by the multiphase system. For example, the LT8708 controls the VIN and VOUT regulation voltages through its FBIN and FBOUT pins. Since the slaves primarily duplicate the master’s IOUT(MASTER) current, the slave’s FBIN and FBOUT pins and related circuitry are typically not used. See the Error Amplifiers section on how they can affect VC and how to disable them. Rev A 14 For more information www.analog.com LT8708-1 OPERATION IIN(MASTER) VIN IOUT(MASTER) 4-SWITCH BUCK-BOOST RIN ROUT VOUT CSNIN CSPOUT CSPIN CSNOUT FBOUT VINCHIP LT8708 MASTER FBIN LD033 IMON_ON LD033 IMON_INP DIR IMON_INN SWEN RVSOFF SYNC LD033 FWD (>1.6V)/ RVS ( 165°C data sheet for more details. SWEN is internally pulled down by the LT8708 and/or LT8708-1(s) when the respective switching regulator is unable or not ready to operate (see CHIP OFF and SWITCHER OFF 1 states in Figure 3). In a multiphase system, the SWEN pins are connected between all phases. Due to the internal SWEN pull-down on the LT8708 and LT8708-1, the external pull-up for the common SWEN node should always have a current limiting resistor. Typically, the common SWEN node is pulled up, through a resistor, to the LT8708’s LDO33 pin. In other cases, the common SWEN node can be digitally driven through a current limiting resistor. TJUNCTION < 160°C AND SHDN > 1.221V AND VINCHIP > 2.5V AND ((INTVCC AND GATEVCC < 4.65V) OR LDO33 < 3.04V) CHIP OFF SWITCHER OFF 1 • SWITCHER OFF • LDOs OFF • SWEN PULLED LOW • SWITCHER DISABLED • INTVCC AND LDO33 OUTPUTS ENABLED • SWEN AND SS PULLED LOW (INTVCC AND GATEVCC > 4.81V) AND LDO33 > 3.075V AND SWEN < 0.8V SWITCHER OFF 2 • SWITCHER DISABLED • INTVCC AND LDO33 OUTPUTS ENABLED • SS PULLED LOW (INTVCC AND GATEVCC > 4.81V) AND LDO33 > 3.075V AND SWEN > 1.208V INITIALIZE • SS PULLED LOW • VC FORCED TO COMMAND NEAR ZERO CURRENT LIMIT SS < 50mV SOFT-START 1 ICP AND ICN < 510mV • SS CHARGES UP ICP OR ICN > 510mV SOFT-START 2 • SS CHARGES UP SS > 0.8V SOFT-START 3 • SS CHARGES UP • SWITCHER ENABLED • M1, M4 ON-TIME SOFT-START • VC IS FREE TO SLEW SS > 1.8V NORMAL MODE • NORMAL OPERATION 87081 F02 Figure 3. Start-Up Sequence (All Values are Typical) Rev A For more information www.analog.com 17 LT8708-1 OPERATION SWEN is used to synchronize the start-up between all phases of the system. If one or more of the phases is unable to operate, SWEN is pulled low by those chips, thus preventing the entire system from starting. After all phases are ready to operate and SWEN has been pulled down below 0.8V (typical) SWEN rises, due to the pullup resistor, and start-up proceeds, for all phases, to the SWITCHER OFF 2 state. When the common SWEN node rises above 1.208V (typical), all the phases proceed to the INITIALIZE state at the same time. Start-Up: Soft-Start of Switching Regulator The soft-start sequence, described in this section, happens independently and in parallel for each phase since each phase has its own SS pin, external capacitor and related circuitry. The remaining discussion concerns the LT8708-1 soft-start behavior. The LT8708 soft-start differs slightly. In the INITIALIZE state, the SS pin is pulled low to prepare for soft-starting the switching regulator. Also, VC is forced to command near zero current, and IMON_OP is forced to ~1.209V (typical) to improve the transient behavior when the LT8708-1 subsequently starts switching. After SS has been discharged to less than 50mV, the SOFT-START 1 state begins. In this state, an integrated 180k (typical) resistor from 3.3V pulls SS up. The rising ramp rate of the SS pin voltage is set by this 180k resistor and the external capacitor connected to this pin. After SS reaches 0.2V (typical), the LT8708-1’s integrated pull-up resistor is reduced from 180k to 90k to increase the rising ramp rate of the SS pin voltage. This ensures that the slave chip enters the normal mode in Figure 3 before the master chip, preventing saturation of the regulation loop during start-up. Switching remains disabled until either (1) ICP or ICN voltage becomes higher than 510mV (typical) (SOFTSTART 3) or (2) SS reaches 0.8V (typical) (SOFT-START 2). As soon as switching is enabled, VC is free to slew under the control of the internal error amplifiers (EA1–EA6). This allows the average IOUT(SLAVE) to quickly follow the average IOUT(MASTER) without saturating the slave’s regulation loop. During soft-start the LT8708-1 employs the same switch control mechanism as the LT8708. See the Switch Control: Soft-Start section of the LT8708 data sheet for more information. When SS reaches 1.8V (typical), the LT8708-1 exits soft-start and enters normal mode. Typical values for the external soft-start capacitor range from 220nF to 2µF. It is recommended to use the same brand and value SS capacitor for all the synchronized LT8708/ LT8708-1(s). Using a slave SS capacitor value significantly higher than the master SS capacitor value can result in undesirable start-up behavior. CONTROL OVERVIEW The LT8708-1 is a slave current mode controller that regulates the average IOUT(SLAVE) based on the master’s ICP and ICN voltages, or equivalently, the average IOUT(MASTER). The main regulation loop involves EA6 (see Figure 1). In a simple example of IOUT(SLAVE) regulation, the CSPOUT–CSNOUT pins receive the IOUT(SLAVE) feedback signal which is summed with the ICP and ICN signals from the LT8708 to generate the IMON_OP voltage using A1 (see Figure 1). The IMON_OP voltage is compared to the internal reference voltage using EA6. Low IMON_OP voltages raise VC, which causes IOUT(SLAVE) to become more positive (or less negative) and increases the current out of the IMON_OP pin. Conversely, higher IMON_OP voltages reduce VC, which causes IOUT(SLAVE) to become less positive (or more negative) and reduces the current flowing out of the IMON_OP pin. The VC voltage typically has a Min to Max range of about 1.2V. The maximum VC voltage commands the most positive inductor current, and thus, commands the most power flow from VIN to VOUT. The minimum VC voltage commands the most negative inductor current, and thus, commands the most power flow from VOUT to VIN. VC is the combined output of five internal error amplifiers EA1–EA6 as shown in Table 3. In a common application, IOUT(SLAVE) would be regulated using the main regulation error amplifier EA6, while error amplifiers EA1 and EA5 are monitoring for excessive input current and EA3 and EA4 are disabled. Rev A 18 For more information www.analog.com LT8708-1 OPERATION Table 3. Error Amplifiers (EA1–EA6) AMPLIFIER NAME PIN NAME USED TO LIMIT OR REGULATE EA1 IMON_INN Negative IIN(SLAVE) EA3 FBIN VIN Voltage pins together. In addition, the RVSOFF pins of all phases should be connected together. Note that the current and power flow can also be restricted to one direction, as needed, by the selected conduction mode discussed in the Unidirectional and Bidirectional Conduction section. Note that when operating in the forward hybrid conduction mode (FHCM), the LT8708-1 operation differs slightly from the LT8708. Instead of measuring the ICN pin voltage for light load detection, the LT8708-1 measures the IMON_ON pin. Light load is detected when IMON_ON is above 245mV (typical). Therefore, FHCM operation requires a 17.4k resistor, and a parallel filter capacitor, from ground to the IMON_ ON pin of the LT8708-1. Reverse hybrid conduction mode (RHCM) operates identically in the LT8708 and LT8708-1. See the Unidirectional and Bidirectional Conduction: HCM section of the LT8708 data sheet for details. POWER SWITCH CONTROL ERROR AMPLIFIERS EA4 FBOUT VOUT Voltage EA5 IMON_INP Positive IIN(SLAVE) EA6 IMON_OP IOUT(SLAVE) The LT8708-1 employs the same power switch control as the LT8708 (see Power Switch Control section of the LT8708 data sheet). Figure 4 shows a simplified diagram of how the four power switches are connected to the inductor, VIN, VOUT and ground. VOUT VIN TG1 M1 SW1 BG1 L M4 TG2 SW2 M2 M3 Five internal error amplifiers combine to drive VC according to Table 4, with the highest priority being at the top. Table 4. Error Amp Priorities TYPICAL CONDITION if IMON_INN > 1.21V else if FBIN < 1.205V or FBOUT > 1.207V or BG2 PURPOSE then VC Rises then VC Falls IMON_INP > 1.209V or Figure 4. Simplified Diagram of the Buck-Boost Switches UNIDIRECTIONAL AND BIDIRECTIONAL CONDUCTION As with the LT8708, the LT8708-1 has one bidirectional and three unidirectional current conduction modes (CCM, HCM, DCM and Burst Mode operation, respectively). The LT8708-1’s MODE, DIR and RVSOFF pins operate in the same way as in the LT8708 to select the desired conduction modes. (See the Unidirectional and Bidirectional Conduction section of the LT8708 data sheet for details). In general, it is highly recommended to keep all phases of an LT8708 system in the same conduction mode. This is done by setting all MODE and DIR pins to the same states, or shorting all MODE pins together and all DIR to Reduce Positive IOUT(SLAVE) or Increase Negative IIN(SLAVE) to Reduce Positive IOUT(SLAVE) VC Rises else 87081 F03 to Reduce Positive IIN(SLAVE) or Increase Negative IIN(SLAVE) to Reduce Positive IIN(SLAVE) IMON_OP > 1.209V RSENSE to Reduce Negative IIN(SLAVE) Default Note that certain error amplifiers are disabled under the conditions shown in Table 5. A disabled error amplifier is unable to affect VC and can be treated as if its associated row is removed from Table 4. Table 5. Automatically Disabled Error Amp Conditions ERROR AMP PIN NAME EA1 IMON_INN EA3 FBIN EA4 FBOUT EA5 IMON_INP EA6 IMON_OP VOUTLOMON ASSERTED VINHIMON ASSERTED RDCM or RHCM 2* 1* 3* Rev A For more information www.analog.com 19 LT8708-1 OPERATION 1* This improves transient response when VOUTLOMON de-asserts. 2* This improves transient response when VINHIMON de-asserts. 80 60 V(CSPOUT–CSNOUT)S (mV) A 1* to 3* indicates that the error amplifier listed for that row is disabled under that column’s condition. The purposes of disabling the respective amplifiers are: AMPLIFIER NAME PIN NAME TIE TO DISABLE EXAMPLE DISABLED PIN CONNECTION EA1 IMON_INN < 0.9V GND EA3 FBIN > 1.5V LDO33 EA4 FBOUT EA5 IMON_INP < 0.9V GND TRANSFER FUNCTION: IOUT(SLAVE) VS IOUT(MASTER) The LT8708-1 regulates IOUT(SLAVE) proportionally to IOUT(MASTER) following the transfer functions1 shown in Figure 5 and Figure 6. The currents are measured (sensed) by the differential CSPOUT–CSNOUT pin voltages for each phase and the information is sent from the master to the slaves via the ICP and ICN pins. The transfer functions are represented by the slave’s current sense voltage (V(CSPOUT–CSNOUT)S) vs the master’s current sense voltage (V(CSPOUT–CSNOUT)M). To convert the axes of Figure 5 and Figure 6 to IOUT(SLAVE) vs IOUT(MASTER), simply divide 0 –20 –40 –80 –80 –60 –40 –20 0 20 40 V(CSPOUT–CSNOUT)M (mV) The primary regulation loop for the LT8708-1 involves EA6, which regulates the average IOUT(SLAVE) based on the ICP and ICN input voltages. Therefore, the IMON_OP pin must always have a proper compensation network connected. See the Loop Compensation section for more information. 60 80 87081 F05 Figure 5. Typical V(CSPOUT–CSNOUT)S vs V(CSPOUT–CSNOUT)M in CCM1 70 60 V(CSPOUT–CSNOUT)S (mV) Table 6. Disabling Unused Amplifiers 20 –60 3* Since power can only transfer from VOUT to VIN, this prevents higher FBOUT/VOUT voltages from interfering with the FBIN/VIN voltage regulation. The remaining error amplifiers can be disabled or used to limit their respective voltages or currents. When unused, the respective input pin(s) should be driven so that they do not interfere with the operation of the remaining amplifiers. Use Table 6 as a guide. 40 50 40 30 20 10 0 0 10 20 30 40 50 60 70 V(CSPOUT–CSNOUT)M (mV) 80 87081 F06 Figure 6. Typical V(CSPOUT–CSNOUT)S vs V(CSPOUT–CSNOUT)M in FDCM, FHCM and Burst Mode Operation1 V(CSPOUT–CSNOUT)S and V(CSPOUT–CSNOUT)M by the slave’s and master’s RSENSE2 values, respectively. Figure  5 shows that increasing the master’s average current sense voltage V(CSPOUT–CSNOUT)M above ±60mV results in no additional current from the slave LT8708‑1. As such, the average of V(CSPOUT–CSNOUT)M should be limited to ±50mV by connecting appropriate resistors from the IMON_OP and IMON_ON pins of the LT8708 to ground (see the IIN and IOUT Current Monitoring and Limiting section of the LT8708 data sheet). 1. The ICP and ICN pins must be connected between the master and slave chips. 17.4k resistors and appropriate parallel capacitors are also required from those pins to ground. Rev A 20 For more information www.analog.com LT8708-1 OPERATION Transfer Function: CCM Figure 5 shows the transfer function of the slave’s regulated current sense voltage (V(CSPOUT–CSNOUT)S) vs the master’s current sense voltage (V(CSPOUT–CSNOUT)M) when the MODE pin is selecting CCM operation. At light current levels (|V(CSPOUT–CSNOUT)M|  20mV), IOUT(SLAVE) is regulated to be the same as IOUT(MASTER), offering good current sharing and thermal balance between the phases. Note: If the LT8708-1 is configured to be in CCM while RVSOFF is being pulled low, use the FDCM transfer function in the next section. Transfer Function: DCM, HCM and Burst Mode Operation Figure 6 shows the transfer function of the slave’s regulated current sense voltage (V(CSPOUT–CSNOUT)S) vs the master’s current sense voltage (V(CSPOUT–CSNOUT)M) when the MODE pin is selecting FDCM, FHCM or Burst Mode operation. The transfer function, in the non-CCM modes, is shown in Figure 6 and has three distinct regions: 1. V(CSPOUT–CSNOUT)M < 10mV: In this region, where the master’s current is relatively small, the slave phases deliver zero current. 2. 10mV < V(CSPOUT–CSNOUT)M < 20.5mV: In this region, where the master’s current is moderate, the slave phases deliver less current than the master. The transfer function is hysteretic in this region. Therefore, the slave current will operate from 0mV to 13.5mV or from 6.7mV to 20.5mV if the master’s V(CSPOUT– CSNOUT)M was most recently below 10mV or above 20.5mV, respectively. 3. V(CSPOUT–CSNOUT)M > 20.5mV: In this region of moderate to high current from the master, the slave delivers the same current as the master. The transfer function is a mirror image of Figure 6 when operating in the RDCM and RHCM conduction modes for V(CSPOUT–CSNOUT)M < 0mV. Simply multiply the values on the X and Y axes of Figure 6 by –1 to illustrate the transfer function. CURRENT MONITORING AND LIMITING Monitoring: IOUT(SLAVE) The LT8708-1 can monitor VOUT current (IOUT(SLAVE)) in the negative direction. An external resistor is connected from the IMON_ON pin to ground, and the resulting voltage is linearly proportional to negative IOUT(SLAVE). Unlike the LT8708’s IMON_ON pin, the LT8708-1’s IMON_ON pin does not regulate or limit IOUT(SLAVE) in the negative direction. See the IIN and IOUT Current Monitoring and Limiting section of the LT8708 data sheet for how to configure the IMON_ON current monitoring. Monitoring and Limiting: IIN(SLAVE) The LT8708-1 can monitor VIN current (IIN(SLAVE)) in both the positive and negative directions by measuring the voltage across a current sense resistor RSENSE1 using the CSPIN and CSNIN pins. The voltage is amplified and a proportional current is forced out of the IMON_INP and IMON_INN pins to allow for monitoring and limiting. This function is identical to the LT8708 and more information can be found in the Current Monitoring and Limiting section of the LT8708 data sheet. As described above, the LT8708-1 has circuitry allowing for independent input current limiting of each phase. This per-phase current limiting is intended to be secondary to the limits imposed by the master. Typically, the master is configured to limit its own input current (IIN(MASTER)) thus limiting the command current to the slave. However, since the slave has its own independent input current sensing Rev A For more information www.analog.com 21 LT8708-1 OPERATION and limiting circuitry, it can be configured with redundant current limiting. It is recommended to set the slave input current limit magnitudes to be the same or higher than those set by the master. See the Applications Information section for more information about the IIN(SLAVE) current monitoring and limiting. As with the LT8708, the LT8708-1 requires a 17.4k resistor and parallel filter capacitor to be connected from ground to the IMON_INP pin when using the RHCM conduction mode. If, in this case, it is also desired to set the LT8708-1’s positive IIN(SLAVE) current limit higher than the LT8708’s positive IIN(MASTER) limit, reduce the value of the LT8708-1’s RSENSE1 resistor as compared to the LT8708’s RSENSE1 value. See Configuring the IIN(SLAVE) Current Limits section for details. MULTIPHASE CLOCKING A multiphase application usually has switching regulators operating at the same frequency but at different phases to reduce voltage and current ripple. The SYNC pin can be used to synchronize the LT8708-1’s switching frequency at a specific phase relative to the master LT8708 chip. A separate clock chip, e.g., LTC6902, LTC6909 etc., can be used to generate the clock signals and drive the SYNC pins of the LT8708 and LT8708-1(s). If only two phases are needed for the multiphase application, i.e., 0° and 180°, the LT8708-1’s SYNC pin can be connected to the LT8708’s CLKOUT pin to obtain the 180° phase shift. The master LT8708 can be synchronized to an external source or can be free-running based on the external RT resistor. It is recommended that the LT8708-1 is always synchronized to the same frequency as the LT8708 through the SYNC pin. Rev A 22 For more information www.analog.com LT8708-1 APPLICATIONS INFORMATION This Applications Information section provides additional details for setting up a multiphase application using the LT8708-1(s) and LT8708. Topics include quick multiphase setup guidelines, choosing the total number of phases, clock synchronization, and selection of various external components. In addition, more information is provided about voltage lockouts, current monitoring, PCB layout considerations. This section wraps up with a design example. QUICK-START MULTIPHASE SETUP This section provides a step-by-step summary on how to setup a multiphase system using the LT8708-1(s) and LT8708. Quick Setup: Design the Master Phase Design the LT8708 application circuit according to the LT8708 data sheet. Make sure the maximum CSPOUT– CSNOUT current sense voltage is limited to ±50mV by setting the IMON_OP and IMON_ON resistor values equal to or higher than 17.4k. This is the master phase. Quick Setup: Design the Slave Phase(s) Step 1 – Power Stage: Apply the same power stage design from the LT8708 application circuit to the LT8708-1 circuit. This includes the inductor, power MOSFETs and their gate resistors, RSENSE, RSENSE filtering, RSENSE1, RSENSE2, CSPIN–CSNIN filtering, CSPOUT–CSNOUT filtering, topside MOSFET driver supply (CB1, DB1, CB2, DB2) and Schottky diodes D1, D2, D3, D4 (if used). See the CIN and COUT Selection section on how to optimize the capacitor values. Step 2 – Peripheral Pins: The following components should be identical on the LT8708 as the LT8708-1: • RT resistor • SS pin capacitor • INTVCC, GATEVCC, VINCHIP and LDO33 pin bypass capacitors Connect identical resistor divider networks on SHDN as well as on VINHIMON and VOUTLOMON (if used). If not used, connect VINHIMON to GND and/or VOUTLOMON to the LT8708-1’s LDO33. Connect the LT8708-1’s FBOUT pin to GND and the FBIN pin to the LT8708-1’s LDO33 node. Step 3 – Interconnect: Connect the LT8708-1’s ICP, ICN, EXTVCC, SWEN and RVSOFF pins to their counterparts on the LT8708. Connect the same control signals, or connect the same value resistor dividers or voltages to the MODE pins and the DIR pins of the LT8708 and LT8708‑1, respectively. Connect the LT8708’s CLKOUT signal or a clock chip’s phase shifted clock to the LT8708‑1’s SYNC pin. Step 4 – Regulation and Limiting: Connect a 17.4k resistor in parallel with a compensation network from IMON_OP to GND. Connect a resistor in parallel with a filter capacitor from IMON_ON to GND for current monitoring. Connect resistors in parallel with filter capacitors from IMON_INP and IMON_INN to GND, respectively, to set the magnitudes of the IIN(SLAVE) current limits to be equal to or higher than their counterparts on the LT8708. Step 5: Repeat steps 1 through 4 to add any additional LT8708-1 phases. Quick Setup: Evaluation Test and optimize the stability of the multiphase system. See the Loop Compensation section for more details. CHOOSING THE TOTAL NUMBER OF PHASES In general, the number of phases needed is selected to meet a multiphase system’s total power requirement as well as each phase’s thermal requirement. In general, for a given application, the more phases that the system has, the less power that each phase needs to deliver, and the better the thermal performance that each phase has. In many cases, the total number of phases is selected to optimize the total input or output RMS current ripple. See the CIN and COUT Selection section for more details. Rev A For more information www.analog.com 23 LT8708-1 APPLICATIONS INFORMATION OPERATING FREQUENCY SELECTION 0.60 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.55 0.50 0.45 0.40 I(IN,RMS)/IOUT The LT8708-1 uses a constant frequency architecture operating between 100kHz and 400kHz. The LT8708-1 should be synchronized to the same frequency as the LT8708 by connecting a clock signal to the SYNC pin. An appropriate resistor must be placed from the RT pin to ground. In general, use the same value RT resistor for all the synchronized LT8708 and LT8708-1(s). See the Operating Frequency Selection section of the LT8708 data sheet on how to select the LT8708’s switching frequency. 0.35 0.30 0.25 0.20 0.15 CIN AND COUT SELECTION VIN and VOUT capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out of the regulator. A parallel combination of capacitors is typically used to achieve high capacitance and low ESR (equivalent series resistance). Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Capacitors with low ESR and high ripple current ratings, such as OS-CON and POSCAP are also available. Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. A ceramic capacitor, of at least 1µF at the maximum VINCHIP operating voltage, should also be placed from VINCHIP to GND as close to the LT8708-1 pins as possible. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss in the higher ESR bulk capacitors. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 VOUT/VIN 87081 F06 Figure 7. Normalized Total Input RMS Ripple Current vs VOUT/VIN for One to Six Phases in Buck Operation The total input RMS ripple current I(IN,RMS) is normalized against the total output current of the multiphase system (IOUT). The graph can be used in place of tedious calculations. From the graph, the minimum total input RMS ripple current can be achieved when the product of the number of phases (N) and the output voltage VOUT is approximately equal to integer multiples of the input voltage VIN or: VOUT/VIN = n/N where n = 1, 2,…, N-1 Therefore, the number of phases can be chosen to minimize the input capacitance for given input and output voltages. CIN and COUT Selection: VIN Capacitance Figure 7 also shows the maximum total normalized input RMS current for one to six phases. Choose an adequate CIN capacitor network to handle this RMS current. Discontinuous VIN current is highest in the buck region due to the M1 switch toggling on and off. Ensure that the CIN capacitor network has low enough ESR and is sized to handle the maximum RMS current. Figure 7 shows the total input capacitor RMS ripple current for one to six phases with the VOUT to VIN ratios in buck operation. CIN is also necessary to reduce the VIN voltage ripple caused by discontinuities and ripple of IIN. The effects of ESR and the bulk capacitance must be considered when choosing the correct capacitor for a given VIN ripple. A low ESR input capacitor sized for the maximum RMS current must be used. Add enough ceramic capacitance to Rev A 24 For more information www.analog.com LT8708-1 TYPICAL APPLICATIONS make sure VIN voltage ripple is adequately low for the application. 3.5 1–PHASE 2–PHASE 3.0 CIN and COUT Selection: VOUT Capacitance 3–PHASE 4–PHASE (VOUT – VIN)/VOUT = n/N 6–PHASE 2.5 I (OUT,RMS)/I OUT Discontinuous VOUT current is highest in the boost region due to the M4 switch toggling on and off. Make sure that the COUT capacitor network has low enough ESR and is sized to handle the maximum RMS current. Figure 8 shows the output capacitor RMS ripple current for one to six phases with the (VOUT – VIN) to VOUT ratios in boost operations. The total output RMS ripple current I(OUT,RMS) is normalized against the total output current of the multiphase system (IOUT). The graph can be used in place of tedious calculations. From the graph, the minimum total output RMS ripple current can be achieved when the product of the number of phases (N) and duty cycle (VOUT – VIN)/VOUT is approximately equal to integers or: 2.0 1.5 1.0 0.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 (VOUT – VIN)/VOUT 87081 F08 Figure 8. Normalized Output RMS Ripple Current vs (VOUT–VIN)/VIN for One to Six Phases in Boost Operation where n = 1,2,…, N-1 Therefore, the number of phases be chosen to minimize the output capacitance for given input and output voltages. Figure 8 also shows the maximum total normalized output RMS current for one to six phases. Choose an adequate COUT capacitor network to handle this RMS current. COUT is also necessary to reduce the VOUT ripple caused by discontinuities and ripple of IOUT. The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given VOUT ripple. A low ESR input capacitor sized for the maximum RMS current must be used. Add enough ceramic capacitance to make sure VOUT voltage ripple is adequate for the application. Figure 7 and Figure 8 show that the peak total RMS input current in buck operation and the peak total RMS output current in boost operation are reduced linearly, inversely proportional to the number of phases used. It is important to note that the ESR-related power loss is proportional to the RMS current squared, and therefore a 3-phase implementation results in 90% less power loss when compared to a single-phase design. Battery/input protection fuse resistance (if used) PCB trace and connector resistance losses are also reduced by the reduction of the ripple current in a multiphase system. The required amount of input and output capacitance is further reduced by the factor, N, due to the effective increase in the frequency of the current pulses. VINHIMON, VOUTLOMON AND RVSOFF VINHIMON and VOUTLOMON offer the identical functions on the LT8708 and LT8708-1(s). See the VINHIMON, VOUTLOMON and RVSOFF section of the LT8708 data sheet for more details. If the VINHIMON and VOUTLOMON functions are used on the LT8708-1(s) as redundant monitoring functions, in general use the same value resistor dividers as on the LT8708. If the VINHIMON and/or VOUTLOMON functions are not used on the LT8708-1(s), tie VINHIMON to GND and/or VOUTLOMON to the respective LT8708-1’s LDO33 pin. The RVSOFF pin has an internal comparator with a rising threshold of 1.374V (typical) and a falling threshold of 1.209V (typical). A low state on this pin inhibits reverse current and power flow. It is recommended to tie the RVSOFF pins of all the synchronized LT8708 and LT8708-1(s) together. In a multiphase system, if one or Rev A For more information www.analog.com 25 LT8708-1 APPLICATIONS INFORMATION more chips’ VINHIMON or VOUTLOMON comparator is triggered, the RVSOFF pin is pulled low to prevent the entire multiphase system from delivering reverse current and power. The multiphase system will exit the RVSOFF operation when all the VINHIMON and VOUTLOMON comparators are de-asserted. CONFIGURING THE IIN(SLAVE) CURRENT LIMITS As discussed in the Monitoring and Limiting: IIN(SLAVE) section, the LT8708-1 can monitor and limit the input current independently of the master. The current limiting discussed in this section is intended to be secondary, or redundant, since the master is primarily in control of the amount of current commanded from the slave. As shown in Figure 9, the LT8708-1 measures IIN(SLAVE) with the CSPIN and CSNIN pins and can independently monitor and limit the current in both positive and negative directions. The operation of the input current monitor circuits is identical to the LT8708. More information about configuring these circuits can be found in the IIN and IOUT Current Monitoring and Limiting section of the LT8708 data sheet. When setting the IIN(SLAVE) current limits, it is recommended to set them equal to or higher than the magnitudes of the IIN(MASTER) limits. Consider that if the slave RSENSE1 FROM SYSTEM VIN TO CONTROLLER VIN IIN(SLAVE) CSPIN LT8708-1 reaches input current limiting before the master, the slave can no longer deliver additional current as requested by the master. With equal IIN(SLAVE) and IIN(MASTER) limits, slight output current mismatch, and hence slight thermal imbalance can still happen due to device tolerance. Bench evaluation should be carried out to ensure the selected IIN(SLAVE) limits meet the application’s thermal and stability requirements. REGULATING IOUT(SLAVE) IOUT(SLAVE): Circuit Description This section describes the control circuitry in the LT8708-1 that regulates the output current IOUT(SLAVE). The master LT8708 sends the ICP and ICN control signals to the slave LT8708-1 to set IOUT(SLAVE). See the Transfer Function: IOUT(SLAVE) vs IOUT(MASTER) section for related information. Figure 10 shows the primary LT8708-1 circuits involved in the regulation of IOUT(SLAVE). Additional circuitry is shown in Figure 1. IOUT(SLAVE) is regulated by a feedback loop with ICP and ICN setting the desired current. The feedback loop involves the following sections: • The VC pin controls the inductor current, thus indirectly controlling IOUT(SLAVE). Higher VC voltage FROM CONTROLLER VOUT RSENSE2 TO SYSTEM VOUT IOUT(SLAVE) ICP ICN FROM FROM MASTER MASTER CSNIN + Ω– gm = 1m A3 + – 1.21V 20μA LT8708-1 + EA1 – 20μA 1.209V TO INDUCTOR CURRENT CONTROL CSPOUT CSNOUT A1 1.209V + EA6 IMON_OP RIMON_INP VC 87081 F09 VC IMON_INP 70μA 87081 F08 CIMON_INN + – – RIMON_INN ICN TO INDUCTOR CURRENT CONTROL + – +– EA5 IMON_INN ICP CIMON_INP RIMON_OP 17.4k Figure 9. IIN(SLAVE) Current Monitor and Limit CIMON_OP Figure 10. IOUT(SLAVE) Current Regulation and Monitor Rev A 26 For more information www.analog.com LT8708-1 TYPICAL APPLICATIONS results in higher IOUT(SLAVE) current and vice versa. VC is driven by error amplifier EA6 during IOUT(SLAVE) regulation. • During regulation, the IMON_OP voltage is very close to the EA6 reference of 1.209V. Small changes in IMON_OP voltage make large adjustments to VC, and thus the IOUT(SLAVE) current. • Resistor RSENSE2 converts the IOUT(SLAVE) current into a voltage that can be measured by amplifier A1. This voltage is denoted as V(CSPOUT–CSNOUT)S in Figure 10. • Transconductance amplifier A1 makes sure that IOUT(SLAVE) is equal to the current set by the ICP and ICN signals. If IOUT(SLAVE) becomes higher than requested by ICP and ICN, additional current is delivered out of A1. This raises IMON_OP which reduces VC and reduces IOUT(SLAVE). Conversely, if IOUT(SLAVE) becomes lower than requested by ICP and ICN, the current out of A1 is reduced. This lowers IMON_OP which raises VC and increases IOUT(SLAVE). Figure 11 illustrates, in CCM mode, the typical relationship between the master’s output current IOUT(MASTER), the resulting ICP and ICN control voltages, and the further resulting IOUT(SLAVE) current. Figure 11 can best be explained with a few examples. In these examples, the output current sense resistors are RSENSE2 = 10mΩ for the master and the slave devices. First, assume the master’s output current IOUT(MASTER) is 4A. This results in the master LT8708 measuring a IOUT(SLAVE) = 10mΩ IOUT(SLAVE) = 10mΩ 60 1.6 80 60 1.0 50 0.8 40 0.6 30 0.4 20 –60 0.2 10 –80 0 20 0.0 0 –0.4 –20 –0.8 –40 ICP, ICN VOLTAGE (V) 70 1.2 0.4 80 90 1.4 40 60 100 V(CSPOUT–CSNOUT)S ICN ICP 87081 F11 Figure 11. IOUT(SLAVE) Control Voltage Relationships (CCM) 0 10 20 30 40 50 60 V(CSPOUT–CSNOUT)M (mV) 70 80 V(CSPOUT–CSNOUT)S (mV) 1.2 V(CSPOUT–CSNOUT)S (mV) 80 –1.6 –80 –60 –40 –20 0 20 40 V(CSPOUT–CSNOUT)M (mV) = – 2A Figure 12 illustrates the relationship between IOUT(MASTER), ICP, ICN and IOUT(SLAVE) in FDCM, FHCM and Burst Mode operation. Use Figure 12, instead of Figure 11, to understand the control voltage relationships when operating in FDCM, FHCM or Burst Mode Operation. Figure 12 can 1.6 V(CSPOUT–CSNOUT)S ICN ICP V(CSPOUT – CSNOUT)S = R SENSE2 –20mV (from Figure 10) 1.8 –1.2 = 4A Alternatively, if the master’s output current IOUT(MASTER) is –2A. Then the master LT8708 will measure a current sense voltage of V(CSPOUT–VCSNOUT)M = –2A • 10mΩ = –20mV. Locate –20mV along the X-axis of Figure 11. The corresponding ICP and ICN voltages are 0V and ~0.7V, respectively. These ICP and ICN voltages are sent from the LT8708 to the LT8708-1. As a result, the LT8708-1 regulates IOUT(SLAVE) to: 2.0 0.8 V(CSPOUT – CSNOUT)S = R SENSE2 40mV (from Figure 10) 100 2.0 ICP, ICN VOLTAGE (V) current sense voltage of V(CSPOUT–VCSNOUT)M = 4A • 10mΩ = 40mV. Locate 40mV along the X-axis of Figure 11. The corresponding ICP and ICN voltages are ~1V and 0V, respectively. These ICP and ICN voltages are sent from the LT8708 to the LT8708-1. As a result, the LT8708-1 regulates IOUT(SLAVE) to: 0 87081 F12 Figure 12. IOUT(SLAVE) Control Voltage Relationships (FDCM, FHCM and Burst Mode Operation) Rev A For more information www.analog.com 27 LT8708-1 APPLICATIONS INFORMATION also be used to understand RDCM and RHCM operation by multiplying the V(CSPOUT–CSNOUT)M and the V(CSPOUT– CSNOUT)S axis values by –1. As mentioned previously, 17.4k resistors must be connected from the ICP and ICN pins to ground. Proper resistor connections are required to produce the correct ICP and ICN voltages, and result in the correct IOUT(SLAVE) currents. IOUT(SLAVE): Configuration IOUT(SLAVE) regulation is the main regulation loop for the LT8708-1 and should always be enabled. Therefore, always connect a 17.4k resistor in parallel with a compensation network from the IMON_OP pin to ground. Note that the IMON_OP pin cannot be used for monitoring the IOUT(SLAVE) current. Figure 5 and Figure 11 show that increasing the master’s average current sense voltage V(CSPOUT–CSNOUT)M above ±60mV results in no additional current from the slave LT8708-1. As such, the target average of V(CSPOUT– CSNOUT)M should be limited to ±50mV by connecting appropriate resistors from the IMON_OP and IMON_ON pins of the LT8708 to ground (see the IIN and IOUT Current Monitoring and Limiting section of the LT8708 data sheet). In addition, the instantaneous differential voltage V (CSPOUT–CSNOUT)S should remain between –100mV and 100mV due to the limited current that can be driven out of IMON_OP. If the instantaneous V(CSPOUT–CSNOUT)S exceeds these limits but the average V(CSPOUT–CSNOUT)S is between –50mV and 50mV, consider including the current sense filter described in the IIN and IOUT Current Monitoring and Limiting section of the LT8708 data sheet. The filter can reduce the instantaneous voltage while preserving the average. In general, use the same value current sense filter for all the synchronized LT8708 and LT8708-1(s). Finally, IMON_OP should be compensated and filtered with capacitor CIMON_OP. At least a few nF of capacitance is usually necessary. LOOP COMPENSATION To compensate a multiphase system of the LT8708 and LT8708-1(s), most of the initial compensation component selection can be done by analyzing the individual voltage regulator and/or current regulator(s) independently of each other. Use the total input and output bulk capacitance of the multiphase system in the stability analysis for each of the following steps. 1. Analyze the stability of the LT8708 as a single phase without any additional LT8708-1 phases included. This includes all the regulation loops that will be used by the master LT8708, such as voltage regulation (FBOUT, FBIN) and/or current regulation (IMON_INP, IMON_INN, IMON_OP, IMON_ON). Determine the initial values for the VC pin compensation network, and the relevant IMON_XX pin capacitors for the master LT8708. Further adjustment of these values will be done in Step 4. Adjustment to CIN and COUT may also be necessary as part of this analysis. See the Loop Compensation section of the LT8708 data sheet for more details. LTspice® transient simulation can be helpful for this step. 2. Analyze the stability of the IOUT(SLAVE) current regulation loop of a standalone LT8708-1 phase. Adjust the VC and IMON_OP compensation networks of the LT8708-1 to achieve stability and maximum bandwidth. Bench stability evaluation of a standalone LT8708-1 can be carried out by driving the ICP and ICN pins with external voltage sources. A similar approach to that used for analyzing the LT8708 in constant-current regulation can be employed in compensating the standalone LT8708-1 current regulator. An IMON_OP capacitor of at least a few nF is necessary to maintain IOUT(SLAVE) regulation loop stability. In addition, adding a resistor of a few hundred Ohms in series with this capacitor can often provide additional phase margin. If any of the IIN(SLAVE) regulation loops, i.e. IMON_INP and IMON_INN, is used for secondary or redundant current limiting, carry out the corresponding stability analysis on the standalone LT8708-1. Use the same Rev A 28 For more information www.analog.com LT8708-1 TYPICAL APPLICATIONS approach that is used for compensating the LT8708’s input current regulation loops. 3. Complete the multiphase system with the LT8708 and LT8708-1(s). A few nF of capacitance should be placed on the ICP and ICN pins near the LT8708 for proper compensation. In addition, adding a few hundred Ohms in series with these capacitors can often provide extra phase margin to the multiphase system. See Figure 2 as an example. 4. Perform the loop stability analysis in simulation and/ or on the bench. Primarily, adjust the LT8708’s VC compensation network for stability. A trim pot and selectable capacitor bank can be used on the VC pin to determine the optimal values. Typically, the LT8708 should be adjusted to have lower bandwidth than the LT8708-1 phases. This can be achieved by increasing the capacitance and/or reducing the series resistance of the LT8708’s VC compensation network. If the LT8708 operates in constant current limit, as set by one or more of the IMON_xx pins, adjust the respective LT8708 IMON_xx filter capacitors as well to achieve optimal loop stability. CIRCUIT BOARD LAYOUT CHECKLIST The LT8708’s circuit board layout guidelines also apply to the LT8708-1(s). Refer to the Circuit Board Layout Checklist section of the LT8708 data sheet for details. In addition: • Route the ICP and ICN traces together with minimum PCB trace spacing from the LT8708 to the LT8708‑1(s). Avoid having these traces pass through noisy areas, such as switch nodes. • Star connect the VIN and VOUT power buses as well as the power GND bus to each LT8708/ LT8708-1(s). Minimize the voltage difference between local VIN, VOUT and power GNDs, respectively. DESIGN EXAMPLE In this section, we start with the Design Example in the LT8708 data sheet, and expand it into a 2-phase regulator. The design requirements from the LT8708 data sheet are listed below with the total output current (IOUT) and the total input current (IIN) specifications doubled for two phases. VIN = 8V to 25V VOLTAGE LOCKOUTS The LT8708-1 offers the same voltage detectors as the LT8708 to make sure the chip is under proper operating conditions. See the Voltage Lockouts section of the LT8708 data sheet for more details. Although allowed with a standalone LT8708, a resistor divider connected to the SWEN pins should never be used for undervoltage detection in a multiphase system (see the Start-Up: SWEN Pin section for proper ways to connect or drive the SWEN pin in a multiphase system). Instead, an external comparator chip can be used to monitor undervoltage conditions, and its output drives the common SWEN node in a multiphase system through a current limiting resistor. VIN_FBIN = 12V (VIN regulation voltage set by LT8708 FBIN loop) VOUT_FBOUT = 12V (VOUT regulation voltage set by LT8708 FBOUT loop) IOUT(MAX, FWD) = 10A IIN(MAX, RVS) = 6A f =150kHz This design operates in CCM. Maximum ambient temperature = 60°C Use the same RT, RSENSE, RSENSE2 resistors, inductor, external MOSFETs and capacitors from the Design Example of the LT8708 data sheet for LT8708-1. SYNC Pin: Since this is a 2-phase system, the slave chip operates 180° out of phase from the master chip. Connect the LT8708’s CLKOUT pin to the LT8708-1’s SYNC pin. Rev A For more information www.analog.com 29 LT8708-1 APPLICATIONS INFORMATION MODE Pin: Connect the MODE pin to GND for CCM operation. And the maximum slave VIN current in the reverse direction is: SWEN and RVSOFF Pins: Connect the SWEN and RVSOFF pins together for the LT8708 and LT8708-1, respectively. This synchronizes the start-up and operation mode between the two chips. ICP and ICN Pins: Connect two 17.4k resistors from the ICP and ICN pins to GND, respectively. Place them next to the LT8708 chip and route the ICP and ICN traces to the LT8708-1’s counterparts, respectively. RIMON_OP Selection: Connect 17.4k from IMON_OP to GND for the LT8708-1. RIMON_ON Selection: LT8708-1’s IMON_ON is only used to monitor the IOUT(SLAVE) in the reverse direction. A same value resistor of 24.9k from the LT8708 design example is selected here to provide an IMON_ON reading on the same scale as the one on the LT8708. RSENSE1, RIMON_INP, RIMON_INN selection: IMON_INP and IMON_INN are used to provide current limits for the LT8708-1 only. They are set to be equal to the maximum per phase VIN current in the forward and reverse directions, respectively. The maximum slave VIN current in the forward direction is: IIN(MAX,FWD,SLAVE) = = 6A • 12V 8V IIN(MAX,RVS,SLAVE) = IIN(IMON_ON,MASTER) = 3.6A Choose RIMON_INP to be around 17.4k, so that the LT8708 1’s VCSPIN–CSNIN limit becomes 50mV, and the RSENSE1 is calculated to be: R SENSE1 = 50mV 9A ≅ 6mΩ Using the equation given in the IIN and IOUT Current Monitoring and Limiting section of the LT8708 data sheet, RIMON_INP is recalculated to be: R IMON_INP = 1.209 Ω ≅ 16.2kΩ A IIN(MAX, FWD,SLAVE) • 1m • R SENSE2 + 20µA V And RIMON_INN is calculated to be: R IMON_INN = 1.21 Ω ≅ 29.4kΩ A IIN(MAX, RVS,SLAVE) • 1m • R SENSE2 + 20µA V FBOUT Pin: Connect FBOUT pin to GND to disable the FBOUT pin. FBIN Pin: Connect FBIN pin to LDO33 of the LT8708-1 to disable the FBIN pin. I(IMON_OP,MASTER) • VOUT VIN,MIN = 9A Rev A 30 For more information www.analog.com – + + 68.1k For more information www.analog.com 100k 665k M6 M5 27.4k CIN5 ×2 100k LD033 1μF CIN1 1μF CIN6 12.1k M7 100k 665k 93.1k CIN4 ×2 LD033 100Ω 2mΩ 20k 100Ω 2mΩ M1 DIR CSPIN VINCHIP SHDN FBIN VINHIMON M8 4.7μF VC 1Ω 0.22μF TO DIODE DB3 54.9k CSPIN VINCHIP SHDN VOUTLOMON FBIN FBOUT VINHIMON SWEN DIR 1Ω 1nF 10k 1Ω M9 33nF VC 470pF 10k 365k 8.2nF RT 365k LT8708-1 2mΩ 1Ω 0.22μF TO DIODE DB2 1μF TO DIODE DB4 1Ω M11 SS 1μF COUT5 4.7nF 4.7μF 17.4k 47nF 100Ω 4.7nF 23.7k 2mΩ 47nF 100Ω COUT1 2mΩ 17.4k 17.4k 100nF COUT6 COUT7 ×2 200Ω 4.7nF 20k 154k 4.7nF 10nF 47nF COUT4 ×2 100k 17.4k 17.4k 100nF COUT2 M5 - M7: T2N7002AK, TOSHIBA CIN4, CIN5, COUT4, COUT7: SUNCON, 18μF, 40V, 40HVP18M 120kHz 4.7nF GATEVCC IMON_OP IMON_ON IMON_INP IMON_INN SYNC CLKOUT INTVCC CSNOUT EXTVCC ICP ICN GND BG2 SW2 BOOST2 TG2 CSPOUT 2mΩ 1Ω 0.22μF SS CSNOUT EXTVCC VOUTLOMON FBOUT ICP ICN INTVCC GATEVCC IMON_OP IMON_ON IMON_INP IMON_INN SYNC CLKOUT 47nF 1Ω M4 GND BG2 SW2 BOOST2 TG2 CSPOUT M10 1nF 10Ω 1nF 10Ω L2 3.3μH RT LT8708 1nF 10Ω 1nF 10Ω M3 L1 3.3μH M1 - M4, M8 - M11: INFINEON BSC010N04LS COUT3, CIN3: 470μF, 50V CIN2, CIN7, COUT1, COUT5: 10µF, 50V, X7R CIN1, CIN6, COUT2, COUT6: 10µF, 50V, X7R 54.9k LD033 LDO33 100k RVSOFF MODE 127k 47nF 0.22μF TG1 BOOST1 SW1 BG1 CSP CSN CSNIN 100nF CIN7 4.7μF SWEN LD033 LDO33 100k RVSOFF MODE 127k 47nF 1Ω TO DIODE DB1 M2 TG1 BOOST1 SW1 BG1 CSP CSN CSNIN 100nF CIN2 DB1, DB2, DB3, DB4: CENTRAL SEMI CMMR1U-02-LTE L1, L2: 3.3μH, WURTH 701014330 XOR: DIODES INC. 74AHC1G86SE-7 CIN3 IIN XOR 220pF *SEE THE UNI AND BIDIRECTIONAL CONDUCTION SECTION OF THE LT8708 DATA SHEET DIR_CTRL RVS (0V) FWD (3V) POWER TRANSFER DECISION LOGIC 10V TO 16V BATTERY VBAT1 DB1 DB2 3.3Ω 4.7μF DB3 TO LT8708-1’S BOOST1 17.4k 4.7μF 200Ω DB4 4.7nF 17.4k 87081 TA03a – + COUT3 TO LT7081’S BOOST2 3.3Ω TO TO LT8708’S LT8708’S BOOST1 BOOST2 23.7k 4.7μF 12.1k 133k + I VBAT2 OUT 4.7nF 200Ω 17.4k 10V TO 16V BATTERY LT8708-1 TYPICAL APPLICATIONS 2-Phase 12V Bidirectional Dual Battery System with FHCM and RHCM Rev A 31 LT8708-1 TYPICAL APPLICATIONS 2-Phase 12V Bidirectional Dual Battery System with FHCM and RHCM Forward Conduction VBAT1 = ~12V, VBAT2 = ~14V, IOUT = ~30A Reverse Conduction VBAT1 = ~12V, VBAT2 = ~14V, IIN = ~30A IL1 IL1 AND IL2 10A/DIV IL1 IL1 AND IL2 10A/DIV IL2 LT8708 SW1 10V/DIV LT8708 SW1 10V/DIV LT8708-1 SW1 10V/DIV LT8708-1 SW1 10V/DIV 3μs/DIV 87081 TA03b IL2 3μs/DIV 87081 TA03c Direction Change with VBAT1 = ~12V, VBAT2 = ~12V DIR 5V/DIV IL1 20A/DIV IL2 20A/DIV 60ms/DIV 87081 TA03d Rev A 32 For more information www.analog.com – + + For more information www.analog.com CLK1 CLK2 CLK3 CLK4 **4-PHASE CLOCK SIGNALS FROM CLOCK CHIP SUCH AS LTC6909 68.1k 20k 340k M6 100k LD033 20k CIN5 ×2 M5 16.9k 1μF CIN1 1μF CIN6 18.2k M7 340k 340k CIN4 ×2 LD033 100Ω 5mΩ 20k 100Ω 5mΩ CIN2 M1 DIR CSPIN VINCHIP SHDN FBIN VINHIMON M8 4.7μF VC 1Ω 0.22μF TO DIODE DB3 54.9k CSPIN VINCHIP SHDN VOUTLOMON FBIN FBOUT VINHIMON SWEN DIR 1Ω 3.3nF 1nF 10k 1Ω M9 3.3nF VC 470pF 10k 365k 12nF RT 365k LT8708-1 1nF 10Ω 1nF 10Ω 1.5mΩ 1Ω 0.22μF TO DIODE DB2 1Ω M4 1μF 1Ω 0.22μF TO DIODE DB4 1Ω M11 120kHz 47nF SS PHASE 4 PHASE 3 1μF 120kHz 2mΩ COUT1 4.7nF 4.7μF 12.1k 93.1k COUT7 ×2 4.7nF 10nF 200Ω 4.7nF 22nF 200Ω COUT4 ×2 17.8k 17.4k 17.4k 100nF COUT6 17.4k 13.3k 100nF COUT2 DB1 DB2 3.3Ω 4.7μF DB3 TO LT8708-1’S BOOST1 17.4k 4.7μF 200Ω DB4 4.7nF 17.4k – + COUT3 TO LT7081’S BOOST2 3.3Ω TO TO LT8708’S LT8708’S BOOST1 BOOST2 23.7k 4.7μF 12.1k 133k + I VBAT2 OUT M5-M7: T2N7002AK, TOSHIBA CIN4, CIN5, COUT4, COUT7: SUNCON, 15μF, 100V, 100HVP15M 17.4k 47nF 100Ω COUT5 2mΩ 4.7nF 30.1k 47nF 100Ω PHASE 2 4.7nF GATEVCC IMON_OP IMON_ON IMON_INP IMON_INN SYNC CLKOUT INTVCC CSNOUT EXTVCC ICP ICN GND BG2 SW2 BOOST2 TG2 CSPOUT 1.5mΩ SS CSNOUT EXTVCC VOUTLOMON FBOUT ICP ICN INTVCC GATEVCC IMON_OP IMON_ON IMON_INP IMON_INN SYNC CLKOUT GND BG2 SW2 BOOST2 TG2 CSPOUT M10 L2, 10μH 68nF RT LT8708 1nF 10Ω 1nF 10Ω M3 L1 10μH M3, M4, M10, M11: INFINEON BSC010N04LS COUT3, CIN3: 1500μF, 63V CIN1, CIN2, CIN6, CIN7, COUT1, COUT2, COUT5, COUT6: 10µF, 100V, X7R 54.9k LD033 LDO33 100k RVSOFF MODE 127k 47nF 0.22μF TG1 BOOST1 SW1 BG1 CSP CSN CSNIN 100nF CIN7 4.7μF SWEN LD033 LDO33 100k RVSOFF MODE 127k 47nF 1Ω TO DIODE DB1 M2 TG1 BOOST1 SW1 BG1CSP CSN CSNIN 100nF DB1, DB2, DB3, DB4: CENTRAL SEMI CMMR1U-02-LTE L1, L2: 10μH, COILCRAFT SER2918H-103KL XOR: DIODES INC. 74AHC1G86SE-7 M1,M2, M8, M9: INFINEON BSC026N08NS5 CIN3 IIN XOR 220pF *SEE THE UNI AND BIDIRECTIONAL CONDUCTION SECTION OF THE LT8708 DATA SHEET DIR_CTRL RVS (0V) FWD (3V) POWER TRANSFER DECISION LOGIC 24V TO 55V BATTERY VBAT1 4.7nF 200Ω 17.4k 10V TO 16V BATTERY 87081 TA04a LT8708-1 TYPICAL APPLICATIONS 4-Phase 48V to 12V Bidirectional Dual Battery System with FHCM and RHCM Rev A 33 LT8708-1 TYPICAL APPLICATIONS 4-Phase 48V to 12V Bidirectional Dual Battery System with FHCM and RHCM Direction Change Phase 1 to 4 Inductor Current DIR 5V/DIV PHASE 1 IL 20A/DIV PHASE 1 TO PHASE 4 IL 5A/DIV PHASE 2 IL 20A/DIV PHASE 3 IL 20A/DIV 56ms/DIV 87081 TA04b 2μs/DIV 87081 TA04c Rev A 34 For more information www.analog.com LT8708-1 PACKAGE DESCRIPTION UHG Package 40-Lead Plastic QFN (5mm × 8mm) (Reference LTC DWG # 05-08-1528 Rev A) 0.70 ±0.05 5.50 ±0.05 5.85 ±0.10 PACKAGE OUTLINE 4.10 ±0.05 3.50 REF 3.10 ±0.10 0.25 ±0.05 6.50 REF 7.10 ±0.05 8.50 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED C 0.35 1.00 TYP 5.00 ±0.10 34 40 0.40 ±0.05 PIN 1 TOP MARK 33 33 1 0.25 ±0.05 0.75 TYP ×4 0.50 BSC 8.00 ±0.10 5.85 ±0.10 3.10 ±0.10 22 0.675 REF 22 14 DETAIL B 21 0.55 REF DETAIL A 15 21 15 R = 0.125 TYP BOTTOM VIEW—EXPOSED PAD 0.20 REF 0.00 – 0.05 0.75 ±0.05 1.00 TYP (UHG) QFN 0417 REV A DETAIL B 0.08 REF DETAIL A 0.203 ±0.008 0.203 +0.058, –0.008 TERMINAL THICKNESS 0.31 REF 0.00 – 0.05 NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. COPLANARITY SHALL NOT EXCEED 0.08MM. 3. WARPAGE SHALL NOT EXCEED 0.10MM. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S). 5. REFER JEDEC M0-220. Rev A For more information www.analog.com 35 LT8708-1 PACKAGE DESCRIPTION LWE Package 64-Lead Plastic Exposed Pad LQFP (10mm × 10mm) (Reference LTC DWG #05-08-1982 Rev A) 10.15 – 10.25 7.50 REF 1 64 49 48 0.50 BSC 5.74 ±0.05 7.50 REF 0.20 – 0.30 10.15 – 10.25 5.74 ±0.05 16 17 PACKAGE OUTLINE 33 32 1.30 MIN RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 12.00 BSC 10.00 BSC 5.74 ±0.10 64 49 SEE NOTE: 3 1 64 49 48 48 1 12.00 BSC 10.00 BSC A 5.74 ±0.10 A 33 16 33 16 C0.30 – 0.50 17 32 17 BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA) 32 11° – 13° R0.08 – 0.20 1.60 1.35 – 1.45 MAX GAUGE PLANE 0.25 0° – 7° LWE64 LQFP 0416 REV A 11° – 13° 0.50 BSC 0.09 – 0.20 1.00 REF 0.17 – 0.27 0.05 – 0.15 SIDE VIEW 0.45 – 0.75 SECTION A – A NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND MAX 0.50mm (20 MILS) ON ANY SIDE OF THE EXPOSED PAD, MAX 0.77mm (30 MILS) AT CORNER OF EXPOSED PAD, IF PRESENT 3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER 4. DRAWING IS NOT TO SCALE Rev A 36 For more information www.analog.com LT8708-1 REVISION HISTORY REV DATE DESCRIPTION A 01/20 Added eLQFP package option. Corrected Block Diagram. Corrected components information. PAGE NUMBER 1, 3, 4, 6, 36, 37 13 31, 33, 36 Rev A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 37 LT8708-1 TYPICAL APPLICATION 4-Phase 48V to 12V Bidirectional Dual Battery System with FHCM and RHCM IIN VBAT1 + + 24V TO 55V BATTERY 5mΩ CIN4 ×2 CIN3 L1 10μH M1 M2 CIN1 CIN2 – 1μF 340k POWER TRANSFER DECISION LOGIC DIR_CTRL *SEE THE UNI AND BIDIRECTIONAL CONDUCTION SECTION OF THE LT8708 DATA SHEET 20k 16.9k 100k M5 18.2k M7 M6 VC 54.9k RT 10k 1nF SS 365k 68nF 17.8k 47nF CSNOUT EXTVCC VOUTLOMON FBOUT ICP ICN INTVCC GATEVCC IMON_OP IMON_ON IMON_INP IMON_INN SYNC CLKOUT 1μF 120kHz 10V TO 16V BATTERY 100nF 100Ω LT8708 LD033 LDO33 100k RVSOFF MODE 127k – GND BG2 SW2 BOOST2 TG2 CSPOUT SWEN 4.7μF 1Ω 3.3nF DIR LD033 COUT3 + 1.5mΩ 1Ω 0.22μF 1nF 10Ω CSPIN VINCHIP SHDN FBIN VINHIMON 340k + COUT4 ×2 TO DIODE DB2 TG1 BOOST1 SW1 BG1CSP CSN CSNIN 47nF COUT2 COUT1 1nF 1Ω 0.22μF 100nF 100Ω 20k RVS (0V) FWD (3V) TO DIODE DB1 1Ω M3 10Ω I VBAT2 OUT 2mΩ M4 93.1k 133k 12.1k 12.1k 4.7μF 4.7μF 200Ω 4.7nF 30.1k 47nF 17.4k 13.3k 22nF 4.7nF 23.7k 3.3Ω DB1 DB2 TO TO LT8708’S LT8708’S BOOST1 BOOST2 200Ω 17.4k 200Ω 17.4k 4.7nF 4.7nF 220pF 68.1k XOR 5mΩ CIN5 ×2 M9 CIN7 1μF 340k 100Ω 100nF 47nF LD033 1Ω 0.22μF 1.5mΩ CSPIN VINCHIP SHDN VOUTLOMON FBIN FBOUT VINHIMON SWEN DIR 54.9k RT 10k 470pF 12nF CLK1 CLK2 CLK3 CLK4 100nF 100Ω GND BG2 SW2 BOOST2 TG2 CSPOUT CSNOUT EXTVCC ICP ICN LT8708-1 VC INTVCC GATEVCC IMON_OP IMON_ON IMON_INP IMON_INN SYNC CLKOUT SS 365k COUT7 ×2 1Ω 3.3nF TG1 BOOST1 SW1 BG1 CSP CSN CSNIN LD033 LDO33 100k RVSOFF MODE 127k 4.7μF 1nF 10Ω COUT6 COUT5 TO DIODE DB4 1nF 1Ω 0.22μF 2mΩ M11 M10 10Ω TO DIODE DB3 1Ω 20k **4-PHASE CLOCK SIGNALS FROM CLOCK CHIP SUCH AS LTC6909 L2, 10μH M8 CIN6 1μF 120kHz 4.7nF 47nF 4.7μF 4.7μF 200Ω 4.7nF 17.4k 17.4k 17.4k 4.7nF 10nF 17.4k DB3 TO LT8708-1’S BOOST1 3.3Ω DB4 TO LT7081’S BOOST2 PHASE 2 PHASE 3 PHASE 4 DB1, DB2, DB3, DB4: CENTRAL SEMI CMMR1U-02-LTE L1, L2: 10μH, COILCRAFT SER2918H-103KL XOR: DIODES INC. 74AHC1G86SE-7 M1, M2, M8, M9: INFINEON BSC026N08NS5 M3,M4, M10, M11: INFINEON BSC010N04LS COUT3, CIN3: 1500μF, 63V CIN1, CIN2, CIN6, CIN7, COUT1, COUT2, COUT5, COUT6: 10µF, 100V, X7R M5, M6, M7: T2N7002AK, TOSHIBA CIN4, CIN5, COUT4, COUT7: SUNCON, 15μF, 100V 100HVP15M SEE MORE DETAILS OF THIS APPLICATION ON PAGE 33. 87081 TA02a RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT8708 80V Synchronous 4-Switch Buck-Boost DC/DC Controller with Flexible Bidirectional Capability 2.8V (Need EXTVCC > 6.4V) ≤ VIN ≤ 80V, 1.3V ≤ VOUT ≤ 80V, 5mm × 8mm, QFN-40 and 10mm × 10mm eLQFP-64 Packages. LT8705A 80V VIN and VOUT Synchronous 4-Switch BuckBoost DC/DC Controller 2.8V ≤ VIN ≤ 80V, Input and Output Current Monitor, 5mm × 7mm QFN-38 and TSSOP-38 Packages LTC®3779 150V VIN and VOUT Synchronous 4-Switch BuckBoost Controller 4.5V ≤ VIN ≤ 150V, 1.2V ≤ VOUT ≤ 150V, Up to 99% Efficiency Drives Logic-Level or STD Threshold MOSFETs, TSSOP-38 Package LTC3899 60V, Triple Output, Buck/Buck/Boost Synchronous Controller with 29µA Burst Mode IQ 4.5V (Down to 2.2V after Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, Buck VOUT Range: 0.8V to 60V, Boost VOUT Up to 60V LTC3895/ LTC7801 150V Low IQ, Synchronous Step-Down DC/DC Controller with 100% Duty Cycle 4V ≤ VIN ≤ 140V, 150V ABS Max, PLL Fixed Frequency 50kHz to 900kHz, 0.8V ≤ VOUT ≤ 60V, Adjustable 5V to 10V Gate Drive, IQ = 40μA, 4mm × 5mm QFN-24, TSSOP-24, TSSOP-38(31) Packages LTC3871 Bidirectional Multiphase DC/DC Synchronous Buck or Boost On-Demand Controller VIN/VOUT Up to 100V, Ideal for High Power 48V/12V Automotive Battery Applications Rev A 38 01/20 www.analog.com © ANALOG DEVICES, INC. 2018-2020