LTC2351-12
6 Channel, 12-Bit, 1.5Msps
Simultaneous Sampling ADC
With Shutdown
DESCRIPTION
FEATURES
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n
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1.5Msps ADC with 6 Simultaneously Sampled
Differential Inputs
250ksps Throughput per Channel
72dB SINAD
Low Power Dissipation: 16.5mW
3V Single Supply Operation
2.5V Internal Bandgap Reference, Can be Overdriven
With External Reference
3-Wire SPI-Compatible Serial Interface
Internal Conversion Triggered by CONV
SLEEP (12μW) Shutdown Mode
NAP (4.5mW) Shutdown Mode
0V to 2.5V Unipolar, or ±1.25V Bipolar Differential
Input Range
83dB Common Mode Rejection
Tiny 32-Pin (5mm × 5mm) QFN Package
The LTC®2351-12 is a 12-bit, 1.5Msps ADC with six simultaneously sampled differential inputs. The device draws
only 5.5mA from a single 3V supply, and comes in a tiny
32-pin (5mm × 5mm) QFN package. A Sleep shutdown
mode further reduces power consumption to 12μW. The
combination of low power and tiny package makes the
LTC2351-12 suitable for portable applications.
The LTC2351-12 contains six separate differential inputs
that are sampled simultaneously on the rising edge of the
CONV signal. These six sampled inputs are then converted
at a rate of 250ksps per channel.
The 83dB common mode rejection allows users to eliminate
ground loops and common mode noise by measuring
signals differentially from the source.
The device converts 0V to 2.5V unipolar inputs differentially,
or ±1.25V bipolar inputs also differentially, depending on the
state of the BIP pin. Any analog input may swing rail-to-rail
as long as the differential input range is maintained.
APPLICATIONS
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Multiphase Power Measurement
Multiphase Motor Control
Data Acquisition Systems
Uninterruptable Power Supplies
The conversion sequence can be abbreviated to convert
fewer than six channels, depending on the logic state of
the SEL2, SEL1 and SEL0 inputs.
The serial interface sends out the six conversion results in 96
clocks for compatibility with standard serial interfaces.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
BLOCK DIAGRAM
CH5–
21
CH4–
18
CH3–
15
12
13
CH2–
11
–
CH2+
10
S AND H
S AND H
9
CH1–
CH1+
8
–
7
S AND H
6
CH0–
CH0+
5
–
3V
VDD
VCC
24
4
+
–
CH3+
14
+
S AND H
16
+
–
CH4+
17
+
S AND H
19
+
+
–
CH5+
20
10μF
S AND H
1.5Msps
12-BIT ADC
25
12-BIT LATCH 0
12-BIT LATCH 1
12-BIT LATCH 2
12-BIT LATCH 3
12-BIT LATCH 4
12-BIT LATCH 5
THREESTATE
SERIAL
OUTPUT
PORT
3
1
2
OVDD
3V
SD0
OGND
0.1μF
MUX
TIMING
LOGIC
2.5V
REFERENCE
30
32
31
33
22
GND
10μF
23
VREF
29
BIP
26
27
28
CONV
SCK
DGND
235112 TA01
SEL2 SEL1 SEL0
235112fa
1
LTC2351-12
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
GND
CH2+
CH2–
GND
GND
CH3+
GND
CH3–
TOP VIEW
Supply Voltage (VDD, VCC, OVDD) ................................4V
Analog and VREF Input Voltages
(Note 3) ................................... –0.3V to (VDD + 0.3V)
Digital Input Voltages ................... –0.3V to (VDD + 0.3V)
Digital Output Voltage .................. –0.3V to (VDD + 0.3V)
Power Dissipation ...............................................100mW
Operation Temperature Range
LTC2351C-12 ........................................... 0°C to 70°C
LTC2351I-12 ........................................–40°C to 85°C
LTC2351H-12 .....................................–40°C to 125°C
Storage Temperature Range...................–65°C to 150°C
16 15 14 13 12 11 10 9
CH4+ 17
8
CH1–
CH4–
18
7
CH1+
GND 19
6
GND
CH5+ 20
5
CH0–
4
CH0+
CH5–
33
21
GND 22
3
OVDD
VREF 23
2
OGND
VCC 24
1
SDO
SCK
DGND
CONV
BIP
SEL0
SEL1
VDD
SEL2
25 26 27 28 29 30 31 32
QFN PACKAGE
32-PIN (5mm s 5mm) PLASTIC QFN
TJMAX = 150°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2351CUH-12#PBF
LTC2351CUH-12#TRPBF
235112
32-Pin (5mm × 5mm) Plastic QFN
0°C to 70°C
LTC2351IUH-12#PBF
LTC2351IUH-12#TRPBF
235112
32-Pin (5mm × 5mm) Plastic QFN
–40°C to 85°C
LTC2351HUH-12#PBF
LTC2351HUH-12#TRPBF
235112
32-Pin (5mm × 5mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. With internal reference, VDD = VCC = 3V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
12
Integral Linearity Error
(Note 5)
l
–1
±0.25
1
LSB
Offset Error
(Note 4)
LTC2351H-12
l
l
–4.5
–5
±1
±1
4.5
5
mV
mV
–3
±0.5
3
mV
(Note 4)
l
–12
±2
12
mV
±1
5
Resolution (No Missing Codes)
Offset Match from CH0 to CH5
Range Error
Range Match from CH0 to CH5
Range Tempco
–5
Internal Reference (Note 4)
External Reference
Bits
±15
±1
mV
ppm/°C
ppm/°C
235112fa
2
LTC2351-12
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference, VDD = VCC = 3V.
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Differential Input Range (Notes 3, 8, 9)
2.7V ≤ VDD ≤ 3.6V, Unipolar
2.7V ≤ VDD ≤ 3.6V, Bipolar
(Note 8)
VCM
Analog Common Mode + Differential Input Range
IIN
Analog Input Leakage Current
MIN
TYP
MAX
0 to 2.5
±1.25
CIN
Analog Input Capacitance
Sample-and-Hold Acquisition Time
tAP
Sample-and-Hold Aperture Delay Time
tJITTER
Sample-and-Hold Aperture Delay Time Jitter
tSK
Channel to Channel Aperture Skew
CMRR
Analog Input Common Mode Rejection Ratio
V
V
0 to VDD
l
tACQ
UNITS
V
1
μA
39
ns
13
pF
l
(Note 6)
fIN = 100kHz, VIN = 0V to 3V
fIN = 10MHz, VIN = 0V to 3V
1
ns
0.3
ps
200
ps
–83
–67
dB
dB
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. With internal reference, VDD = VCC = 3V.
SYMBOL PARAMETER
SINAD
THD
CONDITIONS
MIN
TYP
69
72
71
72
dB
dB
dB
–90
–85
–89
dB
dB
dB
Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal
300kHz Input Signal
100kHz Input Signal (LTC2351H-12)
l
l
68
Total Harmonic Distortion
l
–80
l
–79
100kHz First 5 Harmonics
300kHz First 5 Harmonics
100kHz First 5 Harmonics (LTC2351H-12)
MAX
UNITS
SFDR
Spurious Free Dynamic Range
100kHz Input Signal
300kHz Input Signal
90
85
dB
dB
IMD
Intermodulation Distortion
0.625VP-P, 833kHz into CH0+, 0.625VP-P, 841kHz into CH0–
Bipolar Mode. Also Applicable to Other Channels
–80
dB
Code-to-Code Transition Noise
VREF = 2.5V (Note 17)
0.2
LSBRMS
Full Power Bandwidth
VIN = 2.5VP-P, SDO = 11585LSBP-P (–3dBFS) (Note 15)
50
MHz
Full Linear Bandwidth
S/(N + D) ≥ 68dB, Bipolar Differential Input
5
MHz
INTERNAL REFERENCE CHARACTERISTICS
TA = 25°C. VDD = VCC = 3V.
PARAMETER
CONDITIONS
MIN
VREF Output Voltage
IOUT = 0
2.5
V
15
ppm/°C
VREF Line Regulation
VDD = 2.7V to 3.6V, VREF = 2.5V
600
μV/V
VREF Output Resistance
Load Current = 0.5mA
0.2
Ω
VREF Settling Time
Ext CREF = 10μF
2
ms
VREF Output Tempco
External VREF Input Range
2.55
TYP
MAX
VDD
UNITS
V
235112fa
3
LTC2351-12
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = VCC = 3V.
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 3.3V
l
MIN
VIL
Low Level Input Voltage
VDD = 2.7V
l
VIN = 0V to VDD
l
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VDD = 3V, IOUT = –200μA
l
VOL
Low Level Output Voltage
VDD = 2.7V, IOUT= 160μA
VDD = 2.7V, IOUT = 1.6mA
l
VOUT = 0V and VDD
l
IOZ
Hi-Z Output Leakage DOUT
COZ
Hi-Z Output Capacitance DOUT
ISOURCE
Output Short-Circuit Source Current
ISINK
Output Short-Circuit Sink Current
TYP
MAX
UNITS
2.4
2.5
V
0.6
V
±10
μA
5
pF
2.9
V
0.05
0.4
V
V
±10
μA
1
pF
VOUT = 0V, VDD = 3V
20
mA
VOUT = VDD = 3V
15
mA
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. With internal reference, VDD = VCC = 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
VDD, VCC
Supply Voltage
IDD + ICC
Supply Current
Active Mode, fSAMPLE = 1.5Msps
Active Mode, fSAMPLE = 1.5Msps (LTC2351H-12)
Nap Mode
Nap Mode (LTC2351H-12)
Sleep Mode
2.7
PD
Power Dissipation
Active Mode with SCK, fSAMPLE = 1.5Msps
l
l
l
l
TYP
MAX
3.0
3.6
V
5.5
6
1.5
1.8
4.0
8
9
2
2.5
15
mA
mA
mA
mA
μA
16.5
UNITS
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
MIN
fSAMPLE(MAX) Maximum Sampling Rate per Channel
(Conversion Rate)
l
tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period)
l
tSCK
Clock Period
(Note 16)
l
TYP
MAX
250
40
UNITS
kHz
4
μs
10000
ns
tCONV
Conversion Time
(Notes 6, 17)
96
SCLK cycles
t1
Minimum High or Low SCLK Pulse Width
(Note 6)
2
ns
t2
CONV to SCK Setup Time
(Notes 6, 10)
3
t3
SCK Before CONV
(Note 6)
0
ns
t4
Minimum High or Low CONV Pulse Width
(Note 6)
4
ns
t5
SCK↑ to Sample Mode
(Note 6)
4
ns
t6
CONV↑ to Hold Mode
(Notes 6, 11)
1.2
ns
t7
96th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t8
Minimum Delay from SCK to Valid Bits 0 Through 11
(Notes 6, 12)
10000
8
ns
ns
235112fa
4
LTC2351-12
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL
PARAMETER
CONDITIONS
t9
SCK↑ to Hi-Z at SDO
(Notes 6, 12)
t10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
t11
VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and range specifications apply for a single-ended CH0+
– CH5+ input with CH0– – CH5– grounded and using the internal 2.5V
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between CHx+ and CHx–, x = 0 to 5.
Note 9: The absolute voltage at CHx+ and CHx– must be within this range.
MIN
TYP
MAX
6
2
UNITS
ns
ns
2
ms
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all 6 channels.
235112fa
5
LTC2351-12
TYPICAL PERFORMANCE CHARACTERISTICS
THD, 2nd and 3rd
vs Input Frequency
SINAD vs Input Frequency
74
–50
–50
UNIPOLAR SINGLE-ENDED
59
–74
THD, 2nd, 3rd (dB)
62
THD
–68
THD, 2nd, 3rd (dB)
65
2nd
–80
–86
3rd
–92
53
0.1
10
1
FREQUENCY (MHz)
–74
–86
–92
3rd
–104
–100
–110
0.1
–116
0.1
1
FREQUENCY (MHz)
10
1
FREQUENCY (MHz)
10
235112 G03
235112 G02
SFDR vs Input Frequency
100kHz Unipolar Sine Wave 8192
Point FFT Plot
SNR vs Input Frequency
74
0
86
71
–10
–20
80
68
–30
MAGNITUDE (dB)
SNR (dB)
92
68
2nd
–80
–104
235112 G01
74
THD
–68
–98
–98
56
BIPOLAR SINGLE-ENDED
–56
–62
–62
68
SINAD (dB)
THD, 2nd and 3rd
vs Input Frequency
–56
71
SFDR (dB)
VDD = 3V, TA = 25°C
65
62
62
59
56
56
50
0.1
53
0.1
–40
–50
–60
–70
–80
–90
–100
–110
10
1
FREQUENCY (MHz)
10
0
235112 G05
235112 G04
100kHz Bipolar Sine Wave 8192
Point FFT Plot
1
1
0.8
0.8
0.6
0.6
DIFFERENTIAL LINEARITY (LSB)
–60
–70
–80
–90
–100
INTEGRAL LINEARITY (LSB)
–0
–50
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–110
–120
0
25
75
50
FREQUENCY (kHz)
100
235112 G07
100
125
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
125
75
50
FREQUENCY (kHz)
Integral Linearity
vs Output Code, Unipolar Mode
–10
–40
25
235112 G06
Differential Linearity
vs Output Code, Unipolar Mode
–20
–30
MAGNITUDE (dB)
–120
1
FREQUENCY (MHz)
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
235112 G08
–1
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
235112 G09
235112fa
6
LTC2351-12
TYPICAL PERFORMANCE CHARACTERISTICS
Full Scale Signal Response
VDD = 3V, TA = 25°C
CMRR vs Frequency
3
0
0
–20
–3
–40
–9
CMRR (dB)
MAGNITUDE (dB)
–6
–12
–15
–18
–60
–80
–21
–24
–100
–27
–30
–120
100
FREQUENCY (MHz)
10
1000
100
1k
10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
235112 G11
235112 G10
PSRR vs Frequency
0
–20
–20
–40
–40
PSRR (dB)
CROSSTALK (dB)
Crosstalk vs Frequency
0
–60
–60
–80
–80
–100
–100
–120
–120
100
1k
10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
235112 G12
100
1k
10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
235112 G13
235112fa
7
LTC2351-12
PIN FUNCTIONS
SDO (Pin 1): Three-State Serial Data Output. Each set
of six output data words represent the six analog input
channels at the start of the previous conversion. Data for
CH0 comes out first and data for CH5 comes out last. Each
data word comes out MSB first.
OGND (Pin 2): Ground Return for SDO Currents. Connect
to the solid ground plane.
OVDD (Pin 3): Power Supply for the SDO Pin. OVDD
must be no more than 300mV higher than VDD and can
be brought to a lower voltage to interface to low voltage
logic families. The unloaded high state at SDO is at the
potential of OVDD.
CH3+ (Pin 14): Non-Inverting Channel 3. CH3+ operates
fully differentially with respect to CH3– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH3– (Pin 15): Inverting Channel 3. CH3– operates fully
differentially with respect to CH3+ with a –2.5V to 0V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH4+ (Pin 17): Non-Inverting Channel 4. CH4+ operates
fully differentially with respect to CH4– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH0+ (Pin 4): Non-Inverting Channel 0. CH0+ operates
fully differentially with respect to CH0– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH4– (Pin 18): Inverting Channel 4. CH4– operates fully
differentially with respect to CH4+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute input
range.
CH0– (Pin 5): Inverting Channel 0. CH0– operates fully
differentially with respect to CH0+ with a –2.5V to 0V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH5+ (Pin 20): Non-Inverting Channel 5. CH5+ operates
fully differentially with respect to CH5– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
GND (Pins 6, 9, 12, 13, 16, 19): Analog Grounds. These
ground pins must be tied directly to the solid ground plane
under the part. Analog signal currents flow through these
connections.
CH5– (Pin 21): Inverting Channel 5. CH5– operates fully
differentially with respect to CH5+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute input
range.
CH1+ (Pin 7): Non-Inverting Channel 1. CH1+ operates
fully differentially with respect to CH1– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
GND (PIN 22): Analog Ground for Reference. Analog
ground must be tied directly to the solid ground plane
under the part. Analog signal currents flow through this
connection. The 10μF reference bypass capacitor should
be returned to this pad.
CH1– (Pin 8): Inverting Channel 1. CH1– operates fully
differentially with respect to CH1+ with a –2.5V to 0V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH2+ (Pin 10): Non-Inverting Channel 2. CH2+ operates
fully differentially with respect to CH2– with a 0V to 2.5V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
CH2– (Pin 11): Inverting Channel 2. CH2– operates fully
differentially with respect to CH2+ with a –2.5V to 0V,
or ±1.25V differential swing and a 0V to VDD absolute
input range.
VREF (Pin 23): 2.5V Internal Reference. Bypass to GND and
a solid analog ground plane with a 10μF ceramic capacitor (or 10μF tantalum in parallel with 0.1μF ceramic). Can
be overdriven by an external reference voltage between
2.55V and VDD, VCC.
VCC (Pin 24): 3V Positive Analog Supply. This pin supplies 3V to the analog section. Bypass to the solid analog
ground plane with a 10μF ceramic capacitor (or 10μF
tantalum) in parallel with 0.1μF ceramic. Care should
be taken to place the 0.1μF bypass capacitor as close to
Pin 24 as possible. Pin 24 must be tied to Pin 25.
235112fa
8
LTC2351-12
PIN FUNCTIONS
VDD (Pin 25): 3V Positive Digital Supply. This pin supplies 3V to the logic section. Bypass to DGND pin and
solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum in parallel with 0.1μF ceramic). Keep
in mind that internal digital output signal currents flow
through this pin. Care should be taken to place the 0.1μF
bypass capacitor as close to Pin 25 as possible. Pin 25
must be tied to Pin 24.
SEL2 (Pin 26): Most Significant Bit Controlling the
Number of Channels Being Converted. In combination with
SEL1 and SEL0, 000 selects just the first channel (CH0)
for conversion. Incrementing SELx selects additional
channels(CH0–CH5) for conversion. 101, 110 or 111
select all 6 channels for conversion. Must be kept in a
fixed state during conversion and during the subsequent
conversion to read data.
SEL1 (Pin 27): Middle Significance Bit Controlling the
Number of Channels Being Converted. In combination
with SEL0 and SEL2, 000 selects just the first channel
(CH0) for conversion. Incrementing SELx selects additional
channels for conversion. 101, 110 or 111 select all 6
channels (CH0–CH5) for conversion. Must be kept in a
fixed state during conversion and during the subsequent
conversion to read data.
SEL0 (Pin 28): Least Significant Bit Controlling the
Number of Channels Being Converted. In combination with
SEL1 and SEL2, 000 selects just the first channel (CH0)
for conversion. Incrementing SELx selects additional
channels for conversion. 101, 110 or 111 select all 6
channels (CH0–CH5) for conversion. Must be kept in a
fixed state during conversion and during the subsequent
conversion to read data.
BIP (Pin 29): Bipolar/Unipolar Mode. The input differential range is 0V – 2.5V when BIP is LOW, and it is
±1.25V when BIP is HIGH. Must be kept in fixed state
during conversion and during subsequent conversion to
read data. When changing BIP between conversions the
full acquisition time must be allowed before starting the
next conversion. The output data is in 2’s complement
format for bipolar mode and straight binary format for
unipolar mode.
CONV (Pin 30): Convert Start. Holds the six analog input
signals and starts the conversion on the rising edge. Two
CONV pulses with SCK in fixed high or fixed low state
starts Nap mode. Four or more CONV pulses with SCK in
fixed high or fixed low state starts Sleep mode.
DGND (Pin 31): Digital Ground. This ground pin must be
tied directly to the solid ground plane. Digital input signal
currents flow through this pin.
SCK (Pin 32): External Clock Input. Advances the conversion process and sequences the output data at SD0
(Pin1) on the rising edge. One or more SCK pulses wake
from sleep or nap power saving modes. 16 clock cycles
are needed for each of the channels that are activated by
SELx (Pins 26, 27, 28), up to a total of 96 clock cycles
needed to convert and read out all 6 channels.
EXPOSED PAD (Pin 33): GND. Must be tied directly to the
solid ground plane.
235112fa
9
LTC2351-12
BLOCK DIAGRAM
0.1μF
3V
10μF
4
5
CH0+
CH0–
24
VCC
+
25
VDD
S&H
–
6
7
8
CH1+
CH1–
+
S&H
–
9
CH2+
10
CH2–
11
+
S&H
–
MUX
12 13
14
15
CH3+
CH3–
1.5Msps
12-BIT ADC
+
S&H
OVDD
3V
12-BIT LATCH 0
12-BIT LATCH 1
12-BIT LATCH 2
12-BIT LATCH 3
12-BIT LATCH 4
12-BIT LATCH 5
THREESTATE
SERIAL
OUTPUT
PORT
SD0
OGND
3
1
0.1μF
2
–
16
CH4+
17
CH4–
18
CONV
TIMING
LOGIC
+
SCK
S&H
30
32
–
19
20
21
CH5+
CH5–
+
S&H
–
2.5V
REFERENCE
EXPOSED PAD
33
GND
22
VREF
23
BIP
29
SEL2 SEL1 SEL0
26
27
28
DGND
31
235112 BD
10μF
235112fa
10
94
CONV
96
66
t6
t4
98
68
Hi-Z
35
1
2
36
t8
t2
D11
69
70
D11
D10
71
6
HOLD
7
8
t1
9
t10
10
D10
39
D9
40
D8
41
D7
42
D5
D4
43
44
D9
D8
45
12-BIT DATA WORD
D6
72
D9
73
D8
74
D7
75
D5
D4
76
77
D3
78
12-BIT DATA WORD
D6
79
D2
D7
D5
D4
12-BIT DATA WORD
D6
D3
D2
D1
D0
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH4
D10
11
12
13
14
15
D3
46
D2
47
X
80
81
D0
82
49
X
X
X
84
D11
tTHROUGHPUT
tCONV
18
50
t9
X
19
20
51
52
53
85
87
22
23
24
25
26
D10
D9
D8
27
28
29
55
D9
56
D8
57
D7
58
D5
D4
59
60
61
12-BIT DATA WORD
D6
D3
62
D2
63
D10
88
D9
89
D8
90
D7
91
D5
D4
92
93
D3
94
12-BIT DATA WORD
D6
t6
95
D2
D7
D6
D4
12-BIT DATA WORD
D5
D3
D2
D1
D0
X
t8
96
D1
X
t6
t4
98
SAMPLE
97
D0
X
D1
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH3
54
D10
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH5
86
tTHROUGHPUT
tCONV
D11
t8
21
30
X
2
65
31
X
t8
235112 TD01
Hi-Z
1
64
D0
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1
D11
tTHROUGHPUT
tCONV
Hi-Z
Back to SAMPLE mode if SELx = 010
83
48
D0
17
Back to SAMPLE mode if SELx = 000
16
Back to SAMPLE mode if SELx = 100
D1
X
D1
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH0
5
SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH2
38
4
3
32
D11
X
4
Back to
33
D10
5
D9
6
D8
TIMING DIAGRAMS
D11
37
3
to SAMPLE mode if SELx = 001
34
SAMPLE
97
t3
Back to SAMPLE mode if SELx = 011
67
SDO
INTERNAL
S/H STATUS
95
SCK
LTC2351-12 Timing Diagram
LTC2351-12
235112fa
11
LTC2351-12
TIMING DIAGRAMS
Nap Mode and Sleep Mode Waveforms
SCK
t1
t1
CONV
NAP
SLEEP
t11
VREF
235112 TD02
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
SCK to SDO Delay
SCK
VIH
SCK
VIH
t8
t10
SDO
t9
VOH
SDO
Hi-Z
VOL
235112 TD03
235112fa
12
LTC2351-12
APPLICATIONS INFORMATION
SELECTING THE NUMBER OF CONVERTED CHANNELS
(SEL2, SEL1, SEL0)
These three control pins select the number of channels
being converted. 000 selects only the first channel (CH0)
for conversion. Incrementing SELx selects additional
channels for conversion, up to 6 channels. 101, 110 or
111 select all 6 channels for conversion. These pins must
be kept in a fixed state during conversion and during the
subsequent conversion to read data. When changing modes
between conversions, keep in mind that the output data
of a particular channel will remain unchanged until after
that channel is converted again. For example: convert
a sequence of 4 channels (CH0, CH1, CH2, CH3) with
SELx = 011, then, after these channels are converted
change SELx to 001 to convert just CH0 and CH1. See
Table 1. During the conversion of the first set of two
channels you will be able to read the data from the same
two channels converted as part of the previous group
of 4 channels. Later, you could convert 4 or more channels to read back the unread CH2 and CH3 data that was
converted in the first set of 4 channels. These pins are
often hardwired to enable the right number of channels
for a particular application. Choosing to convert fewer
channels per conversion results in faster throughput of
those channels. For example, 6 channels can be converted
at 250ksps/ch, while 3 channels can be converted at
500ksps/ch.
BIPOLAR/UNIPOLAR MODE
The input voltage range for each of the CHx input differential pairs is UNIPOLAR 0V – 2.5V when BIP is LOW, and
BIPOLAR ±1.25V when BIP is HIGH. This pin must be kept
in fixed state during conversion and during subsequent
conversion to read data. When changing BIP between conversions the full acquisition time must be allowed before
starting the next conversion. After changing modes from
BIPOLAR to UNIPOLAR, or from UNIPOLAR to BIPOLAR,
you can still read the first set of channels in the new mode,
by inverting the MSB to read these channels in the mode
that they were converted in.
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC2351-12 may be
driven differentially or as a single-ended input (i.e., the
CH0– input is grounded). All twelve analog inputs of all
six differential analog input pairs, CH0+ and CH0–, CH1+
and CH1–, CH2+ and CH2–, CH3+ and CH3–, CH4+ and
CH4– and CH5+ and CH5–, are sampled at the same instant. Any unwanted signal that is common to both inputs
of each input pair will be reduced by the common mode
rejection of the sample-and-hold circuit. The inputs draw
only one small current spike while charging the sampleand-hold capacitors at the end of conversion. During
conversion, the analog inputs draw only a small leakage
Table 1. Conversion Sequence Control
(“acquire” represents simultaneous sampling of all channels; CHx represents conversion of channels)
SEL2
SEL1
SEL0
0
0
0
acquire, CH0, acquire, CH0...
CHANNEL ACQUISITION AND CONVERSION SEQUENCE
0
0
1
acquire, CH0, CH1, acquire, CH0, CH1...
0
1
0
acquire, CH0, CH1, CH2, acquire, CH0, CH1, CH2...
0
1
1
acquire, CH0, CH1, CH2, CH3, acquire, CH0, CH1, CH2, CH3...
1
0
0
acquire, CH0, CH1, CH2, CH3, CH4, acquire, CH0,CH1,CH2, CH3, CH4...
1
0
1
acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5...
1
1
0
acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5...
1
1
1
acquire, CH0, CH1, CH2, CH3, CH4, CH5, acquire, CH0, CH1, CH2, CH3, CH4, CH5...
235112fa
13
LTC2351-12
APPLICATIONS INFORMATION
current. If the source impedance of the driving circuit is
low, then the LTC2351-12 inputs can be driven directly. As
source impedance increases, so will acquisition time. For
minimum acquisition time with high source impedance,
a buffer amplifier must be used. The main requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts (the time allowed for settling must be at least 39ns
for full throughput rate). Also keep in mind while choosing an input amplifier the amount of noise and harmonic
distortion added by the amplifier.
CHOOSING AN INPUT AMPLIFIER
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (< 100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain
of 1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω.
The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate
small-signal settling for full throughput rate. If slower op
amps are used, more time for settling can be provided by
increasing the time between conversions. The best choice
for an op amp to drive the LTC2351-12 depends on the
application. Generally, applications fall into two categories:
AC applications where dynamic specifications are most
critical and time domain applications where DC accuracy
and settling time are most critical. The following list is a
summary of the op amps that are suitable for driving the
LTC2351-12. (More detailed information is available in
the Linear Technology Databooks and on the website at
www.linear.com.)
LTC1566-1: Low Noise 2.3MHz Continuous Time
Lowpass Filter.
LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high AVOL, 500μV offset and
520ns settling to 0.5LSB for a 4V swing. THD and noise
are –93dB to 40kHz and below 1LSB to 320kHz (AV = 1,
2VP-P into 1kΩ, VS = 5V), making the part excellent for AC
applications (to 1/3 Nyquist) where rail-to-rail performance
is desired. Quad version is available as LT1631.
LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.
2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and
400ns settling to 0.5LSB for a 4V swing. It is suitable for
applications with a single 5V supply. THD and noise are
–93dB to 40kHz and below 1LSB to 800kHz (AV = 1,
2VP-P into 1kΩ, VS = 5V), making the part excellent for
AC applications where rail-to-rail performance is desired.
Quad version is available as LT1633.
LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/amplifier,
8.5nV/√Hz.
LT1806/LT1807: 325MHz GBWP, –80dBc distortion at
5MHz, unity gain stable, rail-to-rail in and out, 10mA/amplifier, 3.5nV/√Hz.
LT1810: 180MHz GBWP, –90dBc distortion at 5MHz,
unity gain stable, rail-to-rail in and out, 15mA/amplifier,
16nV/√Hz.
LT1818/LT1819: 400MHz, 2500V/μs, 9mA, Single/Dual
Voltage Mode Operational Amplifier.
LT6200: 165MHz GBWP, –85dBc distortion at 1MHz,
unity gain stable, rail-to-rail in and out, 15mA/amplifier,
0.95nV/√Hz.
LT6203: 100MHz GBWP, –80dBc distortion at 1MHz,
unity gain stable, rail-to-rail in and out, 3mA/amplifier,
1.9nV/√Hz.
LT6600: Amplifier/Filter Differential In/Out with 10MHz
Cutoff Frequency.
INPUT FILTERING AND SOURCE IMPEDANCE
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC2351-12 noise and distortion. The small-signal
bandwidth of the sample-and-hold circuit is 50MHz. Any
noise or distortion products that are present at the analog
inputs will be summed over this entire bandwidth. Noisy
input circuitry should be filtered prior to the analog inputs.
A simple 1-pole RC filter is sufficient for many applications. For example, Figure 1 shows a 47pF capacitor from
CHO+ to ground and a 51Ω source resistor to limit the
235112fa
14
LTC2351-12
APPLICATIONS INFORMATION
ANALOG
INPUT
51Ω*
1
47pF*
2
INTERNAL REFERENCE
CH0+
CH0–
LTC2351-12
3
10μF
11
ANALOG
INPUT
51Ω*
4
47pF*
5
VREF
GND
CH1+
CH1–
235112 F01
*TIGHT TOLERANCE REQUIRED TO AVOID
APERTURE SKEW DEGRADATION
Figure 1. RC Input Filter
net input bandwidth to 30MHz. The 47pF capacitor also
acts as a charge reservoir for the input sample-and-hold
and isolates the ADC input from sampling-glitch sensitive
circuitry. High quality capacitors and resistors should be
used since these components can add distortion. NPO
and silvermica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems. When high
amplitude unwanted signals are close in frequency to the desired signal frequency a multiple pole filter is required.
High external source resistance, combined with 13pF
of input capacitance, will reduce the rated 50MHz input
bandwidth and increase acquisition time beyond 39ns.
INPUT RANGE
The analog inputs of the LTC2351-12 may be driven fully
differentially with a single supply. Either input may swing
up to VCC, provided the differential swing is no greater
than 2.5V with BIP (Pin 29) Low, or ±1.25V with (BIP Pin
29) High. The 0V to 2.5V range is also ideally suited for
single-ended input use with single supply applications. The
common mode range of the inputs extend from ground
to the supply voltage VCC. If the difference between the
CH+ and CH– at any input pair exceeds 2.5V (unipolar) or
1.25V (bipolar), the output code will stay fixed at positive
full-scale, and if this difference goes below 0V (unipolar)
or –1.25V (bipolar), the output code will stay fixed at
negative full-scale.
The LTC2351-12 has an on-chip, temperature compensated, bandgap reference that is factory trimmed to 2.5V
to obtain a precise 2.5V input span. The reference amplifier
output VREF, (Pin 23) must be bypassed with a capacitor
to ground. The reference amplifier is stable with capacitors of 1μF or greater. For the best noise performance, a
10μF ceramic or a 10μF tantalum in parallel with a 0.1μF
ceramic is recommended. The VREF pin can be overdriven
with an external reference as shown in Figure 2. The
voltage of the external reference must be higher than the
2.5V of the open-drain P-channel output of the internal
reference. The recommended range for an external reference is 2.55V to VDD. An external reference at 2.55V will
see a DC quiescent load of 0.75mA and as much as 3mA
during conversion.
3.5V TO 18V
23
LT1790-3
10μF
VREF
LTC2351-12
22
GND
235112 F02
Figure 2. Overdriving VREF Pin with an External Reference
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a unipolar voltage span
that equals the difference between the voltage at the
reference buffer output VREF (Pin 23) and the voltage at
ground. The differential input range of the ADC is 0V to
2.5V when using the internal reference. The internal ADC
is referenced to these two nodes. This relationship also
holds true with an external reference.
DIFFERENTIAL INPUTS
The ADC will always convert the difference of CH+ minus
CH–, independent of the common mode voltage at any pair
of inputs. The common mode rejection holds up at high
frequencies (see Figure 3.) The only requirement is that
both inputs not go below ground or exceed VDD.
235112fa
15
LTC2351-12
APPLICATIONS INFORMATION
Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are largely independent of the common
mode voltage. However, the offset error will vary. DC CMRR
is typically better than –90dB.
0
–20
CMRR (dB)
–40
–60
–80
–100
–120
100
1k
10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
Figure 4 shows the ideal input/output characteristics for
the LTC2351-12 in unipolar mode (BIP = Low). The code
transitions occur midway between successive integer LSB
values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The
output code is straight binary with 1LSB = 2.5V/4096 =
610μV for the LTC2351-12. The LTC2351-12 has 0.2 LSB
RMS of Gaussian white noise.
235112 F03
Figure 3. CMRR vs Frequency
STRAIGHT BINARY OUTPUT CODE
111...111
111...110
111...101
POWER-DOWN MODES
000...010
000...001
000...000
0
FS – 1LSB
INPUT VOLTAGE (V)
235112 F04
Figure 4. LTC2351-12 Transfer Characteristic
in Unipolar Mode (BIP = Low)
011...111
2'S COMPLEMENT OUTPUT CODE
Figure 5 shows the ideal input/output characteristics for
the LTC2351-12 in bipolar mode (BIP = High). The code
transitions occur midway between successive integer LSB
values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The
output code is 2’s complement with 1LSB = 2.5V/4096 =
610μV for the LTC2351-12. The LTC2351-12 has 0.2 LSB
RMS of Gaussian white noise.
011...110
011...101
100...010
100...001
100...000
–FS
FS – 1LSB
INPUT VOLTAGE (V)
235112 F05
Upon power-up, the LTC2351-12 is initialized to the
active state and is ready for conversion. The Nap and
Sleep mode waveforms show the power down modes
for the LTC2351-12. The SCK and CONV inputs control
the power down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges
at SCK, put the LTC2351-12 in Nap mode and the power
consumption drops from 16.5mW to 4.5mW. The internal
reference remains powered in Nap mode. One or more
rising edges at SCK wake up the LTC2351-12 very quickly
and CONV can start an accurate conversion within a clock
cycle. Four rising edges at CONV, without any intervening
rising edges at SCK, put the LTC2351-12 in Sleep mode
and the power consumption drops from 16.5mW to 12μW.
One or more rising edges at SCK wake up the LTC2351-12
for operation. The internal reference (VREF ) takes 2ms to
slew and settle with a 10μF load. Using sleep mode more
frequently compromises the accuracy of the output data.
Note that for slower conversion rates, the Nap and Sleep
modes can be used for substantial reductions in power
consumption.
Figure 5. LTC2351-12 Transfer Characteristic
in Bipolar Mode (BIP = High)
235112fa
16
LTC2351-12
APPLICATIONS INFORMATION
DIGITAL INTERFACE
The LTC2351-12 has a 3-wire SPI (Serial Peripheral
Interface) interface. The SCK and CONV inputs and SDO
output implement this interface. The SCK and CONV inputs
accept swings from 3V logic and are TTL compatible, if the
logic swing does not exceed VDD. A detailed description
of the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subsequent rising edges at CONV are ignored by the LTC2351-12
until the following 96 SCK rising edges have occurred. The
duty cycle of CONV can be arbitrarily chosen to be used as
a frame sync signal for the processor serial port. A simple
approach to generate CONV is to create a pulse that is one
SCK wide to drive the LTC2351-12 and then buffer this
signal to drive the frame sync input of the processor serial
port. It is good practice to drive the LTC2351-12 CONV
input first to avoid digital noise interference during the
sample-to-hold transition triggered by CONV at the start
of conversion. It is also good practice to keep the width
of the low portion of the CONV signal greater than 15ns
to avoid introducing glitches in the front end of the ADC
just before the sample-and-hold goes into Hold mode at
the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sine waves
above 100kHz are sampled, the CONV signal must have
as little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement. The challenge is to generate a CONV
signal from this crystal clock without jitter corruption from
other digital circuits in the system. A clock divider and
any gates in the signal path from the crystal clock to the
CONV input should not share the same integrated circuit
with other parts of the system. The SCK and CONV inputs
should be driven first, with digital buffers used to drive
the serial port interface. Also note that the master clock
in the DSP may already be corrupted with jitter, even if it
comes directly from the DSP crystal. Another problem with
high speed processor clocks is that they often use a low
cost, low speed crystal (i.e., 10MHz) to generate a fast,
but jittery, phase-locked-loop system clock (i.e., 40MHz).
The jitter in these PLL-generated high speed clocks can be
several nanoseconds. Note that if you choose to use the
frame sync signal generated by the DSP port, this signal
will have the same jitter of the DSP’s master clock.
The Typical Application figure on page 20 shows a circuit
for level-shifting and squaring the output from an RF signal
generator or other low-jitter source. A single D-type flip flop
is used to generate the CONV signal to the LTC2351-12.
Re-timing the master clock signal eliminates clock jitter
introduced by the controlling device (DSP, FPGA, etc.)
Both the inverter and flip flop must be treated as analog
components and should be powered from a clean analog
supply.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK sends out up to
six sets of 12 data bits, with the MSB sent first. A simple
approach is to generate SCK to drive the LTC2351-12 first
and then buffer this signal with the appropriate number of
inverters to drive the serial clock input of the processor
serial port. Use the falling edge of the clock to latch data
from the serial data output (SDO) into your processor
serial port. The 12-bit serial data will be received in six
16-bit words with 96 or more clocks per frame sync. If
fewer than 6 channels are selected by SEL0–SEL2 for
conversion, then 16 clocks are needed per channel to
convert the analog inputs and read out the resulting data
after the next convert pulse. It is good practice to drive the
LTC2351-12 SCK input first to avoid digital noise interference during the internal bit comparison decision by the
internal high speed comparator. Unlike the CONV input,
the SCK input is not sensitive to jitter because the input
signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends out
up to six sets of 12 bits in the output data stream after the
third rising edge of SCK after the start of conversion with
235112fa
17
LTC2351-12
APPLICATIONS INFORMATION
the rising edge of CONV. The six or fewer 12-bit words are
separated by two don’t care bits and two clock cycles in
high impedance mode. Please note the delay specification
from SCK to a valid SDO. SDO is always guaranteed to
be valid by the next rising edge of SCK. The 16 – 96-bit
output data stream is compatible with the 16-bit or 32-bit
serial port of most processors.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best
performance from the LTC2351-12, a printed circuit board
with ground plane is required. Layout for the printed circuit
board should ensure that digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track. If optimum phase match between the
inputs is desired, the length of the twelve input wires of
the six input channels should be kept matched. But each
pair of input wires to the six input channels should be
kept separated by a ground trace to avoid high frequency
crosstalk between channels.
High quality tantalum and ceramic bypass capacitors
should be used at the VCC, VDD and VREF pins as shown
in the Block Diagram on the first page of this data sheet.
OVDD BYPASS,
0.1μF, 0402
For optimum performance, a 10μF surface mount tantalum
capacitor with a 0.1μF ceramic is recommended for the
VCC, VDD and VREF pins. Alternatively, 10μF ceramic chip
capacitors such as X5R or X7R may be used. The capacitors must be located as close to the pins as possible. The
traces connecting the pins and the bypass capacitors must
be kept short and should be made as wide as possible. The
VCC and VDD bypass capacitor returns to the ground plane
and the VREF bypass capacitor returns to the Pin 22. Care
should be taken to place the 0.1μF VCC and VDD bypass
capacitor as close to Pins 24 and 25 as possible.
Figure 6 shows the recommended system ground connections. All analog circuitry grounds should be terminated at
the LTC2351-12 Exposed Pad. The ground return from the
LTC2351-12 to the power supply should be low impedance
for noise-free operation. The Exposed Pad of the 32-pin
QFN package is also internally tied to the ground pads.
The Exposed Pad should be soldered on the PC board to
reduce ground connection inductance. All ground pins
(GND, DGND, OGND) must be connected directly to the
same ground plane under the LTC2351-12.
HARDWARE INTERFACE TO TMS320C54x
The LTC2351-12 is a serial output ADC whose interface
has been designed for high speed buffered serial ports in
fast digital signal processors (DSPs). Figure 7 shows an
example of this interface using a TMS320C54X.
LTC2351-12
OVDD
CONV
VDD BYPASS,
0.1μF, 0402
VCC BYPASS,
0.1μF, 0402 AND
10μF, 0805
SCK
SDO
OGND
DGND
VREF BYPASS,
10μF, 0805
Figure 6. Recommended Layout
3V
TMS320C54x
5V
3
VCC
30
BFSR
32
BCLKR
B11
1
B10
BDR
2
31
CONV
CLK
3-WIRE SERIAL
INTERFACE LINK
235112 F07
0V TO 3V LOGIC SWING
Figure 7. DSP Serial Interface to TMS320C54x
235112fa
18
LTC2351-12
APPLICATIONS INFORMATION
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial
data can be collected in two alternating 1kB segments,
in real time, at the full 1.5Msps conversion rate of the
LTC2351-12. The DSP assembly code sets frame sync
mode at the BFSR pin to accept an external positive going
pulse and the serial clock at the BCLKR pin to accept an
external positive edge clock. Buffers near the LTC2351-12
may be added to drive long tracks to the DSP to prevent
corruption of the signal to LTC2351-12. This configuration
is adequate to traverse a typical system board, but source
resistors at the buffer outputs and termination resistors
at the DSP, may be needed to match the characteristic
impedance of very long transmission lines. If you need
to terminate the SDO transmission line, buffer it first with
one or two 74ACxx gates. The TTL threshold inputs of the
DSP port respond properly to the 3V swing used with the
LTC2351-12.
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.05
TYP
0.00 – 0.05
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.115
TYP
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ± 0.10
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
235112fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2351-12
TYPICAL APPLICATION
Low-Jitter Clock Timing with RF Sine Generator Using Clock
Squaring/Level Shifting Circuit and Re-Timing Flip-Flop
VCC
0.1μF
1k NC7SVU04P5X
MASTER CLOCK
50Ω
VCC
1k
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
PRE
D
Q
CONV
2351-12
Q
CLR
NL17SZ74
CONVERT ENABLE
1408 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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12-Bit, 2.2Msps Serial ADC
5V or ±5V Supply, 4.096V or ±2.5V Span
LTC1403/LTC1403A
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3V, 15mW, Unipolar Inputs, MSOP Package
ADCs
LTC1403-1/LTC1403A-1 12-/14-Bit, 2.8Msps Serial ADC
3V, 15mW, Bipolar Inputs, MSOP Package
LTC1405
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LTC1407/LTC1407A
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3V, 14mW, 2-Channel Unipolar Input Range
LTC1407-1/LTC1407A-1 12-/14-Bit, 3Msps Simultaneous Sampling ADC
3V, 14mW, 2-Channel Bipolar Input Range
LTC1411
14-Bit, 2.5Msps Parallel ADC
5V, Selectable Spans, 80dB SINAD
LTC1412
12-Bit, 3Msps Parallel ADC
±5V Supply, ±2.5V Span, 72dB SINAD
LTC1420
12-Bit, 10Msps Parallel ADC
5V, Selectable Spans, 72dB SINAD
LTC1608
16-Bit, 500ksps Parallel ADC
±5V Supply, ±2.5V Span, 90dB SINAD
LTC1609
16-Bit, 250ksps Serial ADC
5V Configurable Bipolar/Unipolar Inputs
LTC1864/LTC1865
LTC1864L/LTC1865L
16-Bit, 250ksps 1-/2-Channel Serial ADCs
5V or 3V (L-Version), Micropower, MSOP Package
LTC1592
16-Bit, Serial SoftSpan™ IOUT DAC
±1LSB INL/DNL, Software Selectable Spans
LTC1666/LTC1667/
LTC1668
12-/14-/16-Bit, 50Msps DAC
87dB SFDR, 20ns Settling Time
LT1460-2.5
Micropower Series Voltage Reference
0.10% Initial Accuracy, 10ppm Drift
LT1461-2.5
Precision Voltage Reference
0.04% Initial Accuracy, 3ppm Drift
LT1790-2.5
Micropower Series Reference in SOT-23
0.05% Initial Accuracy, 10ppm Drift
DACs
References
SoftSpan is a trademark of Linear Technology Corporation.
235112fa
20 Linear Technology Corporation
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