LTC2470/LTC2472
Selectable 208sps/833sps,
16-Bit ΔΣ ADCs with 10ppm/°C
Max Precision Reference
Description
Features
n
n
n
n
n
n
n
n
n
n
n
n
n
16-Bit Resolution
Internal, High Accuracy Reference—10ppm/°C (Max)
Single-Ended (LTC2470) or Differential (LTC2472)
Selectable 208sps/833sps Output Rate
1mV Offset Error
0.01% Gain Error
Single Conversion Settling Time for Multiplexed
Applications
Single-Cycle Operation with Auto Shutdown
3.5mA (Typ) Supply Current
2µA (Max) Sleep Current
Internal Oscillator—No External Components
Required
SPI Interface
Small 12-Lead, 3mm × 3mm DFN and MSOP
Packages
The LTC®2470/LTC2472 are small, 16-bit analog-to-digital
converters with an integrated precision reference and
a selectable 208sps or 833sps output rate. They use a
single 2.7V to 5.5V supply and communicate through a
SPI Interface. The LTC2470 is single-ended with a 0V to
VREF input range and the LTC2472 is differential with a
±VREF input range. Both ADC’s include a 1.25V integrated
reference with 2ppm/°C drift performance and 0.1% initial
accuracy. The converters are available in a 12-pin DFN
3mm × 3mm package or an MSOP-12 package. They
include an integrated oscillator and perform conversions
with no latency for multiplexed applications. The LTC2470/
LTC2472 include a proprietary input sampling scheme
that reduces the average input current several orders of
magnitude when compared to conventional delta sigma
converters.
Following a single conversion, the LTC2470/LTC2472
automatically power down the converter and can also be
configured to power down the reference. When both the
ADC and reference are powered down, the supply current
is reduced to 200nA.
Applications
System Monitoring
Environmental Monitoring
n Direct Temperature Measurements
n Instrumentation
n Industrial Process Control
n Data Acquisition
n Embedded ADC Upgrades
n
n
The LTC2470/LTC2472 include a user selectable 208sps
or 833sps output rate and due to a large oversampling
ratio (8,192 at 208sps and 2,048 at 833sps) have relaxed
anti-aliasing requirements.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency ∆∑ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 6208279, 6411242,
7088280, 7164378.
Typical Application
VREF vs Temperature
1.2520
0.1µF
0.1µF
0.1µF
10k
REFOUT
SCK
LTC2472
IN–
10k
R
0.1µF
SDO
CS
REF–
10µF
COMP VCC
IN+
10k
0.1µF
GND
SPI
INTERFACE
REFERENCE OUTPUT VOLTAGE (V)
2.7V TO 5.5V
1.2515
1.2510
1.2505
1.2500
1.2495
1.2490
1.2485
24702 TA01a
1.2480
–50
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
24702 TA01b
24702fb
For more information www.linear.com/LTC2470
1
LTC2470/LTC2472
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (VCC).................................... –0.3V to 6V
Analog Input Voltage
(VIN+, VIN –, VIN, VREF –,
VCOMP, VREFOUT )............................–0.3V to (VCC + 0.3V)
Digital Voltage
(VSDI, VSDO, VSCK, VCS).................–0.3V to (VCC + 0.3V)
Storage Temperature Range................... –65°C to 150°C
Operating Temperature Range
LTC2470C/LTC2472C................................ 0°C to 70°C
LTC2470I/LTC2472I..............................–40°C to 85°C
Pin Configuration
LTC2472
LTC2472
TOP VIEW
REFOUT
1
12 VCC
COMP
2
11 GND
CS
3
SDI
4
13
GND
TOP VIEW
–
10 IN
9 IN+
SCK
5
8 REF–
SDO
6
7 GND
1
2
3
4
5
6
REFOUT
COMP
CS
SDI
SCK
SDO
VCC
GND
IN–
IN+
REF–
GND
MS PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 130°C/W
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL
LTC2470
12
11
10
9
8
7
LTC2470
TOP VIEW
REFOUT
1
12 VCC
COMP
2
11 GND
CS
3
SDI
4
SCK
5
8 REF–
SDO
6
7 GND
13
GND
TOP VIEW
REFOUT
COMP
CS
SDI
SCK
SDO
10 GND
9 IN
1
2
3
4
5
6
12
11
10
9
8
7
VCC
GND
GND
IN
REF–
GND
MS PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 130°C/W
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) PCB GROUND CONNECTION OPTIONAL
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2470CDD#PBF
LTC2470IDD#PBF
LTC2470CDD#TRPBF
LFPV
12-Lead Plastic (3mm × 3mm) DFN
0°C to 70°C
LTC2470IDD#TRPBF
LFPV
12-Lead Plastic (3mm × 3mm) DFN
–40°C to 85°C
LTC2470CMS#PBF
LTC2470CMS#TRPBF
2470
12-Lead Plastic MSOP
0°C to 70°C
LTC2470IMS#PBF
LTC2470IMS#TRPBF
2470
12-Lead Plastic MSOP
–40°C to 85°C
LTC2472CDD#PBF
LTC2472CDD#TRPBF
LFGV
12-Lead Plastic (3mm × 3mm) DFN
0°C to 70°C
LTC2472IDD#PBF
LTC2472IDD#TRPBF
LFGV
12-Lead Plastic (3mm × 3mm) DFN
–40°C to 85°C
24702fb
2
For more information www.linear.com/LTC2470
LTC2470/LTC2472
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2472CMS#PBF
LTC2472CMS#TRPBF
2472
12-Lead Plastic MSOP
0°C to 70°C
LTC2472IMS#PBF
LTC2472IMS#TRPBF
2472
12-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
Resolution
MAX
16
Integral Nonlinearity
Output Rate 208sps (Note 4)
Output Rate 833sps (Note 4)
Offset Error
UNITS
Bits
l
l
2
8
8.5
16
LSB
LSB
l
±1
±2.5
mV
Offset Error Drift
0.05
LSB/°C
Gain Error
l
±0.01
Gain Error Drift
l
0.15
±0.25
% of FS
LSB/°C
Transition Noise
3
µVRMS
Power Supply Rejection DC
80
dB
The
Analog
Inputs l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
+
Positive Input Voltage Range
LTC2472
l
VIN
–
Negative Input Voltage Range
LTC2472
VIN
Input Voltage Range
LTC2470
VIN
+, V
VOR
+
UR
–
VOR , VUR–
Overrange/Underrange Voltage, IN+
Overrange/Underrange Voltage, IN–
CIN
IN+, IN–, IN Sampling Capacitance
IDC_LEAK(IN+, IN–, IN)
IN+, IN– DC Leakage Current (LTC2472)
IN DC Leakage Current (LTC2470)
ICONV
Input Sampling Current (Note 8)
VREF
Reference Output Voltage
Reference Voltage Coefficient
MIN
MAX
UNITS
0
VREF
V
l
0
VREF
V
l
0
VREF
V
– = 0.625V
VIN
+ = 0.625V
VIN
TYP
8
LSB
8
LSB
0.35
VIN = GND (Note 5)
VIN = VCC (Note 5)
l
l
–10
–10
±1
±1
pF
10
10
50
l
(Note 9)
C-Grade
I-Grade
l
1.247
nA
nA
nA
1.25
1.253
V
±2
±5
±10
ppm/°C
ppm/°C
Reference Line Regulation
2.7V ≤ VCC ≤ 5.5V
Reference Short Circuit Current
VCC = 5.5, Forcing Output to GND
l
35
mA
COMP Pin Short Circuit Current
VCC = 5.5, Forcing Output to GND
l
200
µA
–90
dB
Reference Load Regulation
2.7V ≤ VCC ≤ 5.5V, IOUT = 100μA Sourcing
3.5
mV/mA
Reference Output Noise Density
CCOMP= 0.1μF, CREFOUT = 0.1μF, At f =
1ksps
30
nV/√Hz
24702fb
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3
LTC2470/LTC2472
Power Requirements
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion
Conversion
Nap
Sleep
CONDITIONS
MIN
2.7
l
CS = GND (Note 6) LTC2472
CS = GND (Note 6) LTC2470
CS = VCC (Note 6)
CS = VCC (Note 6)
TYP
UNITS
5.5
3.5
2.5
800
0.2
l
l
l
l
MAX
V
5
4
1500
2
mA
mA
µA
µA
Digital Inputs and Digital Outputs
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
l
–10
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –800µA
l
VCC – 0.5
VOL
Low Level Output Voltage
IO = 1.6mA
l
IOZ
Hi-Z Output Leakage Current
TYP
MAX
UNITS
VCC – 0.3
V
0.3
V
10
µA
10
l
pF
V
–10
0.4
V
10
µA
Timing
Characteristics l denotes the specifications which apply over the full operating temperature
The
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
tCONV1
Conversion Time
SPD = 0
l
3.2
4
4.8
tCONV2
Conversion Time
SPD = 1
l
0.8
1
1.2
ms
fSCK
SCK Frequency Range
2
MHz
tlSCK
SCK Low Period
(Note 7)
l
250
thSCK
SCK High Period
(Note 7)
l
250
t1
CS Falling Edge to SDO Low Z
(Note 7)
l
0
100
ns
t2
CS Rising Edge to SDO High Z
(Note 7)
l
0
100
ns
t3
CS Falling Edge to SCK Falling Edge
(Note 7)
l
100
ns
t4
SDI Setup Before SCK↑
(Notes 3, 7)
l
100
ns
t5
SDI Hold After SCK↑
(Notes 3, 7)
l
100
tKQ
SCK Falling Edge to SDO Valid
(Note 7)
l
0
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2. All voltage values are with respect to GND. VCC = 2.7V to 5.5V
unless otherwise specified.
VREFCM = VREF/2, FS = VREF, –VREF ≤ VIN ≤ VREF
VIN = VIN+ – VIN –, VINCM = (VIN+ + VIN –)/2. (LTC2472)
Note 3. Guaranteed by design, not subject to test.
Note 4. Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
UNITS
ms
ns
ns
ns
100
ns
Note 5: CS = VCC. A positive current is flowing into the DUT pin.
Note 6: SCK = VCC or GND. SDO is high impedance.
Note 7: See Figure 5.
Note 8: Input sampling current is the average input current drawn from
the input sampling network while the LTC2470/LTC2472 is actively
sampling the input.
Note 9: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
24702fb
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LTC2470/LTC2472
Typical Performance Characteristics
Integral Nonlinearity
(TA = 25°C, unless otherwise noted)
Integral Nonlinearity
3
VCC = 2.7V
TA = –45°C, 25°C, 90°C
2 OUTPUT RATE = 208sps
Maximum INL vs Temperature
3
6
2
4
1
2
OUTPUT RATE = 208sps
INL (LSB)
INL (LSB)
0
INL (LSB)
VCC = 5.5V
1
0
–1
–1
–2
–2
–2 VCC = 5.5V
TA = –45°C, 25°C, 90°C
OUTPUT RATE = 208sps
–3
0.25
0.75
–1.25
–0.75
–0.25
DIFFERENTIAL INPUT VOLTAGE (V)
–4
–3
–1.25
0.25
0.75
–0.75
–0.25
DIFFERENTIAL INPUT VOLTAGE (V)
1.25
Offset Error vs Temperature
ADC Gain Error vs Temperature
VCC = 4.1V
15
10
VCC = 2.7V
–30
50
–10 10
30
TEMPERATURE (°C)
30
20
VCC = 4.1V
10
VCC = 2.7V
–10
–50 –30
90
–10 10
30
50
TEMPERATURE (°C)
70
VCC = 5.5V
3.7
VCC = 4.1V
3.6
3.5
3.4
VCC = 2.7V
3.3
3.2
250
200
VCC = 4.1V
150
50
–10 10
30
TEMPERATURE (°C)
70
90
100
24702 G07
0
–50
VCC = 2.7V
–30
VCC = 5.5V
5
4
3
VCC = 2.7V
2
50
–10 10
30
TEMPERATURE (°C)
–30
24702 G05
VCC = 5.5V
50
3.1
–30
6
1.2508
300
SLEEP CURRENT (nA)
3.8
7
0
–50
90
350
3.9
24702 G03
8
Sleep Mode Power Supply
Current vs Temperature
4.0
90
1
24702 G04
Conversion Mode Power Supply
Current vs Temperature
3.0
–50
VCC = 5.5V
0
70
70
9
REFERENCE OUTPUT VOLTAGE (V)
0
–50
30
50
–10 10
TEMPERATURE (°C)
Transition Noise vs Temperature
TRANSITION NOISE RMS (µV)
ADC GAIN ERROR (LSB)
OFFSET ERROR (LSB)
20
–30
10
40
25
5
CONVERSION CURRENT (mA)
–6
–50
1.25
50
35
VCC = 5.5V
VCC = 2.7V
24702 G02
24702 G01
30
VCC = 4.1V
0
70
90
24702 G08
50
–10 10
30
TEMPERATURE (°C)
70
90
24702 G06
VREF vs Temperature
1.2507
1.2506
1.2505
1.2504
1.2503
1.2502
–50
–30
50
–10 10
30
TEMPERATURE (°C)
70
90
24702 G09
24702fb
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5
LTC2470/LTC2472
Typical Performance Characteristics
Power Supply Rejection
vs Frequency Applied to VCC
Conversion Time vs Temperature
4.4
TA = 25°C
CONVERSION TIME (ms)
REJECTION (dB)
–40
–60
–80
–120
VCC = 2.7V
1
10
100 1k 10k 100k
FREQUENCY AT VCC (Hz)
1M
10M
1.250335
4.2
1.250330
VCC = 4.1V
4.1
1.250325
1.250320
4.0
3.8
–50
1.250315
VCC = 5.5V
3.9
–100
TA = 25°C
1.250340
4.3
–20
VREF vs VCC
1.250345
VREF (V)
0
(TA = 25°C, unless otherwise noted)
1.250310
–25
25
50
0
TEMPERATURE (°C)
24702 G010
75
100
24702 G11
1.250305
2.0
2.5
3.0
3.5
4.0 4.5
VCC (V)
5.0
5.5
6.0
24702 G12
Pin Functions
REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V,
this voltage sets the full-scale input range of the ADC. For
noise and reference stability connect to a 0.1µF capacitor
tied to GND. This capacitor value must be less than or
equal to the capacitor tied to the reference compensation
pin (COMP). REFOUT cannot be overdriven by an external
reference.
COMP (Pin 2): Internal Reference Compensation Pin. For
low noise and reference stability, tie a 0.1μF capacitor
to GND.
CS (Pin 3): Chip Select (Active LOW) Digital Input. A LOW
on this pin enables the SDO output. A HIGH on this pin
places the SDO output pin in a high impedance state and
any inputs on SDI and SCK will be ignored.
SDI (Pin 4): Serial Data Input Pin. This pin is used to program the sleep mode and the 208sps/833sps output rate.
SCK (Pin 5): Serial Clock Input. SCK synchronizes the
serial data input/output. Once the conversion is complete,
a new data bit is produced at the SDO pin following each
SCK falling edge. Data is shifted into the SDI pin on each
rising edge of SCK.
SDO (Pin 6): Three-State Serial Data Output. SDO is used
for serial data output during the DATA INPUT/OUTPUT
state. This pin goes Hi-Z when CS is high.
GND (Pins 7, 11, Exposed Pad Pin 13 – DFN Package):
Ground. Connect directly to the ground plane through a
low impedance connection.
REF– (Pin 8): Negative Reference Input to the ADC. The
voltage on this pin sets the zero input to the ADC. This
pin should be tied directly to ground or the ground sense
of the input sensor.
IN+ (LTC2472), IN (LTC2470) (Pin 9): Positive input voltage for the LTC2472 differential device. ADC input for the
LTC2470 single-ended device.
IN– (LTC2472), GND (LTC2470) (Pin 10): Negative input
voltage for the LTC2472 differential device. GND for the
LTC2470 single-ended device.
VCC (Pin 12): Positive Supply Voltage. Bypass to GND
with a 10μF capacitor in parallel with a low-series-inductance 0.1μF capacitor located as close to the device as
possible.
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LTC2470/LTC2472
Block Diagram
1
9
10
IN+
(IN)
IN–
(GND)
2
REFOUT
COMP
12
CS
INTERNAL
REFERENCE
ΔΣ A/D
CONVERTER
–
VCC
SPI
INTERFACE
DECIMATING
SINC FILTER
SCK
SDO
SDI
3
5
6
4
ΔΣ A/D
CONVERTER
INTERNAL
OSCILLATOR
8
REF–
( ) PARENTHESIS INDICATE LTC2470
7, 11, 13 DD PACKAGE
GND
7, 11 MS PACKAGE
24702 BD
Figure 1. Functional Block Diagram
Applications Information
Converter Operation
POWER-ON RESET
Converter Operation Cycle
CONVERT
The LTC2470/LTC2472 are low power, delta sigma, analog
to digital converters with a simple SPI interface and a user
selected 208sps/833sps output rate (see Figure 1). The
LTC2472 has a fully differential input while the LTC2470 is
single-ended. Both are pin and software compatible. Their
operation is composed of three distinct states: CONVERT,
SLEEP/NAP, and DATA INPUT/OUTPUT. The operation
begins with the CONVERT state (see Figure 2). Once the
conversion is finished, the converter automatically powers down (NAP) or under user control, both the converter
and reference are powered down (SLEEP). The conversion
result is held in a static register while the device is in this
state. The cycle concludes with the DATA INPUT/OUTPUT
state. Once all 16-bits are read or an abort is initiated the
device begins a new conversion.
The CONVERT state duration is determined by the
LTC2470/LTC2472 conversion time (nominally 4ms or
1ms depending on the selected output rate). Once started,
this operation can not be aborted except by a low power
supply condition (VCC < 2.1V) which generates an internal
power-on reset signal.
After the completion of a conversion, the LTC2470/LTC2472
enters the SLEEP/NAP state and remains there until the
chip select is LOW (CS = LOW). Following this condition,
the ADC transitions into the DATA INPUT/OUTPUT state.
SLEEP/NAP
NO
CS = LOW?
YES
DATA INPUT/OUTPUT
NO
16TH FALLING
EDGE OF SCK
OR
CS = HIGH?
YES
24602 F02
Figure 2. LTC2470/LTC2472 State Transition Diagram
While in the SLEEP/NAP state, when chip select input is
HIGH (CS = HIGH), the LTC2470/LTC2472’s converters are
powered down. This reduces the supply current by approximately 70%. While in the NAP state the reference remains
powered up. The user can power down both the reference
and the converter by enabling the sleep mode during the
DATA INPUT/OUTPUT state. Once the next conversion is
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7
LTC2470/LTC2472
applications information
complete, the SLEEP state is entered and power is reduced
to 2μA (maximum). The reference is powered up once CS
is brought low. The reference startup time is 12ms (if the
reference and compensation capacitor values are both
0.1μF). As the reference and compensation capacitors are
decreased, the startup time is reduced (see Figure 3), but
the transition noise increases (see Figure 4).
Upon entering the DATA INPUT/OUTPUT state, SDO
outputs the sign (D15) of the conversion result. During
this state, the ADC shifts the conversion result serially
through the SDO output pin under the control of the SCK
input pin. There is no latency in generating this data and
the result corresponds to the last completed conversion.
A new bit of data appears at the SDO pin following each
falling edge detected at the SCK input pin and appears
250
200
VCC = 2.7V
TIME (ms)
VCC = 4.1V
50
20
The DATA INPUT/OUTPUT state concludes in one of two
different ways. First, the DATA INPUT/OUTPUT state operation is completed once all 16 data bits have been shifted
out and the clock then goes low. This corresponds to the
16th falling edge of SCK. Second, the DATA INPUT/OUTPUT state can be aborted at any time by a LOW-to-HIGH
transition on the CS input. Following either one of these
two actions, the LTC2470/LTC2472 will enter the CONVERT
state and initiate a new conversion cycle.
15
Power-Up Sequence
VCC = 5.5V
0
–50
0.1
0.01
CAPACITANCE (µF)
1
0.001
24702 F03
Figure 3. Reference Start-Up Time vs VREF and
Compensation Capacitance
25
TRANSITION NOISE (µV RMS)
During the DATA INPUT/OUTPUT state, the LTC2470/
LTC2472 can be programmed to SLEEP or NAP (default)
and the output rate can be updated. Data is shifted into
the device through the SDI pin on the rising edge of SCK.
The input word is 4 bits. If the first bit EN1 = 1 and the
second bit EN2 = 0 the device is enabled for programming.
The following two bits (SPD and SLP) will be written into
the device. SPD is used to select the output rate. If SPD =
0 (Default) the output rate is 208sps and SPD = 1 sets a
833sps output rate. The next bit (SLP) enables the sleep
or nap mode. If SLP = 0 (default) the reference remains
powered up at the end of each conversion cycle. If SLP =
1, the reference powers down following the next conversion cycle. The remaining 12 SDI input bits are ignored
(don’t care).
SDI may also be tied directly to GND or VDD in order to
simplify the user interface. If SDI is tied LOW the output
rate is 208sps and if SDI is tied HIGH the output rate is
833sps. The reference sleep mode is disabled if SDI is
tied to GND or VDD.
150
100
from MSB to LSB. The user can reliably latch this data
on every rising edge of the external serial clock signal
driving the SCK pin.
When the power supply voltage (VCC) applied to the converter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
10
5
0
0.0001
0.001
0.01
0.1
CAPACITANCE (µF)
1
10
24702 F04
Figure 4. Transition Noise RMS vs COMP and
Reference Capacitance
When VCC rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. For proper operation VDD needs
to be restored to normal operating range (2.7V to 5.5V)
24702fb
8
For more information www.linear.com/LTC2470
LTC2470/LTC2472
Applications Information
before the conclusion of the POR cycle. The POR signal
clears all internal registers. Following the POR signal, the
LTC2470/LTC2472 start a conversion cycle and follow the
succession of states shown in Figure 2. The reference
startup time following a POR is 12ms (CCOMP = CREFOUT =
0.1μF). The first conversion following power-up will be
invalid since the reference voltage has not completely
settled. The first conversion following power up can be
discarded using the data abort command or simply read
and ignored. Depending on the value chosen for CCOMP
and CREFOUT, the reference startup can take more than
one conversion period, see Figure 3. If the startup time is
less than 1.2ms (833sps output rate) or 4.8ms (208sps
output rate) then conversions following the first period
are accurate to the device specifications. If the startup
time exceeds 1.2ms or 4.8ms then the user can wait the
appropriate time or use the fixed conversion period as
a startup timer by ignoring results within the unsettled
period. Once the reference has settled, all subsequent
conversion results are valid. If the user places the device
into the sleep mode (SLP = 1, reference powered down)
the reference will require a startup time proportional to
the value of CCOMP and CREFOUT (see Figure 3).
Ease of Use
The LTC2470/LTC2472 data output has no latency, filter
settling delay, or redundant results associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog input voltages requires no
special actions.
The LTC2470/LTC2472 include a proprietary input sampling
scheme that reduces the average input current by several
orders of magnitude when compared to traditional deltasigma architectures. This allows external filter networks
to interface directly to the LTC2470/LTC2472. Since the
average input sampling current is 50nA, an external RC
lowpass filter using 1kΩ and 0.1µF results in
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