LTC2512-24
24-Bit Over-Sampling ADC
with Configurable Flat Passband Digital Filter
FEATURES
n
n
n
n
n
n
n
n
n
n
n
DESCRIPTION
±1ppm INL (Typ)
117dB Dynamic Range (Typ) at 50ksps
108dB Dynamic Range (Typ) at 400ksps
Guaranteed 24-Bits No Missing Codes
Configurable Digital Filter with Synchronization
n Relaxed Anti-Aliasing Filter Requirements
Dual Output 24-Bit SAR ADC
n 24-Bit Digitally Filtered Low Noise Output
n 14-Bit Differential + 8-Bit Common Mode
No Latency Output
Wide Input Common-Mode Range
Guaranteed Operation to 85°C
1.8V to 5V SPI-Compatible Serial I/O
Low Power: 30mW at 1.6Msps
24-Lead 7mm × 4mm DFN Package
The LTC®2512-24 is a low noise, low power, high-performance 24-bit ADC with an integrated configurable digital
filter. Operating from a single 2.5V supply, the LTC251224 features a fully differential input range up to ±VREF,
with VREF ranging from 2.5V to 5.1V. The LTC2512-24
supports a wide common mode range from 0V to VREF
simplifying analog signal conditioning requirements.
The LTC2512-24 simultaneously provides two output
codes: (1) a 24-bit digitally filtered high precision low
noise code, and (2) a 22-bit no latency composite code.
The configurable digital filter reduces measurement noise
by lowpass filtering and down-sampling the stream of
data from the SAR ADC core, giving the 24-bit filtered
output code. The 22-bit composite code consists of a
14-bit code representing the differential voltage and an
8-bit code representing the common mode voltage. The
22-bit composite code is available each conversion cycle,
with no cycle of latency.
APPLICATIONS
n
n
n
n
Seismology
Energy Exploration
Automated Test Equipment (ATE)
High-Accuracy Instrumentation
The digital filter can be easily configured for 4 different
down-sampling factors by pin strapping. The configurations provide a dynamic range of 108dB at 400ksps and
117dB at 50ksps. The digital lowpass filter relaxes the
requirements for analog anti-aliasing. Multiple LTC251224 devices can be easily synchronized using the SYNC pin.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 7705765, 7961132, 8319673, 8576104, 8810443, 9054727,
9231611, 9331709 and Patents pending.
TYPICAL APPLICATION
Integral Nonlinearity
vs Input Voltage
1.8V TO 5V
2.5V
10µF
3
0.1µF
IN+, IN–
ARBITRARY
0V
VREF
DIFFERENTIAL
VREF
VDD
IN+
24-BIT
SAR ADC
CORE
0V
BIPOLAR
VREF
UNIPOLAR
LTC2512-24
PIN SELECTABLE
LOW-PASS
FLAT PASSBAND
DIGITAL FILTER 24-BIT
IN –
0V
0V
DIFFERENTIAL INPUTS IN+/IN– WITH
WIDE INPUT COMMON MODE RANGE
14-BIT
GND
REF
2.5V TO 5.1V
OVDD
MCLK
BUSY
DRL
SDOA
SCKA
RDLA
RDLB
SDOB
SCKB
2
SAMPLE
CLOCK
251224 TA01
47µF
(X7R, 1210 SIZE)
INL ERROR (ppm)
VREF
1
0
–1
–2
–3
–5
–2.5
0
2.5
INPUT VOTLAGE (V)
5
251224f TA01a
251224fa
For more information www.linear.com/LTC2512-24
1
LTC2512-24
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VDD) ...............................................2.8V
Supply Voltage (OVDD) ................................................6V
Reference Input (REF).................................................6V
Analog Input Voltage (Note 3)
IN+, IN– .........................(GND – 0.3V) to (REF + 0.3V)
Digital Input Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3) .......................... (GND – 0.3V) to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2512C-24 ........................................... 0°C to 70°C
LTC2512I-24.........................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
ORDER INFORMATION
TOP VIEW
RDLA 1
RDLB 2
VDD 3
GND 4
IN+ 5
IN– 6
GND 7
REF 8
REF 9
REF 10
SEL0 11
SEL1 12
24 GND
23 GND
22 OVDD
21 BUSY
20 SDOB
19 SCKB
18 SCKA
17 SDOA
16 GND
15 DRL
14 SYNC
13 MCLK
25
GND
DKD PACKAGE
24-LEAD (7mm 4mm) PLASTIC DFN
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC2512-24#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2512CDKD-24#PBF
LTC2512CDKD-24#TRPBF
251224
24-Lead (7mm × 4mm) Plastic DFN
0°C to 70°C
LTC2512IDKD-24#PBF
LTC2512IDKD-24#TRPBF
251224
24-Lead (7mm × 4mm) Plastic DFN
–40°C to 85°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN+
Absolute Input Range (IN+)
(Note 5)
l
–
Absolute Input Range (IN–)
(Note 5)
VIN = VIN+ – VIN–
VIN
VIN+ – VIN– Input Differential Voltage Range
MIN
MAX
UNITS
0
TYP
VREF
V
l
0
VREF
V
l
–VREF
VREF
V
l
0
VREF
V
VCM
Common-Mode Input Range
IIN
Analog Input Leakage Current
10
nA
CIN
Analog Input Capacitance
Sample Mode
Hold Mode
45
5
pF
pF
CMRR
Input Common Mode Rejection Ratio
Filtered Output
VIN+ = VIN– = 4.5VP-P, 2kHz Sine
128
dB
2
251224fa
For more information www.linear.com/LTC2512-24
LTC2512-24
CONVERTER CHARACTERISTICS FOR FILTERED OUTPUT (SDOA)
The l denotes
the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
DF
PARAMETER
CONDITIONS
MIN
Resolution
l
24
No Missing Codes
l
24
Down-sampling Factor
l
4
Transition Noise
DF = 4 (Note 6)
DF = 8 (Note 6)
DF = 16 (Note 6)
DF = 32 (Note 6)
INL
Integral Linearity Error
(Note 7)
l
–3.5
ZSE
Zero-Scale Error
(Note 9)
l
–14
Full-Scale Error
MAX
Bits
32
LSBRMS
LSBRMS
LSBRMS
LSBRMS
±1
3.5
0
14
±7
(Note 9)
l
–100
Full-Scale Error Drift
UNITS
Bits
21
14.9
10.5
7.5
Zero-Scale Error Drift
FSE
TYP
±10
ppm
ppm
ppb/°C
100
±0.05
ppm
ppm/°C
DYNAMIC ACCURACY FOR FILTERED OUTPUT (SDOA)
The l denotes the specifications
which apply over the full operating temperature range, otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 10)
SYMBOL
PARAMETER
CONDITIONS
MIN
DR
Dynamic Range
fIN = 2kHz, VREF = 5V, DF = 4
fIN = 2kHz, VREF = 5V, DF = 8
fIN = 2kHz, VREF = 5V, DF = 16
fIN = 2kHz, VREF = 5V, DF = 32
SINAD
Signal-to-(Noise + Distortion) Ratio
fIN = 2kHz, VREF = 5V, DF = 4
l
103
SNR
Signal-to-Noise Ratio
fIN = 2kHz, VREF = 5V, DF = 4
l
103
THD
Total Harmonic Distortion
fIN = 2kHz, VREF = 5V, DF = 4
fIN = 2kHz, VREF = 2.5V, DF = 4
l
SFDR
Spurious Free Dynamic Range
fIN = 2kHz, VREF = 5V, DF = 4
fIN = 2kHz, VREF = 2.5V, DF = 4
l
TYP
UNITS
108
111
114
117
dB
dB
dB
dB
107
dB
107
–120
–120
dB
–110
dB
dB
120
120
dB
dB
Aperture Delay
500
ps
Aperture Jitter
4
Transient Response
Full-Scale Step
110
MAX
152
psRMS
ns
251224fa
For more information www.linear.com/LTC2512-24
3
LTC2512-24
CONVERTER CHARACTERISTICS FOR NO LATENCY OUTPUT (SDOB)
The l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution:
Differential
Common Mode
l
l
14
8
Bits
Bits
No Missing Codes:
Differential
Common Mode
l
l
14
8
Bits
Bits
Transition Noise
Differential
Common Mode
(Note 6)
INL
Integral Linearity Error
Differential
Common Mode
(Note 7)
DNL
Differential Linearity Error
Differential
Common Mode
1
1
LSBRMS
LSBRMS
±0.2
±0.2
LSB
LSB
±0.2
±0.2
LSB
LSB
–3dB Input Linear Bandwidth
34
MHz
ZSE
Zero Scale Error
Differential
Common Mode
±1
±1
LSB
LSB
FSE
Full Scale Error
Differential
Common Mode
±1
±1
LSB
LSB
REFERENCE INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Notes 4, 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
VREF
Reference Voltage
(Note 5)
l
IREF
Reference Input Current
(Note 11)
l
TYP
2.5
1.5
MAX
UNITS
5.1
V
1.8
mA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
VOL
CONDITIONS
MIN
l
TYP
0.8•OVDD
l
High Level Output Voltage
IO = –500µA
l
Low Level Output Voltage
IO = 500µA
l
l
UNITS
V
l
VIN = 0V to OVDD
MAX
–10
0.2•OVDD
V
10
μA
5
pF
OVDD–0.2
V
0.2
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = OVDD
10
mA
4
–10
10
V
µA
251224fa
For more information www.linear.com/LTC2512-24
LTC2512-24
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VDD
Supply Voltage
OVDD
Supply Voltage
IVDD
IOVDD
IPD
Supply Current
Supply Current
Power Down Mode
1.6Msps Sample Rate
1.6Msps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD + IREF)
PD
Power Dissipation
Power Down Mode
1.6Msps Sample Rate (IVDD)
Conversion Done (IVDD + IOVDD + IREF)
MIN
TYP
MAX
UNITS
l
2.375
2.5
2.625
V
l
1.71
l
l
5.25
V
12
0.4
1
16
350
mA
mA
µA
30
2.5
40
875
mW
µW
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
fSMPL
Maximum Sampling Frequency
(Note 12)
fDRA
Output Data Rate at SDOA
fDRB
Output Data Rate at SDOB
MIN
TYP
MAX
UNITS
l
1.6
Msps
l
400
ksps
(Note 12)
l
1.6
Msps
l
405
tACQ = tCYC – tCONV – tBUSYLH (Note 8)
l
152
ns
l
625
ns
tCONV
Conversion Time
tACQ
Acquisition Time
tCYC
Time Between Conversions
tMCLKH
MCLK High Time
l
20
ns
tMCLKL
Minimum Low Time for MCLK
(Note 13)
l
20
ns
tBUSYLH
MCLK↑ to BUSY↑ Delay
CL = 20pF
l
tDRLLH
MCLK↑ to DRL↑ Delay
CL = 20pF
l
tQUIET
SCKA, SCKB Quiet Time from MCLK↑
(Note 8)
l
10
ns
tSCKA
SCKA Period
(Notes 13, 14)
l
10
ns
tSCKAH
SCKA High Time
l
4
ns
tSCKAL
SCKA Low Time
l
4
ns
tDSDOA
SDOA Data Valid Delay from SCKA↑
CL = 20pF, OVDD = 5.25V
CL = 20pF, OVDD = 2.5V
CL = 20pF, OVDD = 1.71V
l
l
l
tHSDOA
SDOA Data Remains Valid Delay from SCKA↑
CL = 20pF (Note 8)
l
tDSDOADRLL SDOA Data Valid Delay from DRL↓
460
13
18
8.5
8.5
9.5
1
ns
ns
ns
ns
ns
ns
ns
CL = 20pF (Note 8)
l
5
ns
tENAA
Bus Enable Time After RDLA↓
(Note 13)
l
16
ns
tDISA
Bus Relinquish Time After RDLA↑
(Note 13)
l
13
ns
(Notes 13, 14)
tSCKB
SCKB Period
l
10
ns
tSCKBH
SCKB High Time
l
4
ns
tSCKBL
SCKB Low Time
l
4
ns
tDSDOB
SDOB Data Valid Delay from SCKB↑
CL = 20pF, OVDD = 5.25V
CL = 20pF, OVDD = 2.5V
CL = 20pF, OVDD = 1.71V
l
l
l
tHSDOB
SDOB Data Remains Valid Delay from SCKB↑
CL = 20pF (Note 8)
l
8.5
8.5
9.5
1
ns
ns
ns
ns
251224fa
For more information www.linear.com/LTC2512-24
5
LTC2512-24
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
tDSDOBBUSYL
SDOB Data Valid Delay from BUSY↓
CL = 20pF (Note 8)
l
5
ns
tENB
Bus Enable Time After RDLB↓
(Note 13)
l
16
ns
tDISB
Bus Relinquish Time After RDLB↑
(Note 13)
13
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 1.6MHz,
DF = 4.
Note 5: Recommended operating conditions.
Note 6: Transition noise is defined as the noise level of the ADC with IN+
and IN – shorted.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
MIN
TYP
MAX
UNITS
Note 8: Guaranteed by design, not subject to test.
Note 9: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000
0000 0000 and 1111 1111 1111 1111 1111 1111. Full-scale bipolar error
is the worst-case of –FS or +FS untrimmed deviation from ideal first and
last code transitions and includes the effect of offset error.
Note 10: All specifications in dB are referred to a full-scale ±5V input with
a 5V reference voltage.
Note 11: fSMPL = 1.6MHz, IREF varies proportionally with sample rate.
Note 12: fSMPL and fDRB are specified with only shifting out the 14-bit
differential result. Shifting out the 8-bit common-mode result requires
additional I/O time resulting in maximum sampling and output data rates
of 1.42Msps.
Note 13: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 14: tSCKA, tSCKB of 10ns maximum allows a shift clock frequency up
to 100MHz for rising edge capture.
0.8•OVDD
tWIDTH
0.2•OVDD
tDELAY
tDELAY
0.8•OVDD
0.2•OVDD
0.8•OVDD
0.2•OVDD
50%
50%
251224 F01
Figure 1. Voltage Levels for Specifications
6
251224fa
For more information www.linear.com/LTC2512-24
LTC2512-24
TYPICAL PERFORMANCE CHARACTERISTICS
REF = 5V, fSMPL = 1.6Msps, DF = 4, Filtered Output, unless otherwise noted.
Integral Nonlinearity
vs Input Voltage
Differential Nonlinearity
vs Input Voltage
3
Integral Nonlinearity
vs Output Code
3.50
1.0
0.8
2
0.6
1.75
0
–1
INL ERROR (ppm)
0.4
1
DNL (LSB)
INL ERROR (ppm)
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
0.2
0.0
–0.2
–0.4
–1.75
–0.6
–2
0
–0.8
–3
–5
–2.5
0
2.5
INPUT VOTLAGE (V)
–1.0
5
–5
–2.5
0
2.5
INPUT VOLTAGE (V)
DC Histogram, DF = 4
σ = 16.9
16000
12000
12000
12000
COUNTS
16000
4000
8000
4000
–100
0
CODE
100
0
–200
200
20000
0
σ = 8.47
0
CODE
100
0
–50
200
AMPLITUDE (dBFS)
12000
8000
4000
0
CODE
25
50
251224 G07
25
50
251224 G06
0
SNR = 111dB
–20
–40
–60
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
0
CODE
128k Point FFT fSMPL = 1.6Msps,
fIN = 2kHz, DF = 8
SNR = 108dB
–20
–25
251224 G05
–40
–25
8000
128k Point FFT fSMPL = 1.6Msps,
fIN = 2kHz, DF = 4
16000
0
–50
–100
251224 G04
DC Histogram, DF = 32
σ = 12.02
4000
AMPLITUDE (dBFS)
0
–200
COUNTS
DC Histogram, DF = 16
20000
16000
COUNTS
COUNTS
σ = 23.9
5
251224 G03
DC Histogram, DF = 8
20000
8000
–2.5
0
2.5
INPUT VOLTAGE (V)
251224 G02
251224 G01
20000
–3.50
–5
5
ARBITRARY DRIVE
IN+/IN– SWEPT 0V to 5V
0
50
100
150
FREQUENCY (kHz)
200
251224 G08
–180
0
25
50
75
FREQUENCY (kHz)
100
251224 G09
251224fa
For more information www.linear.com/LTC2512-24
7
LTC2512-24
TYPICAL PERFORMANCE CHARACTERISTICS
REF = 5V, fSMPL = 1.6Msps, DF = 4, Filtered Output, unless otherwise noted.
0
SNR = 114dB
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
0
12.5
25
37.5
FREQUENCY (kHz)
–180
50
0
5
251224 G10
10
15
FREQUENCY (kHz)
20
125
25
120
18.75
115
12.5
110
6.25
105
25
251224 G11
Frequency Response,
DF = 4, 8, 16, 32
SNR, SINAD vs Input Frequency
110
10
–10
109
SNR
107
SINAD
–30
–40
–50
–60
–70
106
8
16
DOWN SAMPLING FACTOR (DF)
32
0
251224 G12
SNR, SINAD vs Input Level,
fIN = 2kHz
109
SNR, SINAD (dBFS)
MAGNITUDE (dB)
–20
108
110
DF = 4
DF = 8
DF = 16
DF = 32
0
4
TRANSITION NOISE (LSB)
–40
–60
SNR, SINAD (dBFS)
Dynamic Range, Transition Noise
vs DF
SNR = 117dB
–20
–40
–180
128k Point FFT fSMPL = 1.6Msps,
fIN = 2kHz, DF = 32
DYNAMIC RANGE (dB)
0
128k Point FFT fSMPL = 1.6Msps,
fIN = 2kHz, DF = 16
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
SNR
108
SINAD
107
106
–80
–90
25
50
75
INPUT FREQUENCY (kHz)
SNR, SINAD (dBFS)
–115
FSMPL/8
FSMPL/4
3FSMPL/16
SINAD
104
103
3.5
4
4.5
REFERENCE VOLTAGE (V)
–30
251224 G14
THD, Harmonics vs Reference
Voltage, fIN = 2kHz
–20
–10
INPUT LEVEL (dB)
0
251224 G15
Reference Current
vs Reference Voltage
2.0
THD
–125
2ND
–130
–135
3RD
–140
3
105
–40
–120
105
102
2.5
FSMPL/16
251224 G13
SNR
106
0
FREQUENCY (Hz)
SNR, SINAD vs Reference
Voltage, fIN = 2kHz
107
8
–100
100
REFERENCE CURRENT (mA)
108
0
THD, HARMONICS (dBFS)
105
5
251224 G16
–145
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
5
251224 G17
1.5
1.0
0.5
2.5
3
3.5
4
4.5
REFERENCE VOLTAGE (V)
5
251224 G18
251224fa
For more information www.linear.com/LTC2512-24
LTC2512-24
TYPICAL PERFORMANCE CHARACTERISTICS
REF = 5V, fSMPL = 1.6Msps, DF = 4, Filtered Output, unless otherwise noted.
110
SNR, SINAD vs Temperature,
fIN = 2kHz
–120
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
THD, Harmonics
vs Temperature, fIN = 2kHz
INL vs Temperature
4
3
SNR
108
SINAD
107
106
–122
2
THD
INL ERROR (ppm)
THD, HARMONICS (dBFS)
SNR, SINAD (dBFS)
109
–124
2ND
–126
3RD
MAX INL
1
0
–1
MIN INL
–2
–128
–3
105
–40
–15
10
35
TEMPERATURE (°C)
60
85
–130
–40
–15
251224 G19
Full-Scale Error vs Temperature
10
35
TEMPERATURE (°C)
60
–4
–40
85
Offset Error vs Temperature
10
–15
251224 G20
10
35
TEMPERATURE (°C)
60
85
251224 G21
Supply Current vs Temperature
15
5
–FS
0
+FS
–5
12
3
SUPPLY CURRENT (mA)
ZERO–SCALE ERROR (ppm)
5
2
1
0
–1
–2
IVDD
IOVDD
IREF
9
6
3
–3
–4
–15
10
35
TEMPERATURE (°C)
60
–5
–40
85
–15
251224 G22
10
35
TEMPERATURE (°C)
40
85
0
–40
251224 G23
–15
10
35
TEMPERATURE (°C)
60
85
251224 G24
200
175
30
20
10
0
–40
60
Common Mode Rejection
vs Input Frequency
Shutdown Current vs Temperature
CMR (dB)
–10
–40
POWER–DOWN CURRENT (µA)
FULL–SCALE ERROR (ppm)
4
150
125
100
–15
10
35
TEMPERATURE (°C)
60
85
75
0.0001
0.001
251224 G25
0.01
0.1
FREQUENCY (MHz)
1
4
251224 G26
251224fa
For more information www.linear.com/LTC2512-24
9
LTC2512-24
TYPICAL PERFORMANCE CHARACTERISTICS
REF = 5V, fSMPL = 1.6Msps, No Latency 14-Bit Output, unless otherwise noted.
No Latency Differential Output
128k Point FFT, fIN = 2kHz
No Latency Differential Output DNL
vs Input Voltage
No Latency Differential Output INL
vs Input Voltage
0.5
–20
0.4
0.4
–40
0.3
0.3
INL ERROR (LSB)
SNR = 86dB
–60
–80
–100
0.1
0
–0.1
–120
–0.3
–140
–0.4
–160
–0.5
0
200
400
600
FREQUENCY (kHz)
800
DNL ERROR (LSB)
0.5
0
AMPLITUDE (dBFS)
TA = 25°C, VDD = 2.5V, OVDD = 2.5V, VCM = 2.5V,
0.1
0
–0.1
–0.3
–0.4
–5
251224 G27
–2.5
0
2.5
INPUT VOTLAGE (V)
5
251224 G28
–0.5
–5
–2.5
0
2.5
INPUT VOTLAGE (V)
5
251224 G29
No Latency Common Mode Output
128k Point FFT, fIN = 2kHz
0
SNR = 48dB
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–120
10
0
200
400
600
FREQUENCY (kHz)
800
251224 G30
251224fa
For more information www.linear.com/LTC2512-24
LTC2512-24
PIN FUNCTIONS
RDLA (Pin 1): Read Low Input A (Filtered Output).
When RDLA is low, the serial data output A (SDOA) pin
is enabled. When RDLA is high, SDOA pin is in a highimpedance state. Logic levels are determined by OVDD.
DRL (Pin 15): Data Ready Low Output. A falling edge
on this pin indicates that a new filtered output code is
available in the output register of SDOA. Logic levels are
determined by OVDD.
RDLB (Pin 2): Read Low Input B (No Latency Output).
When RDLB is low, the serial data output B (SDOB) pin
is enabled. When RDLB is high, SDOB pin is in a highimpedance state. Logic levels are determined by OVDD.
SDOA (Pin 17): Serial Data Output A (Filtered Output).
The filtered output code appears on this pin (MSB first)
on each rising edge of SCKA. The output data is in 2’s
complement format. Logic levels are determined by OVDD.
VDD (Pin 3): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10µF
ceramic capacitor.
SCKA (Pin 18): Serial Data Clock Input A (Filtered Output).
When SDOA is enabled, the filtered output code is shifted
out (MSB first) on the rising edges of this clock. Logic
levels are determined by OVDD.
GND (Pins 4, 7, 16, 23, 24): Ground.
IN+ (Pin 5): Positive Analog Input.
IN– (Pin 6): Negative Analog Input.
REF (Pins 8, 9, 10): Reference Input. The range of REF
is 2.5V to 5.1V. This pin is referred to the GND pin and
should be decoupled closely to the pin with a 47µF ceramic
capacitor (X7R, 1210 size, 10V rating).
SEL0, SEL1 (Pins 11, 12): Down-Sampling Factor Select
Input 0, Down-Sampling Factor Select Input 1. Selects the
down-sampling factor for the digital filter. Down-sampling
factors of 4, 8, 16 and 32 are selected for [SEL1 SEL0]
combinations of 00, 01, 10 and 11 respectively. Logic
levels are determined by OVDD.
MCLK (Pin 13): Master Clock Input. A rising edge on this
input powers up the part and initiates a new conversion.
Logic levels are determined by OVDD.
SYNC (Pin 14): Synchronization Input. A pulse on this
input is used to synchronize the phase of the digital filter.
Logic levels are determined by OVDD.
SCKB (Pin 19): Serial Data Clock Input B (No Latency
Output). When SDOB is enabled, the no latency output
code is shifted out (MSB first) on the rising edges of this
clock. Logic levels are determined by OVDD.
SDOB (Pin 20): Serial Data Output B (No Latency Output).
The 22-bit no latency composite output code appears on
this pin (MSB first) on each rising edge of SCKB. The
output data is in 2’s complement format. Logic levels are
determined by OVDD.
BUSY (Pin 21): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
OVDD (Pin 22): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND (Pin 23) close to the pin with
a 0.1µF capacitor.
GND (Exposed Pad Pin 25): Ground. Exposed pad must
be soldered directly to the ground plane.
251224fa
For more information www.linear.com/LTC2512-24
11
LTC2512-24
FUNCTIONAL BLOCK DIAGRAM
VDD = 2.5V
REF = 5V
OVDD = 1.8V TO 5V
LTC2512-24
IN+
+
24-BIT
SAR ADC
IN–
SCKA
24
DIGITAL
FILTER
SDOA
RDLA
SPI
PORT
–
SCKB
14
SDOB
RDLB
MCLK
BUSY
DRL
CONTROL LOGIC
SYNC
SEL0
SEL1
GND
251224f FBD
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
RDLA = RDLB = 0
MCLK
CONVERT
DRL
SCKA
DA22
DA20
DA18
DA16
DA14
DA12
DA10
DA8
DA6
DA4
DA2
DA0
WA6
WA4
WA2
WA0
SDOA
CONVERT
DA23
DA21
DA19
DA17
DA15
DA13
DA11
DA9
DA7
DA5
DA3
DA1
WA7
WA5
WA3
WA1
POWER DOWN AND ACQUIRE
BUSY
SCKB
DB12
DB10
DB8
DB6
DB4
DB2
DB0
CB6
CB4
CB2
CB0
SDOB
DB13
12
DB11
DB9
DB7
DB5
DB3
DB1
CB7
CB5
CB3
CB1
251224 TD
251224fa
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
The LTC2512-24 is a low noise, low power, high-performance 24-bit ADC with an integrated configurable digital
filter. Operating from a single 2.5V supply, the LTC251224 features a fully differential input range up to ±VREF,
with VREF ranging from 2.5V to 5.1V. The LTC2512-24
supports a wide common mode range from 0V to VREF
simplifying analog signal conditioning requirements.
The LTC2512-24 simultaneously provides two output
codes: (1) a 24-bit digitally filtered high precision low
noise code, and (2) a 22-bit no latency composite code.
The configurable digital filter reduces measurement noise
by lowpass filtering and down-sampling the stream of
data from the SAR ADC core, giving the 24-bit filtered
output code. The 22-bit composite code consists of a
14-bit code representing the differential voltage and an
8-bit code representing the common mode voltage. The
22-bit composite code is available each conversion cycle,
with no cycle of latency.
The digital filter can be easily configured for 4 different
down-sampling factors by pin strapping. The configurations provide a dynamic range of 108dB at 400ksps and
117dB at 50ksps. The digital lowpass filter relaxes the
requirements for analog anti-aliasing. Multiple LTC251224 devices can be easily synchronized using the SYNC pin.
CONVERTER OPERATION
The LTC2512-24 operates in two phases. During the
acquisition phase, a 24-bit charge redistribution capacitor
D/A converter (CDAC) is connected to the IN+ and IN– pins
to sample the analog input voltages. A rising edge on the
MCLK pin initiates a conversion. During the conversion
phase, the 24-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing the
sampled inputs with binary-weighted fractions of the reference voltage (e.g. VREF/2, VREF/4 … VREF/16777216). At
the end of conversion, the CDAC output approximates the
sampled analog input. The ADC control logic then passes
the 24-bit digital output code to the digital filter for further
processing. A 14-bit code representing the differential
voltage and an 8-bit code representing the common mode
voltage are combined to form a 22-bit composite code.
The 22-bit composite code is available each conversion
cycle, without any cycle of latency.
TRANSFER FUNCTION
The LTC2512-24 digitizes the full-scale differential voltage
of 2× VREF into 224 levels, resulting in an LSB size of 596nV
with a 5V reference. The ideal transfer function is shown
in Figure 2. The output data is in 2’s complement format.
OUTPUT CODE (TWO’S COMPLEMENT)
OVERVIEW
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
FSR = +FS – –FS
1LSB = FSR/16777216
100...000
–FSR/2
–1 0V 1
FSR/2 – 1LSB
LSB
LSB
INPUT VOLTAGE (V)
251224 F02
Figure 2. LTC2512-24 Transfer Function
ANALOG INPUT
The LTC2512-24 samples the voltage difference (IN+
– IN–) between its analog input pins over a wide common mode input range while attenuating unwanted signals common to both input pins by the common-mode
rejection ratio (CMRR) of the ADC. Wide common mode
input range coupled with high CMRR allows the IN+/IN–
analog inputs to swing with an arbitrary relationship to
each other, provided each pin remains between GND and
VREF. This unique feature of the LTC2512-24 enables it
to accept a wide variety of signal swings, including traditional classes of analog input signals such as pseudodifferential unipolar, pseudo-differential true bipolar, and
fully differential, thereby simplifying signal chain design.
In the acquisition phase, each input sees approximately
45pF (CIN) from the sampling circuit in series with 40Ω
(RON) from the on-resistance of the sampling switch.
The inputs draw a current spike while charging the CIN
251224fa
For more information www.linear.com/LTC2512-24
13
LTC2512-24
APPLICATIONS INFORMATION
REF
RON
40Ω
IN+
REF
IN–
RON
40Ω
requires wider bandwidth than LPF1. This filter also helps
minimize the noise contribution from the buffer. A buffer
amplifier with a low noise density must be selected to
minimize degradation of SNR.
CIN
45pF
CIN
45pF
BIAS
VOLTAGE
LPF2
6800pF
SINGLE-ENDEDINPUT SIGNAL LPF1
10Ω
500Ω
251224 F03
Figure 3. The Equivalent Circuit for the Differential
Analog Input of the LTC2512-24
6600pF
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high impedance inputs of the LTC2512-24 without gain error. A high
impedance source should be buffered to minimize settling
time during acquisition and to optimize ADC linearity. For
best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2512-24. The amplifier provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the ADC inputs.
Noise and Distortion
The noise and distortion of an input buffer amplifier and
other supporting circuitry must be considered since they
add to the ADC noise and distortion. Noisy input signals
should be filtered prior to the buffer amplifier with a low
bandwidth filter to minimize noise. The simple one-pole
RC lowpass filter (LPF1) shown in Figure 4 is sufficient
for many applications.
A coupling filter network (LPF2) should be used between
the buffer and ADC input to minimize disturbances
reflected into the buffer from sampling transients. Long
RC time constants at the analog inputs will slow down
the settling of the analog inputs. Therefore, LPF2 typically
14
10Ω
SINGLE-ENDED- 6800pF
BW = 48kHz TO-DIFFERENTIAL
DRIVER
BW = 1.2MHz
capacitors during acquisition. During conversion, the analog inputs draw only a small leakage current.
IN+
3300pF
LTC2512-24
IN–
251224 F04
Figure 4. Filtering Input Signal
High quality capacitors and resistors should be used in
the RC filters since these components can add distortion. NPO and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self-heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
Input Currents
An important consideration when coupling an amplifier to
the LTC2512-24 is in dealing with current spikes drawn by
the ADC inputs at the start of each acquisition phase. The
ADC inputs may be modeled as a switched capacitor load
of the drive circuit. A drive circuit may rely partially on
attenuating switched-capacitor current spikes with small
filter capacitors CFILT placed directly at the ADC inputs,
and partially on the driver amplifier having sufficient bandwidth to recover from the residual disturbance. Amplifiers
optimized for DC performance may not have sufficient
bandwidth to fully recover at the ADC’s maximum conversion rate, which can produce nonlinearity and other
errors. Coupling filter circuits may be classified in three
broad categories:
251224fa
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
Fully Settled – This case is characterized by filter time
constants and an overall settling time that is consider-ably
shorter than the sample period. When acquisition begins,
the coupling filter is disturbed. For a typical first order RC
filter, the disturbance will look like an initial step with an
exponential decay. The amplifier will have its own response
to the disturbance, which may include ringing. If the input
settles completely (to within the accuracy of the LTC251224), the disturbance will not contribute any error.
Fully Averaged – If the coupling filter capacitors (CFILT) at
the ADC inputs are much larger than the ADC’s sample
capacitors (45pF), then the sampling glitch is greatly
attenuated. The driving amplifier effectively only sees
the average sampling current, which is quite small. At
1.6Msps, the equivalent input resistance is approximately
14k (as shown in Figure 5), a benign resistive load for
most precision amplifiers. However, resistive voltage division will occur between the coupling filter’s DC resistance
and the ADC’s equivalent (switched-capacitor) input resistance, thus producing a gain error.
The input leakage currents of the LTC2512-24 should
also be considered when designing the input drive circuit,
because source impedances will convert input leakage
currents to an added input voltage error. The input leakage currents, both common mode and differential, are
typically extremely small over the entire operating temperature range. Figure 6 shows the input leakage currents
over temperature for a typical part.
14k
(REQ)
CFILT>>45pF
14k
(REQ)
IN–
BIAS
VOLTAGE
CFILT>>45pF
REQ =
1
fSMPL • 45pF
251224 F05
Figure 5. Equivalent Circuit for the Differential
Analog Input of the LTC2512-24 at 1.6Msps
10
VIN = VREF
7
INPUT LEAKAGE (nA)
Partially Settled – In this case, the beginning of acquisition causes a disturbance of the coupling filter, which then
begins to settle out towards the nominal input voltage.
However, acquisition ends (and the conversion begins)
before the input settles to its final value. This generally
produces a gain error, but as long as the settling is linear,
no distortion is produced. The coupling filter’s response
is affected by the amplifier’s output impedance and other
parameters. A linear settling response to fast switchedcapacitor current spikes can NOT always be assumed for
precision, low bandwidth amplifiers. The coupling filter
serves to attenuate the current spikes’ high-frequency
energy before it reaches the amplifier.
LTC2512-24
IN+
4
DIFFERENTIAL
1
COMMON
–2
–5
–40
–15
10
35
TEMPERATURE (°C)
60
85
251224 F06
Figure 6. Common Mode and Differential Input
Leakage Current Over Temperature
Let RS1 and RS2 be the source impedances of the differential input drive circuit shown in Figure 7, and let IL1
and IL2 be the leakage currents flowing out of the ADC’s
analog inputs. The differential voltage error, VE, due to the
leakage currents can be expressed as:
VE =
RS1 +RS2
I +I
• (IL1 –IL2 ) + (RS1 –RS2 ) • L1 L2
2
2
The common mode input leakage current, (IL1 + IL2)/2, is
typically extremely small (Figure 6) over the entire operating temperature range and common mode input voltage
range. Thus, any reasonable mismatch (below 5%) of the
source impedances RS1 and RS2 will cause only a negligible
error. The differential leakage current is also typically very
small, and its nonlinear component is even smaller. Only
the nonlinear component will impact the ADC’s linearity.
251224fa
For more information www.linear.com/LTC2512-24
15
LTC2512-24
APPLICATIONS INFORMATION
RS1
IL1
+
VE
–
RS2
settling and good DC linearity with 1.9nV/RT(Hz) inputreferred noise density, enabling it to achieve the full ADC
data sheet SNR and THD specifications as shown in the
FFT plot in Figure 8b.
IN+
LTC2512-24
IN–
IL2
0
251224 F07
SNR = 107dB
–20
Figure 7. Source Impedances of a Driver and
Input Leakage Currents of the LTC2512-24
AMPLITUDE (dBFS)
–40
For optimal performance, it is recommended that the
source impedances, RS1 and RS2, be between 5Ω and
50Ω and with 1% tolerance. For source impedances in
this range, the voltage and temperature coefficients of
RS1 and RS2 are usually not critical. The guaranteed AC
and DC specifications are tested with 5Ω source impedances, and the specifications will gradually degrade with
increased source impedances due to incomplete settling.
–60
–80
–100
–120
–140
–160
–180
–200
50
The wide common mode input range and high CMRR
of the LTC2512-24 allow the analog input pins, IN+ and
IN–, to swing with an arbitrary relationship to each other,
provided that each pin remains between VREF and GND.
This unique feature of the LTC2512-24 enables it to accept
a wide variety of signal swings, simplifying signal chain
design.
It is recommended that the LTC2512-24 be driven using
the LT6203 ADC driver configured as two unity gain buffers, as shown in Figure 8a. The LT6203 combines fast
251224 F08b
While the circuit shown in Figure 8a is capable of buffering
single-ended input signals, the circuit shown in Figure 9
is preferable when the single-ended signal reference level
is inherently low impedance and doesn’t require buffering. This circuit eliminates one driver and one lowpass
filter, reducing the part count, power dissipation, and SNR
degradation due to driver noise.
1.8V TO 5.1V
10µF
1/2 LT6203
200
Buffering Single-Ended Analog Input Signals
2.5V
+
100
150
FREQUENCY (kHz)
Figure 8b. 128k Point FFT with fIN = 2kHz,
DF = 4 for Circuit Shown in Figure 8a
Buffering Arbitrary Analog Input Signals
VIN+
0
0.1µF
10Ω
–
VDD
1.2nF
OVDD
IN+
LTC2512-24
1.2nF
–
10Ω
1/2 LT6203
VIN–
+
IN –
REF
2.5V TO 5.1V
GND
47µF
(X7R, 1210 SIZE)
251224 F08a
Figure 8a. Buffering Two Single-Ended Analog Input Signals
16
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For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
2.5V
1.8V TO 5V
10µF
VIN+
0.1µF
VDD
+
10Ω
LT6202
OVDD
IN+
–
LTC2512-24
1.2nF
IN –
GND
REF
2.5V TO 5.1V
47µF
(X7R, 1210 SIZE)
251224 F09
Figure 9. Buffering Single-Ended Signals
8V
LT5400-4
1k
1k
1k
5V
0V
VIN+
6800pF
0.1µF
VREF/2
1k
–5V
VOCM
30.1Ω
+
LTC6363
–
0.1µF
30.1Ω
0.1µF
IN+
6800pF
IN–
6800pF
–3V
251224 F10a
Figure 10a. Buffering and Converting a ±5V True Bipolar Input Signal to a Fully Differential Input
Maximizing the SNR Using Fully Differential Input
Drive
In order to maximize the SNR, the input signal swing must
be maximized. A fully differential signal with a commonmode of VREF/2 maximizes the input signal swing. The
circuit in Figure 8a is capable of buffering such a signal.
If the input signal does not have a common-mode of
VREF/2 or is single-ended, the LTC6363 differential amplifier may be used in conjunction with the LT5400-4 precision resistors to produce a fully differential signal with a
common-mode of VREF/2. Figure 10a shows the LTC6363
buffering, level-shifting and performing a single-ended to
differential conversion on a ±5V single-ended true bipolar
input signal. The FFT in Figure 10b shows that near data
sheet performance is obtained with this driver solution.
Though not shown here, the LTC6363 may also be configured to amplify or attenuate a signal to match the full
scale input range of the LTC2512-24.
Driving DC Signals
While the DC specifications of the LTC2512-24 are excellent, the digital filter, having a wide passband and low
passband ripple, is optimized for AC applications. The
digital filter of the LTC2512-24 improves the dynamic
range to 117dB with DF = 32. The LTC2508-32 has
digital filters with much lower bandwidths, leading to
greater noise suppression. Using the digital filter on the
LTC2508-32 with DF = 16384 leads to a dynamic range
of 146dB. This makes the LTC2508-32 a better choice
for digitizing DC inputs.
251224fa
For more information www.linear.com/LTC2512-24
17
LTC2512-24
APPLICATIONS INFORMATION
0
SNR = 107dB
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–140
–160
–180
–200
0
50
100
150
FREQUENCY (kHz)
200
251224 F10b
Figure 10b. 128k Point FFT with fIN = 2kHz,
DF = 4 for Circuit Shown in Figure 10a
ADC REFERENCE
An external reference defines the input range of the
LTC2512-24. A low noise, low temperature drift reference
is critical to achieving the full data sheet performance
of the ADC. Analog Devices offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and high
accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2512-24. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications.
When choosing a bypass capacitor for the LTC6655-5, the
capacitor’s voltage rating, temperature rating, and package size should be carefully considered. Physically larger
capacitors with higher voltage and temperature ratings
tend to provide a larger effective capacitance, better filtering the noise of the LTC6655-5, and consequently facilitating a higher SNR. Therefore, we recommend bypassing
the LTC6655-5 with a 47μF ceramic capacitor (X7R, 1210
size, 10V rating) close to the REF pin.
The REF pin of the LTC2512-24 draws charge (QCONV)
from the 47μF bypass capacitor during each conversion
cycle. The reference replenishes this charge with an
average current, IREF = QCONV/tCYC. The current drawn
from the REF pin, IREF, depends on the sampling rate and
output code. If the LTC2512-24 continuously samples
a signal at a constant rate, the LTC6655-5 will keep the
deviation of the reference voltage over the entire code
span to less than 0.5ppm.
When idling, the REF pin on the LTC2512-24 draws only
a small leakage current (< 1μA). In applications where
a burst of samples is taken after idling for long periods
as shown in Figure 11, IREF quickly goes from approximately 0μA to a maximum of 1mA at 1.6Msps. This step in
average current drawn causes a transient response in the
reference that must be considered, since any deviation in
the reference output voltage will affect the accuracy of the
output code. In applications where the transient response
of the reference is important, the fast settling LTC6655-5
reference is also recommended.
Reference Noise
The dynamic range of the ADC will increase approximately
3dB for every 2× increase in the down-sampling factor
(DF). The SNR should also improve as a function of DF in
the same manner. For large input signals near full-scale,
however, any reference noise will limit the improvement
of the SNR as DF increases, because any noise on the REF
pin will modulate around the fundamental frequency of the
input signal. Therefore, it is critical to use a low-noise reference, especially if the input signal amplitude approaches
full-scale. For small input signals, the dynamic range will
improve as described earlier in this section.
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
MCLK
IDLE
PERIOD
IDLE
PERIOD
Figure 11. MCLK Waveform Showing Burst Sampling
18
For more information www.linear.com/LTC2512-24
251224 F11
251224fa
LTC2512-24
APPLICATIONS INFORMATION
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2512-24 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Dynamic Range
The dynamic range is the ratio of the RMS value of a
full scale input to the total RMS noise measured with
the inputs shorted to VREF/2. The dynamic range of the
LTC2512-24 with DF = 4 is 108dB which improves by 3dB
for every 2× increase in the down-sampling factor.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 12 shows that the LTC2512-24 achieves
a typical SINAD of 108dB at a 1.6MHz sampling rate with
a 2kHz input, and DF = 4.
0
SNR = 108dB
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–140
–160
–180
0
50
100
150
FREQUENCY (kHz)
200
251224 F12
Figure 12. 128k Point FFT Plot of LTC2512-24
with DF = 4, fIN = 2kHz and fSMPL = 1.6MHz
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the
frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as:
THD= 20LOG
V22 + V32 + V42 +!+ VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2512-24 has two power supply pins: the 2.5V
power supply (VDD), and the digital input/output interface
power supply (OVDD). The flexible OVDD supply allows the
LTC2512-24 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems.
Power Supply Sequencing
The LTC2512-24 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2512-24 has
a power-on-reset (POR) circuit that will reset the LTC251224 at initial power-up or whenever the power supply voltage drops below 1V. Once the supply voltage re-enters
the nominal supply voltage range, the POR will re initialize
the ADC. No conversions should be initiated until 200μs
after a POR event to ensure the re-initialization period has
ended. Any conversions initiated before this time will produce invalid results.
Signal-to-Noise Ratio (SNR)
TIMING AND CONTROL
The signal-to-noise ratio (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components except the first
five harmonics and DC. Figure 12 shows that the LTC2512-24
achieves an SNR of 108dB when sampling a 2kHz input at a
1.6MHz sampling rate with DF = 4.
MCLK Timing
A rising edge on MCLK will power up the LTC2512-24 and
start a conversion. Once a conversion has been started,
further transitions on MCLK are ignored until the conversion is complete. For best results, the falling edge
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19
LTC2512-24
APPLICATIONS INFORMATION
of MCLK should occur within 40ns from the start of the
conversion, or after the conversion has been completed.
For optimum performance, MCLK should be driven by a
clean low jitter signal. Converter status is indicated by the
BUSY output which remains high while the conversion
is in progress. Once the conversion has completed, the
LTC2512-24 powers down and begins acquiring the input
signal for the next conversion.
Digital Filtering
The input to the LTC2512-24 is sampled at a rate fSMPL,
and digital words DADC(n) are transmitted to the digital
filter at that rate. Noise from the 24-bit SAR ADC core is
distributed uniformly in frequency from DC to fSMPL/2.
Figure 15 shows the frequency spectrum of DADC(n) at
the output of the SAR ADC core. In this example, the
bandwidth of interest fB is a small fraction of fSMPL/2.
Internal Conversion Clock
16
SUPPLY CURRENT (mA)
The LTC2512-24 has internal timing circuity that is
trimmed to achieve a maximum conversion time of 460ns.
With a maximum sample rate of 1.6Msps, a minimum
acquisition time of 152ns is guaranteed without any external adjustments.
Auto Power Down
The LTC2512-24 automatically powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of MCLK.
During power-down, data from the last conversion can be
clocked out. To minimize power dissipation during powerdown, disable SDOA, SDOB and turn off SCKA, SCKB. The
auto power-down feature will reduce the power dissipation of the LTC2512-24 as the sampling rate is reduced.
Since power is consumed only during a conversion, the
LTC2512-24 remains powered down for a larger fraction of the conversion cycle (tCYC) at lower sample rates,
thereby reducing the average power dissipation which
scales with the sampling rate as shown in Figure 13.
DECIMATION FILTERS
Many ADC applications use digital filtering techniques
to reduce noise. An FPGA or DSP is typically needed to
implement a digital filter. The LTC2512-24 features an
integrated decimation filter that provides 4 selectable digital filtering functions without any external hardware, thus
simplifying the application solution. Figure 14 shows the
LTC2512-24 digitally filtered output signal path, wherein
the output DADC(n) of the 24-bit SAR ADC core is passed
on to the integrated decimation filter.
20
IVDD
IOVDD
IREF
12
8
4
0
0
0.4
0.8
1.2
SAMPLING RATE (Msps)
1.6
251224 F13
Figure 13. Power Supply Current of
the LTC2512-24 vs Sampling Rate
INTEGRATED DECIMATION FILTER
24-BIT DADC(n)
SAR ADC
CORE
VIN
DIGITAL
FILTER
D1(n)
DOWN
SAMPLER
DOUT(k)
251224 F14
Figure 14. LTC2512-24 Digitally Filtered Output Signal Path
DADC
fB
fSMPL/2
251224 F15
Figure 15. Frequency Spectrum of SAR ADC Core Output
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APPLICATIONS INFORMATION
DC to half the sampling frequency (a.k.a. the Nyquist frequency). An input signal whose bandwidth exceeds the
Nyquist frequency, when sampled, will experience distortion due to an effect called “Aliasing”.
D1
DIGITAL FILTER CUTOFF FREQUENCY
fSMPL/2
fB
251224 F16
Figure 16. Frequency Spectrum of Digital Filter Core Output
The digital filter integrated in the LTC2512-24 suppresses
out-of-band noise power, thereby lowering overall noise
and increasing the dynamic range (DR). The lower the filter bandwidth, the lower the noise, and the higher the DR.
Figure 16 shows the corresponding frequency spectrum of
D1(n) at the output of the digital filter, where noise beyond
the cutoff frequency is suppressed by the digital filter.
When aliasing, frequency components greater than the
Nyquist frequency undergo a frequency shift and appear
within the Nyquist bandwidth. Figure 17 illustrates aliasing in the time domain. The solid line shows a sinusoidal input signal of a frequency greater than the Nyquist
frequency (fO/2). The circles show the signal sampled
at fO. Note that the sampled signal is identical to that of
sampling another sinusoidal input signal of a lower frequency shown with the dashed line. To avoid aliasing, it
is necessary to band limit an input signal to the Nyquist
bandwidth before sampling. A filter that suppresses
spectral components outside the Nyquist bandwidth is
called an “Anti-Aliasing Filter”(AAF).
Down-Sampling
INPUT SIGNAL
SAMPLED SIGNAL
(ALIASED)
The output data rate of the digital filter is reduced by a
down-sampler without causing spectral interference in
the bandwidth of interest.
The down-sampler reduces the data rate by passing every
DF th sample to the output, while discarding all other samples. The sampling frequency fO at the output of the down
sampler is the ratio of fSMPL and DF, i.e., fO = fSMPL/DF.
The LTC2512-24 enables the user to select DF according to a desired bandwidth of interest. The four available
configurations can be selected by pin strapping pins SEL0
and SEL1. Table 1 summarizes the different decimation
filter configurations and properties.
Aliasing
The maximum bandwidth that a signal being sampled can
have and be accurately represented by its samples is the
Nyquist bandwidth. The Nyquist bandwidth ranges from
251224 F17
Figure 17. Time Domain View of Aliasing
Anti-Aliasing Filters
Figure 18 shows a typical signal chain including a lowpass AAF and an ADC sampling at a rate of fO. The AAF
rejects input signal components exceeding fO/2, thus
avoiding aliasing. If the bandwidth of interest is close
to fO/2, then the AAF must have a very steep roll-off. The
complexity of the analog AAF increases with the steepness of the roll-off, and it may be prohibitive if a very
steep filter is required.
Table 1. Properties of Filters in LTC2512-24
SEL1:SEL0
00
01
10
11
DOWN SAMPLING FACTOR
(DF)
4
8
16
32
–3dB BANDWIDTH WHEN
fSMPL = 1.6MHz
133kHz
66.7kHz
33.3kHz
16.7kHz
OUTPUT DATA RATE (ODR)
WHEN fSMPL = 1.6MHz
400ksps
200ksps
100ksps
50ksps
DYNAMIC RANGE
108dB
111dB
114dB
117dB
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Alternatively, a simple low-order analog filter in combination with a digital filter can be used to create a mixedmode equivalent AAF with a very steep roll-off. A mixedmode filter implementation is shown in Figure 19 where
an analog filter with a gradual roll-off is followed by the
LTC2512-24 sampling at a rate of fSMPL = DF • fO. The
LTC2512-24 has an integrated digital filter at the output
of the ADC core. The equivalent AAF, HEQ(f), is the product
of the frequency responses of the analog filter H1(f) and
f0
ANTI-ALIASING FILTER
VIN
DOUT (k)
AT fO(sps)
ADC
f0/2
f0
251224 F18
Figure 18. ADC Signal Chain with AAF
digital filter H2(f), as shown in Figure 20. The digital filter
provides a steep roll-off, allowing the analog filter to have
a relatively gradual roll-off.
The digital filter in the LTC2512-24 operates at the ADC
sampling rate fSMPL and suppresses signals at frequencies exceeding fO/2. The frequency response of the digital filter H2(f) repeats at multiples of fSMPL, resulting in
unwanted passbands at each multiple of fSMPL. The analog filter should be designed to provide adequate suppression of the unwanted passbands, such that HEQ(f)
has only one passband corresponding to the frequency
range of interest. Larger DF settings correspond to less
bandwidth of the digital filter, allowing for the analog filter
to have a more gradual roll-off. A simple first- or secondorder analog filter will provide adequate suppression for
most systems.
fSMPL = DF • fO
LTC2512-24
ANALOG FILTER
DOWN-SAMPLER
DIGITAL FILTER
H1
H2
fSMPL – f0/2
VIN
f0/2
ADC
CORE
IMAGE
D1 (n)
fSMPL – f0/2
f0/2
fSMPL
DOUT (k)
AT f0 (sps)
DF
fSMPL
251224 F19
Figure 19. Mixed-Mode Filter Signal Chain
H1
H2
ANALOG FILTER
DIGITAL FILTER
fSMPL – f0/2
f0/2
fSMPL
HEQ
fSMPL – f0/2
f0/2
fSMPL
EQUIVALENT AAF
VIN
TO ADC
f0/2
fSMPL
251224 F20
Figure 20. Mixed-Mode Anti-Aliasing Filter (AAF)
22
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response undergoes a sharp decrease. At fO/2, the stopband begins. There is a minimum of 65dB attenuation
over the entire stopband region for frequencies in the
range of fO/2 to fSMPL – fO/2. The minimum attenuation in
the stopband improves to 80dB over the frequency range
of 2fO/3 to fSMPL – 2fO/3.
Frequency Response of Digital Filters
Figure 21a shows the magnitude of the frequency response
of the digital filter when the LTC2512-24 is configured to
operate with DF = 4 at a sampling rate of fSMPL. In this
case, fO is fSMPL/4. Note that a replica of the passband
occurs at fSMPL and multiples thereof. In each configuration, the digital filter provides a finite impulse response
(FIR) filter with a lowpass amplitude response and linear
phase response.
The FIR filter coefficients of the 4 digital filter configurations are available at http://www.linear.com/docs/55376.
Table 2 lists the length and group delay of each digital
filter’s response.
Figure 21b shows the amplitude response in the frequency range from DC to fO. Labels are shown for four
distinct regions: a low ripple passband, a 3dB passband,
a transition band and a stopband. The low ripple passband
ranges from DC to fO/4 and provides a constant amplitude
(±0.001dB) as shown in Figure 21c. The 3dB passband
ranges from DC to fO/3 where the amplitude response
has dropped by 3dB. The transition band is defined from
fO/3 to fO/2 and is where the magnitude of the amplitude
Table 2. Length of Digital Filter
DOWN-SAMPLING
FACTOR (DF)
4
8
16
32
LENGTH OF DIGITAL FILTER
IMPULSE RESPONSE
(NUMBER OF MCLK PERIODS)
140
280
560
1120
GROUP DELAY
(17.5 OUTPUT
SAMPLES)
43.75µs
87.5µs
175µs
350µs
20
10
0
–10
MAGNITUDE (dB)
–20
HIGHLIGHTED AREA
SHOWN IN FIGURE 21B
–30
–40
–50
–60
–70
–80
–90
–100
0
f
O
f
/2
f
SMPL
SMPL
FREQUENCY (Hz)
251224 F21a
Figure 21a. Magnitude of Frequency Response of Digital Filter with DF = 4
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LTC2512-24
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20
TRANSITION BAND
3dB PASSBAND
10
STOPBAND
LOW RIPPLE
PASSBAND
0
–10
HIGHLIGHTED AREA
SHOWN IN FIGURE 21C
MAGNITUDE (dB)
–20
–30
65dB
80dB
–40
–50
–60
–70
–80
–90
–100
0
f /4
O
f /3
O
f /2
O
2f /3
f
O
FREQUENCY (Hz)
O
251224 F21b
Figure 21b. Highlighted Portion of Frequency Response from Figure 21a
0.002
0.001dB
MAGNITUDE (dB)
0.001
0
–0.001
–0.001dB
–0.002
0
FREQUENCY (Hz)
f /4
O
251224 F21c
Figure 21c. Low Ripple Passband Portion of Frequency Response from Figure 21b
24
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LTC2512-24
APPLICATIONS INFORMATION
Settling Time and Group Delay
DIGITAL INTERFACE
The length of each digital filter’s impulse response determines its settling time. Linear phase filters exhibit constant delay time versus input frequency (that is, constant
group delay). Group delay of the digital filter is defined to
be the delay to the center of the impulse response.
The LTC2512-24 features two digital serial interfaces.
Serial interface A is used to read the filtered output data.
Serial interface B is used to read the no latency output
data. Both interfaces support a flexible OVDD supply,
allowing the LTC2512-24 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V
and 3.3V systems.
LTC2512-24 is optimized for low latency, and it provides fast settling. Figure 22 shows the output settling
behavior after a step change on the analog inputs of the
LTC2512-24. The X axis is given in units of output sample
number. The step response is representative for all values
of DF. Full settling is achieved in 35 output samples.
1
0
Analog Step Input Signal
Digital Filter Output D1(n)
LTC2512−24 Output Samples Dout(k)
−2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Output Sample Number
251224 F22
Figure 22. Step Response of LTC2512-24
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LTC2512-24
APPLICATIONS INFORMATION
Filtered Output Data
Distributed Read
Figure 23 shows a typical operation for reading the filtered output data. The I/O register contains filtered output
codes DOUT(k) provided by the decimation filter. DOUT(k)
is updated once in every DF number of conversion cycles.
A timing signal DRL indicates when DOUT(k) is updated.
DRL goes high at the beginning of every DFth conversion, and it goes low when the conversion completes. The
24-bits of DOUT(k) can be read out before the beginning
of the next A/D conversion.
LTC2512-24 enables the user to read out the contents
of the I/O register over multiple conversions. Figure 24
shows a case where one bit of DOUT(k) is read for each
of 24 consecutive A/D conversions, enabling the use of
a much slower serial clock (SCKA). Transitions on the
digital interface should be avoided during A/D conversion
operations (when BUSY is high).
CONVERSION
NUMBER
1
2
DF
DF+1
DF+2
2DF
2DF+1
2DF+2
3DF
MCLK
DF NUMBER OF
CONVERSIONS
DF NUMBER OF
CONVERSIONS
DF NUMBER OF
CONVERSIONS
DRL
FILTERED OUTPUT
REGISTER
DOUT(0)
DOUT(1)
(REGISTER UPDATED ONCE
EVERY DF CONVERSIONS)
DOUT(2)
1 24
DOUT(3)
1 24
1 24
SCKA
251224 F23
Figure 23. Typical Filtered Output Data Operation Timing
DF NUMBER OF CONVERSIONS
CONVERSION
NUMBER 0
1
2
3
23
24
25
DF
DF+1
MCLK
DRL
FILTERED OUTPUT
REGISTER
DOUT(0)
1
2
3
(REGISTER UPDATED ONCE FOR
EVERY DF CONVERSIONS)
DOUT(1)
24
1
SCKA
1 SCKA
1 SCKA
1 SCKA
1 SCKA/CNV
1 SCKA
0 SCKA
24 SCKA
251224 F24
Figure 24. Reading Out Filtered Output Data with Distributed Read
26
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LTC2512-24
APPLICATIONS INFORMATION
Synchronization
The output of the digital filter D1(n) is updated every
conversion, whereas the down-sampler output DOUT(k)
is updated only once every DF number of conversions.
Synchronization is the process of selecting when the output DOUT(k) is updated.
This is done by applying a pulse on the SYNC pin of the
LTC2512-24. The I/O register for DOUT(k) is updated at
each multiple of DF number of conversions after a SYNC
pulse is provided, as shown in Figure 25. A timing signal
DRL indicates when DOUT(k) is updated.
The SYNC function allows multiple LTC2512-24 devices,
operated from the same master clock using a common
CONVERSION
NUMBER
1
2
DF
DF+1
SYNC signal, to be synchronized with each other. This
allows each LTC2512-24 device to update its output register at the same time. Note that all devices being synchronized must operate with the same DF.
Periodic Synchronization
SYNC pulses that reinforce an existing synchronization do
not interfere with normal operation. Figure 26 shows a
case where a SYNC pulse is applied for each DF number of conversions to continually reinforce a synchronization. Figure 26 indicates synchronization windows
when a SYNC pulse may be applied to reinforce the
synchronized operation.
DF+2
2DF
2DF+1
2DF+2
3DF
MCLK
DRL
DF NUMBER
OF CONVERSIONS
SYNC
FILTERED OUTPUT
REGISTER
DF NUMBER
OF CONVERSIONS
DOUT(0)
DF NUMBER
OF CONVERSIONS
DOUT(1)
DOUT(2)
DOUT(3)
251224 F25
Figure 25. Synchronization Using a Single SYNC Pulse
CONVERSION
NUMBER
1
2
DF
DF+1
DF+2
2DF
2DF+1
2DF+2
3DF
3DF+1
MCLK
SYNCHRONIZATION
WINDOW
SYNCHRONIZATION
WINDOW
SYNCHRONIZATION
WINDOW
DRL
SYNC
FILTERED OUTPUT
REGISTER
DOUT(0)
DOUT(1)
DOUT(2)
DOUT(3)
251224 F26
Figure 26. Synchronization Using a Periodic SYNC Pulse
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LTC2512-24
APPLICATIONS INFORMATION
Self-Correcting Synchronization
No Latency Output Data
Figure 27 shows a case where an unexpected glitch on
MCLK causes an extra A/D conversion to occur. This extra
conversion alters the update instants for DOUT(k). The
applied periodic SYNC pulse reestablishes the desired
synchronization and self corrects within one conversion
cycle. Note that the digital filter is reset when the synchronization is changed (reestablished).
Figure 28 shows a typical operation for reading the no
latency output data. The no latency I/O register holds a
22-bit composite code R(n) from the most recent sample
taken of inputs IN+ and IN– at the rising edge of MCLK.
The first 14 bits of R(n) represent the input voltage difference (IN+ – IN–), MSB first. The last 8 bits represent
the common-mode input voltage (IN+ + IN–)/2, MSB first.
USER CONVERSION
NUMBER
1
2
DF–1
DF
DF+1
2DF–1
2DF
2DF+1
2DF+2
USER PROVIDED
MCLK
SYNCHRONIZATION
WINDOW
UNWANTED
GLITCH
CORRUPTED
MCLK
EXPECTED DRL
DRL W/O
PERIODIC SYNC
DF NUMBER
OF CONVERSIONS
DF NUMBER
OF CONVERSIONS
PERIODIC SYNC
EXPECTED DRL
CORRECTED DRL
DRL WITH
PERIODIC SYNC
251224 F27
Figure 27. Recovering Synchronization from Unexpected Glitch
1
CONVERSION 0
NUMBER
2
3
4
5
6
MCLK
BUSY
NO-LATENCY
OUTPUT REGISTER
R(0)
1
22
R(1)
1
22
R(2)
1
22
R(3)
1
22
R(4)
1
22
R(5)
1
22
R(6)
1
22
SCKB
251224 F28
Figure 28. Typical Nyquist Output Data Operation Timing
28
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Configuration Word
Table 3. Configuration WORD for Different DF Values
An 8-bit configuration word, WA[7:0], is appended to the
24-bit output code on SDOA to produce a total output
word of 32 bits as shown in Figure 29. The configuration word designates which downsampling factor (DF)
the digital filter is configured to operate with. Clocking
out the configuration word is optional. Table 3 lists the
configuration words for each DF value.
DF
4
8
16
32
WA[7:0]
00100110
00110110
01000110
01010110
MCLK
CONVERT
DRL
SCKA
DA22
DA20
DA18
DA16
DA14
DA12
DA10
DA8
DA6
DA4
DA2
DA0
WA6
WA4
WA2
WA0
SDOA
DA23
DA21
DA19
DA17
DA15
DA13
DA11
DA9
DA7
DA5
DA3
DA1
WA7
WA5
WA3
WA1
251224 F29
Figure 29. Using a Single LTC2512-24 with DF = 4 to Read Filtered Output
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29
LTC2512-24
APPLICATIONS INFORMATION
Filtered Output Data, Single Device, DF = 4
Figure 30 shows an LTC2512-24 configured to operate
with DF = 4. With RDLA grounded, SDOA is enabled and
MSB (DA23) of the output result is available tDSDOBUSYL
after the falling edge of DRL.
MASTER CLK
DIGITAL HOST
MCLK
RDLA
SEL0
SEL1
IRQ
DRL
LTC2512-24
DATA IN
SDOA
SCKA
CLK
RDLA = GND
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
tMCLKH
tMCLKL
MCLK
DRL
tDRLLH
BUSY
tCONV
tBUSYLH
tSCKA
SCKA
1
2
3
SDOA
30
31
32
tSCKAL
tHSDOA
tDSDOADRLL
tQUIET
tSCKAH
tDSDOA
DA31
DA30
DA29
DA1
DA0
251224 F30
Figure 30. Using a Single LTC2512-24 with DF = 4 to Read Filtered Output
30
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APPLICATIONS INFORMATION
Filtered Output Data, Multiple Devices, DF = 4
Figure 31 shows two LTC2512-24 devices configured to
operate with DF = 4, while sharing MCLK, SYNC, SCKA
and SDOA. By sharing MCLK, SYNC, SCKA and SDOA, the
number of required signals to operate multiple ADCs in
parallel is reduced. Since SDOA is shared, the RDLA input
of each ADC must be used to allow only one LTC2512-24
to drive SDOA at a time in order to avoid bus conflicts.
As shown in Figure 31, the RDLA inputs idle high and are
individually brought low to read data out of each device
between conversions. When RDLA is brought low, the
MSB of the selected device is output on SDOA.
SYNC
RDLAX
RDLAY
MASTER CLK
RDLA
SYNC
SEL0
SEL1
MCLK
LTC2512-24
X
SCKA
RDLA
SYNC
SEL0
SEL1
SDOA
DIGITAL HOST
MCLK
LTC2512-24
Y
SCKA
IRQ
DRL
DATA IN
SDOA
CLK
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
tMCLKL
MCLK
DRL
tDRLLH
BUSY
tCONV
tBUSYLH
RDLAX
RDLAY
SYNC
tSCKA
SCKA
1
tENA
SDOA
tHSDOA
tQUIET
tSCKAH
2
3
tSCKAL
tDSDOA
30
31
32
33
34
35
62
63
64
tDISA
Hi-Z
Hi-Z
Hi-Z
DA31X DA30X DA29X
DA1X DA0X
DA31Y DA30Y DA29Y
DA1Y DA0Y
251224 F31
Figure 31. Reading Filtered Output with Multiple Devices Sharing MCLK, SCKA and SDOA
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31
LTC2512-24
APPLICATIONS INFORMATION
No Latency Output Data, Single Device
Figure 32 shows a single LTC2512-24 configured to read
the no latency data out. With RDLB grounded, SDOB is
enabled and MSB (DB13) of the output result is available
tDSDOBBUSYL after the falling edge of BUSY.
MASTER CLK
DIGITAL HOST
MCLK
RDLB
LTC2512-24
SCKB
BUSY
IRQ
SDOB
DATA IN
CLK
CONVERT
RDLB = GND
CONVERT
POWER-DOWN AND ACQUIRE
tCYC
tMCLKH
tMCLKL
MCLK
tACQ = tCYC – tCONV – tBUSYLH
BUSY
tCONV
tACQ
tBUSYLH
tSCKBH
tSCKB
SCKB
1
2
3
SDOB
13
14
tSCKBL
tHSDOB
tDSDOBBUSYL
12
tQUIET
tDSDOB
DB13
DB12
DB11
DB1
DB0
CB7
251224 F32
Figure 32. Using a Single LTC2512-24 to Read No Latency Output
32
251224fa
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
No Latency Output Data, Multiple Devices
Figure 33 shows multiple LTC2512-24 devices configured
to read no latency data out, while sharing MCLK, SCKB
and SDOB. By sharing MCLK, SCKB and SDOB, the number of required signals to operate multiple ADCs in parallel
is reduced. Since SDOB is shared, the RDLB input of each
ADC must be used to allow only one LTC2512-24 to drive
SDOB at a time in order to avoid bus conflicts. As shown
in Figure 33, the RDLB inputs idle high and are individually brought low to read data out of each device between
conversions. When RDLB is brought low, the MSB of the
selected device is output on SDOB.
RDLBX
RDLBY
MASTER CLK
MCLK
RDLB
LTC2512-24
X
SCKB
DIGITAL HOST
MCLK
RDLB
SDOB
LTC2512-24
Y
SCKB
BUSY
IRQ
SDOB
DATA IN
CLK
CONVERT
CONVERT
POWER-DOWN AND ACQUIRE
tMCLKL
MCLK
BUSY
tCONV
tBUSYLH
RDLBX
RDLBY
tSCKB
SCKB
1
tENB
SDOB
tHSDOB
tQUIET
tSCKBH
2
3
tSCKBL
tDSDOB
20
21
22
23
24
25
42
43
44
tDISB
Hi-Z
Hi-Z
DB13X DB12X DB11X
CB1X CB0X
Hi-Z
DB13Y DB12Y DB11Y
CB1Y CB0Y
251224 F33
Figure 33. Reading No Latency Output with Multiple Devices Sharing MCLK, SCKB and SDOB
251224fa
For more information www.linear.com/LTC2512-24
33
LTC2512-24
APPLICATIONS INFORMATION
Filtered Output Data, No Latency Data, Single Device
shared SDO bus at a time in order to avoid bus conflicts.
As shown in Figure 34, the RDLA and RDLB inputs idle
high and are individually brought low to read data from
each serial output when data is available. When RDLA
is brought low, the MSB of the filtered output data from
SDOA is output on the shared SDO bus. When RDLB is
brought low, the MSB of the no latency data output from
SDOB is output on the shared SDO bus.
Figure 34 shows a single LTC2512-24 configured to read
both filtered and no latency output data, while sharing
SDOA with SDOB and SCKA with SCKB. Sharing signals
reduces the total number of required signals to read both
the filtered and no latency data from the ADC. Since SDOA
and SDOB are shared, the RDLA and RDLB inputs of the
ADC must be used to allow only one output to drive the
RDLA
RDLB
MASTER CLK
DIGITAL HOST
MCLK
RDLA
RDLB
IRQ
DRL
LTC2512-24
SDOA
SEL0
SDOB
SEL1 SCKA
SCKB
DATA IN
CLK
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
tMCLKL
MCLK
DRL
tDRLLH
BUSY
tCONV
tBUSYLH
RDLA
RDLB
tSCKA
SCKA/
SCKB
1
2
3
tHSDOA
tENA
SDOA/
SDOB
Hi-Z
tSCKB
tSCKAH
22
23
tSCKAL
25
DA1
DA0
26
CB7
Hi-Z
DB13
27
44
45
46
tSCKBL
tHSDOB
tDSDOB
tENB
tDISA
tDSDOA
DA23 DA22 DA21
24
tQUIET
tSCKBH
DB12 DB11
CB1
CB0
Hi-Z
251224 F34
Figure 34. Reading Filtered Output and No Latency Output by Sharing SCK, and SDO
34
251224fa
For more information www.linear.com/LTC2512-24
LTC2512-24
BOARD LAYOUT
To obtain the best performance from the LTC2512-24, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common
returns for these bypass capacitors are essential to the
low noise operation of the ADC. A single solid ground
plane is recommended for this purpose. When possible,
screen the analog input traces using ground.
Reference Design
For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer to
http://www.linear.com/docs/55376, the evaluation kit for
the LTC2512-24. DC2222A is designed to achieve the full
data sheet performance of the LTC2512-24. Customer
board layout should copy DC2222A grounding, and placement of bypass capacitor as closely as possible.
251224fa
For more information www.linear.com/LTC2512-24
35
LTC2512-24
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2512-24#packaging for the most recent package drawings.
DKD Package
24-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1864 Rev Ø)
0.70 ±0.05
4.50 ±0.05
6.43 ±0.05
2.64 ±0.05
3.10 ±0.05
PACKAGE
OUTLINE
0.50 BSC
0.25 ±0.05
5.50 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
13
R = 0.115
TYP
24
R = 0.05
TYP
0.40 ±0.10
6.43 ±0.10
4.00 ±0.10
2.64 ±0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
12
0.75 ±0.05
0.50 BSC
0.25 ±0.05
5.50 REF
BOTTOM VIEW—EXPOSED PAD
0.200 REF
(DKD24) DFN 0210 REV Ø
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
36
1
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
251224fa
For more information www.linear.com/LTC2512-24
LTC2512-24
REVISION HISTORY
REV
DATE
DESCRIPTION
A
02/18
Corrected order of [SEL1 SEL0] bits
PAGE NUMBER
11
Corrected configuration WORD bits WA[7:0] in Table 3
29
251224fa
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license
is granted
by implication
or otherwise under any patent or patent rights of Analog Devices.
For more
information
www.linear.com/LTC2512-24
37
LTC2512-24
TYPICAL APPLICATION
Buffering and Converting a ±10V True Bipolar Input Signal to a Fully Differential ADC Input
1k
8V
6800pF
0.1µF
2k
0V
–10V
VREF/2
2k
10V
VOCM
30.1Ω
+
LTC6363
–
VIN+
0.1µF
30.1Ω
IN+
5V
2.5V
REF
VDD
6800pF
LTC2512-24
IN–
GND
0.1µF
6800pF
–3V
1k
251224 TA02
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REFERENCES
AMPLIFIERS
38
251224fa
LT 0218 REV A • PRINTED IN USA
www.linear.com/LTC2512-24
For more information www.linear.com/LTC2512-24
ANALOG DEVICES, INC. 2016
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