TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009
CAP-FREE NMOS 400 mA LOW-DROPOUT REGULATORS
WITH REVERSE CURRENT PROTECTION
FEATURES
– Adjustable Output from 1.2 V to 5.5 V
– Custom Outputs Available
1
• Controlled Baseline
– One Assembly
– One Test Site
– One Fabrication Site
• Extended Temperature Performance of
–55°C to 125°C
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree (1)
• Stable With No Output Capacitor or Any Value
or Type of Capacitor
• Input Voltage Range of 1.7 V to 5.5 V
• Ultra-Low Dropout Voltage: 75 mV Typical
• Excellent Load Transient Response—With or
Without Optional Output Capacitor
• New NMOS Topology Delivers Low Reverse
Leakage Current
• Low Noise: 30 µVRMS Typical
(10 Hz to 100 kHz)
• 0.5% Initial Accuracy
• 1% Overall Accuracy Over Line, Load, and
Temperature
• Less Than 1-µA Max IQ in Shutdown Mode
• Thermal Shutdown and Specified Min/Max
Current Limit Protection
• Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.2 V to 3.3 V
2
(1)
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
APPLICATIONS
•
•
•
•
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry Such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
Optional
VIN
Optional
IN
VOUT
OUT
TPS736xx
EN
GND
NR
Optional
Typical Application Circuit for Fixed-Voltage Versions
N/C - No internal connection
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009 .................................................................................................................................................. www.ti.com
DESCRIPTION
The TPS736xx family of low-dropout (LDO) linear voltage regulators uses a new topology—an NMOS pass
element in a voltage-follower configuration. This topology is stable using output capacitors with low ESR and
allows operation without a capacitor. It also provides high reverse blockage (low reverse current) and ground-pin
current that is nearly constant over all values of output current.
The TPS736xx uses an advanced BiCMOS process to yield high precision while delivering low dropout voltages
and low ground-pin current. Current consumption, when not enabled, is under 1 µA and ideal for portable
applications. The low output noise (30 µVRMS with 0.1-µF CNR) is ideal for powering VCOs. These devices are
protected by thermal shutdown and foldback current limit.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT INFORMATION
VOUT (1)
PRODUCT
xx is normal output voltage (for example, 25 = 2.5 V, 01 = Adjustable (2)).
yyy is package designator.
z is package quantity.
TPS736xxMyyyREP
(1)
(2)
Additional output voltages from 1.25 V to 4.3 V in 100 mV increments are available on a quick-turn basis using innovative factory
EEPROM programming. Minimum order quantities apply; contact TI for details and availability.
For fixed 1.2-V operation, tie FB to OUT.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
SOT23 - DBV
–55°C to 125°C
(1)
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
TPS73601MDBVREP
PJRM
TPS73615MDBVREP
T59
TPS73618MDBVREP
T60
TPS73625MDBVREP
T61
TPS73630MDBVREP
T62
TPS73632MDBVREP
T63
TPS73633MDBVREP
T64
SOT223 - DCQ
TPS73601MDCQREP
PWZM
SON - DRB
TPS73601MDRBREP
PMNM
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
TERMINAL FUNCTIONS
NAME
SOT23
(DBV)
PIN NO.
2
SOT223
(DCQ)
PIN NO.
3x3 SON
(DRB)
PIN NO.
DESCRIPTION
IN
1
1
8
GND
2
3, 6
4, Pad
EN
3
5
5
Enable. Driving EN high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. See the Shutdown section under Applications Information for more details.
EN can be connected to IN if not used.
NR
4
4
3
Fixed-voltage versions only. Connecting an external capacitor to this pin bypasses noise
generated by the internal bandgap, reducing output noise to low levels.
FB
4
4
3
Feedback. Adjustable-voltage version only. This is the input to the control loop error
amplifier and is used to set the output voltage of the device.
OUT
5
2
1
Output of the regulator. There are no output capacitor requirements for stability.
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Unregulated input supply
Ground
Copyright © 2006–2009, Texas Instruments Incorporated
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009
16
14
Years estimated life
12
10
8
6
4
2
0
100
A.
110
120
130
Continuous TJ − 5C
140
150
160
TJ = TJA × W + TA (Standard. JESD 51 conditions)
Figure 1. TPS736xxDBVzEP Estimated Device Life at Elevated Temperatures Electromigration Fail Mode
Copyright © 2006–2009, Texas Instruments Incorporated
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3
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009 .................................................................................................................................................. www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
VIN range
–0.3 to 6
V
VEN range
–0.3 to 6
V
–0.3 to 5.5
V
VOUT range
Peak output current
Internally limited
Output short-circuit duration
Indefinite
Continuous total power dissipation
See Dissipation Ratings Table
Junction temperature range, TJ
–55 to 150
°C
Storage temperature range
–65 to 150
°C
2
kV
500
V
Human-Body Model - HBM
ESD rating
(1)
Charged-Device Model - CDM
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS (1)
BOARD
PACKAGE
RθJC
RθJA
DERATING FACTOR
ABOVE TA = 25°C
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
Low-K (2)
DBV
64°C/W
255°C/W
3.9 mW/°C
392 mW
216 mW
157 mW
High-K (3)
DBV
64°C/W
180°C/W
5.6 mW/°C
556 mW
306 mW
222 mW
Low-K (2)
DCQ
15°C/W
53°C/W
18.9 mW/°C
1887 mW
1038 mW
755 mW
(3)
DCQ
15°C/W
45°C/W
22.2 mW/°C
2222 mW
1222 mW
889 mW
DRB
1.2°C/W
40°C/W
25.0 mW/°C
2500 mW
1375 mW
1000 mW
High-K
High-K (3) (4)
(1)
(2)
(3)
(4)
4
See the Thermal Protection section for more information related to thermal design.
The JEDEC Low-K (1s) board design used to derive this data was a 3 in × 3 in, two-layer board with 2 oz copper traces on top of the
board.
The JEDEC High-K (2s2p) board design used to derive this data was a 3 in × 3 in, multilayer board with 1 oz internal power and ground
planes, and 2-oz copper traces on the top and bottom of the board.
Based on preliminary thermal simulations.
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009
ELECTRICAL CHARACTERISTICS
over operating temperature range (TA = –55°C to 125°C), VIN = VOUT(nom) + 0.5 V (1), IOUT = 10 mA, VEN = 1.7 V, and
COUT = 0.1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
VIN
Input voltage range (1)
(2)
VFB
Internal reference (TPS73601)
Accuracy (1)
ΔVOUT%/ΔVIN
TJ = 25°C
Nominal
TJ = 25°C
Over VIN, IOUT,
and T
VOUT + 0.5 V ≤ VIN ≤ 5.5 V,
10 mA ≤ IOUT ≤ 400 mA
Line regulation (1)
ΔVOUT%/ΔIOUT Load regulation
TYP
1.7
Output voltage range
(TPS73601)
VOUT
MIN
MAX
UNIT
5.5
V
1.21
V
VFB
5.5 –
VDO
V
–0.5%
0.5%
1.198
–1%
VO(nom) + 0.5 V ≤ VIN ≤ 5.5 V
1.2
±0.5%
1%
0.01
1 mA ≤ IOUT ≤ 400 mA
0.002
10 mA ≤ IOUT ≤ 400 mA
0.0005
%/V
%/mA
VDO
Dropout voltage (3)
(VIN = VOUT(nom) – 0.1 V)
IOUT = 400 mA
ZO(DO)
Output impedance in dropout
1.7 V ≤ VIN ≤ VOUT + VDO
ICL
Output current limit
VOUT = 0.9 × VOUT(nom)
ISC
Short-circuit current
VOUT = 0 V
450
IREV
Reverse leakage current (4) (–IIN)
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
0.1
IGND
Ground-pin current
IOUT = 10 mA (IQ)
400
550
IOUT = 400 mA
800
1000
ISHDN
Shutdown current (IGND)
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5 V
0.02
1
µA
IFB
FB pin current (TPS73601)
0.1
0.45
µA
PSRR
Power-supply rejection ratio
(ripple rejection)
VN
Output noise voltage
BW = 10 Hz to 100 kHz
tSTR
Startup time
VEN(HI)
Enable high (enabled)
VEN(LO)
Enable low (shutdown)
IEN(HI)
Enable pin current (enabled)
TSD
Thermal shutdown temperature
TA
Operating ambient temperature
(1)
(2)
(3)
(4)
75
200
Ω
0.25
400
650
f = 100 Hz, IOUT = 400 mA
58
f = 10 kHz, IOUT = 400 mA
37
COUT = 10 µF, No CNR
27 × VOUT
COUT = 10 µF, CNR = 0.01 µF
8.5 × VOUT
VOUT = 3 V, RL = 30 Ω, COUT = 1 µF,
CNR = 0.01 µF
800
0
0.02
Shutdown, temperature increasing
160
Reset, temperature decreasing
140
-55
µA
µA
dB
µVRMS
µs
VIN
VEN = 5.5 V
mA
mA
15
600
1.7
mV
V
0.5
V
0.1
µA
°C
125
°C
Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
For VOUT(nom) < 1.6 V, when VIN ≤ 1.6 V, the output locks to VIN and may result in a damaging over-voltage level on the output. To avoid
this situation, disable the device before powering down the VIN.
VDO is not measured for the TPS73615 (VOUT(nom) = 1.5 V) since minimum VIN = 1.7 V.
See the Applications section for more information.
Copyright © 2006–2009, Texas Instruments Incorporated
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TPS73633-EP
5
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009 .................................................................................................................................................. www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
IN
4-MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
Current
Limit
OUT
8 kW
GND
R1
R2
R1 + R2 = 80 kW
NR
Figure 2. Fixed-Voltage Version
Standard 1% Resistor
Values for Common
Output Voltages
IN
VO
4-MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
GND
8 kW
80 kW
R2
1.2 V
Short
Open
1.5 V
23.2 kΩ
95.3 kΩ
1.8 V
28 kΩ
56.2 kΩ
2.5 V
39.2 kΩ
36.5 kΩ
2.8 V
44.2 kΩ
33.2 kΩ
3V
46.4 kΩ
30.9 kΩ
3.3 V
52.3 kΩ
30.1 kΩ
NOTE: VOUT = (R1 + R2)/R2 × 1.204;
R1R2 ≅ 19 kΩ for best
accuracy
OUT
Current
Limit
R1
R1
FB
R2
Figure 3. Adjustable-Voltage Version
6
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009
TYPICAL CHARACTERISTICS
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
LOAD REGULATION
LINE REGULATION
0.20
0.5
Referred to IOUT = 10 mA
0.4
0.2
Change in VOUT (%)
−40°C
25°C
125°C
0.3
Change in VOUT (%)
Referred to VIN = VOUT + 0.5 V at IOUT = 10 mA
0.15
0.1
0
−0.1
−0.2
−0.3
0.10
0
−0.05
−40°C
−0.10
−0.15
−0.4
−0.20
−0.5
0
50
100
150
200
250
300
350
0
400
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VIN − VOUT (V)
IOUT (mA)
Figure 4.
Figure 5.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
100
100
TPS73625DBV
TPS73625DBV
IOUT = 400 mA
125°C
80
80
60
VDO (mV)
VDO (mV)
25°C
125°C
0.05
25°C
40
−40°C
20
50
100
150
200
250
300
40
20
0
0
60
350
0
−50
400
−25
0
25
50
75
100
125
Temperature (°C)
IOUT (mA)
Figure 6.
Figure 7.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
IOUT = 10 mA
16
25
IOUT = 10 mA
All Voltage Versions
Percent of Units (%)
Percent of Units (%)
14
20
15
10
12
10
8
6
4
5
2
0
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
100
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/°C)
Figure 8.
Figure 9.
Copyright © 2006–2009, Texas Instruments Incorporated
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TPS73633-EP
7
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009 .................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
GROUND-PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
900
900
800
800
700
700
600
600
I GND (µA)
1000
IGND (µA)
1000
500
400
300
500
400
300
VIN = 5.5 V
VIN = 4 V
VIN = 2 V
200
100
0
100
200
300
VIN = 5.5 V
VIN = 3 V
VIN = 2 V
200
100
0
0
−50
400
−25
IOUT (mA)
25
50
Temperature (°C)
Figure 10.
Figure 11.
CURRENT LIMIT vs VOUT
(FOLDBACK)
GROUND PIN CURRENT in SHUTDOWN
vs TEMPERATURE
0
75
100
125
1
800
VENABLE = 0.5 V
VIN = VO + 0.5 V
700
ICL
600
500
IGND (µA)
Current Limit (mA)
IOUT = 400 mA
ISC
400
300
0.1
200
100
TPS73633
0.01
−50
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−25
0
VOUT (V)
Figure 12.
100
125
CURRENT LIMIT vs TEMPERATURE
800
800
750
750
700
700
Current Limit (mA)
Current Limit (mA)
75
Figure 13.
CURRENT LIMIT vs VIN
650
600
550
500
450
650
600
550
500
450
400
1.5
8
25
50
Temperature (°C)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
400
−50
−25
VIN (V)
25
50
Temperature (°C)
Figure 14.
Figure 15.
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0
75
100
125
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN – VOUT
40
90
IOUT = 100 mA
COUT = Any
80
35
IOUT = 1 mA
COUT = 10 µF
60
50
30
IOUT = 100 mA
COUT = 1 µF
IOUT = 1 mA
COUT = Any
40
25
PSRR (dB)
Ripple Rejection (dB)
70
IOUT = 1 mA
COUT = 1 µF
20
15
30
20
10
VIN = VOUT + 1 V
IOUT = Any
COUT = 0 µF
100
10k
10
IOUT = 100 mA
COUT = 10 µF
0
0
10
1k
Frequency = 100 kHz
COUT = 10 µF
VOUT = 2.5 V
5
100k
1M
0
10M
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Frequency (Hz)
VIN − VOUT (V)
Figure 16.
Figure 17.
NOISE SPECTRAL DENSITY
CNR = 0 µF
NOISE SPECTRAL DENSITY
CNR = 0.01 µF
1
1.8
2.0
1
eN (µV/√Hz)
eN (µV/√Hz)
COUT = 1 µF
COUT = 0 µF
0.1
COUT = 10 µF
COUT = 1 µF
0.1
COUT = 0 µF
COUT = 10 µF
IOUT = 150 mA
IOUT = 150 mA
0.01
0.01
10
100
1k
10k
100k
10
1k
Frequency (Hz)
Figure 18.
Figure 19.
RMS NOISE VOLTAGE vs COUT
10k
100k
RMS NOISE VOLTAGE vs CNR
60
140
VOUT = 5 V
VOUT = 5 V
120
50
100
VN (RMS)
40
VN (RMS)
100
Frequency (Hz)
VOUT = 3.3 V
30
VOUT = 3.3 V
80
60
20
VOUT = 1.5 V
10
COUT = 0 µF
10 Hz < Frequency < 100 kHz
0
40
VOUT = 1.5 V
20
COUT = 0 µF
10 Hz < Frequency < 100 kHz
0
0.1
1
10
1p
10p
100p
COUT (µF)
CNR (F)
Figure 20.
Figure 21.
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1n
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10n
9
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009 .................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
TPS73633
LOAD TRANSIENT RESPONSE
TPS73633
LINE TRANSIENT RESPONSE
COUT = 0 µF
VIN = 3.8 V
100 mV/tick
IOUT = 400 mA
VOUT
COUT = 1 µF
50 mV/tick
COUT = 0 µF
50 mV/div
VOUT
VOUT
COUT = 10 µF
20 mV/tick
VOUT
COUT = 100 µF
50 mV/div
VOUT
5.5 V
dVIN
400 mA
I OUT
50 mA/tick
10 mA
1 V/div
VIN
10 µs/div
10 µs/div
Figure 22.
Figure 23.
TPS73633
TURNON RESPONSE
TPS73633
TURNOFF RESPONSE
RL = 1 kΩ
COUT = 0 µF
RL = 20 Ω
COUT = 10 µF
VOUT
RL = 20 Ω
COUT = 1 µF
1V/div
= 0.5 V/µs
dt
4.5 V
RL = 20 Ω
COUT = 1 µF
RL = 1 kΩ
COUT = 0 µF
1 V/div
RL = 20 Ω
COUT = 10 µF
VOUT
2V
2V
VEN
1V/div
1 V/div
0V
0V
VEN
100 µs/div
100 µs/div
Figure 24.
Figure 25.
TPS73633
POWER UP/POWER DOWN
IENABLE vs TEMPERATURE
10
6
5
4
VIN
VOUT
IENABLE (nA)
Volts
3
2
1
1
0.1
0
−1
−2
50 ms/div
Figure 26.
10
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0.01
−50
−25
0
25
50
Temperature (°C)
75
100
125
Figure 27.
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP
TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
TPS73601
IFB vs TEMPERATURE
60
160
55
140
50
120
45
100
IFB (nA)
VN (rms)
TPS73601
RMS NOISE VOLTAGE vs CADJ
40
35
80
60
30
VOUT = 2.5 V
COUT = 0 µF
R1 = 39.2 kΩ
10 Hz < Frequency < 100 kHz
25
20
10p
100p
40
20
1n
10n
0
−50
−25
CFB (F)
0
25
50
75
Temperature (°C)
100
Figure 28.
Figure 29.
TPS73601
LOAD TRANSIENT, ADJUSTABLE VERSION
TPS73601
LINE TRANSIENT, ADJUSTABLE VERSION
CFB = 10 nF
R1 = 39.2 kΩ
COUT = 0 µF
200 mV/div
VOUT
COUT = 0 µF
125
VOUT = 2.5 V
CFB = 10 nF
100 mV/div
VOUT
COUT = 10 µF
100 mV/div
COUT = 10 µF
200 mV/div
VOUT
VOUT
4.5 V
3.5 V
400 mA
VIN
10 mA
25 µs/div
Figure 30.
Copyright © 2006–2009, Texas Instruments Incorporated
IOUT
5 µs/div
Figure 31.
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TPS73633-EP
11
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TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009 .................................................................................................................................................. www.ti.com
APPLICATION INFORMATION
The TPS736xx belongs to a family of new-generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS736xx ideal for
portable applications. This regulator family offers a
wide selection of fixed-output voltage versions and an
adjustable-output version. All versions have thermal
and overcurrent protection, including foldback current
limit.
Figure 32 shows the basic circuit connections for the
fixed-voltage models. Figure 33 shows the
connections for the adjustable-output version
(TPS73601). R1 and R2 can be calculated for any
output voltage using the formula in Figure 33. Sample
resistor values for common output voltages are
shown in Figure 3. For the best accuracy, make the
parallel combination of R1 and R2 approximately 19
kΩ.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
Optional output capacitor.
May improve load transient,
noise, or PSRR.
IN
VOUT
OUT
TPS736xx
EN
GND
NR
Optional bypass
capacitor to reduce
output noise
VIN
IN
EN
Optional output capacitor.
May improve load transient,
noise, or PSRR.
OUT
TPS736xx
GND
VOUT
R1
CFB
FB
R2
VOUT =
(R1 + R2)
R1
× 1.204
The TPS736xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
VIN − VOUT < 0.5 V and multiple low ESR capacitors
are in parallel, ringing may occur when the product of
COUT and total ESR drops below 50 Ω. Total ESR
includes all parasitic resistance, including capacitor
ESR and board, socket, and solder-joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance meets this requirement.
Output Noise
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS736xx and
it generates approximately 32 µVRMS (10 Hz to
100 kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
(R1 ) R2)
+ 32 mVRMS
R2
V N + 32 mVRMS
Figure 32. Typical Application Circuit for
Fixed-Voltage Versions
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
supply near the regulator. This counteracts reactive
input sources and improves transient response, noise
rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated, or the device is
located several inches from the power source.
Optional capacitor
reduces output noise
and improves
transient response.
Figure 33. Typical Application Circuit for
Adjustable-Voltage Versions
Input and Output Capacitor Requirements
VOUT
VREF
(1)
Since the value of VREF is 1.2 V, this relationship
reduces to:
mV RMS
V N(mVRMS) + 27
V OUT(V)
V
(2)
ǒ
Ǔ
for the case of no CNR.
An internal 27-kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10 nF, the total noise in the 10-Hz to 100-kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
mV RMS
V N(mVRMS) + 8.5
V OUT(V)
V
(3)
ǒ
Ǔ
for CNR = 10 nF.
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in Figure 21.
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1-µF to 1-µF low ESR capacitor across the input
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009
The TPS73601 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, CFB, from the output to the FB pin
reduces output noise and improves load transient
performance.
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the
dc
dropout.
Values
of
VIN – VOUT above this line ensure normal transient
response.
The TPS736xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250 µV of switching noise
at ~4 MHz; however, charge-pump noise contribution
is negligible at the output of the regulator for most
values of IOUT and COUT.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
the TPS736xx can take a couple of hundred
microseconds to return to the specified regulation
accuracy.
Board Layout Recommendation to Improve
PSRR and Noise Performance
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
Internal Current Limit
The TPS736xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
VOUT drops below 0.5 V. See Figure 12 for a graph of
IOUT vs VOUT.
Shutdown
The enable (EN) pin is active high and is compatible
with standard TTL-CMOS levels. VEN below 0.5 V
(max) turns the regulator off and drops the ground-pin
current to approximately 10 nA. When shutdown
capability is not required, EN can be connected to
VIN. When a pullup resistor is used, and operation
down to 1.8 V is required, use pullup resistor values
below 50 kΩ.
Transient Response
The low open-loop output impedance provided by the
NMOS pass element in a voltage-follower
configuration allows operation without an output
capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
1 µF) from the output pin to ground reduces
undershoot magnitude but increases duration. In the
adjustable version, the addition of a capacitor, CFB,
from the output to the adjust pin also improves the
transient response.
The TPS736xx does not have active pulldown when
the output is overvoltage. This allows applications
that connect higher voltage sources, such as
alternate power supplies, to the output. This also
results in an output overshoot of several percent if
load current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor COUT and the internal/external load
resistance. The rate of decay is given by:
Fixed-voltage version:
dVńdt +
Dropout Voltage
The TPS736xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
C OUT
VOUT
80 kW ø R LOAD
(4)
Adjustable-voltage version:
dVńdt +
C OUT
V OUT
80 kW ø (R 1 ) R 2) ø R LOAD
(5)
For large step changes in load current, the TPS736xx
requires a larger voltage drop from VIN to VOUT to
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Reverse Current
The NMOS pass element of the TPS736xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element,
EN must be driven low before the input voltage is
removed. If this is not done, the pass element may be
left on due to stored charge on the gate.
After EN is driven low, no bias voltage is needed on
any pin for reverse current blocking. Note that
reverse current is specified as the current flowing out
of the IN pin due to voltage applied on the OUT pin.
There is additional current flowing into the OUT pin
due to the 80-kΩ internal resistor divider to ground
(see Figure 2 and Figure 3).
For the TPS73601, reverse current may flow when
VFB is more than 1 V above VIN.
Thermal Protection
Thermal protection disables the output when the
junction temperature rises to approximately 160°C,
allowing the device to cool. When the junction
temperature cools to approximately 140°C, the output
circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to 125°C maximum. To
estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
14
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35°C above the maximum expected ambient
condition of the application. This produces a
worst-case junction temperature of 125°C at the
highest
expected
ambient
temperature
and
worst-case load.
The internal protection circuitry of the TPS736xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS736xx into thermal
shutdown degrades reliability.
Power Dissipation
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are shown in the Power Dissipation Ratings table.
Using heavier copper increases the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also
improves the heatsink effectiveness.
Power dissipation depends on input voltage and load
conditions. Power dissipation is equal to the product
of the output current times the voltage drop across
the output pass element (VIN to VOUT):
P D + (VIN * VOUT) I OUT
(6)
Power dissipation can be minimized by using the
lowest-possible input voltage necessary to ensure the
required output voltage.
Package Mounting
Solder-pad footprint recommendations for the
TPS736xx are presented in application bulletin Solder
Pad Recommendations for Surface-Mount Devices
(AB-132), available from the TI web site at
www.ti.com.
Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP
TPS73633-EP
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
(1)
TPS73601MDBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PJRM
TPS73601MDCQREP
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
PWZM
TPS73601MDRBREP
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
PMNM
TPS73615MDBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T59
TPS73618MDBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T60
TPS73625MDBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T61
TPS73630MDBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T62
TPS73632MDBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T63
TPS73633MDBVREP
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T64
TPS73633MDBVREPG4
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T64
V62/06626-01XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
PJRM
V62/06626-01YE
ACTIVE
SOT-223
DCQ
6
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
PWZM
V62/06626-01ZE
ACTIVE
SON
DRB
8
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
PMNM
V62/06626-02XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T59
V62/06626-03XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T60
V62/06626-04XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T61
V62/06626-05XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T62
V62/06626-06XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T63
V62/06626-07XE
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 125
T64
The marketing status values are defined as follows:
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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