LTC2933
Programmable Hex Voltage
Supervisor with EEPROM
Features
Description
Supervises 6 Power Supplies
nn I2C Adjustable UV and OV Trip Points
nn Guaranteed Threshold Accuracy: ±1%
nn I2C/SMBus Interface
nn Internal EEPROM
nn 256 Programmable Thresholds per Channel
nn Up to Three Range Settings per Channel
nn Two General Purpose Inputs
nn Three General Purpose Inputs/Outputs
nn Programmable Output Delays
nn Supply Voltage Range: 3.4V to 13.9V
nn Supply Voltage Power Sharing from V1 to V4
nn 16-Pin 5mm × 4mm DFN and SSOP Packages
The LTC®2933 is an EEPROM configurable voltage supervisor which can simultaneously monitor up to six power
supply voltage inputs. Each voltage detector offers I2C
programmable over/undervoltage thresholds in various
ranges and increments.
nn
Two general purpose inputs (GPI) can be configured as
programmable manual reset (MR), UV disable (UVDIS),
margin (MARG) or auxiliary comparator (AUXC) inputs.
Three general purpose pins (GPIO) can be configured for
input or output operation. When configured as an input, a
GPIO pin can be mapped to any other GPIO configured as
output. The GPIO pins can also be configured as ALERT
or fault outputs. Faults can be configured with programmable delay-on-release times. Output type and polarity
are also configurable.
Applications
High Availability Computer Systems
Network Servers
nn Telecom Equipment
nn Data Storage Systems
nn
nn
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Status and history registers log faults and can be polled
via the I2C interface. A fault snapshot is also backed up
in internal EEPROM. All parameters are programmable
via the I2C interface. Configuration EEPROM supports
autonomous operation without additional software.
Typical Application
Precision Multiple Power Supply Supervisor
V1 to V6 Threshold Error
vs Temperature
100nF
SYSTEM
V1 V2 V3 V4 V5 V6
220nF
GPIO1
VDD33
MR
LTC2933
GPI1
GPIO2
GPIO3
RST
OV
GND
ASEL
0.5
0
–0.5
ALERT
–1
–50
SDA
GPI2
THRESHOLD ERROR (%)
1
12V
5V
3.3V
DC/DC
CONVERTERS 2.5V
1.8V
1.5V
SCL
2933 TA01a
–25
0
25
50
TEMPERATURE (°C)
75
100
2933 TA01b
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1
LTC2933
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltages:
V1........................................................... –0.3V to 14V
V2, V3, V4................................................. –0.3V to 6V
Input/Output Voltages:
SDA, SCL, GPI1, GPI2, V5, V6................... –0.3V to 6V
GPIO1, GPIO2, GPIO3............................. –0.3V to 14V
VDD33..................................................... –0.3V to 3.6V
ASEL....................................................–0.3V to VDD33
Operating Temperature Range:
LTC2933C................................................. 0°C to 70°C
LTC2933I..............................................–40°C to 85°C
Storage Temperature Range................. –65°C to 150°C*
Maximum Junction Temperature......................... 125°C*
Lead Temperature Range (Soldering, 10 sec):
SSOP Package................................................... 300°C
* See Applications Information section for detailed EEPROM derating
information for junction temperatures in excess of 85°C.
Pin Configuration
TOP VIEW
TOP VIEW
V4
1
16 V5
V4
1
16 V5
V3
2
15 V6
V3
2
15 V6
V2
3
14 GPI1
V2
3
14 GPI1
V1
4
13 GPI2
V1
4
13 GPI2
VDD33
5
12 SCL
5
12 SCL
GND
6
11 SDA
VDD33
GND
6
11 SDA
GPIO3
7
10 GPIO1
GPIO3
7
10 GPIO1
ASEL
8
9
GPIO2
ASEL
8
9
17
GPIO2
DHD16 PACKAGE
16-LEAD (5mm × 4mm) PLASTIC DFN
GN PACKAGE
16-LEAD PLASTIC SSOP NARROW
TJMAX = 125°C, θJA = 41.7°C/W, θJCbottom = 4.3°C/W
EXPOSED PAD (PIN 17) PCB GND CONNECTION OPTIONAL
TJMAX = 125°C, θJA = 110°C/W, θJCtop = 40°C/W
Order Information
http://www.linear.com/product/LTC2933#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2933CDHD#PBF
LTC2933CDHD#TRPBF
2933
16-Lead (5mm × 4mm) Plastic DFN
0°C to 70°C
LTC2933IDHD#PBF
LTC2933IDHD#TRPBF
2933
16-Lead (5mm × 4mm) Plastic DFN
–40°C to 85°C
LTC2933CGN#PBF
LTC2933CGN#TRPBF
2933
16-Lead Plastic SSOP
0°C to 70°C
LTC2933IGN#PBF
LTC2933IGN#TRPBF
2933
16-Lead Plastic SSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
2933fa
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LTC2933
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and V1 = 12V. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Characteristics
Vn
Supply Voltage Range
V1
l
3.4
13.9
V
V2 to V4
l
3.4
5.8
V
3.37
V
VDD33
VDD33 Regulator Output Voltage
IVDD33 = –1mA
l
3.22
IDD
VDD33 Regulator Current Limit
VDD33 = 0V
l
–5.5
InSUP
V1 to V4 Supply Current
Highest Voltage Supplies Current
l
3.3
mA
Writing to EEPROM
0.7
mA
1.5
mA
Voltage Supervisor Characteristics
V1RANGE
V2RANGE to
V6RANGE
V1STEP
V2STEP to
V6STEP
V1ERR
V2ERR to
V6ERR
V1 Monitoring Range
V2 to V6 Monitoring Range
V1 Threshold Programming Step (LSB)
V2 to V6 Threshold Programming Step
(LSB)
V1 Threshold Accuracy
V2 to V6 Threshold Accuracy
Medium Range
l
1
5.8
V
High Range
l
2.5
13.9
V
Precision Range
l
0.2
1.2
V
Low Range
l
0.5
3
V
Medium Range
l
1
5.8
V
Medium Range
20
mV
High Range
50
mV
Precision Range
4
mV
Low Range
10
mV
Medium Range
20
mV
Medium Range, 3V < V1 < 5.8V
Medium Range, 1V < V1 < 3V
l
l
±1.5
±45
%
mV
High Range, 7.5V < V1 < 13.9V
High Range, 2.5V < V1 < 7.5V
l
l
±1.5
±112.5
%
mV
Precision Range, 0.6V < Vn < 1.2V
Precision Range, 0.2V < Vn < 0.6V
l
l
±1
±6
%
mV
Low Range, 1.5V < Vn < 3 V
Low Range, 0.5V < Vn < 1.5V
l
l
±1
±15
%
mV
Medium Range, 3V < Vn < 5.8V
Medium Range, 1V < Vn < 3V
l
l
±1
±30
%
mV
RIN
Vn Input Impedance
Low, Medium and High Range
l
IIN
Vn Input Current
Precision Range, V2 to V4 = 1.2V
Precision Range, V5 to V6 = 1.2V
l
l
tRT
Vn Comparator Response Time
2LSB of Overdrive
20LSB of Overdrive
l
Active Low
l
200
kΩ
100
25
±2
±10
µA
nA
40
µs
µs
Manual Reset Characteristics
tMRI
Input Pulse Width
tMRR
Glitch Rejection
5
µs
1
µs
GPIn Characteristics
VITH
Input Threshold Voltage
ILEAK
Leakage Current
VGPI = 6V
l
IPU
Internal Pull-Up Current
VGPI = 2V
l
l
0.6
1
1.4
V
±2
µA
–5
–15
–30
µA
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3
LTC2933
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and V1 = 12V. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
0.49
0.5
0.51
V
±20
nA
Auxiliary Comparator Characteristics
VACIN
Input Threshold Voltage
IACIN
Input Current
Input Voltage = 0.5V
tACRT
Response Time
40mV Overdrive
l
l
9
µs
GPIOn Characteristics
VOL
Output Low Voltage
VITH
Input Threshold Voltage
ISINK = 3mA
l
l
0.4
V
0.6
1
1.4
V
ILEAK
Leakage Current
VGPIO = 13.9V
l
±2
µA
IPU
Internal Pull-Up Current
VGPIO = 2V
l
–5
–15
–30
µA
tDRO
Programmable Output Delay-on-Release
000b
001b
010b
011b
100b
101b
110b
111b
l
l
l
l
l
l
l
l
1.1
4.5
17
35
143
286
1140
0.001
1.6
6.4
26
51
205
410
1640
0.050
2.2
8.7
34
69
275
550
2200
ms
ms
ms
ms
ms
ms
ms
ms
GPIO1_DELAY_ON_RELEASE,
GPIO2_DELAY_ON_RELEASE and
GPIO3_DELAY_ON_RELEASE
EEPROM Characteristics
Retention
Retention (Notes 5, 6)
l
10
Years
Endurance
Endurance (Notes 5, 6)
l
10,000
Cycles
tEEFS
Fault Storage Time (Note 4)
Backup Fault Storage Operation
10
ms
tEEPR
Programming Time
I2C NACK’s During STORE_USER Operation
100
ms
tEERU
Restore Time
RESTORE_USER Command
1
ms
Digital Inputs SCL, SDA
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
VHYST
Input Hysteresis (Note 4)
ILEAK
Input Leakage Current
2
V
0.8
40
SCL, SDA = GND to 5.5V
l
ISINK = 3mA
–1
V
mV
1
µA
l
0.4
V
VDD33 –
0.4
V
Digital Output SDA
VOL
Digital Output Low Voltage
Digital Input ASEL
VIH
Input High Threshold Voltage
l
VIL
Input Low Threshold Voltage
l
0.4
IIH,IL
High, Low Input Current
ASEL = 0, VDD33
l
–20
20
µA
IFLOAT
Hi-Z Input Current
0.5V < ASEL < VDD33 – 0.5V
l
–10
10
µA
400
kHz
V
Serial Bus Timing Characteristics (Note 3)
fSCL
Serial Clock Frequency
l
10
tLOW
Serial Clock LOW Period
l
1.3
µs
tHIGH
Serial Clock HIGH Period
l
0.6
µs
tBUF
Bus Free Time Between STOP and START
l
1.3
µs
tHD:STA
START Condition Hold Time
l
600
ns
4
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LTC2933
Electrical
Characteristics
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C and V1 = 12V. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
tSU:STA
START Condition Setup Time
l
600
ns
tSU:STO
STOP Condition Setup Time
l
600
ns
tHD:DAT
Data Hold Time
LTC2933 Receiving Data
l
0
LTC2933 Transmitting Data
l
300
l
100
TYP
MAX
UNITS
ns
900
ns
tSU:DAT
Data Setup Time
tSP
Pulse Width of Spike Suppressed
100
ns
tTIMEOUT_BUS
Time Allowed to Complete Any Command
After Which Time SDA Will Be Released
and Command Terminated
32
ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 3: Maximum capacitive load, CB, for SCL and SDA is 400pF. Data and
clock rise time (tr) and fall time (tf) are:
(20 + 0.1 • CB)(ns) < tr < 300ns, and
(20 + 0.1 • CB)(ns) < tf < 300ns
CB = capacitance of one bus line in pF. SCL and SDA external pull-up
voltage, VIO , is 3V < VIO < 5.5V.
ns
Note 4: Guaranteed by design, not directly tested.
Note 5: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 6: EEPROM endurance and retention will be degraded when TJ > 85°C.
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LTC2933
Timing Diagrams
Vn Supervisor Timing
Vn
Vn_THR
tRT
GPIOn
tDRO
2933 TD01
I2C Timing
SDA
tf
tLOW
tr
tSU:DAT
tHD:STA
tf
tSP
tBUF
tr
SCL
S
6
tHD:STA
tHD:DAT
tHIGH
Sr
tSU:STA
tSU:STO
P
S
2933 TD02
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LTC2933
Typical Performance Characteristics
V1 to V4 Supply Current
vs Supply Voltage
400
3.4
VDD33 vs Supply Voltage
3.290
VDD33 vs Temperature
V1
3.3
V1 = 13.9V
3.285
V1 = 10V
V2-V4
340
320
300
3.2
VDD33 (V)
360
VDD33 (V)
SUPPLY CURRENT (µA)
380
3.1
3
6
9
12
SUPPLY VOLTAGE (V)
2.9
15
0
3
6
9
12
SUPPLY VOLTAGE (V)
2933 G01
V1 Comp Response Time
vs Overdrive
15
3.270
–50
–25
2933 G02
0
25
50
TEMPERATURE (°C)
75
100
2933 G03
Aux Comp Response Time
vs Overdrive
V2 to V6 Comp Response Time
vs Overdrive
250
V1 = 3.4V
3.275
3.0
0
V1 = 5V
3.280
50
250
200
150
150
100
V1 = 6V
50
40
V2-V6 = 0.2V
DELAY (µs)
200
DELAY (µs)
DELAY (µs)
V1 = 1V
100
30
20
10
50
V2-V6 = 1.2V
0
5
10
15
OVERDRIVE (LSB)
20
0
25
1.15
NORMALIZED DELAY
GPIO (V)
0
25
20
3
2
1
0
20
40
60
80
OVERDRIVE (mV)
2933 G05
100
120
2933 G06
GPIO Voltage
vs Output Sink Current
200
1.20
4
0
10
15
OVERDRIVE (LSB)
Normalized GPIO Delay
vs Temperature
10k PULL-UP FROM GPIOn TO V1
25°C
5
5
2933 G04
GPIO Pins During Power-Up
6
0
OD = 20LSB
150
1.10
1.05
1.00
0.95
OD = 2LSB
0.90
VOLTAGE (mV)
0
100
50
0.85
0
4
2
V1 (V)
6
2933 G07
0.80
–50
–25
50
25
75
0
TEMPERATURE (°C)
100
125
2933 G08
0
0
0.5
1
2
1.5
2.5
CURRENT (mA)
3
3.5
2933 G09
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7
LTC2933
Pin Functions
ASEL: Ternary I2C Bus Address Select. Can be connected
to ground, VDD33, or left unconnected to select one of
three addresses.
Exposed Pad (DFN Package Only): Ground. The exposed
pad may be left open or connected to device ground.
GND: Ground.
GPIO1, GPIO2, GPIO3: General Purpose Input/Output.
Each GPIO is configurable as either input, open-drain
output, or weak pull-up output. Output polarity is programmable. When configured as outputs, these pins
respond to selectable UV conditions, OV conditions, MR,
auxiliary comparator output, or other input-configured
GPIOn with programmable delay-on-release. These pins
can also be configured as ALERT per SMBus standard.
When configured as inputs, each pin can be mapped to
any other output. These pins have an optional 15µA pullup to VDD33. Unused GPIO pins should be tied to VDD33
or have their pull-up enabled.
GPI1, GPI2: General Purpose Inputs. Configurable as one
of four possibilities (no duplication):
• Manual reset (MR) input, active low, 15µA pull-up to
VDD33
•
UV disable (UVDIS), active low, 15µA pull-up to VDD33.
Outputs ignore UV faults.
V2 to V4: Low Voltage Supervisor Input. Programmable
thresholds from 0.2V to 1.2V in 4mV increments (precision range), from 0.5V to 3V in 10mV increments (low
range) or from 1V to 5.8V in 20mV increments (medium
range). Bypass this pin to ground with a 0.1µF (or greater)
capacitor and apply 3.4V minimum through a low impedance, if used to power the part. The highest voltage on
V1 to V4 is automatically selected as supply voltage. See
the Applications Information section for information on
unused channels.
V5 to V6: Low Voltage Supervisor Input. Programmable
thresholds from 0.2V to 1.2V in 4mV increments (precision
range), from 0.5V to 3V in 10mV increments (low range)
or from 1V to 5.8V in 20mV increments (medium range).
If unused, tie to ground. See the Applications Information
section for information on unused channels.
VDD33: 3.3V Internal Regulator Output. A 220nF capacitor
to ground is required.
PIN NAME
PIN TYPE
PIN (DFN)
PIN (SSOP)
V4
In
1
1
V3
In
2
2
V2
In
3
3
V1
In
4
4
VDD33
Out
5
5
6
6
• Margin (MARG), active low, 15µA pull-up to VDD33.
Outputs ignore both UV and OV faults.
GND
Ground
GPIO3
In/Out
7
7
ASEL
In
8
8
• Hi-Z Auxiliary Comparator (AUXC) Input. Programmable Polarity.
GPIO2
In/Out
9
9
GPIO1
In/Out
10
10
SDA
In/Out
11
11
SCL: I2C Serial Clock (400kHz maximum). Needs external
pull-up resistor.
SDA: I2C Serial Data. Needs external pull-up resistor.
V1: High Voltage Supervisor Input. Programmable thresholds, from 1V to 5.8V in 20mV increments (medium range)
or from 2.5V to 13.9V in 50mV increments (high range).
Bypass this pin to ground with a 0.1µF (or greater) capacitor and apply 3.4V minimum through a low impedance, if
used to power the part. The highest voltage on V1 to V4
is automatically selected as supply voltage. If unused, tie
to ground. See the Applications Information section for
information on unused channels.
8
SCL
In
12
12
GPI2
In
13
13
GPI1
In
14
14
V6
In
15
15
V5
In
16
16
17
N/A
Exposed Pad
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LTC2933
Block Diagram
VDD33
I/O CELL 1
EEPROM
I2C
INTERFACE
CHANNEL 1
V1_THR_HI
REF
DELAY-ONRELEASE
POLARITY
GPIO1
GPIO2
V1_POL_HI
+
MUX
REF
+
V1_THR_LO
GPIO3
I/O CELL 3
–
8-BIT DAC
COMP1_HI
V1_RANGE
SELECT
I/O CELL 2
V1
REF
TIMING
CONFIGURABLE
LOGIC ARRAY
ASEL
SELECT
REGISTERS
SCL
SDA
15µA
POLARITY
INPUT CELL 1
COMP1_LO
VDD33
GND
–
8-BIT DAC
REFERENCE
15µA
V1_POL_LO
V2
CHANNEL 2
V3
CHANNEL 3
V4
AUX
COMP
+
0.5V
+–
GPI1
–
CHANNEL 4
V5
CHANNEL 5
V6
INPUT CELL 2
GPI2
CHANNEL 6
REGULATOR
VDD33
2933 BD
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9
LTC2933
Operation
The LTC2933 can perform the following operations:
Threshold Accuracy
• Accept I2C bus programming commands.
The LTC2933 ±1% threshold accuracy specification
improves the reliability of the system over supervisors
with wider threshold tolerances. A less accurate voltage
supervisor increases the required system voltage margin.
This in turn increases the probability of system malfunction.
• Simultaneously monitor up to six inputs with respect
to programmed fault limits.
• Configure and monitor for OV/UV faults using two
independent comparators per channel.
•
Configure two general purpose inputs as manual reset
(MR), undervoltage disable (UVDIS), margin (MARG)
or auxiliary comparator (AUXC) inputs.
• Configure three general purpose inputs/outputs
(GPIOn) to output faults, inputs from GPIn or from
other GPIOn.
• Independently select each general purpose output
polarity and type (open-drain or weak pull-up).
• Independently select each general purpose output
response delay-on-release (with respect to the moment its condition is internally cleared).
•
Generate interrupt (ALERT) signals in response to any
voltage faults, as well as the logic state of the inputs.
Consider a 5V ±10% supply: it may vary between 4.5V and
5.5V and the circuitry powered by it must operate reliably
within this band. An ideal, perfectly accurate supervisor
would generate a reset at exactly 4.5V. The LTC2933
threshold varies ±1% around the nominal threshold voltage, in the medium range, if the selected value is greater
than 3V. The reset threshold band and the power supply
tolerance bands should not overlap, in order to prevent
false alarms when the power supply actually meets its
specified tolerance band (see Figure 1).
A ±10% threshold is usually set to 11% below the nominal
input voltage, or 4.45V in this example. The threshold is
guaranteed to be within the 4.4V to 4.5V band over temperature. To prevent malfunction, the powered system
must operate reliably down to 4.4V.
• Store register contents to EEPROM.
• Store voltage and timing fault history to EEPROM.
•
SUPPLY TOLERANCE
Restore EEPROM contents into the operating memory,
by I2C command and at power-up.
• Report voltage fault status and history.
• Software write-protect the operating memory.
NOMINAL SUPPLY VOLTAGE
5V
MINIMUM RELIABLE
SYSTEM VOLTAGE
IDEAL SUPERVISOR
THRESHOLD
4.5V
–10%
4.45V
–11%
4.4V
–12%
REGION OF POTENTIAL MALFUNCTION
2933 F01
Figure 1. 1% Threshold Accuracy Improves System Reliability
10
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LTC2933
Operation
I2C Serial Digital Interface
generating SCL to allow the transfer. In the event of an
OV/UV fault, the LTC2933 can be configured to assert the
ALERT output low in order to notify the host.
The LTC2933 communicates with a host (master) using
the I2C serial bus interface. The Timing Diagram shows
the timing relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is
not in use. External pull-up resistors or current sources
are required on these lines.
Slave Address
The LTC2933 can respond to one of three addresses. By
connecting the address ASEL input to VDD33, GND, or by
floating it, the slave address is determined as shown in
the following table. The LTC2933 always responds to the
special addresses.
The LTC2933 is a transmit/receive slave-only device. The
master device must initiate data transfer on the bus by
LTC2933 Slave Address Table
ASEL
0
HI-Z
1
7-Bit Address
0x1C
0x1D
0x1E
8-Bit Address
0x38
0x3A
0x3C
LTC2933 Special Slave Addresses
7-Bit
Address
8-Bit
Address
0x0C
0x19
Alert Response Address. Independent of the ASEL pin.
0x1B
0x36
Global address to which all LTC2933’s will respond. Independent of the ASEL pin.
Description
Communication Protocols
S
Sr
Rd
Wr
A
P
START CONDITION
REPEATED START CONDITION
READ (BIT VALUE OF 1)
WRITE (BIT VALUE OF 0)
ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
STOP CONDITION
MASTER TO SLAVE
SLAVE TO MASTER
Send Byte Format
1
S
1
1
SLAVE ADDRESS Wr A COMMAND CODE A
7
1
1
8
P
Write Word Format
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
8
1
8
1
1
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
Read Word Format
1
S
7
1
1
8
1
SLAVE ADDRESS Wr A COMMAND CODE A
1
7
1
1
Sr SLAVE ADDRESS Rd A
8
1
DATA BYTE LOW
A
1
1
DATA BYTE HIGH A
8
P
2933 F00
1
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11
LTC2933
Operation
Register Command Set
COMMAND
FUNCTION
WRITE_PROTECT
GPI_CONFIG
DESCRIPTION
Contains lock key code and write lock.
Configure GPI2 and GPI1 assignment, GPIOn mapping
and MR internal response.
GPIO1_CONFIG
Configure GPIO1 type, delay-on-release and mapping to
GPIO2, GPIO3.
GPIO2_3_CONFIG Configure GPIO3 type, delay-on-release and mapping
to GPIO1 and GPIO2. Configure GPIO2 type, delay-onrelease and mapping to GPIO1 and GPIO3.
V1_THR
Encode high and low voltage thresholds on channel V1.
V2_THR
Encode high and low voltage thresholds on channel V2.
R/W/S
(See Note)
R/W
R/W
DATA LENGTH COMMAND
(BITS)
BYTE
16
0x00
16
0x01
DEFAULT VALUE
1010_1010_1010_1000b
X001_0000_X000_0000b
R/W
16
0x02
X000_0000_0010_1011b
R/W
16
0x03
0010_1011_0010_1011b
R/W
16
0x04
1101_1110_1010_1000b
R/W
16
0x05
1110_1001_1011_0001b
V3_THR
Encode high and low voltage thresholds on channel V3.
R/W
16
0x06
1000_1011_0110_0101b
V4_THR
Encode high and low voltage thresholds on channel V4.
R/W
16
0x07
1110_1001_1011_0001b
V5_THR
Encode high and low voltage thresholds on channel V5
R/W
16
0x08
1001_1011_0111_0011b
V6_THR
Encode high and low voltage thresholds on channel V6.
R/W
16
0x09
0111_1010_0101_1000b
V1_CONFIG
Encode comparator range, polarity and GPIOn mapping.
R/W
16
0x0A
XXXX_XX00_1000_1001b
V2_CONFIG
Encode comparator range, polarity and GPIOn mapping.
R/W
16
0x0B
XXXX_XX00_1000_1001b
V3_CONFIG
Encode comparator range, polarity and GPIOn mapping.
R/W
16
0x0C
XXXX_XX00_1000_1001b
V4_CONFIG
Encode comparator range, polarity and GPIOn mapping.
R/W
16
0x0D
XXXX_XX01_1000_1001b
V5_CONFIG
Encode comparator range, polarity and GPIOn mapping.
R/W
16
0x0E
XXXX_XX01_1000_1001b
V6_CONFIG
Encode comparator range, polarity and GPIOn mapping.
R/W
16
0x0F
XXXX_XX01_1000_1001b
HISTORY_WORD
CLEAR_HISTORY
STORE_USER
RESTORE_USER
Read the fault history. Read only.
Clear volatile memory history register. Write only.
Store volatile memory to EEPROM. Write only.
Restore volatile memory from EEPROM. Write only.
R
S
S
S
16
0
0
0
0x11
0x1B
0x1C
0x1D
NA
NA
NA
NA
BACKUP_WORD
Read the EEPROM backup of the first fault history.
Read only.
R
16
0x1E
NA
STATUS_WORD
Read the fault status. Read only.
R
16
0x1F
NA
Note: R = read, W = write, S = send byte
12
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LTC2933
Operation
Detailed Command Register Descriptions
WRITE_PROTECT (Command Byte 0x00)
The WRITE_PROTECT command provides the ability to
prevent any write operations into the volatile memory, if
WRITE_LOCK = 1. KEY may be changed when WRITE_LOCK
= 0, or in the same command that sets WRITE_LOCK = 1.
When locked, WRITE_LOCK can only be written to 0 if
KEY matches the existing value in memory. For effective
protection against false writes, KEY should contain at
least one bit set to 1.
Writes to supported commands are ignored when
WRITE_LOCK = 1. All commands may be read regardless
of the WRITE_LOCK bit setting.
WRITE_PROTECT Data Contents
BIT(S)
SYMBOL
PURPOSE
b[15:2]
KEY
Must match against programmed combination in order to deactivate write lock.
Factory default 10_1010_1010_1010b (0x2AAA).
b[1]
Reserved
Ignore
b[0]
WRITE_LOCK
0: Unlocked. Writes to volatile memory are permitted.
1: Locked. Writing to volatile memory is not permitted. To unlock, set WRITE_LOCK = 0 with the
appropriate key.
Factory default 0.
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13
LTC2933
Operation
GPI_CONFIG (Command Byte 0x01)
The GPI_CONFIG command configures internal response
to a manual reset, sets each GPI function, and optionally maps GPI pins configured as Manual Reset (MR) or
Auxiliary Comparator (AUXC) to one or more GPIO pins.
GPI_CONFIG Data Contents
BIT(S)
SYMBOL
OPERATION
b[15]
Reserved
Ignore
b[14]
GPI2_MR_RESPONSE
Effective only if the input GPI2 is MR configured.
0: Disable CLEAR_HISTORY response.
1: Enable CLEAR_HISTORY response on falling edge of GPI2.
Factory default 0.
GPI2_CONFIG
000b: Manual Reset (MR) active low, 15µA pull-up.
001b: Reserved.
010b: Margin (MARG) active low, 15µA pull-up. Overvoltage and undervoltage faults are inhibited.
011b: UV Disable (UVDIS) active low, 15µA pull-up. Undervoltage faults are inhibited.
100b: and 101b: Auxiliary Comparator (AUXC) positive input on GPI2.
110b: and 111b: Auxiliary Comparator (AUXC) negative input on GPI2.
Factory default 010b.
b[10]
MAP_GPI2_TO_GPIO3
0: GPI2 input is not mapped to GPIO3.
1: GPI2 input is mapped to GPIO3 if configured as MR or AUXC.
Factory default 0.
b[9]
MAP_GPI2_TO_GPIO2
0: GPI2 input is not mapped to GPIO2.
1: GPI2 input is mapped to GPIO2 if configured as MR or AUXC.
Factory default 0.
b[8]
MAP_GPI2_TO_GPIO1
0: GPI2 input is not mapped to GPIO1.
1: GPI2 input is mapped to GPIO1 if configured as MR or AUXC.
Factory default 0.
b[13:11]
b[7]
Reserved
Ignore
b[6]
GPI1_MR_RESPONSE
Effective only if the input GPI1 is MR configured.
0: Disable CLEAR_HISTORY response.
1: Enable CLEAR_HISTORY response on falling edge of GPI1.
Factory default 0.
GPI1_CONFIG
000b: Manual Reset (MR) active low, 15µA pull-up.
001b: Reserved.
010b: Margin (MARG) active low, 15µA pull-up. Overvoltage and undervoltage faults are inhibited.
011b: UV Disable (UVDIS) active low, 15µA pull-up. Undervoltage faults are inhibited.
100b: and 101b: Auxiliary Comparator (AUXC) positive input on GPI1.
110b: and 111b: Auxiliary Comparator (AUXC) negative input on GPI1.
Factory default 000b.
b[2]
MAP_GPI1_TO_GPIO3
0: GPI1 input is not mapped to GPIO3.
1: GPI1 input is mapped to GPIO3 if configured as MR or AUXC.
Factory default 0.
b[1]
MAP_GPI1_TO_GPIO2
0: GPI1 input is not mapped to GPIO2.
1: GPI1 input is mapped to GPIO2 if configured as MR or AUXC.
Factory default 0.
b[0]
MAP_GPI1_TO_GPIO1
0: GPI1 input is not mapped to GPIO1.
1: GPI1 input is mapped to GPIO1 if configured as MR or AUXC.
Factory default 0.
b[5:3]
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LTC2933
Operation
GPIO1_CONFIG (Command Byte 0x02)
The GPIO1_CONFIG command configures the GPIO1
mapping, delay-on-release time, output type, and polarity.
If GPIO1_TYPE_AND_POLARITY is configured as ALERT
(100b or 111b), the output is latched and cleared after the
LTC2933 acknowledges the alert response address (see
SMBus protocol), HISTORY_WORD is read, or a CLEAR_
HISTORY command is received. Only one GPIOn pin should
be configured as ALERT. GPIOn_DELAY_ON_RELEASE
does not apply to a GPIOn pin configured as ALERT.
GPIO1_CONFIG Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:8]
Reserved
Ignore
b[7]
MAP_GPIO1_TO_GPIO3
0: GPIO1 input is not mapped to GPIO3.
1: GPIO1 input is mapped to GPIO3.
Factory default 0.
b[6]
MAP_GPIO1_TO_GPIO2
0: GPIO1 input is not mapped to GPIO2.
1: GPIO1 input is mapped to GPIO2.
Factory default 0.
b[5:3]
GPIO1_DELAY_ON_RELEASE
000b: Delay selected is 0.
001b: Delay selected is 1.6ms.
010b: Delay selected is 6.4ms.
011b: Delay selected is 26ms.
100b: Delay selected is 51ms.
101b: Delay selected is 205ms.
110b: Delay selected is 410ms.
111b: Delay selected is 1.64s.
Factory default 101b (205ms).
b[2:0]
GPIO1_TYPE_AND_POLARITY
000b: Active H input.
001b: Active L input.
010b: Active H open-drain output.
011b: Active L open-drain output.
100b: Active L open-drain ALERT output.
101b: Active H, weak pull-up output.
110b: Active L, weak pull-up output.
111b: Active L, weak pull-up ALERT output.
Factory default 011b (Active L open-drain output).
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15
LTC2933
Operation
GPIO2_3_CONFIG (Command Byte 0x03)
The GPIO2_3_CONFIG command configures GPIO2 and
GPIO3 mapping, delay-on-release time, output type, and
polarity. If GPIO2_TYPE_AND_POLARITY is configured as
ALERT (100b or 111b), or GPIO3_TYPE_AND_POLARITY is
configured as ALERT (100b or 111b), the output is latched,
and is cleared after the LTC2933 acknowledges the alert
response address (see SMBus protocol), HISTORY_WORD
is read, or a CLEAR_HISTORY command is received.
Only one GPIOn pin should be configured as ALERT.
GPIOn_DELAY_ON_RELEASE does not apply to a GPIOn
pin configured as ALERT.
GPIO2_3_CONFIG Data Contents
BIT(S)
b[15]
SYMBOL
MAP_GPIO3_TO_GPIO2
b[14]
MAP_GPIO3_TO_GPIO1
b[13:11]
GPIO3_DELAY_ON_RELEASE
b[10:8]
GPIO3_TYPE_AND_POLARITY
b[7]
MAP_GPIO2_TO_GPIO3
b[6]
MAP_GPIO2_TO_GPIO1
b[5:3]
GPIO2_DELAY_ON_RELEASE
b[2:0]
GPIO2_TYPE_AND_POLARITY
16
OPERATION
0: GPIO3 is not mapped into GPIO2.
1: GPIO3 is mapped into GPIO2.
Factory default 0.
0: GPIO3 is not mapped into GPIO1.
1: GPIO3 is mapped into GPIO1.
Factory default 0.
000b: Delay selected is 0.
001b: Delay selected is 1.6ms.
010b: Delay selected is 6.4ms.
011b: Delay selected is 26ms.
100b: Delay selected is 51ms.
101b: Delay selected is 205ms.
110b: Delay selected is 410ms.
111b: Delay selected is 1.64s.
Factory default 101b (205ms).
000b: Active H input.
001b: Active L input.
010b: Active H open-drain output.
011b: Active L open-drain output.
100b: Active L open-drain ALERT output.
101b: Active H, weak pull-up output.
110b: Active L, weak pull-up output.
111b: Active L, weak pull-up ALERT output.
Factory default 011b (Active L open-drain output).
0: GPIO2 is not mapped into GPIO3.
1: GPIO2 is mapped into GPIO3.
Factory default 0.
0: GPIO2 is not mapped into GPIO1.
1: GPIO2 is mapped into GPIO1.
Factory default 0.
000b: Delay selected is 0.
001b: Delay selected is 1.6ms.
010b: Delay selected is 6.4ms.
011b: Delay selected is 26ms.
100b: Delay selected is 51ms.
101b: Delay selected is 205ms.
110b: Delay selected is 410ms.
111b: Delay selected is 1.64s.
Factory default 101b (205ms).
000b: Active H input.
001b: Active L input.
010b: Active H open-drain output.
011b: Active L open-drain output.
100b: Active L open-drain ALERT output.
101b: Active H, weak pull-up output.
110b: Active L, weak pull-up output.
111b: Active L, weak pull-up ALERT output.
Factory default 011b (Active L open-drain output).
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LTC2933
Operation
V1_THR (Command Byte 0x04), V2_THR (0x05),
V3_THR (0x06), V4_THR (0x07),V5_THR (0x08),
V6_THR (0x09)
The Vn_THR command allows the user to specify the high
and low threshold monitoring voltages on each channel.
Vn_THR Data Contents Channels V1 to V6
BIT(S)
SYMBOL
OPERATION
b[15:8]
Vn_THR_HI
The COMPn_HI threshold. See the Applications Information section. Factory default settings of 0xDE, 0xE9, 0x8B, 0xE9,
0x9B, 0x7A correspond to 13.35V, 5.56V, 3.68V, 2.78V, 2.00V and 1.67V for channels V1 to V6, respectively.
b[7:0]
Vn_THR_LO
The COMPn_LO threshold. See the Applications Information section. Factory default settings of 0xA8, 0xB1, 0x65, 0xB1,
0x73, 0x58 correspond to 10.65V, 4.44V, 2.92V, 2.22V, 1.60V and 1.33V for channels V1 to V6, respectively.
V1_CONFIG (Command Byte 0x0A), V2_CONFIG (0x0B),
V3_CONFIG (0x0C), V4_CONFIG (0x0D),
V5_CONFIG (0x0E), V6_CONFIG (0x0F)
The Vn_CONFIG command programs V1 through V6
comparator range, polarity and mapping to GPIOn.
Vn_CONFIG Data Contents Channel V1 to V6
BIT(S)
SYMBOL
OPERATION
b[15:10]
Reserved
Ignore
Vn_RANGE
Channel V1:
00b: High Range.
01b: Medium Range.
10b and 11b: Reserved.
Factory default 00b.
b[9:8]
Channels V2, V3, V4, V5 and V6:
00b: Medium Range.
01b: Low Range.
10b and 11b: Precision Range.
Factory defaults are 00b on V2 to V3 and 01b on V4, V5 and V6.
b[7]
Vn_POL_HI
Controls polarity of COMPn_HI output reported by STATUS_WORD. See STATUS_WORD
description for details.
0: Undervoltage. Indicates a fault when the input voltage is below Vn_THR_HI.
1: Overvoltage. Indicates a fault when the input voltage is above Vn_THR_HI.
Factory default 1.
b[6]
Vn_POL_LO
b[5]
MAP_COMPn_HI_TO_GPIO3
b[4]
MAP_COMPn_HI_TO_GPIO2
b[3]
MAP_COMPn_HI_TO_GPIO1
Controls polarity of COMPn_LO output reported by STATUS_WORD. See STATUS_WORD
description for details.
0: Undervoltage. Indicates a fault when the input voltage is below Vn_THR_LO.
1: Overvoltage. Indicates a fault when the input voltage is above Vn_THR_LO.
Factory default 0.
0: High comparator not mapped to GPIO3.
1: High comparator mapped to GPIO3.
Factory default 0.
0: High comparator not mapped to GPIO2.
1: High comparator mapped to GPIO2.
Factory default 0.
0: High comparator not mapped to GPIO1.
1: High comparator mapped to GPIO1.
Factory default 1.
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17
LTC2933
Operation
Vn_CONFIG Data Contents Channel V1 to V6
BIT(S)
b[2]
SYMBOL
MAP_COMPn_LO_TO_GPIO3
b[1]
MAP_COMPn_LO_TO_GPIO2
b[0]
MAP_COMPn_LO_TO_GPIO1
OPERATION
0: Low comparator not mapped to GPIO3.
1: Low comparator mapped to GPIO3.
Factory default 0.
0: Low comparator not mapped to GPIO2.
1: Low comparator mapped to GPIO2.
Factory default 0.
0: Low comparator not mapped to GPIO1.
1: Low comparator mapped to GPIO1.
Factory default 1.
HISTORY_WORD (Command Byte 0x11)
CLEAR_HISTORY (Command Byte 0x1B)
The HISTORY_WORD command returns two bytes of
information with a summary of the faults since power was
applied or HISTORY_WORD was last cleared. HISTORY_
WORD is located in volatile memory and is automatically
updated each time a fault occurs. HISTORY_WORD is
cleared using the CLEAR_HISTORY command.
The CLEAR_HISTORY command clears all the faults logged
in the volatile HISTORY_WORD register. A manual reset
performs the same operation if GPIn_MR_RESPONSE = 1.
Clearing HISTORY_WORD does not affect the STATUS_
WORD content. Processing of the CLEAR_HISTORY
command typically takes less than 10ms, and the part will
not acknowledge other I2C operations during that time.
HISTORY_WORD Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:13]
Reserved
Ignore
b[12]
V6_HI_LATCHED_FAULT
1: Latched V6_HI_FAULT.
0: No fault.
b[11]
V6_LO_LATCHED_FAULT
1: Latched V6_LO_FAULT.
0: No fault.
b[10]
V5_HI_LATCHED_FAULT
1: Latched V5_HI_FAULT.
0: No fault.
b[9]
V5_LO_LATCHED_FAULT
1: Latched V5_LO_FAULT.
0: No fault.
b[8]
V4_HI_LATCHED_FAULT
1: Latched V4_HI_FAULT.
0: No fault.
b[7]
V4_LO_LATCHED_FAULT
1: Latched V4_LO_FAULT.
0: No fault.
b[6]
V3_HI_LATCHED_FAULT
1: Latched V3_HI_FAULT.
0: No fault.
b[5]
V3_LO_LATCHED_FAULT
1: Latched V3_LO_FAULT.
0: No fault.
b[4]
V2_HI_LATCHED_FAULT
1: Latched V2_HI_FAULT.
0: No fault.
b[3]
V2_LO_LATCHED_FAULT
1: Latched V2_LO_FAULT.
0: No fault.
b[2]
V1_HI_LATCHED_FAULT
1: Latched V1_HI_FAULT.
0: No fault.
b[1]
V1_LO_LATCHED_FAULT
1: Latched V1_LO_FAULT.
0: No fault.
b[0]
Reserved
Ignore
18
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LTC2933
Operation
BACKUP_WORD (Command Byte 0x1E)
STORE_USER (Command Byte 0x1C)
RESTORE_USER (Command Byte 0x1D)
The STORE_USER and RESTORE_USER commands
access nonvolatile EEPROM memory. Once a command
is stored in EEPROM using STORE_USER, it will
be restored to volatile operating memory with the
RESTORE_USER command or when the part powers up.
After the first fault occurs, HISTORY_WORD is written to
EEPROM for backup. Any subsequent BACKUP_WORD
write following a fault is inhibited until the CLEAR_HISTORY
command is issued. BACKUP_WORD can be retrieved
by sending a RESTORE_USER command followed by a
BACKUP_WORD read. BACKUP_WORD can be cleared
in EEPROM by sending a CLEAR_HISTORY command
followed by a STORE_USER command.
BACKUP_WORD Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:13]
Reserved
Ignore
b[12]
V6_HI_STORED_FAULT
1: Stored V6_HI_FAULT.
0: No fault.
b[11]
V6_LO_STORED_FAULT
1: Stored V6_LO_FAULT.
0: No fault.
b[10]
V5_HI_STORED_FAULT
1: Stored V5_HI_FAULT.
0: No fault.
b[9]
V5_LO_STORED_FAULT
1: Stored V5_LO_FAULT.
0: No fault.
b[8]
V4_HI_STORED_FAULT
1: Stored V4_HI_FAULT.
0: No fault.
b[7]
V4_LO_STORED_FAULT
1: Stored V4_LO_FAULT.
0: No fault.
b[6]
V3_HI_STORED_FAULT
1: Stored V3_HI_FAULT.
0: No fault.
b[5]
V3_LO_STORED_FAULT
1: Stored V3_LO_FAULT.
0: No fault.
b[4]
V2_HI_STORED_FAULT
1: Stored V2_HI_FAULT.
0: No fault.
b[3]
V2_LO_STORED_FAULT
1: Stored V2_LO_FAULT.
0: No fault.
b[2]
V1_HI_STORED_FAULT
1: Stored V1_HI_FAULT.
0: No fault.
b[1]
V1_LO_STORED_FAULT
1: Stored V1_LO_FAULT.
0: No fault.
b[0]
Reserved
Ignore
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19
LTC2933
Operation
STATUS_WORD (Command Byte 0x1F)
The STATUS_WORD command returns two bytes
of information with a summary of the current faults.
The STATUS_WORD content is read directly from the
comparators and is a snapshot of the current state.
STATUS_WORD faults may be disabled by setting GPI1_
CONFIG = 010b (MARG), GPI1_CONFIG = 011b (UVDIS),
GPI2_CONFIG = 010b (MARG) or GPI2_CONFIG = 011b
(UVDIS) and asserting the appropriate GPIn pin.
STATUS_WORD Data Contents
BIT(S)
SYMBOL
OPERATION
b[15:13]
Reserved
Ignore
V6_HI_FAULT
V6_POL_HI = 1 (default).
1: Fault (V6 greater than V6_THR_HI).
0: No fault (V6 less than V6_THR_HI).
b[12]
V6_POL_HI = 0.
1: Fault (V6 less than V6_THR_HI).
0: No fault (V6 greater than V6_THR_HI).
b[11]
V6_LO_FAULT
V6_POL_LO = 1.
1: Fault (V6 greater than V6_THR_LO).
0: No fault (V6 less than V6_THR_LO).
V6_POL_LO = 0 (default).
1: Fault (V6 less than V6_THR_LO).
0: No fault (V6 greater than V6_THR_LO).
b[10]
V5_HI_FAULT
V5_POL_HI = 1 (default).
1: Fault (V5 greater than V5_THR_HI).
0: No fault (V5 less than V5_THR_HI).
V5_POL_HI = 0.
1: Fault (V5 less than V5_THR_HI).
0: No fault (V5 greater than V5_THR_HI).
b[9]
V5_LO_FAULT
V5_POL_LO = 1.
1: Fault (V5 greater than V5_THR_LO).
0: No fault (V5 less than V5_THR_LO).
V5_POL_LO = 0 (default).
1: Fault (V5 less than V5_THR_LO).
0: No fault (V5 greater than V5_THR_LO).
b[8]
V4_HI_FAULT
V4_POL_HI = 1 (default).
1: Fault (V4 greater than V4_THR_HI).
0: No fault (V4 less than V4_THR_HI).
V4_POL_HI = 0.
1: Fault (V4 less than V4_THR_HI).
0: No fault (V4 greater than V4_THR_HI).
b[7]
V4_LO_FAULT
V4_POL_LO = 1.
1: Fault (V4 greater than V4_THR_LO).
0: No fault (V4 less than V4_THR_LO).
V4_POL_LO = 0 (default).
1: Fault (V4 less than V4_THR_LO).
0: No fault (V4 greater than V4_THR_LO).
b[6]
V3_HI_FAULT
V3_POL_HI = 1 (default).
1: Fault (V3 greater than V3_THR_HI).
0: No fault (V3 less than V3_THR_HI).
V3_POL_HI = 0.
1: Fault (V3 less than V3_THR_HI).
0: No fault (V3 greater than V3_THR_HI).
20
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LTC2933
Operation
STATUS_WORD Data Contents
BIT(S)
b[5]
SYMBOL
OPERATION
V3_LO_FAULT
V3_POL_LO = 1.
1: Fault (V3 greater than V3_THR_LO).
0: No fault (V3 less than V3_THR_LO).
V3_POL_LO = 0 (default).
1: Fault (V3 less than V3_THR_LO).
0: No fault (V3 greater than V3_THR_LO).
b[4]
V2_HI_FAULT
V2_POL_HI = 1 (default).
1: Fault (V2 greater than V2_THR_HI).
0: No fault (V2 less than V2_THR_HI).
V2_POL_HI = 0.
1: Fault (V2 less than V2_THR_HI).
0: No fault (V2 greater than V2_THR_HI).
b[3]
V2_LO_FAULT
V2_POL_LO = 1.
1: Fault (V2 greater than V2_THR_LO).
0: No fault (V2 less than V2_THR_LO).
V2_POL_LO = 0 (default).
1: Fault (V2 less than V2_THR_LO).
0: No fault (V2 greater than V2_THR_LO).
b[2]
V1_HI_FAULT
V1_POL_HI = 1 (default).
1: Fault (V1 greater than V1_THR_HI).
0: No fault (V1 less than V1_THR_HI).
V1_POL_HI = 0.
1: Fault (V1 less than V1_THR_HI).
0: No fault (V1 greater than V1_THR_HI).
b[1]
V1_LO_FAULT
V1_POL_LO = 1.
1: Fault (V1 greater than V1_THR_LO).
0: No fault (V1 less than V1_THR_LO).
V1_POL_LO = 0 (default).
1: Fault (V1 less than V1_THR_LO).
0: No fault (V1 greater than V1_THR_LO).
b[0]
Reserved
Ignore
2933fa
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21
LTC2933
Applications Information
Power Supply
The LTC2933 is powered from any one of the voltage
monitoring inputs V1 to V4. A virtual diode-OR scheme
selects the highest supply voltage. V1 to V4 should be
driven by a low impedance source for proper operation of
the diode-OR circuit. The LTC2933 generates a regulated
3.3V supply on the VDD33 pin. A 100nF external capacitor
from the highest supply voltage pin (V1 to V4) to GND is
required in order to decouple any supply noise. A 220nF
external capacitor from VDD33 to GND is required to properly
compensate the internal voltage regulator.
Power-Up Condition
When power is applied such that at least one of the supply
inputs V1 to V4 exceeds 3.4V, the part turns on and the
EEPROM contents are loaded into the volatile operating
memory. This operation typically takes less than 200µs.
Power-Down Condition
If all of the supply inputs, V1 to V4, drop below 3.4V, the
internal regulator will start to fall out of regulation. Once
VDD33 falls below the internal undervoltage lockout voltage,
the GPIO outputs will pull low. See the Typical Performance
Characteristics section.
Voltage Threshold Programming
The V1 input has a high range that is based on a full scale
of 2.25V to 15V. The 8-bit programming step size is 50mV.
Some of these thresholds are outside of the 14V abs max
voltage rating of the V1 input. On the high range, threshold
accuracy below 2.5V and above 13.9V is not specified, but
the thresholds are reachable.
The command byte for the voltage threshold can be calculated for the V1 to V6 medium range with the following
equation:
Command Byte = ROUND [50 • (VTH – 0.9)]
Inputs from V2 through V6 have a low range that is based
on a full scale of 0.45V to 3V. The 8-bit programming step
size is 10mV. On the low range, threshold accuracy below
0.5V is not specified, but the thresholds are reachable.
The command byte for the voltage threshold can be
calculated for the V2 to V6 low range with the following
equation:
Command Byte = ROUND [100 • (VTH – 0.45)]
Inputs from V2 through V6 have a precision range that
is based on a full scale of 0.18V to 1.2V. The 8-bit programming step size is 4mV. On the low range, threshold
accuracy below 0.2V is not specified, but the thresholds
are reachable.
The command byte for the voltage threshold can be
calculated for the V2 to V6 precision range with the following equation:
Command Byte = ROUND [250 • (VTH – 0.18)]
Although all six channels have built-in glitch immunity,
100nF bypass capacitors on the V1 to V4 inputs are recommended because the largest V1 to V4 voltage is also
the power supply for the device.
Unused Channels
The command byte for the voltage threshold can be calculated for the V1 high range with the following equation:
The user must connect all unused channel inputs to
ground , program their configuration words (Vn_CONFIG)
to 0x01C0, and program their thresholds (Vn_THR) to
0x0000 in order to avoid false faults.
Command Byte = ROUND [20 • (VTH – 2.25)]
Auxiliary Comparators
Inputs from V1 through V6 have a medium range that is
based on a full scale of 0.9V to 6V. The 8-bit programming step size is 20mV. On the medium range, threshold
accuracy below 1V and above 5.8V is not specified, but
the thresholds are reachable.
Two additional auxiliary comparators can be connected
to the general purpose inputs with either their inverting
or their noninverting input while the other input internally
connects to a 0.5V reference voltage. These low offset, low
drift comparators can be used for additional monitoring
purposes.
22
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LTC2933
Applications Information
If the tap point on an external resistive divider from an
external voltage, VTRIP, to GND (see Figure 2) connects to
the auxiliary comparator input, the trip voltage is:
⎛ R1 ⎞
VTRIP = 0.5V • ⎜1+ ⎟
⎝ R2 ⎠
In a negative voltage application (also shown in Figure 2)
the resistive divider is connected between the negative
voltage being sensed and VDD33, and the trip voltage is:
⎛ R3 ⎞
VTRIP = 0.5V − 2.8V • ⎜ ⎟
⎝ R4 ⎠
The minimum value for R4 is limited by the VDD33 current
sourcing capability at:
3.3V −0.5V
= 2.8kΩ
1mA
not respond to UV type faults. This feature is useful when
power cycling the monitored supply. An internal 15µA
current source pulls UVDIS to VDD33.
Margin
When a GPIn pin is configured as MARG, the input is
active low. When MARG is grounded, the LTC2933 does
not respond to any OV or UV faults. This feature is useful
when margining the monitored supply. An internal 15µA
current source pulls MARG to VDD33.
Outputs
The GPIOn outputs are open-drain, with an optional internal
15µA current source pulling to VDD33 and can tolerate a
pull-up voltage up to 14V.
All faults, GPIn, or other GPIOn inputs mapped to a GPIOn
output are combined with a logical OR function.
Manual Reset
When a GPIn pin is configured as MR, the input is active low. If GPIn_MR_RESPONSE = 1, the HISTORY_
WORD register is cleared when MR is pulled low.
An internal 15µA current source pulls MR to VDD33.
The MR input can also be mapped to a GPIO pin and combined with COMPn_HI and COMPn_LO faults to generate
a system reset signal.
UV Disable
When a GPIn pin is configured as UVDIS, the input is
active low. When UVDIS is grounded, the LTC2933 does
VTRIP
The GPIOn pins have programmable delay-on-release
timing. The GPIOn pin asserts its active state immediately
and de-asserts after the delay-on-release time has elapsed.
Any fault causing a GPIOn pin to assert while its delay-onrelease timer is active will reset the delay-on-release timer.
When a GPIOn indicates an alert, the alert may be cleared
using the standard SMBus Alert Response Address (ARA)
protocol. Alerts may also be cleared by reading (or clearing) HISTORY_WORD unless the condition causing the
alert persists.
LTC2933
VDD33 = 3.3V
LTC2933
R1
R4
+
–
R2
+
–
0.5V
–
+
R3
VTRIP
+
–
0.5V
2933 F02
Figure 2. Auxiliary Comparator Usage
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23
LTC2933
Applications Information
Write Protect Features
where:
When the WRITE_LOCK lock bit is set high, all I2C write
word commands are ignored. This feature protects against
accidental writing. The lock bit may still be written when
the device is write-protected if the provided value for KEY
matches the value in memory.
AF = acceleration factor
Ea = activation energy = 1.5eV
k = 8.617 • 10–5 eV/°k
TUSE = 85°C maximum specified operating temperature
EEPROM
TSTRESS = actual temperature °C
The user may save and restore configuration data to the
operating memory registers at any time with STORE_USER
and RESTORE_USER commands. Upon power-up, userstored data is automatically loaded into the operating
memory. The part ignores I2C commands while performing
EEPROM transactions.
Example: Calculate effect on retention when operating at
a temperature of 95°C for 10 hours.
TSTRESS = 95°C, TUSE = 85°C, AF = 3.74
So, the overall retention of the EEPROM was degraded
by 37.4 hours as a result of operation at a junction temperature of 95°C for 10 hours. Note that the effect of this
overstress is negligible when compared to the overall
EEPROM retention rating of 10 years (87,600 hours) at a
temperature of 85°C.
Nondestructive operation above TA = 85°C is possible,
but may result in a slight degradation of the retention
characteristics. The degradation in EEPROM retention
for temperatures exceeding 85°C can be approximated
by calculating the acceleration factor:
AF = e
Negative Supply Power Monitor
⎡⎛ E ⎞ ⎛
⎞⎤
1
1
−
⎢⎜ a ⎟ • ⎜
⎟⎥
TSTRESS + 273 ⎠⎦
⎣⎝ k ⎠ ⎝ TUSE + 273
Figure 3 illustrates how to configure the LTC2933 to
monitor a negative supply rail. Assume the need to monitor the following supply rails: 1.5V within a ±5% system
specification, 3.3V, 5V and –5V, within a ±10% system
specification. In this example V1 and V2 are not used.
5V
5V
DC/DC
3.3V
3.3V
1.5V
1.5V
–5V
–5V
R1
249k
0.1µF
4.7k
0.22µF
4.7k
SYSTEM
R2
100k
VDD33 V1
V2
V3
V4
V5
V6
RST
GPIO1
GPI1
GPIO2
LTC2933
GPIO3
MR
OV
ALERT
SDA
SCL
GND
ASEL
GPI2
MARG
NOTE: INTERNAL GPI01-3 PULL-UP ENABLED
2933 F03
Figure 3. Negative Power Supply Monitor
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LTC2933
Applications Information
Channel V6 is set to medium range, channels V3 and V4
are set to high range, channel V5 is set to precision range,
and channels V1 and V2 are not used.
Select low range for V6 (0.5V to 3V):
V6_THR_HI = ROUND [100 • (1.5 • 1.06 –0.45)] = 114
V6_THR_LO = ROUND [100 • (1.5 • 0.94 –0.45)] = 96
Select medium range for V3 and V4 (1V to 6V):
V3_THR_HI = ROUND [50 • (3.3 • 1.11 – 0.9)] = 139
V3_THR_LO = ROUND [50 • (3.3 • 0.89 – 0.9)] = 101
V4_THR_HI = ROUND [50 • (5 • 1.11 – 0.9)] = 233
V4_THR_LO = ROUND [50 • (5 • 0.89 – 0.9)] = 177
To monitor –5V, use an external resistive divider connected
between VDD33 and the negative rail. The voltage at VDD33
is 3.3V. In order to minimize the error introduced by the
leakage current into the V5 input pin, the output of this
divider is targeted to lie within the precision voltage range
(0.2V to 1.2V). The OV and UV thresholds for the –5V rail
are calculated as follows:
V5MIN =
(3.3 • R1) − 1.1• (5 • R2)
> 0.2V
R1+R2
V5MAX =
(3.3 • R1) − 0.9 • (5 • R2)
< 1.2V
R1+R2
The normal polarities of the OV and UV comparators need
to be swapped, since a drop of the negative supply below
its specified absolute value increases V5MAX beyond its
encoded threshold. An increase of the negative supply
above its specified absolute value decreases V5MIN below
its encoded threshold.
The GPIOn outputs are programmed as RST (active low
system reset), OV (active low system OV) and ALERT
(active low ALERT, see SMBus specification). The UV
comparators are mapped to GPIO1 and GPIO3. The OV
comparators are mapped to GPIO2 and GPIO3. The GPI1
input is configured as MR (manual reset) and is mapped
to GPIO1. The GPI2 input is configured as MARG (margin
testing) allowing the system to disable OV and UV faults
during margin testing.
R1 = 249k ±0.1% and R2 = 100k ±0.1% satisfy the
previous relationships. The programming codes can be
calculated as shown in the following equations:
V5MIN =
(3.3 • 0.98) • (249 • 0.999)−(1.1• 5) • (100 • 1.001)
= 0.728V
(249 • 0.999)+(100 • 1.001)
V5MAX =
(3.3 • 1.02) • (249 • 1.001)−(0.9 • 5) • (100 • 0.999)
= 1.115V
(249 • 1.001)+(100 • 0.999)
V5_THR _HI = ROUND⎡⎣250 • (0.728 • 0.99 − 0.18)⎤⎦ = 135
V5_THR _LO = ROUND⎡⎣250 • (1.115 • 1.01− 0.18)⎤⎦ = 237
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25
LTC2933
Applications Information
Eleven-Channel Supply Power Monitor
Figure 4 illustrates how to use multiple LTC2933 supervisors to monitor power rails. The system consists of
two cascaded LTC2933 supervisors, both of them being
powered from a common 12V dedicated rail connected to
V1 to supervise ten supplies, plus the 12V rail.
The first supervisor monitors six rails and generates RST1
and OV1 signals if a rail faults. The MR signal on GPI1 is
also mapped into RST1.
The second supervisor monitors the remaining five channels and generates RST and OV signals in response to any
faults. The GPI1 input is connected to the first supervisor
RST1 output and is mapped to the second supervisor
GPIO1 pin to generate the system RST signal. The GPI2
input is connected to the first supervisor OV1 output and
is mapped to the second supervisor GPIO2 pin to generate the system OV signal. Thus, if any of the supervised
rails faults or if there is a valid MR signal, an appropriate
global RST or OV is generated.
Both GPIO3 outputs of the LTC2933 supervisors are
wired together and configured as ALERT signals, per the
SMBus protocol.
12V
5V
3.3V
2.5V
1.8V
1.5V
1.25V
1.0V
1.0V
0.9V
0.9V
DC/DC
MR
V1
GPI2
GPI1
V2
V3
VDD33
V4
0.22µF
LTC2933
SYSTEM
V5
ASEL
V6
SCL
GND
GPIO1
GPIO2
RST1
V1
GPIO3
GPI2
GPI1
SDA
OV1
V2
V3
VDD33
V4
0.22µF
0.1µF
LTC2933
V5
ASEL
V6
SCL
GND
GPIO1
GPIO2
RST
OV
GPIO3
SDA
ALERT
NOTE: INTERNAL GPI01-3 PULL-UP ENABLED
2933 F04
Figure 4. 11-Channel Supply Power Monitor
26
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LTC2933
Typical Applications
Two-Channel Voltage Monitoring with EEPROM Fault
Storage Power Backup
Figure 5 in the Typical Applications section illustrates an
EEPROM fault storage power backup circuit. The LTC2933
is supplied by the 12V rail, which is also monitored on V1.
The other monitored rail, 1.8V on V3, is too low to provide
adequate supply voltage, in case the 12V line collapses
to ground. In case such a fault occurs, the LTC2933 still
needs adequate power for EEPROM backup fault storage,
which takes less than 10ms. This is provided by the 22µF
capacitor connected between the V2 pin and ground, which
is charged from the 12V rail through R1. Since the V2
voltage may not exceed 6V, a 4.7V voltage-limiting Zener
diode connected between V2 and ground is necessary. In
this example, V4 through V6 are not used.
The minimum value of the charge-storage capacitor is
calculated as:
CMIN =
=
I 2SUP(MAX) • t EEFS
1.5mA • 10ms
= 11.5µF
4.7V − 3.4V
The temperature sensors are four 2N3904 diode-connected
BJTs, strategically placed inside the oven/dryer, which are
forward-biased at constant current through 10k resistors
connected to the regulated 3.3V pin. The diode voltages,
which exhibit a negative 2.2mV/°C temperature coefficient, are monitored on the V2 to V5 inputs, set to the
precision range.
The OV faults, corresponding to under-the-limit temperatures, are mapped into GPIO1, which controls the electric
heater through a power MOSFET switch and a relay.
The UV faults, corresponding to over-the-limit temperatures, are mapped into GPIO2, which controls the cooling
fan through a power MOSFET switch.
All faults are also mapped into GPIO3, which alerts the
microprocessor on system status.
The maximum value of R1 is determined by the V2 pin
input current and the Zener diode reverse leakage current:
V1− V2
RMAX =
IZ(MIN) + V2 / RIN(MIN)
Figure 6 in the Typical Applications section illustrates a
low cost, 4-point temperature control system, which is
suited for such commercial applications as electric ovens
and dryers.
A microprocessor is used to program the appropriate
temperature limits into the LTC2933, via the I2C interface.
V2 − V2MIN
R1 has to limit the Zener diode reverse current to a value below its maximum rating. This determines R1’s minimum
value.
V1− V2 12V − 4.7V
RMIN =
=
= 73kΩ
IZ(MAX)
0.1mA
=
Low Cost Multipoint Temperature Control System
The diode connected in series with the fan 12V supply
protects the LTC2933 against inductive voltage spikes
which can propagate on its V1 supply pin through the
common 12V line.
Such a low cost system can control oven/dryer temperature
within ±10°C accuracy, over a 50°C to 150°C range, after
proper calibration.
12V − 4.7V
= 336kΩ
0.01mA + 4.7V / 400k
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27
LTC2933
Typical Applications
Seven-Power Supply Monitor
Figure 7 in the Typical Applications section illustrates
how to use the LTC2933 auxiliary comparators to expand
power supply monitoring to seven channels. The system is
powered by a 12V source, which is also monitored. The 9V
rail can be monitored, in addition to the six input channels
(12V, 5V, 3.3V, 2.5V, 1.8V and 24V), using an external
resistive divider which feeds the OV and UV tap voltages
to the auxiliary comparators on inputs GPI1 and GPI2.
The GPI1 comparator monitors the UV limit and is programmed for negative polarity. The GPI2 comparator monitors the OV limit and is programmed for positive polarity.
A second resistive divider is used to divide the 24V rail
voltage down to 1.08V, in order to use the low leakage,
low range of the V5 channel.
Since the auxiliary comparators’ thresholds are fixed at
0.5V ±10mV, to monitor a 9V ±10% power supply, the
following equations apply:
R2+R3
0.51V
=
R1+R2+R3 0.9 • 9V
R3
0.49V
=
R1+R2+R3 1.1• 9V
For R3 = 8.87k, the equations yield: R2 = 2.4k and R1 =
168k.
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LTC2933
Typical Applications
DC/DC
12V
12V
1.8V
1.8V
R1
220k
22µF
MMSZ4688
4.7V
100nF
SYSTEM
220nF
V1
VDD33
V2
V3
V4
V6
GPIO1
LTC2933
GPI1
MR
V5
GPIO2
GPIO3
RST
OV
ALERT
SDA
SCL
GND
ASEL
GPI2
2933 F05
NOTE: INTERNAL GPI01-3 PULL-UP ENABLED
Figure 5. 2-Channel Voltage Monitoring with EEPROM Fault Storage Power Backup
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29
LTC2933
Typical Applications
2N3904
×4
10nF
10nF
10nF
TELEDYNE
712D
12V
110VAC
10nF
12V
HEATER
1N4001
10k
×4
100nF
12V
12V
10k
×2
220nF
VDD33
V1
V2
V3
V4
V5
V6
Si4420DY
GPIO1
GPI1
GPIO2
GPIO3
LTC2933
MR
FAN
12V DC/5.4W
PMB1212PLB3-A
Si4420DY
ALERT
SDA
SYSTEM
SCL
GND
ASEL
GPI2
2933 F06
NOTE: INTERNAL GPIO3 PULL-UP ENABLED
Figure 6. Low Cost Multipoint Temperature Control System
30
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LTC2933
Package Description
Please refer to http://www.linear.com/product/LTC2933#packaging for the most recent package drawings.
DHD Package
16-Lead Plastic DFN (5mm × 4mm)
(Reference LTC DWG # 05-08-1707 Rev A)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.44 ±0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
4.34 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
5.00 ±0.10
(2 SIDES)
9
4.00 ±0.10
(2 SIDES)
R = 0.115
TYP
0.40 ±0.10
16
2.44 ±0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
8
0.200 REF
1
0.25 ±0.05
0.50 BSC
0.75 ±0.05
0.00 – 0.05
(DHD16) DFN REV A 1113
4.34 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJGD-2) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
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31
LTC2933
Package Description
Please refer to http://www.linear.com/product/LTC2933#packaging for the most recent package drawings.
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ±.0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ±.004
× 45°
(0.38 ±0.10)
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
2 3
4
5 6
7
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.0250
(0.635)
BSC
GN16 REV B 0212
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
32
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LTC2933
Revision History
REV
DATE
DESCRIPTION
A
01/17
Raised storage temperature; clarified maximum junction temperature.
PAGE NUMBER
2
Added Notes 5 and 6.
5
Updated V2 to V4 pin function.
8
Changed to binary representation for the Default Value column.
12
Updated factory default threshold voltages in Vn_THR register.
Updated sections: Power Supply, Manual Reset, Outputs, Write Protect Features.
Added 4.7k pull-ups in Figure 3.
17
22, 23, 24
24
2933fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2933
33
LTC2933
Typical Application
DC/DC
24V
12V
9V
5V
3.3V
2.5V
1.8V
24V
12V
9V
5V
3.3V
2.5V
1.8V
R1
168k
100k
4.7k
0.1µF
4.7k
SYSTEM
4.7k
R2
2.4k
V1 V2
GPI1
GPI2
R3
8.87k
V3
V4
V5 V6
GPIO1
LTC2933
GPIO2
GPIO3
VDD33
0.22µF
RST
OV
ALERT
SDA
GND
ASEL
SCL
2933 F07
NOTE: INTERNAL GPI01-3 PULL-UP ENABLED
Figure 7. 7-Power Supply Monitor
Related Parts
PART NUMBER DESCRIPTION
COMMENTS
LTC2908
Precision 6-Input Supply Monitor
Reset: VCC = 0.5V, ±1.5% Accuracy Over Temperature, Internal VCC Auto
Select
LTC2910
Octal Positive/Negative Voltage Monitor
8 Adjustable Inputs (0.5V), ±1.5% Accuracy, Input Glitch Rejection,
Pin-Selectable Input Polarity
LTC2930
Configurable 6-Supply Monitor with Adjustable Reset
Timer, Manual Reset
16 Selectable Thresholds
LTC2931
Configurable 6-Supply Monitor with Adjustable Reset
and Watchdog Timers
16 Selectable Thresholds, Reset Timer, Separate Voltage Monitor Outputs
LTC2932
Configurable 6-Supply Monitor with Adjustable Reset
Timer and Supply Tolerance
16 Selectable Thresholds, Threshold Tolerance, Separate Voltage Monitor
Outputs
LTC2937
Programmable Six Channel Sequencer and Voltage
Supervisor with EEPROM
Time and Event Based Sequencing, 0.75% Accurate UV/OV Supervision,
I2C Interface
LTC2939
Configurable 6-Supply Monitor with Processor
Supervisory Functions
16 Selectable Thresholds, Adjustable Reset Timer, Watchdog Timeout,
Watchdog Status Output
LTC2936
Programmable Hex Voltage Supervisor with EEPROM and
Comparator Outputs
256 Programmable Thresholds, Comparator Outputs, EEPROM,
I2C Interface
LTC2977
8-Channel PMBus Power System Manager
0.25% TUE 16-Bit ADC, Voltage/Temperature Monitoring and Supervision
LTC2974
4-Channel PMBus Power System Manager
0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and
Supervision
LTC2975
4-Channel PMBus Power System Manager
0.25% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and
Supervision, Input Current and Power, Input Energy Accumulator
LTC2980
16-Channel PMBus Power System Manager
Dual LTC2977
LTC2970
Dual I2C Power Supply Monitor and Margining Controller
Monitors Voltage and Current on Two Power Supplies. Margins to 0.5%
Accuracy
34 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2933
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC2933
2933fa
LT 0117 REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2013
工商网监
湘ICP备2023018690号
