LTC6955
Ultralow Jitter, 7.5GHz,
11 Output Fanout
Buffer Family
DESCRIPTION
FEATURES
LTC6955: 11 Output Buffer
nn LTC6955-1: 10 Buffered Outputs and One ÷2 Output
nn Additive Output Jitter ~45fs RMS (ADC SNR Method)
nn Additive Output Jitter < 5fs RMS
(Integration BW = 12kHz to 20MHz, f = 7.5GHz)
nn Eleven Ultralow Noise CML Outputs
nn Parallel Control for Multiple Output Configurations
nn –40°C to 125°C Operating Junction Temperature
Range
nn
APPLICATIONS
High Performance Data Converter Clocking
SONET, Fibre Channel, GigE Clock Distribution
nn Low Skew and Jitter Clock and Data Fanout
nn Wireless and Wired Communications
nn Single-Ended to Differential Conversion
nn
nn
The LTC®6955 is a high performance, ultralow jitter,
fanout clock buffer with eleven outputs. Its 4-pin parallel
control port allows for multiple output setups, enabling
any number between three and eleven outputs, as well as
a complete shutdown. The parallel port also provides the
ability to invert the output polarity of alternating outputs,
simplifying designs with top and bottom board routing.
Each of the CML outputs can run from DC to 7.5GHz.
The LTC6955-1 replaces one output buffer with a divideby-2 frequency divider, allowing it to drive Analog Devices’
LTC6952 or LTC6953 to generate JESD204B subclass 1
SYSREF signals. These SYSREFs can pair with ultralow
jitter device clocks from the LTC6955-1, which can run
at frequencies up to 7.5GHz.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 8319551 and 8819472.
TYPICAL APPLICATION
7GHz Cumulative Phase Noise
ADF4371 Driving LTC6955
Generation of Multiple Low Jitter 7GHz Clocks
SEL3
SEL2
3.3V
10kΩ
SEL1
SEL0
VD+
3.3V
VOUT+
3.3V
LTC6955
BUFFER
7.4nH
ADF4371
REFP
.01µF
7.4nH
10pF
3.3V
IN+
RF8N
REFN
10pF
RF8P
VIN+
1pF
–80
–90
POWERED DOWN OR
ADDITIONAL CLOCKS
0.1µF
OUT6+
/1
Crystek
CCHD-575-25-100
100MHz Ref Osc 1nF
OUT0±
OUT1±
OUT2±
OUT3±
OUT4±
OUT5±
OUT7±
OUT9±
OUT6–
100Ω
0.1µF
OUT8+
/1
1nH 1pF
OUT8–
100Ω
/1
OUT10–
0.1µF
7.00GHz
CLOCKS
–110
–120
–130
–140
–150 TOTAL COMBINED
RMS JITTER = 67fs
–160
ADF4371 RMS JITTER = 50fs
–170 LTC6955 RMS JITTER = 45fs
EQUIVALENT ADC SNR METHOD
–180
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M 40M
6955 TA01b
0.1µF
OUT10+
IN–
0.1µF
ADF4371
ADF4371 + LTC6955
–100
PHASE NOISE (dBc/Hz)
FILT
100Ω
0.1µF
6955 TA01a
Rev. 0
Document Feedback
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1
LTC6955
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
GND
NC
NC
NC
NC
NC
NC
NC
TEMP
SEL0
SEL1
TOP VIEW
SEL2
Supply Voltages
V+ (VIN+, VD+, VOUT+) to GND................................3.6V
Voltage on All Pins.....................GND – 0.3V to V+ + 0.3V
Current into OUTx +, OUTx –, (x = 0 to 10).............±25mA
Operating Junction Temperature Range, TJ (Note 2)
LTC6955I and LTC6955I-1.................. –40°C to 125°C
Junction Temperature, TJMAX................................. 130°C
Storage Temperature Range................... –65°C to 150°C
52 51 50 49 48 47 46 45 44 43 42 41
SEL3 1
40 FILT
VD+ 2
39 VIN+
OUT10–
3
38 IN–
OUT10+
4
37 IN+
+
5
36 NC
VOUT
OUT9– 6
35 VOUT+
OUT9+
7
VOUT
+
34 OUT0+
8
OUT8–
9
32 VOUT+
OUT8+
10
31 OUT1+
VOUT 11
30 OUT1–
OUT7–
12
29 VOUT+
OUT7+
13
28 OUT2+
VOUT 14
27 OUT2–
53
(GND)
33 OUT0–
+
+
VOUT+
OUT3+
OUT3–
VOUT+
OUT4+
OUT4–
VOUT+
OUT5+
OUT5–
VOUT+
OUT6+
OUT6–
15 16 17 18 19 20 21 22 23 24 25 26
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
TJMAX = 130°C, θJC = 2°C/W, θJA = 31°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6955IUKG#PBF
LTC6955IUKG#TRPBF
LTC6955UKG
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 125°C
LTC6955IUKG-1#PBF
LTC6955IUKG-1#TRPBF
LTC6955UKG-1
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev. 0
2
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LTC6955
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VD+ = VIN+ = VOUT+ = 3.3V unless otherwise specified (Note 2).
All voltages are with respect to GND.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
l
0.25
0.8
l
–8
2
l
1.6
MAX
UNITS
7500
MHz
1.6
VP-P
8
dBm
Input (IN+, IN–)
fIN
Frequency Range
Input Power Level
l
RZ = 50Ω, Single-Ended
Self-Bias Voltage
Input Common Mode Voltage
2.05
800 mVP-P Differential Input
V
2.7
V
Input Duty Cycle
50
%
Minimum Input Slew Rate
100
V/µs
Input Resistance
Differential
250
Ω
Input Capacitance
Differential
1.0
pF
Digital Pin Specifications
VIH
High-Level Input Voltage
SEL3, SEL2, SEL1, SEL0, FILT
l
VIL
Low-Level Input Voltage
SEL3, SEL2, SEL1, SEL0, FILT
l
VIHYS
Input Voltage Hysteresis
SEL3, SEL2, SEL1, SEL0, FILT
Input Current
SEL3, SEL2, SEL1, SEL0, FILT
1.55
V
0.8
250
±1
l
V
mV
µA
Clock Outputs (OUT0+, OUT0–, OUT1+, OUT1–, OUT2+, OUT2–, …, OUT10+, OUT10–)
fOUT
VOD
tR
LTC6955 Output Frequency
Differential Termination = 100Ω,
All Outputs
l
0
7500
MHz
LTC6955-1 Output Frequency
Differential Termination = 100Ω,
All Outputs Except OUT10
l
0
7500
MHz
Differential Termination = 100Ω,
OUT10 Only
l
0
3750
MHz
Output Differential Voltage
Differential Termination = 100Ω
l
320
550
mVP-P
Output Resistance
Differential
Output Common Mode Voltage
Differential Termination = 100Ω
Output Rise Time, 20% to 80%
Differential Termination = 100Ω
tF
Output Fall Time, 80% to 20%
Differential Termination = 100Ω
DC
Output Duty Cycle
Differential Termination = 100Ω
tPD
LTC6955 Propagation Delay,
All Outputs
VFILT < VIL, TA = 25°C
100
Ω
+ – 1.0
V
VOUT
50
ps
50
l
45
50
ps
55
220
%
ps
VFILT > VIH, TA = 25°C
230
ps
LTC6955-1 Propagation Delay,
All Outputs Except OUT10
VFILT < VIL, TA = 25°C
220
ps
VFILT > VIH, TA = 25°C
230
ps
LTC6955-1 Propagation Delay,
OUT10 Only
VFILT < VIL, TA = 25°C
280
ps
VFILT > VIH, TA = 25°C
290
ps
0.23
ps/°C
Propagation Delay, Temperature
Variation
tSKEW
420
LTC6955 Skew, All Outputs Except
OUT0 (Note 4)
Same Part
l
±10
±25
ps
Across Multiple Parts
l
±20
±50
ps
LTC6955-1 Skew, All Outputs Except Same Part
OUT0 and OUT10 (Note 4)
Across Multiple Parts
l
±10
±25
ps
l
±20
±50
ps
Rev. 0
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3
LTC6955
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VD+ = VIN+ = VOUT+ = 3.3V unless otherwise specified (Note 2).
All voltages are with respect to GND.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply Voltages
VOUT+ Supply Range
l
3.15
3.3
3.45
V
VD+ Supply Range
l
3.15
3.3
3.45
V
+ Supply Range
l
3.15
3.3
3.45
V
350
420
mA
VIN
Power Supply Currents
IDDOUT
LTC6955 VOUT+ Supply Current
(Note 3)
LTC6955-1 VOUT
(Note 3)
IDD – 3.3V
SEL = 14, All Outputs Active
+ Supply Current
+,
LTC6955 or LTC6955-1 Sum VD
VIN+ Supply Currents (Note 3)
l
SEL = 1, Three Outputs Active
105
mA
SEL = 0 or 15, All Outputs Off
90
µA
SEL = 14, All Outputs Active
l
358
430
mA
SEL = 1, Three Outputs Active
108
mA
SEL = 0 or 15, All Outputs Off
90
µA
SEL = 14, All Outputs Active
l
85
110
mA
SEL = 1, Three Outputs Active
67
mA
SEL = 0, All Outputs Off, Temp Diode Off
20
µA
SEL = 15, All Outputs Off, Temp Diode On
360
µA
Additive Phase Noise, Jitter and Spurious (Note 5)
Output Noise/Jitter, fIN = 7.5GHz
Output Noise/Jitter, fIN = 1.0GHz
Phase Noise Floor
–155.2
dBc/Hz
RMS Jitter, 12kHz to 20MHz Integration BW
5
fsRMS
RMS Jitter, ADC SNR Method (Note 6)
45
fsRMS
Phase Noise Floor
–164
dBc/Hz
RMS Jitter, 12kHz to 20MHz Integration BW
7
fsRMS
RMS Jitter, ADC SNR Method (Note 6)
45
fsRMS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6955 is guaranteed to meet specified performance limits
over the full operating junction temperature range of –40°C to 125°C.
Note 3: The SEL code (SEL) programs the state of each output as
described in Table 2. SEL’s value is determined by the voltage state of the
SELx pins. If VSELx > VIH, its digital value (SELx) is “1”. If VSELx < VIL, its
digital value (SELx) is “0”. The SEL code is equal to 8 • SEL3 + 4 • SEL2 +
2 • SEL1 + SEL0.
Note 4: For LTC6955, skew is defined as the difference between the zerocrossing time of a given output and the average zero-crossing time of all
outputs. For LTC6955-1, skew is defined as the difference between the
zero-crossing time of a given output and the average zero-crossing time of
outputs 0 to 9.
Note 5: Additive phase noise and jitter from LTC6955 only. Incoming clock
phase noise is not included.
Note 6: Additive RMS jitter (ADC SNR method) is calculated by integrating
the distribution section’s measured additive phase noise floor out to fCLK.
Actual ADC SNR measurements show good agreement with this method.
Note 7: The LTC6955 is driven from a VCO (CVCO55CC-4000-4000)
through a splitter. The other side of the splitter drives the input of a
LTC6952 to lock the VCO in a PLL. The reference for the LTC6952 PLL is a
Pascal OCXO-E, fREF = 100MHz, PREF = 6dBm.
Note 8: Measured using DC2611.
Note 9: Cable loss is de-embeded in this plot, but board and connector
losses are not. Output board traces are approximately 5cm long.
Note 10: Data for outputs 0 to 9 was taken on 1304 total parts from four
assembly lots (two LTC6955 and two LTC6955-1). Data for LTC6955
OUT10 was taken on 710 parts from two assembly lots. Data for
LTC6955-1 OUT10 was taken on 594 parts from two assembly lots.
Rev. 0
4
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LTC6955
TYPICAL+ PERFORMANCE
CHARACTERISTICS
+
+
TA = 25°C. VD = VIN = VOUT = 3.3V, unless otherwise noted.
Total Phase Noise, Driven from
VCO in a Locked PLL, fIN =
4000MHz, FILT = GND
VCO: CVCO55CC–4000–4000
NOTE 7
–110
–120
900
FILT = GND
FILT = V+
800
NOTES 5, 6
700
JITTER (fsRMS)
PHASE NOISE (dBc/Hz)
1000
–130
–140
–150
600
500
400
300
–160
–170
–180
100
200
VCO OUTPUT
LTC6955 OUTPUT
LTC6955–1 OUT10 (DIV 2)
1k
100
10k
100k
1M
OFFSET FREQUENCY (Hz)
1
INPUT SLEW RATE (V/ns)
10
0.3
0.2
0.1
0.0
–0.1
–0.2
–0.3
Differential Output Swing
vs Frequency, Junction
Temperature
CML Differential Output at 1GHz
0.2
0.1
0.0
–0.1
–0.2
–0.3
–0.4
NOTE 9
–0.5
200ps/DIV
1.00
fIN = 200MHz
NOTES 4, 10
10
0.90
0.80
125°C
25°C
–40°C
0.70
0.60
0.50
6955 G04
20
SKEW (ps)
DIFFERENTIAL OUTPUT SWING (VP–P)
0.3
6955 G03
50ps/DIV
Expected Skew Variation
for a Single LTC6955
1.10
0.5
0.4
NOTE 9
–0.5
6955 G02
6955 G01
DIFFERENTIAL OUTPUT (V)
0.4
–0.4
0
0.1
10M 40M
CML Differential Output at 7.5GHz
0.5
DIFFERENTIAL OUTPUT (V)
–100
Additive Jitter vs Input Slew Rate,
ADC SNR Method
1
–10
+3σ
–20
AVERAGE
–3σ
NOTES 8, 9
0
0
2
3
4
5
6
OUTPUT FREQUENCY (GHz)
7
–30
0
1
2
3
4 5 6
OUTPUT
7
8
6955 G05
60
50
fIN = 200MHz
NOTES 4, 10
20
DIVIDE BY 2
OUTPUT
70
SKEW (ps)
SKEW (ps)
0
30
20
10
–30
–10
60
–20
0
–20
80
NOTE 4
10
40
–10
LTC6955-1 OUT10 Skew vs
Frequency, Junction Temperature
DELAY (ps)
70
6955 G06
Skew Variation with Junction
Temperature for a Single Typical
LTC6955
Expected Skew Variation
for a Single LTC6955-1
9 10
+3σ
AVERAGE
–3σ
0 1 2 3
–30
4 5 6
OUTPUT
7
8
9 10
6955 G07
–40
–40 –20
OUT0
OUT1
OUT2
OUT3
0
20
OUT4
OUT5
OUT6
OUT7
40 60
TJ (°C)
OUT8
OUT9
OUT10
80
100 120
6955 G08
125°C
70°C
25°C
–40°C
50
40
0
1
2
3
4
5
6
INPUT FREQUENCY (GHz)
NOTE 4
7
6955 G09
Rev. 0
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5
LTC6955
TYPICAL+ PERFORMANCE
CHARACTERISTICS
+
+
TA = 25°C. VD = VIN = VOUT = 3.3V, unless otherwise noted.
LTC6955 and LTC6955-1
Propagation Delay Variation,
Input to OUT5
Propagation Delay vs Frequency,
Junction Temperature
280
600
260
250
NUMBER OF PARTS
PROPAGATION DELAY (ps)
700
FILT = GND
270
240
230
220
210
125°C
70°C
25°C
–40°C
200
190
180
0
1
2
3
4
5
FREQUENCY (GHz)
6
fIN = 200MHz
FILT = GND
500
400
300
200
100
0
210
7
215
6955 G10
LTC6955 Supply Current
vs Junctiion Temperature
and Voltage
500
470
500
450
400
350
CURRENT (mA)
CURRENT (mA)
455
440
425
410
395
230
6955 G11
3.15V
3.30V
3.45V
NOTE 3
250
200
150
100
365
50
ALL OUTPUTS ON
350
–40 –20 0
20
40 60
TJ (°C)
80
0
100 120
6955 G12
500
LTC6955-1 Supply Current
vs Voltage and SEL Setting
500
3.15V
3.3V
3.45V
485
470
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SEL SETTING
6955 G13
LTC6955-1 Supply Current
vs Junction Temperature and
Voltage
450
400
3.15V
3.3V
3.45V
350
CURRENT (mA)
455
CURRENT (mA)
225
300
380
440
425
410
300
250
200
395
150
380
100
365
220
TPD (ps)
LTC6955 Supply Current
vs Voltage and SEL Setting
3.15V
3.3V
3.45V
485
NOTE 10
50
ALL OUTPUTS ON
350
–40 –20
0
20
40 60
TJ (°C)
80
100 120
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SEL SETTING
6955 G14
6955 G15
Rev. 0
6
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LTC6955
PIN FUNCTIONS
SEL3, SEL2, SEL1, SEL0 (Pins 1, 52, 51, 50): Parallel
Port Control Bits. These CMOS inputs control the output
configuration. See the Operation section for more details.
VD+ (Pin 2): 3.15 to 3.45V Positive Supply Pins for Parallel
Port. This pin should be bypassed directly to the ground
plane using a 0.1µF ceramic capacitor as close to the pin
as possible.
VOUT+ (Pins 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35):
3.15 to 3.45V Positive Supply Pins for Outputs. Each pin
should be separately bypassed directly to the ground
plane using a 0.01µF ceramic capacitor as close to the
pin as possible.
OUT10+, OUT10– (Pins 3, 4): Output Signals. The output is buffered and presented differentially on these pins.
The outputs have 50Ω (typical) output resistance per side
(100Ω differential). The far end of the transmission line
is typically terminated with 100Ω connected across the
outputs. For the LTC6955, this output is an undivided
version of the input, identical to the other outputs. For
the LTC6955-1, only this output is a frequency divided
by two version of the input signal. See the Operation and
Applications Information section for more details.
OUT9+, OUT9– (Pins 6, 7): Output Signals. The output is
buffered and presented differentially on these pins. The
outputs have 50Ω (typical) output resistance per side
(100Ω differential). The far end of the transmission line
is typically terminated with 100Ω connected across the
outputs. This output is an undivided version of the input.
OUT8+, OUT8– (Pins 9, 10): Same as OUT9.
OUT7+, OUT7– (Pins 12, 13): Same as OUT9.
OUT6+, OUT6– (Pins 15, 16): Same as OUT9.
NC (Pin 36): Not Connected Internally. It is recommended
that this pin be connected to the ground pad (Pin 53).
IN+, IN– (Pins 37, 38): Input Signals. The differential
signal placed on these pins is buffered with a low noise
amplifier and fed to the internal distribution path and outputs. These self-biased inputs present a differential 250Ω
(typical) resistance to aid impedance matching. They may
be driven single-ended by using the matching circuit in
the Applications Information section.
VIN+ (Pins 39): 3.15 to 3.45V Positive Supply Pin for
Input Circuitry. This pin should be bypassed directly to
the ground plane using a 0.01µF ceramic capacitor as
close to the pin as possible.
FILT (Pin 40): Input Filter Control Pin. When tied to GND,
the input is not filtered. When tied to V+, the input is
filtered to improved noise performance of low slew rate
input signals. See the Operation section for details.
GND (Pin 41): Negative Power Supply (Ground). This pin
should be tied directly to the ground plane with multiple
vias.
NC (Pins 42, 43, 44, 45, 46, 47, 48): No Connect. These
pins should be left open or connected to GND.
TEMP (Pin 49): Temperature Measurement Pin. When
enabled, this outputs a temperature measurement diode
voltage. See the Operation section for details.
GND (Exposed Pad Pin 53): Negative Power Supply
(Ground). The package exposed pad must be soldered
directly to the PCB land. The PCB land pattern should
have multiple thermal vias to the ground plane for both
low ground inductance and also low thermal resistance.
OUT5+, OUT5– (Pins 18, 19): Same as OUT9.
OUT4+, OUT4– (Pins 21, 22): Same as OUT9.
OUT3+, OUT3– (Pins 24, 25): Same as OUT9.
OUT2+, OUT2– (Pins 27, 28): Same as OUT9.
OUT1+, OUT1– (Pins 30, 31): Same as OUT9.
OUT0+, OUT0– (Pins 33, 34): Same as OUT9.
Rev. 0
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7
LTC6955
BLOCK DIAGRAM
LTC6955 Block Diagram
NC
NC
NC
NC
NC
NC
NC GND
FILT
48
47
46
45
44
43
42
40
41
36 NC
LTC6955
39 VIN+
37 IN+
VD+ 2
38 IN–
SEL0 50
SEL1 51
PARALLEL
CONTROL
SEL2 52
35 VOUT+
34 OUT0+
33 OUT0–
SEL3 1
32 VOUT+
31 OUT1+
30 OUT1–
TEMP 49
29 VOUT+
28 OUT2+
GND 53
EXPOSED
PAD
27 OUT2–
VOUT+ 5
26 VOUT+
OUT10+ 4
25 OUT3+
OUT10– 3
24 OUT3–
VOUT+ 8
23 VOUT+
OUT9+ 7
22 OUT4+
OUT9– 6
21 OUT4–
VOUT+ 11
20 VOUT+
OUT8+ 10
19 OUT5+
OUT8– 9
18 OUT5–
VOUT+ 14
17 VOUT+
OUT7+ 13
16 OUT6+
OUT7– 12
15 OUT6–
6955 BD
Rev. 0
8
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LTC6955
BLOCK DIAGRAM
LTC6955-1 Block Diagram
NC
NC
NC
NC
NC
NC
NC GND
FILT
48
47
46
45
44
43
42
40
41
36 NC
LTC6955 - 1
39 VIN+
37 IN+
VD+ 2
38 IN–
SEL0 50
SEL1 51
35 VOUT+
PARALLEL
CONTROL
34 OUT0+
SEL2 52
33 OUT0–
SEL3 1
32 VOUT+
31 OUT1+
30 OUT1–
TEMP 49
29 VOUT+
28 OUT2+
EXPOSED
GND 53
PAD
27 OUT2–
VOUT+ 5
OUT10+ 4
OUT10– 3
26 VOUT+
/2
25 OUT3+
24 OUT3–
VOUT+ 8
23 VOUT+
OUT9+ 7
22 OUT4+
OUT9– 6
21 OUT4–
VOUT+ 11
20 VOUT+
OUT8+ 10
19 OUT5+
OUT8– 9
18 OUT5–
VOUT+ 14
17 VOUT+
OUT7+ 13
16 OUT6+
OUT7– 12
15 OUT6–
69551 BD
Rev. 0
For more information www.analog.com
9
LTC6955
TIMING DIAGRAMS
Propagation Delay and Output Skew
IN–
IN+
tPD
tSKEW0
OUT0+
OUT0–
tSKEW1
OUT1+
OUT1–
tSKEW2
OUT2+
OUT2–
tSKEW3
OUT3+
OUT3–
tSKEW3
OUT10+
OUT10–
6955 TD01
AVERAGE ZERO CROSSING TIME OF ALL OUTPUTS
Differential CML Rise/Fall Times
80%
20%
tR
tF
6955 TD02
Rev. 0
10
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LTC6955
OPERATION
The LTC6955 is a high-performance multi-output clock
buffer that operates up to 7.5GHz. The device is able to
achieve superior integrated jitter performance by way of
its excellent output noise floor.
Input Buffer
The LTC6955’s input buffer provides a flexible interface to
either differential or single-ended frequency sources. The
inputs are self-biased, and AC-coupling is recommended
for applications using external VCO/VCXO/VCSOs.
However, the input can also be driven DC-coupled by
LVPECL, CML, or any other driver type within the input’s
specified common mode range. See the Applications
Information section for more information on common
input interface configurations, noting that the LTC6955’s
input buffer has an internal differential resistance of 250Ω
as shown in Figure 1.
BIAS
VIN+
2.1V
VIN+
935Ω
125Ω
100V/µs, although better performance will be achieved
with a higher slew rate. For applications with an input slew
rate less than 2V/ns, better phase noise performance will
be achieved by enabling the internal broadband noise filtering circuit within the input buffer. This is accomplished
by setting the FILT pin (pin 40) to V+. Note that setting
FILT = V+ when the slew rate of the input is greater than
2V/ns will degrade the overall phase noise performance.
See Table 1 for recommended settings of FILT.
Table 1. FILT Control Voltage
FILTV
Slew Rate of Input
V+
< 2V/ns
GND
≥ 2V/ns
CML Output Buffers (OUT0 to OUT10)
All of the outputs are ultralow noise, low skew 2.5V CML
buffers. Each output can be AC or DC coupled and terminated with 100Ω differential. If a single-ended output is
desired, each side of the CML output can be individually
AC coupled and terminated with 50Ω. See Figure 2 for
circuit details.
VOUT+
125Ω
IN+
33Ω
FILT
50Ω
IN–
50Ω
OUTx+
6955 F01
OUTx–
Figure 1. Simplified Input Interface Schematic
The maximum frequency for the input buffer is 7.5GHz, and
the maximum amplitude is 1.6VP-P. It is also important that
the input signal be low noise and have a slew rate of at least
6955 F02
Figure 2. Simplified CML Interface Schematic (All OUTx)
Rev. 0
For more information www.analog.com
11
LTC6955
OPERATION
Output Programming
TEMP Pin
The LTC6955’s eleven outputs can be configured by
setting the state of the four SELx pins. Three to eleven
outputs can be enabled at one time, and odd outputs
have the additional ability to be enabled with their output
inverted. See Table 2 for full programming details, where
OFF means the output is disabled, ON means the output is
enabled and not inverted from the input, and INV means
the output is enabled and inverted from the input.
The TEMP pin outputs a temperature measurement diode
voltage when enabled. For an approximate die temperature, a calibration point is required. Measure the TEMP
pin voltage (VTEMPC) with the LTC6955 powered down
(SEL3 = SEL2 = SEL1 = SEL0 = 1) at a known temperature (tCAL). Then calculate the operating temperature in a
desired application by measuring the TEMP voltage again
(VTEMP) and using the following equation:
t = 665 • (VTEMPC – VTEMP) + tCAL
where t and tCAL are in °C, and VTEMPC and VTEMP are in V.
The TEMP diode is enabled in all modes except a full
shutdown (SEL3 = SEL2 = SEL1 = SEL0 = 0) as shown
in Table 2.
Table 2. Output Programming with SELx Pins (Note 3)
SEL
CODE SEL3
0
0
SEL2
SEL1
0
0
# OF
ACTIVE
SEL0 OUTPUTS
0
0
OUT0 OUT1
OFF
OFF
OUT2
OUT3
OUT4 OUT5
OFF
OFF
OFF
OFF
OUT6
OUT7
OUT8
OFF
OFF
OFF
OUT9 OUT10 TEMP
OFF
OFF
OFF
1
0
0
0
1
3
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
ON
2
0
0
1
0
4
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
3
0
0
1
1
5
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
4
0
1
0
0
6
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
5
0
1
0
1
7
OFF
OFF
ON
OFF
ON
OFF
ON
INV
ON
INV
ON
ON
6
0
1
1
0
7
OFF
OFF
ON
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
7
0
1
1
1
8
OFF
OFF
ON
OFF
ON
INV
ON
INV
ON
INV
ON
ON
8
1
0
0
0
8
OFF
OFF
ON
OFF
ON
ON
ON
ON
ON
ON
ON
ON
9
1
0
0
1
9
OFF
OFF
ON
INV
ON
INV
ON
INV
ON
INV
ON
ON
10
1
0
1
0
9
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
11
1
0
1
1
10
OFF
INV
ON
INV
ON
INV
ON
INV
ON
INV
ON
ON
12
1
1
0
0
10
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
13
1
1
0
1
11
ON
INV
ON
INV
ON
INV
ON
INV
ON
INV
ON
ON
14
1
1
1
0
11
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
15
1
1
1
1
0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
Rev. 0
12
For more information www.analog.com
LTC6955
APPLICATIONS INFORMATION
Introduction
Input
The LTC6955 can be used in any application where multiple outputs of the same clock frequency are needed. It
is especially effective for data converter clocking, where
ultralow jitter is often necessary to prevent negative
impact on the data converter’s noise performance.
The LTC6955’s input buffer, shown in Figure 1, has a frequency range of DC to 7.5GHz. The buffer has a partial
on-chip differential input termination of 250Ω, allowing some flexibility for an external matching network if
desired. Figure 3 shows recommended interfaces for different input signal types.
0.1µF
RF OSCILLATOR
50Ω OUTPUT
0.1µF
IN–
Z0
75Ω
0.1µF
+
CML
OR
LVDS
LTC6955
30Ω
–
IN+
IN+
Z0
IN–
Z0
0.1µF
AC-Coupled RF Sine Wave Oscillator (fIN < 5GHz)
AC-Coupled Differential CML or LVDS (fIN < 5GHz)
1pF
RF OSCILLATOR
50Ω OUTPUT
0.1µF
1pF
IN–
Z0
1nH
50Ω
1pF
+
CML
OR
LVDS
LTC6955
IN+
AC-Coupled RF Sine Wave Oscillator (fIN ≥ 5GHz)
–
1nH 1pF
LVPECL
160Ω
LTC6955
IN–
Z0
+
LVPECL
–
150Ω
150Ω
DC-Coupled Differential LVPECL*
160Ω
Z0
IN–
Z0
0.1µF
IN+
Z0
160Ω
LTC6955
IN–
Z0
0.1µF
AC-Coupled Differential LVPECL
IN+
Z0
CML
LTC6955
AC-Coupled Differential CML or LVDS (fIN ≥ 5GHz)
IN+
Z0
IN+
Z0
150Ω
150Ω
LTC6955
160Ω
LTC6955
IN–
* DC coupled CML and LVPECL input common mode level must be within the
min and max levels specified in the Electrical Characteristics. All LTC6951,
LTC6952, LTC6953, and LTC6955 CML output levels are acceptable.
DC-Coupled Differential CML*
6955 F03
Figure 3. Common Input Interface Configurations. All ZO Signal Traces Are 50Ω Transmission Lines
Rev. 0
For more information www.analog.com
13
LTC6955
APPLICATIONS INFORMATION
LTC6955 Design Example with Eight ADCs
This design example consists of a system of eight analogto-digital converters (ADCs) being driven from a single
LTC6955. Assume PCB layout constraints require four
ADCs on the top of the circuit board and four on the bottom. This means the LTC6955 should ideally provide four
non-inverted clocks for the topside ADCs and four inverted
clocks for the bottom side ADCs. Referring to Table 2, SEL
code 9 provides the closest number and polarity of active
outputs, even though one spare output will be active.
Figure 4 shows a block diagram of the proposed system.
Note that any active output should be terminated with
100Ω, even if it is not used.
For this example, assume the input is being driven single-ended by a 500MHz sine wave oscillator with output
swing of 1.6VP-P. The incoming slew rate (SR) can be
determined from the following equation:
SR = VAMP • 2π • fIN
where VAMP is the input amplitude (in VP) and fIN is the
input frequency (in Hz). In this example:
SR = 0.8VP • 2π • 500MHz = 2.5V/ns
Referring to Table 1, set the FILT pin to GND since 2.5V/ns
is greater than 2V/ns.
500MHz OSCILLATOR
OR VCO
0.1µF
75Ω
+
100Ω
30Ω
– +
V+
FILT
SEL0
SEL1
SEL2
SEL3
+ –
+ –
+ –
OUT0
OUT1
OUT2
+
OUT3
INV
OUT4
OUT5
INV
OUT10
LTC6955
PCB TOP
– +
OUT9
INV
– +
OUT8
– +
OUT7
INV
– +
OUT6
100Ω
–
+
–
+
–
+
–
–
–
100Ω
100Ω
100Ω
100Ω
100Ω
MAY BE ROUTED INTO
VCO INPUT OF LTC6952
FOR CLOSED LOOP
PHASE LOCKING OF VCO.
CLK
100Ω
100Ω
CLK
+
+
CLK
–
–
CLK
+
+
CLK
–
–
CLK
+
+
CLK
–
–
CLK
+
ADC0
PCB TOP
ADC1
PCB BOTTOM
ADC2
PCB TOP
ADC3
PCB BOTTOM
ADC4
PCB TOP
ADC5
PCB BOTTOM
ADC6
PCB TOP
ADC7
PCB BOTTOM
6955 F04
Figure 4. Block Diagram for LTC6955 Design Example
Rev. 0
14
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LTC6955
APPLICATIONS INFORMATION
Supply Bypassing and PCB Layout Guidelines
Care must be taken when creating a PCB layout to minimize power supply decoupling and ground inductances.
All power supply V+ pins should be bypassed directly to
the ground plane using either a 0.01µF or a 0.1µF ceramic
capacitor as called out in the Pin Functions section as
close to the pin as possible. Multiple vias to the ground
plane should be used for all ground connections, including to the power supply decoupling capacitors.
The presence of the divide-by-2 output on the LTC6955-1
causes a spur to appear on the other buffered outputs of
the part. This spur can be improved by adding a ferrite
bead in series with the VOUT+ supply pin for OUT10 (Pin 6).
See the Typical Application Generation of 7.25GHz, 52fs
ADC SNR Jitter Clocks Using LTC6952 and LTC6955-1
for an example.
The package’s exposed pad is a ground connection, and
must be soldered directly to the PCB land. The PCB land
pattern should have multiple thermal vias to the ground
plane for both low ground inductance and also low thermal resistance (see Figure 5 for an example). An example
of grounding for electrical and thermal performance can
be found on the DC2611 layout.
6955 F05
Figure 5. PCB Top Metal Layer Pin and Exposed Ground Pad
Design. Pin 41 Is Signal Ground and Connected Directly to the
Exposed Pad Metal
Rev. 0
For more information www.analog.com
15
LTC6955
APPLICATIONS INFORMATION
ADC Clocking and Jitter Requirements
Adding noise directly to a clean signal clearly reduces its
signal to noise ratio (SNR). In data acquisition applications, digitizing a clean signal with a noisy clock signal
also degrades the SNR. This issue is best explained in
the time domain using jitter instead of phase noise. For
this discussion, assume that the jitter is white (flat with
frequency) and of Gaussian distribution.
Figure 6 shows a sine wave signal entering a typical data
acquisition circuit composed of an ADC, an input signal
amplifier and a sampling clock. Also shown are three signal sampling scenarios for sampling the sine wave at its
zero crossing.
SINE WAVE
INPUT SIGNAL
AMP
In the first scenario, a perfect sine wave input is buffered
by a noiseless amplifier to drive the ADC. Sampling is performed by a perfect, zero jitter clock. Without any added
noise or sampling clock jitter, the ADC’s digitized output
value is very clearly determined and perfectly repeatable
from cycle to cycle.
In the second scenario, a perfect sine wave input is buffered by a noisy amplifier to drive the ADC. Sampling is
performed by a perfect, zero jitter clock. The added noise
results in an uncertainty in the digitized value, causing an
error term which degrades the SNR. The degraded SNR in
this scenario, from adding noise to the signal, is expected.
ADC
BITS
SAMPLING CLOCK
SINE WAVE
INPUT SIGNAL WITH
NOISELESS AMP
VSAMPLE
SINE WAVE
INPUT SIGNAL WITH
NOISY AMP
∆V = VERROR
SINE WAVE
INPUT SIGNAL WITH
NOISELESS AMP
∆V = VERROR
tJ
PERFECT SAMPLING CLOCK
PERFECT SAMPLING CLOCK
6955 F06
SAMPLING CLOCK WITH ADDED JITTER
Figure 6. A Typical Data Acquisition Circuit Showing the Sampling Error
Effects of a Noisy Amplifier and a Jittery Sampling Clock
Rev. 0
16
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LTC6955
APPLICATIONS INFORMATION
In the third scenario, a perfect sine wave input is buffered
by a noiseless amplifier to drive the ADC. Sampling is
performed by a clock signal with added jitter. Note that
as the signal is slewing, the jitter of the clock signal leads
to an uncertainty in the digitized value and an error term
just as in the previous scenario. Again, this error term
degrades the SNR.
A real-world system will have both additive amplifier noise
and sample clock jitter. Once the signal is digitized, determining the root cause of any SNR degradation – amplifier
noise or sampling clock jitter – is difficult.
Degradation of the SNR due to sample clock jitter only
occurs if the analog input signal is slewing. If the analog
input signal is stationary (DC) then it does not matter
when in time the sampling occurs. Additionally, a faster
slewing input signal yields a greater error (more noise)
than a slower slewing input signal.
Figure 7 demonstrates this effect. Note how much larger
the error term is with the fast slewing signal than with the
slow slewing signal. To maintain the data converter’s SNR
performance, digitization of high input frequency signals
requires a clock with much less jitter than applications
with lower frequency input signals.
FAST
SINE WAVE
SLOW
SINE WAVE
It is important to note that the frequency of the analog
input signal determines the sample clock’s jitter requirement. The actual sample clock frequency does not matter.
Many ADC applications that under-sample high frequency
signals have especially challenging sample clock jitter
requirements.
The previous discussion was useful for gaining an intuitive feel for the SNR degradation due to sampling clock
jitter.
Quantitatively, the actual sample clock jitter requirement
for a given application is calculated as follows:
∆V = VERROR(SLOW)
tJ
6955 F07
(1)
2 • π • fSIG
Where fSIG is the highest frequency signal to be digitized
expressed in Hz, SNRdB is the SNR requirement in decibels and tJ(TOTAL) is the total RMS jitter in seconds. The
total jitter is the RMS sum of the ADC’s aperture jitter and
the sample clock jitter calculated as follows:
t J(TOTAL) =
2
2
t J(CLK) + t J(ADC)
(2)
Alternatively, for a given total jitter, the attainable SNR is
calculated as follows:
∆V = VERROR(FAST)
t J(TOTAL) =
−SNRdB
10 20
(
SNR dB = −20 log 10 2 • π • fSIG • t J(TOTAL)
)
(3)
These calculations assume a full-scale sine wave input
signal. If the input signal is a complex, modulated signal
with a moderate crest factor, the peak slew rate of the
signal may be lower and the sample clock jitter requirement may be relaxed.
Figure 7. Fast and Slow Sine Wave Signals
Sampled with a Jittery Clock
Rev. 0
For more information www.analog.com
17
LTC6955
APPLICATIONS INFORMATION
These calculations are also theoretical. They assume a
noiseless ADC with infinite resolution. All realistic ADCs
have both added noise and a resolution limit. The limitations of the ADC must be accounted for to prevent overspecifying the sampling clock.
Figure 8 plots the previous equations and provides a
simple, quick way to estimate the sampling clock jitter
requirement for a given input signal or the expected SNR
performance for a given sample clock jitter.
124
The RMS jitter of an ADC clock source can be indirectly
measured by comparing a jitter dominated SNR measurement to a non-jitter dominated SNR measurement. A jitter
dominated SNR measurement (SNRjitter) is created by
applying a low jitter, high frequency full-scale sine wave
to the ADC analog input. A non-jitter dominated SNR measurement (SNRbase) is created by applying a very low
amplitude (or low frequency) sine wave to the ADC analog
input. The total clock jitter (tJ(TOTAL)) can be calculated
using Equation 4.
TOTAL CLOCK
JITTER (RMS)
114
104
SNR (dB)
94
84
74
64
54
44
34
10fs
20fs
50fs
100fs
200fs
500fs
1ps
t J(TOTAL) =
10
⎡
⎛ SNR jitter ⎞
⎛ SNRbase ⎞ ⎤
⎢ −⎜
⎟
−⎜
⎟⎥
1
10
⎠ −10 ⎝ 10
⎠⎥
log10⎢10 ⎝
⎢
⎥
2
⎢
⎥
⎣
⎦
2πfIN
(4)
Assuming the inherent aperture jitter of the ADC (tJ(ADC))
is known, the jitter of the clock generator (tJ(CLK)) is
obtained using Equation 2.
24
0.01
0.1
1
10
FREQUENCY OF FULL-SCALE INPUT SIGNAL (GHz)
ADC Sample Clock Input Drive Requirements
6955 F08
Figure 8. SNR vs Input Signal Frequency vs Sample Clock Jitter
Measuring Clock Jitter Indirectly Using ADC SNR
For some applications, integrating a clock generator’s
phase noise within a defined offset frequency range (i.e.
12kHz to 20MHz) is sufficient to calculate the clock’s
impact on the overall system performance. In these situations, the RMS jitter can be calculated from a phase
noise measurement.
However, other applications require knowledge of the
clock’s phase noise at frequency offsets that exceed the
capabilities of today’s phase noise analyzers. This limitation makes it difficult to calculate jitter from a phase noise
measurement.
Modern high speed, high resolution ADCs are incredibly
sensitive components able to match or exceed laboratory instrument performance in many regards. Noise or
interfering signals on the analog signal input, the voltage
reference or the sampling clock input can easily appear
in the digitized data. To deliver the full performance of
any ADC, the sampling clock input must be driven with a
clean, low jitter signal.
Figure 9 shows a simplified version of a typical ADC sample clock input. In this case the input pins are labeled
ENC± for Encode while some ADCs label the inputs CLK±
for Clock. The input is composed of a differential limiting
amplifier stage followed by a buffer that directly controls
the ADC’s track and hold stage.
The sample clock input amplifier also benefits from a
fast slewing input signal as the amplifier has noise of its
own. By slewing through the crossover region quickly,
the amplifier noise creates less jitter than if the transition
were slow.
Rev. 0
18
For more information www.analog.com
LTC6955
APPLICATIONS INFORMATION
Using the LTC6955 to Drive ADC Sample Clock Inputs
VDD
The LTC6955’s CML outputs are designed to interface
with standard CML or LVPECL devices while driving transmission lines with far-end termination. Figure 11 shows
DC coupled and AC coupled output configurations for the
CML outputs.
1.2V
ENC+
10k
OUTx+
ENC–
6955 F09
CLK+
ZO
LTC6955
100Ω
OUTx–
ZO
CLK–
OUTx+
ZO
CLK+
ADC
ADCs THAT CAN
ACCEPT A 2.2V
COMMON MODE
SIGNAL
ADC
AC-COUPLED
INTO LVDS OR
ADCs WITH A
SELF BIASED
INPUT
Figure 9. Simplified Sample Clock Input Circuit
As shown in Figure 9, the ADC’s sample clock input is
typically differential, with a differential sampling clock
delivering the best performance. Figure 9 also shows
the sample clock input having a different common mode
input voltage than the LTC6955’s CML outputs. Most ADC
applications will require AC coupling to convert between
the two common mode voltages.
LTC6955
100Ω
OUTx–
ZO
CLK–
6955 F11
Figure 11. OUTx CML Connections to ADC
Sample Clock Inputs (ZO = 50Ω)
Transmission Lines and Termination
Interconnection of high speed signaling with fast rise
and fall times requires the use of transmission lines with
properly matched termination. The transmission lines
may be stripline, microstrip or any other design topology. A detailed discussion of transmission line design
is beyond the scope of this data sheet. Any mismatch
between the transmission line’s characteristic impedance
and the terminating impedance results in a portion of
the signal reflecting back toward the other end of the
transmission line. In the extreme case of an open or short
circuit termination, all of the signal is reflected back. This
signal reflection leads to overshoot and ringing on the
waveform. Figure 10 shows the preferred method of farend termination of the transmission line.
ZO
100Ω
ZO
6955 F10
Figure 10. Far-End Transmission Line Termination (Z0 = 50Ω)
Rev. 0
For more information www.analog.com
19
LTC6955
TYPICAL APPLICATIONS
Generation of 7.25GHz, 52fs ADC SNR Jitter Clocks Using LTC6952 and LTC6955-1
OUT0±
OUT1±
OUT2±
OUT3±
OUT4±
OUT5±
OUT7±
OUT9±
FILT
SEL3
SEL2
3.3V
3.3V
10k
FB
MMZ0603
3.3V
49.9Ω
Crystek
CVCO55XT7250-7250
SEL1
SEL0
VD+
LTC6955-1
BUFFER
VOUT+ (PIN 6)
VOUT+
OUT6–
VIN+
1pF
100Ω
OUT8+
/1
OUT8–
1nH
1pF
fVCO
0.1µF
OUT6+
/1
IN+
POWERED DOWN OR
ADDITIONAL 7.25GHZ CLOCKS
100Ω
ADJUST LTC6952 ADEL
REGISTERS TO ALIGN
SYSREF PAIRS TO
LTC6955-1 CLOCKS
0.1µF
0.1µF
7.25GHz
CLOCKS
0.1µF
3.3V
VREF+
VVCO+
VCO+
OUT10+
IN–
/2
OUT10–
VTUNE
fOUT = 3.625GHz
160Ω
OUT9 –
1µF
1µF
100Ω
REF+
49.9Ω
1µF
TO SYNC OUTPUTS:
TOGGLE SSYNC REGISTER BIT
REF –
EZS_SRQ+
EZS_SRQ–
VD+ VOUT+
3.3V
100Ω
0.1µF
CAN BE USED AS
CLOCKS ≤ 3.625GHZ
OR SYSREFS
6955 TA02a
400
3.625GHz (LTC6952)
7.25GHz (LTC6955–1)
CLOCK & SYSREF (mV)
0
–120
–130
–140
–150
–160 LTC6955–1 RMS JITTER = 52fs
LTC6952 RMS JITTER = 93fs
EQUIVALENT ADC SNR METHOD
–170
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
OUT0±
OUT1±
OUT2±
OUT3±
OUT4±
OUT5±
OUT6±
OUT7±
OUT10±
7.25GHz JESD204B
CLK to SYSREF Alignment
Calibration Over Temperature
LTC6955-1 and LTC6952
Phase Noise fVCO = 7.25GHz
PHASE NOISE (dBc/Hz)
0.1µF
6.8nF
63Ω
Crystek
CCHD-575-25-125
125MHz Ref Osc
–110
0.1µF
LTC6952
CP
500nF
–100
100Ω
OUT9+
VCO–
63Ω
10nF
OUT8 –
VCP+
5V
0.1µF
OUT8+
–400 LTC6955–1
CLOCK
SYSREF VALID
CLOCK EDGE
400
LTC6952 DIE TEMP (TJ)
0
100°C, ADEL=1
25°C, ADEL=6
–40°C, ADEL=9
LTC6952
SYSREF
10M 40M
–400
–500
6955 TAO2b
–250
0
TIME (ps)
250
500
6955 TAO2c
Rev. 0
20
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LTC6955
PACKAGE DESCRIPTION
UKG
Package
UKG Package
52-Lead
QFN(7mm
(7mm× 8mm)
× 8mm)
52-LeadPlastic
Plastic QFN
(ReferenceLTC
LTC DWG
DWG ##05-08-1729
RevRev
Ø) Ø)
(Reference
05-08-1729
7.50 ±0.05
6.10 ±0.05
5.50 REF
(2 SIDES)
0.70 ±0.05
6.45 ±0.05
6.50 REF 7.10 ±0.05 8.50 ±0.05
(2 SIDES)
5.41 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
(2 SIDES)
0.75 ±0.05
0.00 – 0.05
R = 0.115
TYP
5.50 REF
(2 SIDES)
51
52
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
8.00 ±0.10
(2 SIDES)
6.50 REF
(2 SIDES)
6.45 ±0.10
5.41 ±0.10
R = 0.10
TYP
TOP VIEW
0.200 REF
0.00 – 0.05
0.75 ±0.05
(UKG52) QFN REV Ø 0306
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
SIDE VIEW
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
more by
information
www.analog.com
subject to change without notice. No license For
is granted
implication or
otherwise under any patent or patent rights of Analog Devices.
21
LTC6955
TYPICAL APPLICATION
Generation of 4GHz, 52fs ADC SNR Jitter Clocks Using LTC6952 and LTC6955
LTC6955 vs LTC6952 4GHz Phase Noise
–100
SEL3
SEL2
10kΩ
3.3V
SEL1
SEL0
LTC6955
BUFFER
V D+
3.3V
VOUT+
/1
OUT0±
OUT1±
OUT2±
OUT3±
OUT4±
OUT5±
OUT7±
OUT9±
Crystek
CVCO55CC4000-4000
fVCO
0.1µF
0.1µF
3.3V
30Ω
VIN+
/1
0.1µF
100Ω
100Ω
IN–
/1
VTUNE
OUT10–
VCO+
160Ω
VCO–
LTC6952
1µF
100Ω
REF+
0.47µF
LTC6952Wizard REGISTER VALUES:
FILE: LTC6952_LTC6955_4GHz
49.9Ω
TO SYNC OUTPUTS:
TOGGLE SSYNC REGISTER BIT
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M 40M
1µF
0.1µF
100Ω
REF –
EZS_SRQ+
EZS_SRQ–
VD+ VOUT+
3.3V
OUT2 –
OUT1±
OUT3±
OUT4±
OUT5±
OUT6±
OUT7±
OUT8±
OUT9±
OUT10±
0.1µF
0.1µF
OUT2+
CP
Crystek
CCHD-575-25-100
100MHz Ref Osc
LTC6952 (6 OUTPUTS ON)
LTC6955 (ALL OUTPUT ON)
OUT0+
OUT0 –
VCP+
5V
1µF
1.2µF
VVCO+ VREF+
22nF
48.7Ω
–150
3.3V
48.7Ω
33nF
–140
6955 TA03b
0.1µF
fOUT = 4GHz
–130
–170
4GHz CLOCKS
OUT10+
75Ω
–120
–160
0.1µF
0.1µF
OUT8+
OUT8–
IN+
POWERED DOWN OR
ADDITIONAL 4GHZ CLOCKS
OUT6+
OUT6–
LTC6955 RMS JITTER = 52fs
LTC6952 RMS JITTER = 78fs
EQUIVALENT ADC SNR METHOD
–110
PHASE NOISE (dBc/Hz)
FILT
100Ω
SYSREF PAIRS TO
LTC6955 CLOCKS
0.1µF
CAN BE USED AS
CLOCKS ≤ 4GHZ
OR SYSREFS
6955 TA03a
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC6952
Ultralow Jitter, 4.5GHz PPL with 11 Outputs and
JESD204B Support
PLL with Eleven Independent CML Outputs with Dividers and Delays,
65fs Additive ADC SNR Jitter
LTC6953
Ultralow Jitter, 4.5GHz Clock Distributor with 11
Outputs and JESD204B Support
Eleven Independent CML Outputs with Dividers and Delays,
65fs Additive ADC SNR Jitter
LTC6945/
LTC6946
Ultralow Noise and Spurious Integer-N Synthesizers
370MHz to 6.39GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor,
–157dBc/Hz Wideband Output Phase Noise Floor
LTC6947/
LTC6948
Ultralow Noise and Spurious Frac-N Synthesizers
350MHz to 6.39GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor,
–157dBc/Hz Wideband Output Phase Noise Floor
LTC6950
1.4GHz Low Phase Noise, Low Jitter PLL with Clock
Distribution
Four Independent LVPECL Outputs with 18fsRMS Additive Jitter
(12kHz to 20MHz)
LTC6951
Ultralow Jitter Multioutput Clock Synthesizer with
Integrated VCO
Four Independent CML Outputs and One LVDS Output, Integrated VCO,
110fs ADC SNR Jitter
LTC6954
Low Phase Noise, Triple Output Clock Distribution
Divider/Driver
LVPECL, LVDS and CMOS Outputs with < 20fsRMS Additive Jitter
(12kHz to 20MHz)
Rev. 0
22
12/18
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For more information www.analog.com
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