19-1771; Rev 0; 9/00
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
Features
The MAX9110/MAX9112 single/dual low-voltage differential signaling (LVDS) transmitters are designed for
high-speed applications requiring minimum power consumption, space, and noise. Both devices support
switching rates exceeding 500Mbps while operating
from a single +3.3V supply, and feature ultra-low 250ps
(max) pulse skew required for high-resolution imaging
applications, such as laser printers and digital copiers.
The MAX9110 is a single LVDS transmitter, and the
MAX9112 is a dual LVDS transmitter.
Both devices conform to the EIA/TIA-644 LVDS standard.
They accept LVTTL/CMOS inputs and translate them to
low-voltage (350mV) differential outputs, minimizing electromagnetic interference (EMI) and power dissipation.
These devices use a current-steering output stage, minimizing power consumption, even at high data rates. The
MAX9110/MAX9112 are available in space-saving 8-pin
SOT23 and SO packages. Refer to the MAX9111/
MAX9113 data sheet for single/dual LVDS line receivers.
♦ Low 250ps (max) Pulse Skew for High-Resolution
Imaging and High-Speed Interconnect
♦ Space-Saving 8-Pin SOT23 and SO Packages
♦ Pin-Compatible Upgrades to DS90LV017/017A
and DS90LV027/027A (SO Packages)
♦ Guaranteed 500Mbps Data Rate
♦ Low 22mW Power Dissipation at 3.3V
(31mW for MAX9112)
♦ Conform to EIA/TIA-644 Standard
♦ Single +3.3V Supply
♦ Flow-Through Pinout Simplifies PC Board Layout
♦ Driver Outputs High Impedance when Powered Off
Ordering Information
________________________Applications
Laser Printers
Network Switches/Routers
Digital Copiers
LCD Displays
Cellular Phone Base
Stations
Backplane Interconnect
Clock Distribution
TEMP.
RANGE
PINPACKAGE
TOP
MARK
MAX9110EKA-T
-40°C to +85°C
8 SOT23-8
AADN
MAX9110ESA
-40°C to +85°C
8 SO
MAX9112EKA-T
-40°C to +85°C
8 SOT23-8
MAX9112ESA
-40°C to +85°C
8 SO
PART
Telecom Switching
Equipment
—
AADO
—
Typical Operating Circuit appears at end of data sheet.
Pin Configurations/Functional Diagrams/Truth Table
TOP VIEW
MAX9110
MAX9110
MAX9112
MAX9112
VCC 1
8
DO-
DIN 1
8
DO-
VCC 1
8
DO1- DIN1 1
8
DO1-
DIN 2
7
DO+ GND 2
7
DO+
DIN1 2
7
DO1+ GND 2
7
DO1+
N.C.
3
6
N.C.
N.C.
3
6
N.C.
DIN2
3
6
DO2+ DIN2
3
6
DO2+
GND 4
5
N.C.
VCC 4
5
N.C.
GND 4
5
DO2-
VCC 4
5
DO2-
SO
DIN_
SOT23
SO
SOT23
DO_+
DO_-
L
H
L
H
H
L
0.8V < VDIN_ < 2.0V
X
X
H = LOGIC LEVEL HIGH
L = LOGIC LEVEL LOW
X = UNDETERMINED
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX9110/MAX9112
General Description
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC to GND) ..................................-0.3V to +4V
Input Voltage (VDIN_ to GND).....................-0.3V to (VCC + 0.3V)
Output Voltage (VDO_+, VDO_- to GND or VCC) ...-0.3V to +3.9V
Output Short-Circuit Duration
(DO_+, DO_- to VCC or GND) ................................Continuous
ESD Protection (Human Body Model, DO_+, DO_-)..........±11kV
Continuous Power Dissipation (TA = +70°C)
8-Pin SOT23 (derate 7.52mW/°C above +70°C)...........602mW
8-Pin SO (derate 5.88mW/°C above +70°C)...............471mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering,10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100Ω ±1%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA =
+25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Differential Output Voltage
Change in Magnitude of Output
Voltage for Complementary
Output States
Offset Voltage
VOD
Figure 1
250
350
450
mV
ΔVOD
Figure 1
0
2
35
mV
VOS
Figure 1
1.125
1.25
1.375
V
Change in Magnitude of Offset
Voltage for Complementary
Output States
ΔVOS
Figure 1
0
2
25
mV
+10
µA
-20
mA
VCC
V
Power-Off Leakage Current
IO(OFF)
Short-Circuit Output Current
IO(SHORT)
CONDITIONS
VDO_ _ = 0 or VCC, VCC = 0 or open
-10
DIN_ = VCC, VDO_+ = 0 or
DIN_ = GND, VDO_- = 0
Input High Voltage
VIH
2.0
Input Low Voltage
VIL
Input Current High
IIH
DIN_ = VCC or 2V
Input Current Low
IIL
DIN_ = GND or 0.8V
No-Load Supply Current
ICC
No load, DIN_ = VCC or 0
Supply Current
ICC
DIN_ = VCC or 0
GND
0
-20
10
0.8
V
20
µA
-3
0
µA
4.5
6
mA
MAX9110
6.7
8
MAX9112
9.4
13
mA
AC CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V,
TA = +25°C.) (Notes 3, 4, 5; Figures 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential High-to-Low
Propagation Delay
tPHLD
1
1.54
2.5
ns
Differential Low-to-High
Propagation Delay
tPLHD
1
1.58
2.5
ns
Differential Pulse Skew
|tPHLD - tPLHD| (Note 6)
tSKD1
40
250
ps
Channel-to-Channel Skew (Note 7)
tSKD2
70
400
ps
2
_______________________________________________________________________________________
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
(VCC = +3.0V to +3.6V, RL = 100Ω ±1%, CL = 5pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V,
TA = +25°C.) (Notes 3, 4, 5; Figures 2, 3)
PARAMETER
SYMBOL
Part-to-Part Skew
High-to-Low Transition Time
CONDITIONS
MIN
TYP
MAX
tSKD3
(Note 8)
1
tSKD4
(Note 9)
1.5
tTHL
Low-to-High Transition Time
tTLH
Maximum Operating Frequency
fMAX
(Note 10)
0.25
0.6
1
0.25
0.6
1
UNITS
ns
ns
ns
250
MHz
Note 1: Maximum and minimum limits over temperature are guaranteed by design. Devices are production tested at TA = +25°C.
Note 2: By definition, current into the device is positive and current out of the device is negative. Voltages are referred to device
ground except VOD.
Note 3: AC parameters are guaranteed by design and characterization.
Note 4: CL includes probe and fixture capacitance.
Note 5: Signal generator conditions for dynamic tests: VOL = 0, VOH = 3V, f = 20MHz, 50% duty cycle, RO = 50Ω, tR ≤ 1ns, and tF ≤
1ns (0 to 100%).
Note 6: tSKD1 is the magnitude difference of differential propagation delays in a channel; tSKD1 = | tPHLD - tPLHD |.
Note 7: tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of the other channel on the
same device (MAX9112).
Note 8: tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5°C
of each other.
Note 9: tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply
and temperature ranges.
Note 10: fMAX signal generator conditions: VOL = 0, VOH = +3V, frequency = 250MHz, tR ≤ 1ns, tF ≤ 1ns (0 to 100%) 50% duty cycle.
Transmitter output criteria: duty cycle = 45% to 55%, VOD ≥ 250mV.
Typical Operating Characteristics
(VCC = +3.3V, RL = 100Ω, CL = 5pF, VIH = +3V, VIL = GND, fIN = 20MHz, TA = +25°C, unless otherwise noted.) (Figures 2, 3)
8.0
B
C
A
MAX9110 toc02
7.2
7.1
7.0
6.9
6.8
6.7
6.6
7.0
2.0
1.8
PROPAGATION DELAY (ns)
SUPPLY CURRENT (mA)
8.5
7.5
7.3
CURRENT SUPPLY (mA)
A: VCC = +3.0V
B: VCC = +3.3V
C: VCC = +3.6V
9.0
7.4
MAX9110 toc01
9.5
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
MAX9110 toc03
MAX9110
SUPPLY CURRENT
vs. INPUT FREQUENCY
tPLHD
1.6
tPHLD
1.4
1.2
1.0
6.5
0.8
6.4
6.5
1
100
10k
1M
INPUT FREQUENCY (Hz)
100M
1G
-40
-15
10
35
TEMPERATURE (°C)
60
85
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
3
MAX9110/MAX9112
AC CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL = 100Ω, CL = 5pF, VIH = +3V, VIL = GND, fIN = 20MHz, TA = +25°C, unless otherwise noted.) (Figures 2, 3)
DIFFERENTIAL PULSE SKEW
vs. SUPPLY VOLTAGE
tPHLD
1.4
1.2
1.0
60
40
20
0
0.8
-15
10
35
60
3.1
TRANSITION TIME vs. SUPPLY VOLTAGE
3.2
3.3
3.4
3.5
580
560
TRANSITION TIME (ps)
600
tTLH
tTHL
450
350
300
3.2
3.3
540
520
tTHL
500
3.4
3.5
480
460
MAX9110 toc06
1.40
1.30
1.25
1.20
1.15
1.10
1.05
OUTPUT LOW
1.00
-40
-15
10
35
60
3.0
85
3.1
3.2
3.3
DIFFERENTIAL OUTPUT VOLTAGE
vs. LOAD RESISTANCE
DIFFERENTIAL OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
375
350
325
300
275
450
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9110 toc10
400
425
VCC = +3.3V
400
VCC = +3V
375
350
VCC = +3.6V
325
300
275
250
250
3.0
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
3.5
3.6
3.4
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
425
85
OUTPUT HIGH
1.35
420
450
60
1.45
440
3.6
35
OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
tTLH
SUPPLY VOLTAGE (V)
DIFFERENTIAL OUTPUT VOLTAGE (mV)
10
1.50
400
3.1
-15
TEMPERATURE (°C)
TRANSITION TIME vs. TEMPERATURE
400
4
-40
MAX9110 toc08
650
3.0
20
3.6
600
MAX9110 toc07
700
500
40
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
550
60
0
3.0
85
OUTPUT VOLTAGE (V)
-40
80
MAX9110 toc09
1.6
80
100
MAX9110 toc11
tPLHD
MAX9110 toc05
DIFFERENTIAL PULSE SKEW (ps)
1.8
PROPAGATION DELAY (ns)
100
MAX9110 toc04
2.0
DIFFERENTIAL PULSE SKEW
vs. TEMPERATURE
DIFFERENTIAL PULSE SKEW (ps)
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
TRANSITION TIME (ps)
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
75.0
87.5
100.0
112.5
125.0
137.5
150.0
LOAD RESISTANCE (Ω)
_______________________________________________________________________________________
3.5
3.6
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
OUTPUT LOW VOLTAGE
vs. LOAD RESISTANCE
OUTPUT HIGH VOLTAGE
vs. LOAD RESISTANCE
1.09
1.42
1.41
VCC = +3V
1.40
1.39
MAX9110 toc13
VCC = +3.6V
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
1.44
1.43
1.10
MAX9110 toc12
1.45
VCC = +3.3V
1.38
1.08
VCC = +3.6V
1.07
1.06
1.05
VCC = +3V
1.04
VCC = +3.3V
1.03
1.37
1.02
1.36
1.01
1.00
1.35
75.0
87.5
100.0
112.5
125.0
137.5
75.0
150.0
87.5
100.0
112.5
125.0
137.5
150.0
LOAD RESISTANCE (Ω)
LOAD RESISTANCE (Ω)
Pin Description
PIN
MAX9110
NAME
MAX9112
FUNCTION
SOT23
SO
SOT23
SO
4
1
4
1
VCC
1
2
—
—
DIN
—
—
1, 3
2, 3
DIN1, DIN2
3, 5, 6
3, 5, 6
—
—
N.C.
No Connection. Not internally connected.
2
4
2
4
GND
Ground
7
7
—
—
DO+
—
—
6, 7
6, 7
DO2+, DO1+
8
8
—
—
DO-
—
—
5, 8
5, 8
DO2-, DO1-
Positive Supply
Transmitter Input
Noninverting Transmitter Output
Inverting Transmitter Output
Detailed Description
The MAX9110/MAX9112 single/dual LVDS transmitters
are intended for high-speed, point-to-point, low-power
applications. These devices accept CMOS/LVTTL
inputs with data rates exceeding 500Mbps. The
MAX9110/MAX9112 reduce power consumption and
EMI by translating these signals to a differential voltage
in the 250mV to 450mV range across a 100Ω load while
drawing only 9.4mA of supply current for the dualchannel MAX9112.
A current-steering approach induces less ground
bounce and no shoot-through current, enhancing noise
margin and system speed performance. The output
_______________________________________________________________________________________
5
MAX9110/MAX9112
Typical Operating Characteristics (continued)
(VCC = +3.3V, RL = 100Ω, CL = 5pF, VIH = +3V, VIL = GND, fIN = 20MHz, TA = +25°C, unless otherwise noted.) (Figures 2, 3)
CL
DO_+
DO_ +
RL/2
DIN_
S
VCC
VOS
GND
VOD
DIN_
GENERATOR
VO
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
RL/2
RL
DO_ -
50Ω
CL
DO_-
Figure 1. LVDS Transmitter VOD and VOS Test Circuit
Figure 2. Transmitter Propagation Delay and Transition Time
Test Circuit
3V
DIN_
1.5V
1.5V
tPLHD
tPHLD
0
DO_ -
VOH
0V DIFFERENTIAL
0
DO_+
VOL
80%
0
VDIFF
80%
VDIFF = VDO_+ - VDO_-
0
20%
20%
tTLH
tTHL
Figure 3. Transmitter Propagation Delay and Transition Time Waveforms
stage presents a symmetrical, high-impedance output,
reducing differential reflection and timing distortion. The
driver outputs are short circuit current limited and enter a
high-impedance state when the device is not powered.
LVDS Operation
The LVDS interface standard is a signaling method
intended for point-to-point communication over a controlled impedance medium as defined by the EIA/TIA644 LVDS standard. The LVDS standard uses a lower
voltage swing than other common communication standards, achieving higher data rates with reduced power
consumption while reducing EMI emissions and system
susceptibility to noise.
LVDS transmitters such as the MAX9110/MAX9112
convert CMOS/LVTTL signals to low-voltage differential
signals at rates in excess of 500Mbps. The MAX9110/
MAX9112 current-steering architecture requires a resistive load to terminate the signal and complete the trans6
mission loop. Because the device switches the direction of current flow and not voltage levels, the actual
output voltage swing is determined by the value of the
termination resistor at the input of an LVDS receiver.
Logic states are determined by the direction of current
flow through the termination resistor. With a typical
3.5mA output current, the MAX9110/MAX9112 produce
an output voltage of 350mV when driving a 100Ω load.
The steady-state-voltage peak-to-peak swing is twice
the differential voltage, or 700mV (typ).
Applications Information
Supply Bypassing
Bypass VCC with high-frequency surface-mount ceramic
0.1µF and 0.001µF capacitors in parallel, as close to the
device as possible, with the smaller valued capacitor the
closest. For additional supply bypassing, place a 10µF
tantalum or ceramic capacitor at the point where power
enters the circuit board.
_______________________________________________________________________________________
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
Board Layout
For LVDS applications, a four-layer PC board that provides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the input and LVDS signals from each other to prevent coupling. Separate the
input and LVDS signal planes with the power and ground
planes for best results.
Typical Operating Circuit
+3.3V
+3.3V
Cables and Connectors
Transmission media should have a differential characteristic impedance of about 100Ω. Use cables and connectors that have matched impedance to minimize
impedance discontinuities.
Avoid the use of unbalanced cables, such as ribbon or
simple coaxial cable. Balanced cables, such as twisted
pair, offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
0.001μF
DIN_
0.001μF
0.1μF
RT = 100Ω
DRIVER
RECEIVER
0.1μF
OUT_
LVDS
MAX9110
MAX9112
MAX9111
MAX9113
Termination
Termination resistors should match the differential characteristic impedance of the transmission line. Because
the MAX9110/MAX9112 are current-steering devices,
an output voltage will not be generated without a termination resistor. Output voltage levels are dependent
upon the termination resistor value. Resistance values
may range between 75Ω and 150Ω.
Minimize the distance between the termination resistor
and receiver inputs. Use a single 1% to 2% surfacemount resistor across the receiver inputs.
Chip Information
MAX9110 TRANSISTOR COUNT: 765
MAX9112 TRANSISTOR COUNT: 765
PROCESS: CMOS
_______________________________________________________________________________________
7
MAX9110/MAX9112
Differential Traces
Output trace characteristics affect the performance of
the MAX9110/MAX9112. Use controlled impedance
traces to match trace impedance to both transmission
medium impedance and termination resistor. Eliminate
reflections and ensure that noise couples as common
mode by running the differential traces close together.
Reduce skew by matching the electrical length of the
traces. Excessive skew can result in a degradation of
magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in impedance. Avoid 90° turns and
minimize the number of vias to further prevent impedance discontinuities.
Package Information
SOT23, 8L.EPS
MAX9110/MAX9112
Single/Dual LVDS Line Drivers with
Ultra-Low Pulse Skew in SOT23
MARKING
0
0
PACKAGE OUTLINE, SOT-23, 8L BODY
21-0078
G
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
工商网监
湘ICP备2023018690号
