OP249_07

Dual, Precision JFET High Speed Operational Amplifier OP249 FEATURES Fast slew rate: 22 V/μs typical Settling time (0.01%): 1.2 μs maximum Offset voltage: 300 μV maximum High open-loop gain: 1000 V/mV minimum Low total harmonic distortion: 0.002% typical Improved replacement for AD712, LT1057, OP215, TL072, and MC34082 PIN CONFIGURATIONS OUT A –IN A +IN A V– 1 2 3 4 OP249 A B 8 7 6 5 V+ OUT B 00296-001 00296-002 –IN B +IN B Figure 1. 8-Lead CERDIP (Q-8) and 8-Lead PDIP (N-8) +IN A 1 2 3 4 8 –IN A OUT A V+ OUT B APPLICATIONS Output amplifier for fast DACs Signal processing Instrumentation amplifiers Fast sample-and-holds Active filters Low distortion audio amplifiers Input buffer for ADCs Servo controllers V– +IN B –IN B A 7 6 5 OP249 B Figure 2. 8-Lead SOIC (R-8) GENERAL DESCRIPTION The OP249 is a high speed, precision dual JFET op amp, similar to the popular single op amp, the OP42. The OP249 outperforms available dual amplifiers by providing superior speed with excellent dc performance. Ultrahigh open-loop gain (1 kV/mV minimum), low offset voltage, and superb gain linearity makes the OP249 the industry’s first true precision, dual high speed amplifier. With a slew rate of 22 V/μs typical and a fast settling time of less than 1.2 μs maximum to 0.01%, the OP249 is an ideal choice for high speed bipolar DAC and ADC applications. The excellent dc performance of the OP249 allows the full accuracy of high resolution CMOS DACs to be realized. 0.01 Symmetrical slew rate, even when driving large load, such as, 600 Ω or 200 pF of capacitance and ultralow distortion, make the OP249 ideal for professional audio applications, active filters, high speed integrators, servo systems, and buffer amplifiers. The OP249 provides significant performance upgrades to the TL072, AD712, OP215, MC34082, and LT1057. 870ns 100 90 TA = 25°C VS = ±15V VO = 10V p-p RL = 10kΩ AV = 1 100 90 00296-003 00296-004 10mV 500ns 0.001 20 5V 1µs 100 1k 10k 20k Figure 3. Fast Settling (0.01%) Figure 4. Low Distortion, AV = 1, RL = 10 kΩ Figure 5. Excellent Output Drive, RL = 600 Ω Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. 00296-005 10 0% 10 0% OP249 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Pin Configurations ........................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Typical Performance Characteristics ..............................................7 Applications Information .............................................................. 13 Open-Loop Gain Linearity ....................................................... 14 Offset Voltage Adjustment ........................................................ 14 Settling Time............................................................................... 14 DAC Output Amplifier.............................................................. 15 Disscusion on Driving ADCs ................................................... 16 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 19 REVISION HISTORY 5/07—Rev. E to Rev. F Updated Format..................................................................Universal Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Table 3 and Table 4....................................................... 5 Changes to Table 5............................................................................ 6 Changes to Figure 31...................................................................... 11 Changes to Figure 37 and Figure 38............................................. 12 Deleted OP249 SPICE Macro-Model Section ............................ 14 Deleted Figure 18; Renumbered Sequentially ............................ 14 Deleted Table I ................................................................................ 15 Changes to Discussion on Driving ADCs Section..................... 17 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 9/01—Rev. D to Rev. E Edits to Features and Pin Connections ..........................................1 Edits to Electrical Characteristics .............................................. 2, 3 Edits to Absolute Maximum Ratings, Package Type, and Ordering Guide..................................................................................4 Deleted Wafer Test Limits and Dice Characteristics Section ......5 Edits to Typical Performance Characteristics................................8 Edits to Macro-Model Figure........................................................ 15 Edits to Outline Dimensions......................................................... 17 Rev. F | Page 2 of 20 OP249 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = ±15 V, TA = 25°C, unless otherwise noted. Table 1. Parameter Offset Voltage Long Term Offset Voltage 1 Offset Stability Input Bias Current Input Offset Current Input Voltage Range 2 Symbol VOS VOS IB IOS IVR Conditions Min OP249A Typ 0.2 1.5 30 6 12.5 ±11 Common-Mode Rejection Power-Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = ±11 V VS = ± 4.5 V to ±18 V VO = ±10 V, RL = 2 kΩ R L = 2 kΩ 80 1000 ±12.0 Short-Circuit Current Limit ISC Output shorted to ground ±20 Supply Current Slew Rate Gain Bandwidth Product 3 Settling Time Phase Margin Differential Input Impedance Open-Loop Output Resistance Voltage Noise Voltage Noise Density ISY SR GBW tS ΘM ZIN RO en p-p en No load, VO = 0 V RL = 2 kΩ, CL = 50 pF 10 V step 0.01% 4 0 dB gain −33 5.6 22 4.7 0.9 55 1012||6 35 2 75 26 17 16 0.003 ±15 −12.5 36 ±50 7.0 18 3.5 1.2 ±20 –33 5.6 22 4.7 0.9 55 1012||6 35 2 75 26 17 16 0.003 ±15 −12.5 90 12 1400 12.5 Max 0.5 0.8 75 25 ±11 80 31.6 500 ±12.0 –12.5 36 ±50 7.0 –12.5 90 12 1200 12.5 Min OP249F Typ 0.2 1.5 30 6 12.5 Max 0.7 1.0 75 25 Unit mV mV μV/month pA pA V V V dB μV/V V/mV V V V mA mA mA mA V/μs MHz μs Degrees Ω||pF Ω μV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz pA/√Hz V VCM = 0 V, TA = 25°C VCM = 0 V, TA = 25°C 50 18 3.5 1.2 Current Noise Density Voltage Supply Range 1 2 3 in VS 0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz fO = 1 kHz ±4.5 ±18 ±4.5 ±18 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent wafer lots at 125°C with LTPD of three. Guaranteed by CMR test. Guaranteed by design. 4 Settling time is sample tested. Rev. F | Page 3 of 20 OP249 VS = ±15 V, TA = 25°C, unless otherwise noted. Table 2. Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range 1 Symbol VOS IB IOS IVR Conditions VCM = 0 V, TA = 25°C VCM = 0 V TA = 25°C ±11 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = ±11 V VS = ±4.5 V to ±18 V VO = ±10 V; RL = 2 kΩ R L = 2 kΩ 76 500 ±12.0 Short-Circuit Current Limit ISC Output shorted to ground ±20 Supply Current Slew Rate Gain Bandwidth Product 2 Settling Time Phase Margin Differential Input Impedance Open-Loop Output Resistance Voltage Noise Voltage Noise Density ISY SR GBW tS ΘM ZIN RO en p-p en No load; VO = 0 V RL = 2 kΩ, CL = 50 pF 10 V step 0.01% 0 dB gain −33 5.6 22 4.7 0.9 55 1012||6 35 2 75 26 17 16 0.003 ±15 −12.5 36 ±50 7.0 −12.0 90 12 1100 12.5 Min OP249G Typ 0.4 40 10 12.5 Max 2.0 75 25 Unit mV pA pA V V V dB μV/V V/mV V V V mA mA mA mA V/μs MHz μs Degree Ω||pF Ω μV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz pA/√Hz V 50 18 1.2 Current Noise Density Voltage Supply Range 1 2 in VS 0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz fO = 1 kHz ±4.5 ±18 Guaranteed by CMR test. Guaranteed by design. Rev. F | Page 4 of 20 OP249 VS = ±15 V, −40°C ≤ TA ≤ +85°C for F grade and −55°C ≤ TA ≤ +125°C for A grade, unless otherwise noted. Table 3. Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current 1 Input Offset Current1 Input Voltage Range 2 Symbol VOS TCVOS IB IOS IVR ±11 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = ±11 V VS = ±4.5 V to ±18 V RL = 2 kΩ; VO = ±10 V R L = 2 kΩ 76 500 ±12 Supply Current 1 2 Conditions Min OP249A Typ Max 0.12 1.0 1 4 0.04 12.5 −12.5 110 5 1400 12.5 −12.5 5.6 5 20 4 Min OP249F Typ Max 0.5 1.1 2.2 0.3 0.02 12.5 6 4.0 1.2 Unit mV μV/°C nA nA V V V dB μV/V V/mV V V V mA ±11 80 50 250 ±12 7.0 −12.5 5.6 7.0 −12.5 90 7 1200 12.5 100 ISY No load, VO = 0 V TA = 85°C for F grade; TA = 125°C for A grade. Guaranteed by CMR test. VS = ±15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted. Table 4. Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current 1 Input Offset Current1 Input Voltage Range 2 Symbol VOS TCVOS IB IOS IVR Conditions Min OP249G Typ 1.0 6 0.5 0.04 12.5 −12.5 95 10 1200 12.5 −12.5 5.6 Max 3.6 25 4.5 1.5 Unit mV μV/°C nA nA V V V dB μV/V V/mV V V V mA ±11 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = ±11 V VS = ±4.5 V to ±18 V RL = 2 kΩ; VO = ±10 V R L = 2 kΩ 76 250 ±12.0 Supply Current 1 2 100 ISY No load, VO = 0 V 7.0 TA = 85°C. Guaranteed by CMR test. Rev. F | Page 5 of 20 OP249 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage Input Voltage 2 Differential Input Voltage2 Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range OP249A (Q) OP249F (Q) OP249G (N, R) Junction Temperature Range OP249A (Q), OP249F (Q) OP249G (N, R) Lead Temperature (Soldering, 60 sec) 1 2 1 Rating ±18 V ±18 V 36 V Indefinite −65°C to +175°C −55°C to +125°C −40°C to +85°C −40°C to +85°C −65°C to +175°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Resistance Package Type 8-Lead CERDIP (Q) 8-Lead PDIP (N) 8-Lead SOIC (R) 1 θJA1 134 96 150 θJC 12 37 41 Unit °C/W °C/W °C/W Absolute maximum ratings apply to packaged parts, unless otherwise noted. For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage. θJA is specified for worst-case mounting conditions, that is, θJA is specified for device in socket for CERDIP and PDIP packages; θJA is specified for device soldered to printed circuit board for SOIC package. ESD CAUTION Rev. F | Page 6 of 20 OP249 TYPICAL PERFORMANCE CHARACTERISTICS 120 100 TA = 25°C VS = ±15V RL = 2kΩ 0 GAIN 45 90 Θm = 55 20 0 –20 1k 135 180 225 100M 120 TA = 25°C VS = ±15V OPEN-LOOP GAIN (dB) 80 60 40 POWER SUPPLY REJECTION (dB) 100 80 +PSRR 60 –PSRR 40 PHASE PHASE (°C) 20 00296-009 10k 100k 1M 10M 00296-006 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Open-Loop Gain, Phase vs. Frequency 65 VS = ±15V 10 28 Figure 9. Power Supply Rejection vs. Frequency 60 8 GAIN BANDWIDTH PRODUCT (MHz) 26 VS = ±15V RL = 2kΩ CL = 50pF PHASE MARGIN (°C) SLEW RATE (V/µs) 24 –SR 22 +SR Θm 55 GBW 50 4 6 20 18 00296-010 –50 –25 0 25 50 75 100 00296-007 45 –75 2 125 16 –75 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Phase Margin, Gain Bandwidth Product vs. Temperature 140 120 100 80 60 40 20 0 100 18 00296-008 Figure 10. Slew Rate vs. Temperature 28 TA = 25°C VS = ±15V 26 COMMON-MODE REJECTION (dB) TA = 25°C VS = ±15V RL = 2kΩ SLEW RATE (V/µs) 24 22 20 16 1k 10k 100k 1M 10M 0 0.2 0.4 0.6 0.8 1.0 FREQUENCY (Hz) DIFFERENTIAL INPUT VOLTAGE (V) Figure 8. Common-Mode Rejection vs. Frequency Figure 11. Slew Rate vs. Differential Input Voltage Rev. F | Page 7 of 20 00296-011 OP249 35 TA = 25°C VS = ±15V 30 0.01 TA = 25°C VS = ±15V VO = 10V p-p RL = 10kΩ AV = 1 SLEW RATE (V/µs) 25 NEGATIVE 20 POSITIVE 15 10 00296-012 00296-015 5 0 100 200 300 400 CAPACITIVE LOAD (pF) 500 0.001 20 100 1k 10k 20k Figure 12. Slew Rate vs. Capacitive Load 10 8 6 TA = 25°C VS = ±15V AVCL = 1 0.1% 4 2 0 –2 –4 –6 –8 –10 0 200 400 600 800 SETTLING TIME (ns) 0.1% 00296-013 Figure 15. Distortion vs. Frequency 0.01 TA = 25°C VS = ±15V VO = 10V p-p RL = 2kΩ AV = 1 OUTPUT STEP SIZE (V) 0.01% 0.01% 1000 0.001 20 100 1k 10k 20k Figure 13. Step Size vs. Settling Time 100 TA = 25°C VS = ±15V Figure 16. Distortion vs. Frequency 0.01 TA = 25°C VS = ±15V VO = 10V p-p RL = 600Ω AV = 1 VOLTAGE NOISE DENSITY (nV/ Hz) 80 60 40 20 00296-014 0 0 100 FREQUENCY (Hz) 1k 10k 0.001 20 100 1k 10k 20k Figure 14. Voltage Noise Density vs. Frequency Figure 17. Distortion vs. Frequency Rev. F | Page 8 of 20 00296-017 00296-016 OP249 0.1 TA = 25°C VS = ±15V VO = 10V p-p RL = 10kΩ AV = 1 +1µV 500mV 1s –1µV 00296-018 0.01 20 100 1k 10k 20k BANDWIDTH (0.1Hz TO 10Hz) TA = 25°C, VS = ±15V Figure 18. Distortion vs. Frequency 60 0.1 TA = 25°C VS = ±15V VO = 10V p-p RL = 2kΩ AV = 10 50 CLOSED-LOOP GAIN (dB) Figure 21. Low Frequency Noise TA = 25°C VS = ±15V AVCL = 100 40 30 20 10 0 –10 AVCL = 10 AVCL = 5 AVCL = 1 00296-022 00296-019 0.01 20 –20 1k 10k 100k 1M 10M 00296-021 100M 100 1k 10k 20k FREQUENCY (Hz) Figure 19. Distortion vs. Frequency 50 Figure 22. Closed-Loop Gain vs. Frequency 0.1 TA = 25°C VS = ±15V VO = 10V p-p RL = 600kΩ AV = 10 40 TA = 25°C VS = ±15V IMPEDANCE (Ω) 30 AVCL = 1 20 AVCL = 10 10 00296-023 AVCL = 100 00296-020 0.01 20 0 100 1k 10k 100k 1M 10M 100 1k 10k 20k FREQUENCY (Hz) Figure 20. Distortion vs. Frequency Figure 23. Closed-Loop Output Impedance vs. Frequency Rev. F | Page 9 of 20 OP249 30 20 15 OUTPUT VOLTAGE SWING (V) 25 TA = 25°C RL = 2kΩ OUTPUT VOLTAGE (V p-p) 10 5 0 –5 –10 00296-027 20 15 AD8512 10 OP249 00296-024 5 AD712 0 1k –15 –20 1M FREQUENCY (Hz) 10M 0 ±5 ±10 SUPPLY VOLTAGE (V) ±15 ±20 Figure 24. Output Voltage vs. Frequency 90 80 70 VS = ±15V RL = 2kΩ VIN = 100mV p-p Figure 27. Output Voltage Swing vs. Supply Voltage 6.0 VS = ±15V NO LOAD 5.8 OVERSHOOT (%) 60 50 40 30 20 AVCL = 1 NEGATIVE EDGE AVCL = 1 POSITIVE EDGE SUPPLY CURRENT (mA) 00296-025 5.6 5.4 00296-028 10 0 AVCL = 5 0 100 200 300 400 500 5.2 –75 –50 –25 0 25 50 75 100 125 LOAD CAPACITANCE (pF) TEMPERATURE (°C) Figure 25. Small Overshoot vs. Load Capacitance 16 14 TA = 25°C VS = ±15V 5.8 +VOHM = |–VOHM| 10 8 6 4 00296-026 Figure 28. Supply Current vs. Temperature 6.0 MAXIMUM OUTPUT SWING (V) SUPPLY CURRENT (mA) 12 5.6 TA = +125°C 5.4 TA = –55°C TA = +25°C 5.2 2 0 100 1k LOAD RESISTANCE (Ω) 10k 5.0 0 5 10 SUPPLY VOLTAGE (V) 15 20 Figure 26. Maximum Output Voltage Swing vs. Load Resistance Figure 29. Supply Current vs. Supply Voltage Rev. F | Page 10 of 20 00296-029 OP249 180 160 140 120 UNITS 100 80 60 40 00296-030 10k TA = 25°C VS = ±15V 415 × OP249 (830 OP AMPS) INPUT BIAS CURRENT (pA) VS = ±15V VCM = 0V 1k 100 10 00296-033 20 0 –1000 –800 –600 –400 –200 0 200 400 600 800 1000 1 –75 –50 –25 0 25 50 75 100 125 VOS (µV) TEMPERATURE (°C) Figure 30. VOS Distribution (N-8) Figure 33. Input Bias Current vs. Temperature 300 270 240 210 180 UNITS 150 120 90 60 30 0 0 2 4 6 8 10 12 14 16 18 20 22 00296-031 104 VS = ±15V –40°C TO +85°C (830 OP AMPS) TA = 25°C VS = ±15V 103 BIAS CURRENT (pA) 102 101 00296-034 24 100 –15 –10 –5 0 5 10 15 TCVOS (µV/°C) COMMON-MODE VOLTAGE (V) Figure 31. TCVOS Distribution (N-8) 50 VS = ±15V 40 40 50 Figure 34. Bias Current vs. Common-Mode Voltage TA = 25°C VS = ±15V 30 INPUT BIAS CURRENT (pA) 00296-032 OFFSET VOLTAGE (µV) 30 20 20 10 10 00296-035 0 0 1 2 3 4 5 0 0 2 4 6 8 10 TIME AFTER POWER APPLIED (Minutes) TIME AFTER POWER APPLIED (Minutes) Figure 32. Offset Voltage Warm-Up Drift Figure 35. Bias Current Warm-Up Drift Rev. F | Page 11 of 20 OP249 80 80 SHORT-CIRCUIT OUTPUT CURRENT (mA) TA = 25°C VCM = 0V VS = ±15V SOURCE 60 SINK INPUT OFFSET CURRENT (pA) 60 40 40 20 00296-036 20 00296-038 0 –75 –50 –25 0 25 50 75 100 125 0 –75 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 36. Input Offset Current vs. Temperature 12000 VS = ±15V 10000 Figure 38. Short-Circuit Output Current vs. Junction Temperature OPEN-LOOP GAIN (V/mV) 8000 RL = 10kΩ 6000 RL = 2kΩ 4000 2000 00296-037 0 –75 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) Figure 37. Open-Loop Gain vs. Temperature Rev. F | Page 12 of 20 OP249 APPLICATIONS INFORMATION V+ +IN VOUT 100 90 –IN 10 0% 5V A) OP249 1µs 100 90 V– Figure 39. Simplified Schematic (1/2 OP249) 10 0% 2 00296-039 OP249 +3V 3 1/2 5V 1 1µs B) LT1057 5kΩ +18V 6 8 100 90 OP249 +3V 5 4 1/2 7 00296-040 5kΩ –18V 10 0% 00296-041 Figure 40. Burn-In Circuit 5V C) AD712 1µs The OP249 represents a reliable JFET amplifier design, featuring an excellent combination of dc precision and high speed. A rugged output stage provides the ability to drive a 600 Ω load and still maintain a clean ac response. The OP249 features a large signal response that is more linear and symmetric than previously available JFET input amplifiers. Figure 41 compares the large signal response of the OP249 to other industry-standard dual JFET amplifiers. Typically, the slewing performance of the JFET amplifier is specified as a number of V/μs. There is no discussion on the quality, that is, linearity and symmetry of the slewing response. Figure 41. Large-Signal Transient Response, AV = 1, VIN = 20 V p-p, ZL = 2 kΩ//200 pF, VS = ±15 V The OP249 was carefully designed to provide symmetrically matched slew characteristics in both the negative and positive directions, even when driving a large output load. The slewing limitation of the amplifier determines the maximum frequency at which a sinusoidal output can be obtained without significant distortion. However, it is important to note that the nonsymmetric slewing typical of previously available JFET amplifiers adds a higher series of harmonic energy content to the resulting response—and an additional dc output component. Examples of potential problems of nonsymmetric slewing behavior can be in audio amplifier applications, where a natural low distortion sound quality is desired and in servo or signal processing systems where a net dc offset cannot be tolerated. The linear and symmetric slewing feature of the OP249 makes it an ideal choice for applications that exceed the full power bandwidth range of the amplifier. Rev. F | Page 13 of 20 OP249 R4 +V 100 90 VIN R1 200kΩ R3 OP249 R2 31Ω 1/2 VOUT R5 50kΩ –V Figure 44. Offset Adjustment for Inverting Amplifier Configuration 10 0% 00296-042 +V R5 R3 50kΩ R1 200kΩ R2 33Ω –V VIN R4 50mV 1µs OP249 VOS ADJUST RANGE = ±V GAIN = VOUT VIN =1+ 1/2 VOUT Figure 42. Small-Signal Transient Response, AV = 1, ZL = 2 kΩ||100 pF, No Compensation, VS = ±15 V As with most JFET input amplifiers, the output of the OP249 can undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion does not damage the amplifier, nor does it cause an internal latch-up condition. Supply decoupling should be used to overcome inductance and resistance associated with supply lines to the amplifier. A 0.1 μF and a 10 μF capacitor should be placed between each supply pin and ground. R2 R1 R5 R4 + R2 00296-045 R5 IF R2