A6261KLJTR-T-1

A6261 Protected LED Array Driver FEATURES AND BENEFITS DESCRIPTION • AEC-Q100 qualified • Total LED drive current up to 400 mA (LP, LJ, and LY packages) or 300 mA (LJ) • Current shared equally up to 100 mA by up to 4 strings (LP and LY) • 6 to 50 V supply • Low dropout voltage • LED output short-to-ground and thermal protection • Disable on open LED detection option • Enable input for PWM control • Current slew rate limit during PWM • Current set by reference resistor • Automotive temperature range (K, –40°C to 150°C) The A6261 is a linear, programmable current regulator providing up to 100 mA from each of four outputs (LP and LY) to drive arrays of high brightness LEDs. The regulated LED current from each output, accurate to 5%, is set by a single reference resistor. Current matching in each string is better than 10% without the use of ballast resistors. Driving LEDs with constant current ensures safe operation with maximum possible light output. The A6261 in the LJ package offers two pins with 200 mA each channel (A6261LJ-1) and with 100 mA and 200 mA maximum output current (A6261LJ). PACKAGES Short detection is provided to protect the LEDs and the A6261 during a short-to-ground at any LED output pin. An open LED in any of the strings disables all outputs, but can be overridden. Shorted LED output pins or open LEDs are indicated by a fault flag. 8-pin SOICN with exposed thermal pad (suffix LJ) Output control is provided by an enable input, giving direct control for PWM applications. Outputs can be connected in parallel or left unused as required. A temperature monitor is included to reduce the LED drive current if the chip temperature exceeds a thermal threshold. 10-pin MSOP with exposed thermal pad (suffix LY) The device packages are an 8-pin SOICN (suffix LJ), a 10-pin MSOP (LY), and a 16-pin TSSOP (LP), all with exposed pad for enhanced thermal dissipation. They are lead (Pb) free, with 100% matte-tin leadframe plating. 16-pin TSSOP with exposed thermal pad (suffix LP) Not to scale + + Power input Power input VIN VIN A6261 A6261 (LP, LY Packages) (LJ Package) PWM dimming input EN LA1 FF LA2 PWM dimming input EN LA1 FF LA2 IREF IREF LA3 THTH THTH LA4 GND – GND – Typical Application Diagrams A6261A-DS, Rev. 15 MCO-0000361 February 4, 2020 A6261 Protected LED Array Driver SELECTION GUIDE Part Number Ambient Operating Temperature, TA (°C) Packing Current Package A6261KLJTR-T –40 to 125 3000 pieces per 13-in. reel LA1 = 200 mA LA2 = 100 mA 8-pin SOIC with exposed thermal pad A6261KLJTR-T-1 –40 to 125 3000 pieces per 13-in. reel LA1 = LA2 = 200 mA 8-pin SOIC with exposed thermal pad A6261ELPTR-T –40 to 85 4000 pieces per 13-in. reel A6261KLPTR-T –40 to 125 4000 pieces per 13-in. reel A6261KLYTR-T –40 to 125 4000 pieces per 13-in. reel LA1-LA4 = 100 mA 16-pin TSSOP with exposed thermal pad 10-pin MSOP with exposed thermal pad ABSOLUTE MAXIMUM RATINGS [1] Characteristic Load Supply Voltage Symbol Notes VIN Rating Unit –0.3 to 50 V Pin EN –0.3 to 50 V All LAx pins –0.3 to 50 V Pin FF –0.3 to 50 V Pins IREF, THTH –0.3 to 6.5 V E temperature range –40 to 85 °C K temperature range –40 to 125 °C 150 °C 175 °C –55 to 150 °C Ambient Operating Temperature Range [2] TA Maximum Continuous Junction Temperature TJ(max) Transient Junction Temperature TtJ Storage Temperature Range Tstg [1] With Overtemperature event not exceeding 10 seconds, lifetime duration not exceeding 10 hours, ensured by design characterization respect to GND. by power dissipation. [2] Limited THERMAL CHARACTERISTICS [3]: May require derating at maximum conditions; see application information Characteristic Symbol Test Conditions* LJ package Package Thermal Resistance (Junction to Ambient) RθJA LP package LY package Package Thermal Resistance (Junction to Pad) [3] Value Unit On 4-layer PCB based on JEDEC standard 35 °C/W On 2-layer PCB with 0.8 in.2 of copper area each side 62 °C/W On 4-layer PCB based on JEDEC standard 34 °C/W 43 °C/W On 4-layer PCB based on JEDEC standard 48 °C/W On 2-layer PCB with 2.5 in.2 of copper area each side 48 °C/W 2 °C/W On 2-layer PCB with 3.8 in.2 of copper area each side RθJP To be verified by characterization for LP and LY. Additional thermal information available on the Allegro™ website. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 A6261 Protected LED Array Driver +V VIN THTH IREF Current Regulators Control Logic EN Temp Comp Temp Monitor LA1 Slew Limit LA3 Current Reference LA4 FF RTH LA2 Fault Control RREF PAD GND LP and LY packages only Functional Block Diagram PINOUT DIAGRAMS AND TERMINAL LIST TABLE 8 FF THTH 1 IREF 2 PAD Terminal List Table Number 7 EN GND 3 6 VIN LA1 4 5 LA2 LJ Package Name LJ LP LY Function EN 7 13 9 Enable FF 8 14 10 Fault output GND 3 5 3 Ground reference NC 1 16 NC NC 2 15 NC IREF 2 4 2 Current reference THTH 3 14 FF LA1 4 6 4 LED anode (+) connection 1 IREF 4 13 EN LA2 5 7 5 LED anode (+) connection 2 LA3 – 10 6 LED anode (+) connection 3 LA4 – 11 7 LED anode (+) connection 4 NC – 1,2,8, 9,15,16 – No connection; connect to GND PAD – – – Exposed thermal pad GND 5 PAD 12 VIN LA1 6 11 LA4 LA2 7 10 LA3 NC 8 9 NC LP Package THTH 1 10 FF THTH 1 3 1 Thermal threshold IREF 2 9 EN VIN 6 12 8 Supply GND 3 PAD 8 VIN LA1 4 7 LA4 LA2 5 6 LA3 LY Package Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 A6261 Protected LED Array Driver ELECTRICAL CHARACTERISTICS [1]: Valid at TJ = –40°C to 150°C, VIN = 7 to 40 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit SUPPLY AND REFERENCE VIN Functional Operating Range [2] VIN 6 – 50 V VIN Quiescent Current IINQ All LAx pins connected to VIN – – 10 mA VIN Sleep Current IINS EN = GND, VIN = 16 V – – 10 µA tON VIN > 7 V to ILA2 < –5 mA, RREF = 125 Ω (except LJ-1 version); VIN > 7 V to ILA2 < –10 mA, RREF = 125 Ω (LJ-1 version) 5 20 30 µs 1.15 1.2 1.25 V Startup Time CURRENT REGULATION Reference Voltage Reference Current Ratio Current Accuracy [3] Current Matching [4] Output Current Maximum Output Current Minimum Drop-Out Voltage Output Disable Threshold Current Slew Time VIREF 0.7 mA < IREF < 8.8 mA GH0 LP and LY packages, ILAx / IREF – 12.5 – – GH1 LJ package only ILA1 / IREF, LJ-1 package, ILAx/IREF – 25 – – GH2 LJ package only ILA2 / IREF – 12.5 – – 10% ILANx > ILAx > 100% ILANx –5 ±4 5 % ILAx = 10 mA, LJ-1 (200 mA × 2 channel) option [5] – 10 – % LP and LY packages only –20 mA > ILAx > –100 mA, LJ-1 package only –40 mA > ILAx > –200 mA, VLAx match to within 1 V – 5 10 % ILAx EN = high – GHx × IREF – – ILAN0 IREF = 8 mA, EN = high, LP, LY and LA2 pin of LJ package –105 –100 –95 mA ILAN1 IREF = 8 mA, EN = high, LJ-1 and LA1 pin of LJ package –210 –200 –190 mA ILAxmax IREF = 9.2 mA, EN = high, LP, LY and LA2 pin of LJ package – – –110 mA ILA1max IREF = 9.2 mA, EN = high, LJ-1 and LA1 pin of LJ package – – –220 mA VIN – VLAx , ILAx = –100 mA, LP, LY and LA2 pin of LJ package – – 800 mV VIN – VLAx , ILAx = –200 mA, LJ-1 and LA1 pin of LJ package – – 800 mV VIN – VLAx , ILAx = –40 mA , LP, LY and LA2 pin of LJ package – – 660 mV VIN – VLAx , ILAx = –80 mA, LJ-1 and LA1 pin of LJ package – – 660 mV VIN – VLAx 65 – 160 mV Current rising or falling between 10% and 90% 50 80 110 µs EILAx EIMLAx VDO VODIS tSL Continued on the next page… Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 A6261 Protected LED Array Driver ELECTRICAL CHARACTERISTICS [1] (continued): Valid at TJ = –40°C to 150°C, VIN = 7 to 40 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit LOGIC INPUTS FF AND EN Input Low Voltage VIL – – 0.8 V Input High Voltage VIH 2 – – V Input Hysteresis (EN pin) VIhys 150 350 – mV Pull-Down Resistor (EN pin) RPD – 50 – kΩ Output Low Voltage (FF pin) VOL – – 0.4 V IOL = 1 mA PROTECTION Short Detect Voltage Short-Circuit Source Current Short Release Voltage VSCD Measured at LAx 1.2 – 1.8 V ISCS0 Short present LAx to GND: LP, LY and LA2 pin of LJ package –2 –0.8 –0.5 mA ISCS1 Short present LAx to GND: LJ-1 and LA1 pin of LJ package –4 –1.6 –1 mA VSCR Measured at LAx – – 1.9 V Short Release Voltage Hysteresis VSChys VSCR – VSCD 200 – 500 mV Open-Load Detect Voltage VOCD VIN – VLAx 170 – 450 mV Open-Load Detect Delay tOCD – 2 – ms Thermal Monitor Activation Temperature TJM TJ with ISEN = 90%, THTH pin is open 95 115 130 °C ISEN = 50% –3.5 –2.5 –1.5 %/°C 120 135 150 °C Thermal Monitor Slope dISEN/dTJ Thermal Monitor Low Current Temperature TJL TJ at ISEN = 25%, THTH pin is open Overtemperature Shutdown TJF Temperature increasing – 170 – °C Overtemperature Hysteresis TJhys Recovery = TJF – TJhys – 15 – °C [1] For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. is correct but parameters are not guaranteed outside the general limits (7 to 40 V). [3] When EN = high, E ILAx = 100 × [( | ILAx | × RREF / 15 ) –1], with ILAx in mA and RREF in kΩ, for LP, LY and LA2 pin of LJ package. [4] E IMLA = 100 × max ( | ILAx– ILA(AV) | ) / ILA(AV) , where ILA(AV) is the average current of all active outputs. [5] Guaranteed by design and characterization, not production tested. [2] Function Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 A6261 Protected LED Array Driver FUNCTIONAL DESCRIPTION The A6261 is a linear current regulator that is designed to provide drive current and protection for parallel strings of series-connected high brightness LEDs. The LP and LY options provide up to four matched programmable current outputs at up to 100 mA, and LJ-1 option provides two outputs with 200mA per channel, whereas the LJ option provides two outputs, LA1 = 200 mA and LA2 = 100 mA. All the outputs have low minimum dropout voltages below the main supply voltage. For 12 V power net applications, optimum performance is achieved when driving all strings of 1 to 3 series connected LEDs, at rated current per string. The A6261 is specifically designed for use in applications where the LED current is controlled by a single logic input or a highside switched supply. In addition, the A6261 disables all LEDs on detecting a single open LED. Current regulation is maintained and the LEDs protected during a short-to-ground at any point in the LED string. A short-to-ground on any regulator output terminal will disable that output and set the fault flag. An open load on any output will set the fault flag and disable all outputs. Remaining outputs can be re-enabled by pulling the fault flag output low. Individual outputs can be disabled by connecting the output to VIN. LA[1:4]. Current source connected to the anode of the first LED in each string. Connect directly to VIN to disable the respective output. In this document, “LAx” indicates any one output of the ICs. FF. Open drain fault flag, used with an external pull-up resistor, to indicate open, short, or overtemperature conditions. FF is inactive when a fault is present. During an open-load condition, FF can be pulled low to force the remaining outputs on. LED Current Level The LED current is controlled by four matching linear current regulators between the VIN pin and each of the LAx outputs. The basic equation that determines the nominal output current at each LAx pin is: Given EN = high, IREF = 1.2 (1) RREF and ILAx = GHx × IREF (2) where ILAx is in mA and RREF is in kΩ. Integrated thermal management reduces the regulated current level at high internal junction temperatures to limit power dissipation. The output current may be reduced from the set level by the thermal monitor circuit. Pin Functions Conversely, the reference resistors may be calculated from: VIN Supply to the control circuit and current regulators. A small value ceramic bypass capacitor, typically 100 nF, should be connected from close to this pin to the GND pin. GND. Ground reference connection. Should be connected directly to the negative supply. EN. Logic input to enable LED current output. This provides a direct on/off action and can be used for direct PWM control. IREF. 1.2 V reference to set current reference. Connect resistor, RREF, to GND to set reference current. THTH. Sets the thermal monitor threshold, TJM , where the output current starts to reduce with increasing temperature. Connecting THTH directly to GND will disable the thermal monitor function. RREF = 1.2 × GHx ILAx (3) where ILAx is in mA and RREF is in kΩ. For example, where the required current is 90 mA per channel in LP or LY package the resistor value will be : RREF = 15 90 = 167 Ω These equations completely define the output currents with respect to the setting resistors. However, for further reference, a more detailed description of the internal reference current calculations is included below. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 A6261 It is important to note that because the A6261 is a linear regulator, the maximum regulated current is limited by the power dissipation and the thermal management in the application. All current calculations assume adequate heatsinking for the dissipated power. Thermal management is at least as important as the electrical design in all applications. In high-current, high-ambient temperature applications, the thermal management is the most important aspect of the systems design. The application section below provides further detail on thermal management and the associated limitations. Operation with Fewer LED Strings or Higher Currents Protected LED Array Driver rents, or by connecting the output directly to VIN to disable the regulator for that output. When a regulator is disabled, it will not indicate an open load and will not affect the fault flag or the operation of the remaining regulator outputs. Sleep Mode When EN is held low, the A6261 will be in shutdown mode and all sections will be in a low-power sleep mode. The input current will be typically less than 10 µA. This means that the complete circuit, including LEDs, may remain connected to the power supply under all conditions. The A6261 may be configured to use fewer than four LED strings, either by connecting outputs together for higher cur- Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 A6261 Safety Features The circuit includes several features to ensure safe operation and to protect the LEDs and the A6261: Protected LED Array Driver VIN A6261 LA1 LA2 LA3 LA4 • The current regulators between VIN and each LAx output provide a natural current limit due to the regulation. • Each LAx output includes a short-to-ground detector that will disable the output to limit the dissipation. A. Any LED cathode short-to-ground. Current remains regulated in non-shorted LEDs. Matching may be affected. FF is low. GND • An open circuit on any output will disable all outputs. • The thermal monitor reduces the regulated current as the temperature rises. • Thermal shutdown completely disables the outputs under extreme overtemperature conditions. VIN A6261 LA1 LA2 LA3 LA4 SHORT CIRCUIT DETECTION A short-to-ground on any LED cathode (Figure 1A) will not result in a short fault condition. The current through the remaining LEDs will remain in regulation and the LEDs will be protected. Due to the difference in the voltage drop across the LEDs as a result of the short, the current matching in the A6261 may exceed the specified limits. Any LAx output that is pulled below the short detect voltage (Figure 1B) will disable the regulator on that output and allow the fault flag, FF, to go high. A small current will be sourced from the disabled output to monitor the short and detect when it is removed. When the voltage at LAx rises above the short detect voltage, the fault flag will be removed and the regulator re-enabled. A shorted LED (Figure 1C) will not result in a short fault condition. The current through the remaining LEDs will remain in regulation and the LEDs will be protected. Due to the difference in the voltage drop across the LEDs as a result of the short, the current matching in the A6261 may exceed the specified limits. A short between LEDs in different strings (Figure 1D) will not result in a short fault condition. The current through the remaining LEDs will remain in regulation, and the LEDs will be protected. The current will be summed and shared by the affected strings. Current matching in the strings will then depend on the LED forward voltage differences. B. Any LAx output short-to-ground. Shorted output is disabled. Other outputs remain active. FF is high. GND VIN A6261 LA1 LA2 LA3 LA4 C. Shorted LEDs. Current remains regulated. Matching may be affected. Only the shorted LED is inactive. FF is low. GND VIN A6261 LA1 LA2 LA3 LA4 D. Short between LEDs in different strings. Current remains regulated. Current is summed and shared by affected strings. Intensity match dependent on voltage binning. FF is low. GND Figure 1: Short-Circuit Conditions Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 A6261 Protected LED Array Driver OPEN-LOAD DETECTION TEMPERATURE MONITOR An open-load condition is detected when the voltage across the regulator, VIN – VLAx , is less than the open-load detect voltage, VOCD , but greater than the output disable threshold voltage, VODIS . When this condition is present for more than the openload detect time, tOCD , then all regulators will be disabled and the fault flag allowed to go high. A temperature monitor function, included in the A6261, reduces the LED current as the silicon junction temperature of the A6261 increases (see Figure 2). By mounting the A6261 on the same thermal substrate as the LEDs, this feature can also be used to limit the dissipation of the LEDs. As the junction temperature of the A6261 increases, the regulated current level is reduced, reducing the dissipated power in the A6261 and in the LEDs. The current is reduced from the 100% level at typically 2.5% per degree Celsius until the point at which the current drops to 25% of the full value, defined at TJL . Above this temperature, the current will continue to reduce at a lower rate until the temperature reaches the overtemperature shutdown threshold temperature, TJF. Pulling the fault flag low will override the open-load fault action and all enabled regulators will be switched on. This state will be maintained while the fault flag is held low. If the fault flag is allowed to go high the A6261 will return to the open-load fault condition and will disable all regulators. Each of the four regulators includes a limiter to ensure that the output voltage will not rise higher than the output disable threshold voltage below VIN when driven by the regulator. This means that the voltage across the regulator will not be less than the output disable voltage, unless it is forced by connecting the LAx pin to VIN. However if a load becomes disconnected, the regulator will pull the LAx pin up to the limit, which will ensure that the voltage across the regulator, VIN – VLAx , is less than the open-load detect voltage, VOCD . Note that an open load may also be detected if the sum of the forward voltages of the LEDs in a string is close to or greater than the supply voltage on VIN. The temperature at which the current reduction begins can be adjusted by changing the voltage on the THTH pin. When THTH is left open, the temperature at which the current reduction begins is defined as the thermal monitor activation temperature, TJM, and is specified in the characteristics table at the 90% current level. 110 100 90 Relative Sense Current (%) The regulators will remain disabled until either the power is cycled off and on, the EN input is taken low then high, or the fault flag, FF, is pulled low. If the power is cycled or EN is pulsed low, the regulators will start in the enabled state, unless disabled by tying the output to VIN, and the open-load detection timer will be reset. If the open load is still present the regulators will again be disabled after the open-load detect time. 80 70 60 50 40 30 20 TJM 10 TJL 0 70 80 90 100 110 120 130 140 150 160 170 180 Junction Temperature, TJ (°C) Figure 2: Temperature Monitor Current Reduction Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 A6261 Protected LED Array Driver Thermal monitor activation temperature can be set to a desired level by setting the voltage on the THTH pin (VTHTH). There is an internal 1 V source connected with a series resistor to the THTH pin inside the IC. A resistor connected between THTH and GND will reduce VTHTH and increase TJM. A resistor connected between THTH and a reference supply greater than 1 V will increase VTHTH and reduce TJM. Figure 3a shows the relationship between TJM and VTHTH while Figure 3b shows typical resistor values, either pull up or pull down, to set the voltage on THTH pin. Now, based on the TJM requirement, estimate the required VTHTH voltage from Figure 3a, and then, depending on the VTHTH value, decide the THTH pin resistor from Figure 3b. THTH pin resistor may either pull up or pull down depending on VTHTH. As an example, if TJM of 90°C is required, then from Figure 3a, VTHTH should be 1.115 V. To achieve this voltage, use Figure 3b to estimate THTH pin resistor (RTH). If the pull-up voltage is 5 V, then a 211 kΩ resistor should be used. If the pull-up voltage is 3 V, use a 100 kΩ resistor. In extreme cases, if the chip temperature exceeds the overtemperature limit, TJF , all regulators will be disabled. The temperature will continue to be monitored and the regulators re-activated when the temperature drops below the threshold provided by the specified hysteresis. Note that it is possible for the A6261 to transition rapidly between thermal shutdown and normal operation. This can happen if the thermal mass attached to the exposed thermal pad is small and TJM is increased to close to the shutdown temperature. The period of oscillation will depend on TJM, the dissipated power, the thermal mass of any heatsink present, and the ambient temperature. 1.25 1.25 1.20 1.2 RTH Pull up to 5 V 1.15 1.15 1.10 VTHTH (V) VTHTH (V) 1.1 1.05 1 RTH Pull up to 3 V 1.05 1.00 RTH Pull down to GND 0.95 0.95 0.90 0.9 0.85 0.85 0.80 0.8 70 80 90 100 110 120 130 140 Thermal Monitor Activation Temperature, T JM (°C ) Figure 3a: Relationship Between TJM and VTHTH 150 0 50 100 150 200 250 RTH (kΩ) Figure 3b: Typical Resistor Values to Set Voltage on THTH Pin Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 A6261 Protected LED Array Driver APPLICATION INFORMATION Power Dissipation The most critical design considerations when using a linear regulator such as the A6261 are the power produced internally as heat and the rate at which that heat can be dissipated. There are three sources of power dissipation in the A6261: Note that the voltage drop across the regulator, VREG , is always greater than the specified minimum dropout voltage, VDO . The output current is regulated by making this voltage large enough to provide the voltage drop from the supply voltage to the total forward voltage of all LEDs in series, VLED . The total power dissipated in the A6261 is the sum of the quiescent power, the reference power, and the power in each of the four regulators: • The quiescent power to run the control circuits • The power in the reference circuit • The power due to the regulator voltage drop The elements relating to these dissipation sources are illustrated in Figure 4. QUIESCENT POWER The quiescent power is the product of the quiescent current, IINQ , and the supply voltage, VIN , and is not related to the regulated current. The quiescent power, PQ, is therefore defined as: PQ = VIN × IINQ (4) REFERENCE POWER The reference circuit draws the reference current from the supply and passes it through the reference resistor to ground. The reference current is 8% of the output current on any one active output. The reference circuit power is the product of the reference current and the difference between the supply voltage and the reference voltage, typically 1.2 V. The reference power, PREF , is therefore defined as: (VIN – VREF) × VREF PREF = RREF PDIS = PQ + PREF + PREGA + PREGB + PREGC + PREGD The power that is dissipated in each string of LEDs is: PLEDx = VLEDx × ILEDx From these equations (and as illustrated in Figure 5) it can be seen that, if the power in the A6261 is not limited, then it will increase as the supply voltage increases but the power in the LEDs will remain constant. VIN (5) A6261 VREG ILAx In most application circuits, the largest dissipation will be produced by the output current regulators. The power dissipated in each current regulator is simply the product of the output current and the voltage drop across the regulator. The total current regulator dissipation is the sum of the dissipation in each output regulator. The regulator power for each output is defined as: where x is 1, 2, 3, or 4. (8) where x is A, B, C, or D, and VLEDx is the voltage across all LEDs in the string. REGULATOR POWER PREGx = (VIN – VLEDx ) × ILEDx (7) (6) LAx VIN IREF IINQ VLED IREF VREF RREF GND Figure 4: Internal Power Dissipation Sources Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 A6261 Protected LED Array Driver the graph shows the current as the supply voltage increases from 14 to 17 V. As the supply voltage increases, without the thermal foldback feature, the current would remain at 50 mA, as shown by the dashed line. The solid line shows the resulting current decrease as the thermal foldback feature acts. Power Dissipation, PD (W) 3.0 2.5 2.0 1.5 LED Power 1.0 A6261 Power 0.5 0 8 9 10 12 13 11 Supply Voltage, VIN (V) 14 15 16 If the thermal foldback feature did not affect LED current, the current would increase the power dissipation and therefore the silicon temperature. The thermal foldback feature reduces power in the A6261 in order to limit the temperature increase, as shown in Figure 7. The figure shows the operation of the A6261 under the same conditions as Figure 6. That is, 4 strings of 3 red LEDs, each string running at 50 mA with each LED forward voltage at 2.3 V. The graph shows the temperature as the supply voltage Figure 5: Power Dissipation versus Supply Voltage 54 Dissipation Limits 52 There are two features limiting the power that can be dissipated by the A6261: thermal shutdown and thermal foldback. If the thermal foldback feature is disabled by connecting the THTH pin to GND, or if the thermal resistance from the A6261 to the ambient environment is high, then the silicon temperature will rise to the thermal shutdown threshold and the current will be disabled. After the current is disabled, the power dissipated will drop and the temperature will fall. When the temperature falls by the hysteresis of the thermal shutdown circuit, then the current will be re-enabled and the temperature will start to rise again. This cycle will repeat continuously until the ambient temperature drops or the A6261 is switched off. The period of this thermal shutdown cycle will depend on several electrical, mechanical, and thermal parameters and could be from a few milliseconds to a few seconds. ILED (mA) THERMAL SHUTDOWN The thermal monitor will reduce the LED current as the temperature of the A6261 increases above the thermal monitor activation temperature, TJM , as shown in Figure 6. The figure shows the operation of the A6261 with 4 strings of 3 red LEDs, each string running at 50 mA. The forward voltage of each LED is 2.3 V and 48 46 4 Strings VLED = 6.9 V ILED = 50 mA TA = 50°C 44 With thermal monitor 42 40 14.0 14.5 15.0 15.5 16.0 Supply Voltage, VIN (V) 16.5 17.0 Figure 6: LED current versus Supply Voltage 130 125 THERMAL FOLDBACK 120 TJ (°C) If there is a good thermal connection to the A6261, then the thermal foldback feature will have time to act. This will limit the silicon temperature by reducing the regulated current and therefore the dissipation. Without thermal monitor 50 4 Strings VLED = 6.9 V ILED = 50 mA TA = 50°C 115 Without thermal monitor With thermal monitor 110 105 100 14.0 14.5 15.0 15.5 16.0 Supply Voltage, VIN (V) 16.5 17.0 Figure 7: Junction Temperature versus Supply Voltage Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 A6261 Protected LED Array Driver increases from 14 to 17 V. Without the thermal foldback feature, the temperature would continue to increase up to the thermal shutdown temperature as shown by the dashed line. The solid line shows the effect of the thermal foldback function in limiting the temperature rise. Figures 6 and 7 show the thermal effects where the thermal resistance from the silicon to the ambient temperature is 40°C/W. Thermal performance can be enhanced further by using a significant amount of thermal vias as described below. LJ Package Thermal Dissipation The amount of heat that can pass from the silicon of the A6261 to the ambient environment depends on the thermal resistance of the structures connected to the A6261. The thermal resistance, RθJA , is a measure of the temperature rise created by the power dissipated and is usually measured in degrees Celsius per watt (°C/W). The temperature rise, ΔT, is calculated from the power dissipated, PD , and the thermal resistance, RθJA , as: ΔT = PD × RθJA LP Package (9) A thermal resistance from silicon to ambient, RθJA , of approximately 30°C/W (LP package) or 34°C/W (LY package), can be achieved by mounting the A6261 on a standard FR4 double-sided printed circuit board (PCB) with a copper area of a few square inches on each side of the board under the A6261. Multiple thermal vias, as shown in Figure 8, help to conduct the heat from the exposed pad of the A6261 to the copper on each side of the board. The thermal resistance can be reduced by using a metal substrate or by adding a heatsink. Supply Voltage Limits In some applications, the available supply voltage can vary over a two-to-one range— for example, emergency lighting systems using battery backup. In such systems is it necessary to design the application circuit such that the system meets the required performance targets over a specified voltage range. To determine this range when using the A6261, there are two limiting conditions: LY Package Figure 8: Board Via Layout for Thermal Dissipation • For maximum supply voltage, the limiting factor is the power that can be dissipated from the regulator without exceeding the temperature at which the thermal foldback starts to reduce the output current below an acceptable level. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13 A6261 Protected LED Array Driver • For minimum supply voltage, the limiting factor is the maximum dropout voltage of the regulator, where the difference between the load voltage and the supply is insufficient for the regulator to maintain control over the output current. defined as the voltage above which the LED current drops below the acceptable minimum. MINIMUM SUPPLY LIMIT: REGULATOR SATURATION VOLTAGE Note that, if the thermal monitor circuit is disabled (by connecting the THTH pin to GND), then the maximum supply limit will be determined by the specified maximum continuous operating temperature, 150°C. The supply voltage, VIN , is always the sum of the voltage drop across the high-side regulator, VREG , and the forward voltage of the LEDs in the string, VLED, as shown in Figure 4. VLED is constant for a given current and does not vary with supply voltage. Therefore, VREG provides the variable difference between VLED and VIN . VREG has a minimum value below which the regulator can no longer be guaranteed to maintain the output current within the specified accuracy. This level is defined as the regulator dropout voltage, VDO. The minimum supply voltage, below which the LED current does not meet the specified accuracy, is therefore determined by the sum of the minimum dropout voltage, VDO , and the forward voltage of the LEDs in the string, VLED . The supply voltage must always be greater than this value and the minimum specified supply voltage, that is: VIN > VDO + VLED, and VIN > VIN (min) (10) As an example, consider the configuration used in Figures 6 and 7 above, namely 4 strings of 3 red LEDs, each string running at 50 mA, with each LED forward voltage at 2.3 V. The minimum supply voltage will be approximately: VIN(min) = 0.55 + (3 × 2.3) = 7.45 V MAXIMUM SUPPLY LIMIT: THERMAL LIMITATION As described above, when the thermal monitor reaches the activation temperature, TJM (due to increased power dissipation as the supply voltage rises), the thermal foldback feature causes the output current to decrease. The maximum supply voltage is therefore This can be estimated by determining the maximum power that can be dissipated before the internal (junction) temperature of the A6261 reaches TJM. The maximum power dissipation is therefore defined as: PD(max) = ∆T RθJA (11) where ΔT is difference between the thermal monitor activation temperature, TJM , of the A6261 and the maximum ambient temperature, TA(max), and RθJA is the thermal resistance from the internal junctions in the silicon to the ambient environment. If minimum LED current is not a critical factor, then the maximum voltage is simply the absolute maximum specified in the parameter tables above. Application Examples In some filament bulb replacement applications, the supply may be provided by a PWM-driven, high-side switch. The A6261 can be used in this application by simply connecting EN to VIN. If neither fault action nor fault reporting is required, then FF should be tied to ground. When power is applied, there will be a short startup delay, tON , before the current starts to rise. The current rise time will be limited by the internal current slew rate control. The application circuit options in Figure 9 show operation with a higher voltage supply and with combinations of outputs tied together and disabled. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14 A6261 Protected LED Array Driver + + 24 V 12 V PWM high-side drive VIN VIN A6261 A6261 (LP, LY Packages) EN LA1 FF LA2 IREF LA3 THTH LA4 PWM dimming input Fault output (LP, LY Packages) LA1 LA2 EN LA3 LA4 FF IREF THTH GND GND – – B. Higher voltage operation A. High brightness (HB) LED incandescent lamp replacement + + 14 V 12 V VIN VIN A6261 A6261 PWM dimming input (LP, LY Packages) PWM dimming input (LJ Package) EN LA1 LA2 FF LA2 IREF LA3 IREF THTH LA4 THTH EN LA1 FF GND GND – – C. Mix of output combinations D. A6261LJ: Single output with 100mA. For 200 mA single output, connect LA2 to VIN and LEDs to LA1. Figure 9: Typical Applications with Various Supply and Output Options. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15 A6261 Protected LED Array Driver Binning Resistor Arrangement An external binning resistor can be connected in series with the IREF pin to set appropriate current through various LED batches. A filter capacitor of 100 nF should be placed after RREF1 as shown in Figure 10. ILAx(min) = (1.2 × GHX) ÷ (RREF1 + RREF2) (12) (13) ILAx(max) = (1.2 × GHX) ÷ RREF1 LED Driver Board LED Board VIN A6261 (LJ Package) RREF1 FF LA1 EN THTH LA2 LED1 LED2 LED3 LED4 IREF GND CREF RREF2 Figure 10: Application Circuit for Binning – Current-setting resistor (RREF2) can be placed on LED board for different bins of LEDs. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 16 A6261 Protected LED Array Driver PACKAGE OUTLINE DRAWINGS For Reference Only – Not for Tooling Use (Reference MS-012BA) Dimensions in millimeters – NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 4.90 ±0.10 1.27 0.65 8° 0° 8 8 0.25 0.17 1.75 B 2.41 NOM 3.90 ±0.10 6.00 ±0.20 2.41 5.60 A 1.04 REF 1 2 1 1.27 0.40 3.30 NOM 3.30 0.25 BSC Branded Face 2 C PCB Layout Reference View SEATING PLANE GAUGE PLANE C 8X 0.10 1.70 MAX C SEATING PLANE 0.51 0.31 1.27 BSC 0.15 0.00 A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Figure 11: Package LJ, 8-Pin SOICN with Exposed Thermal Pad Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 17 A6261 Protected LED Array Driver For Reference Only – Not for Tooling Use (Reference MO-153 ABT) Dimensions in millimeters. NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 0.65 0.45 8º 0º 5.00 ±0.10 16 16 0.20 0.09 1.70 B 3 NOM 4.40 ±0.10 3.00 6.40 ±0.20 A 6.10 0.60 ±0.15 1.00 REF 1 2 3 NOM 1 0.25 BSC 2 Branded Face 3.00 SEATING PLANE C 16X 0.10 SEATING PLANE C 0.30 0.19 GAUGE PLANE C PCB Layout Reference View 1.20 MAX 0.65 BSC NNNNNNN YYWW LLLL 0.15 0.00 A Terminal #1 mark area B Exposed thermal pad (bottom surface); dimensions may vary with device C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D 1 D Standard Branding Reference View N = Device part number = Supplier emblem Y = Last two digits of year of manufacture W = Week of manufacture L = Characters 5-8 of lot number Branding scale and appearance at supplier discretion Figure 12: Package LP, 16-Pin TSSOP with Exposed Thermal Pad Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 18 A6261 Protected LED Array Driver For Reference Only – Not for Tooling Use (Reference JEDEC MO-187) Dimensions in millimeters – NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 0° to 6° 3.00 ±0.10 10 0.15 ±0.05 3.00 ±0.10 4.88 ±0.20 A 0.53 ±0.10 1 2 1.98 1 0.25 Seating Plane 2 Gauge Plane A Terminal #1 mark area B Exposed thermal pad (bottom surface) B 1.73 10 0.86 ±0.05 SEATING PLANE 0.27 0.18 0.50 REF 0.05 0.15 Figure 13: Package LY, 10-Pin MSOP with Exposed Thermal Pad Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 19 A6261 Protected LED Array Driver Revision History Number Date Description 8 September 10, 2013 9 December 6, 2014 10 June 25, 2015 11 September 30, 2015 12 July 28, 2016 Add LJ package Add LJ-1 package; revised Selection Guide Temperature Monitor text on page 9 updated to match EC table: derating slope is –2.5% per °C Removed Contact Factory status from A6261KLJTR-T-1; THTH pin resistor (RTHTH) selection description modified; Binning resistor application note added; figure 2 updated. Updated Figure 10 13 January 8, 2018 Updated Current Accuracy characteristic in EC table (page 4) 14 January 21, 2019 Minor editorial updates 15 February 4, 2020 Minor editorial updates Copyright 2020, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 20